WO2021224982A1 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
WO2021224982A1
WO2021224982A1 PCT/JP2020/018638 JP2020018638W WO2021224982A1 WO 2021224982 A1 WO2021224982 A1 WO 2021224982A1 JP 2020018638 W JP2020018638 W JP 2020018638W WO 2021224982 A1 WO2021224982 A1 WO 2021224982A1
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Prior art keywords
coil
substrate
transmission
side substrate
receiving
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PCT/JP2020/018638
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French (fr)
Japanese (ja)
Inventor
雅俊 長谷川
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ウルトラメモリ株式会社
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Priority to JP2022519874A priority Critical patent/JP7278016B2/en
Priority to PCT/JP2020/018638 priority patent/WO2021224982A1/en
Publication of WO2021224982A1 publication Critical patent/WO2021224982A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/11—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate

Definitions

  • the present invention relates to a semiconductor device.
  • RAM volatile memory
  • DRAM Dynamic Random Access Memory
  • logic chips arithmetic units
  • the capacity has been increased by miniaturizing the memory (memory cell array, memory chip) and increasing the number of cells in a plane.
  • this kind of large capacity has reached its limit due to the weakness to noise due to miniaturization and the increase in area.
  • Patent Document 1 when power is supplied from the primary coil to the secondary coil, the power supply loss is reduced by arranging the relay coil.
  • the relay coil of Patent Document 1 employs a mechanism for adjusting the resonance frequency in order to supply electric power by resonance. Therefore, the technique described in Patent Document 1 is not suitable for non-contact communication for transmitting signals of various frequencies.
  • Patent Document 2 discloses an electronic circuit in which three pairs of transmitting coils and receiving coils arranged on concentric circles are arranged coaxially in order. Then, in Patent Document 2, when a signal is transmitted from one transmitting coil to the other two receiving coils, one end of the other two transmitting coils is released, so that the other two transmitting coils interfere with communication. It suppresses doing. However, in Patent Document 2, it is not possible to increase the strength of the received signal.
  • An object of the present invention is to provide a semiconductor device capable of increasing the strength of a received signal.
  • the present invention is a semiconductor device including a plurality of semiconductor substrates to be laminated, wherein a transmission coil arranged on the transmission side substrate, which is one of the semiconductor substrates, and the semiconductor substrate different from the transmission side substrate are used.
  • An intermediate substrate which is at least one semiconductor substrate between a receiving coil arranged on a receiving side substrate and overlapping with the transmitting coil in a stacking direction and the transmitting side substrate and the receiving side substrate.
  • the present invention relates to a semiconductor device including an intermediate coil arranged at a position where the transmitting coil and the receiving coil overlap in a stacking direction, and both ends of which are electrically open.
  • the intermediate coil is a semiconductor substrate between the receiving side substrate and the transmitting side substrate, which is closer to the receiving side substrate than the intermediate point between the receiving side substrate and the transmitting side substrate. It is preferably placed in either.
  • a plurality of the intermediate coils are arranged on one intermediate substrate.
  • FIG. 1 It is a top view of the semiconductor substrate laminated on the semiconductor device which concerns on one Embodiment of this invention.
  • a cross-sectional view of the semiconductor device of one embodiment is shown.
  • a first embodiment of the semiconductor device of one embodiment is shown.
  • a second embodiment of the semiconductor device of one embodiment is shown.
  • the semiconductor device 1 is, for example, a member including a plurality of semiconductor substrates 10 to be laminated.
  • the semiconductor device 1 is, for example, a memory member having a memory chip (DRAM chip).
  • the semiconductor device 1 realizes non-contact communication between the laminated semiconductor substrates 10.
  • the semiconductor device 1 can improve the ease of manufacture and the degree of integration by, for example, performing communication using a magnetic field.
  • the semiconductor device 1 according to the following embodiment is intended to improve the communication strength in non-contact communication.
  • the semiconductor device 1 includes a plurality of semiconductor substrates 10, a transmission circuit 20, a transmission coil 30, a reception circuit 40, a reception coil 50, and an intermediate coil 60. Be prepared.
  • the semiconductor substrate 10 is, for example, a silicon substrate.
  • the semiconductor substrate 10 includes a wiring layer arranged on one surface.
  • five semiconductor substrates 10 are provided: a first substrate 11, a second substrate 12, a third substrate 13, a fourth substrate 14, and a fifth substrate 15.
  • the second substrate 12 and the third substrate 13 are adhered with the wiring layers 112 and 113 facing each other.
  • the fourth substrate 14 and the fifth substrate 15 are adhered with the wiring layers 114 and 115 facing each other.
  • the third substrate 13 and the fourth substrate 14 are adhered so that the surfaces opposite to the wiring layers 113 and 114 face each other.
  • the first substrate 11 and the second substrate 12 are adhered so that the surfaces opposite to the wiring layers 111 and 112 face each other.
  • the transmission coil 30 is a signal transmission coil arranged on the semiconductor substrate 10.
  • the transmission coil 30 is arranged on a transmission-side substrate, which is one semiconductor substrate 10.
  • the transmission coil 30 is arranged in the wiring layers 111 and 115 of the first substrate 11 and the fifth substrate 15. That is, the transmission coils 30a, 30c, and 30e of the first substrate 11 are arranged on the wiring layer 111 of the first substrate 11 which is the transmission side substrate. Further, the transmission coils 30b, 30d, and 30f of the fifth substrate 15 are arranged on the wiring layer 115 of the fifth substrate 15 which is the transmission side substrate.
  • the transmission coils 30a, 30c, 30e of the first substrate 11 and the transmission coils 30b, 30d, 30f of the fifth substrate 15 are arranged at positions where they do not overlap in the stacking direction D.
  • the transmission circuit 20 is, for example, an electronic circuit.
  • the transmission circuit 20 applies a transmission signal as an electric signal to the transmission coil.
  • the transmission circuit 20 generates a magnetic flux corresponding to the transmission signal in the transmission coil 30.
  • the receiving coil 50 is a signal receiving coil arranged on the semiconductor substrate 10.
  • the receiving coil 50 is arranged on a receiving side substrate, which is a semiconductor substrate 10 different from the transmitting side substrate. Further, the receiving coil 50 is arranged at a position where it overlaps with the transmitting coil 30 in the stacking direction D.
  • the receiving coil 50 is arranged in the wiring layers 111 and 115 of the first substrate 11 and the fifth substrate 15. That is, the receiving coils 50b, 50d, and 50f of the first substrate 11 are arranged on the wiring layer 111 of the first substrate 11 which is the receiving side substrate. Further, the receiving coils 50a, 50c, 50e of the fifth substrate 15 are arranged on the wiring layer 115 of the fifth substrate 15 which is the receiving side substrate.
  • the receiving coils 50a, 50c, 50e of the fifth substrate 15 are arranged at positions where they overlap with the transmitting coils 30a, 30c, 30e of the first substrate 11 in the stacking direction D.
  • the receiving coils 50b, 50d, 50f of the first substrate 11 are arranged at positions where they overlap with the transmitting coils 30b, 30d, 30f of the fifth substrate 15 in the stacking direction D.
  • the receiving circuit 40 is, for example, an electronic circuit.
  • the reception circuit 40 acquires a transmission signal received by the reception coil 50 as a reception signal.
  • the intermediate coil 60 is a coil in which both ends are electrically released.
  • the intermediate coil 60 is arranged on an intermediate substrate, which is at least one semiconductor substrate 10 between the transmitting side substrate and the receiving side substrate.
  • the intermediate coil 60 is arranged in the wiring layer of the intermediate substrate.
  • the intermediate coil 60 is arranged at least in the wiring layer 112 of the second substrate 12.
  • the intermediate coil 60 is arranged, for example, in the wiring layers 112 and 113 of the second substrate 12 and the third substrate 13.
  • the intermediate coil 60 is arranged at a position where it overlaps the transmitting coil 30 and the receiving coil 50 in the stacking direction D.
  • the intermediate coil 60c is arranged at a position where the transmission coil 30c of the first substrate 11 and the reception coil 50c of the fifth substrate 15 overlap in the stacking direction D.
  • the intermediate coil 60d is arranged at a position where the transmission coil 30d of the fifth substrate 15 and the reception coil 50d of the first substrate 11 overlap in the stacking direction D.
  • the intermediate coil 60e is arranged at a position where the transmission coil 30e of the first substrate 11 and the reception coil 50e of the fifth substrate 15 overlap in the stacking direction D.
  • the intermediate coil 60f is arranged at a position where the transmission coil 30f of the fifth substrate 15 and the reception coil 50f of the first substrate 11 overlap in the stacking direction D.
  • a plurality of intermediate coils 60 are arranged on one intermediate substrate.
  • the four intermediate coils 60c, 60d, 60e, 60f are arranged on the second substrate 12, for example.
  • the transmission circuit 20 applies an electric signal for transmission to the transmission coil 30 of the fifth substrate 15.
  • the transmission coil 30 converts an electric signal into a magnetic field.
  • the receiving coil 50 of the first substrate 11 generates an electric signal based on the magnetic field converted by the transmitting coil 30 of the fifth substrate 15.
  • the receiving circuit 40 receives the signal by acquiring the electric signal generated by the receiving coil 50 of the first substrate 11. As a result, one communication channel is formed.
  • the intermediate coil 60 in the intermediate coil 60 arranged on the second substrate 12 (and the third substrate 13), a transient minute current sufficient to charge its own parasitic capacitance flows with the start of transmission of the transmission signal. .. As a result, a reception voltage corresponding to the distance from the transmission coil 30 is generated at both ends of the intermediate coil 60. Subsequently, the current flowing due to the generated reception voltage changes in the opposite direction to the case of the closed loop (coil whose ends are not released). Therefore, the intermediate coil 60 generates a magnetic field in a direction that strengthens the change in the magnetic field of the transmission coil 30. As a result, the change in the magnetic field at the position of the receiving coil 50 is larger than that without the intermediate coil 60. That is, the voltage value of the received signal received by the receiving coil 50 can be made larger than that in the case where the intermediate coil 60 is not provided.
  • Example 1 Next, the first embodiment of the semiconductor device 1 in the present embodiment will be described with reference to FIGS. 2 and 3.
  • the signal transmitted from the transmission coil 30 arranged on the fifth substrate was received by the reception coil 50 arranged on the first substrate.
  • the transmission coil 30 and the reception coil 50 were set as follows.
  • Transmission coil 30 15 turns, diameter 70 ⁇ m, line width 1.4 ⁇ m, line spacing 0.3 ⁇ m
  • Receiving coil 50 30 turns, diameter 70 ⁇ m, line width 0.3 ⁇ m, line spacing 0.3 ⁇ m
  • the distance between the transmitting coil 30 and the receiving coil 50 was set to 40 ⁇ m.
  • the received signal is received in three modes: no intermediate coil 60, the intermediate coil 60 is arranged on the second substrate 12 (1), and the intermediate coil 60 is arranged on the 2nd substrate 12 and the 3rd substrate 13 (2).
  • the intermediate coil 60 was set as follows. Intermediate coils 60c, 60d (second substrate only): 25 turns, diameter 70 ⁇ m, line width 1.0 ⁇ m, line spacing 0.3 ⁇ m Intermediate coils 60e, 60f (second substrate and third substrate): 20 turns, diameter 56 ⁇ m, line width 1.0 ⁇ m, line spacing 0.3 ⁇ m
  • the voltage amplitude of the receiving coil 50 was increased by arranging the intermediate coil 60 regardless of whether the current of the transmitting coil 30 was 360 ⁇ A, 500 ⁇ A, 640 ⁇ A, or 730 ⁇ A. rice field. Further, it was found that the voltage amplitude of the receiving coil 50 can be made larger by arranging a plurality of intermediate coils 60.
  • the numerical value shown together with the voltage waveform of the receiving coil 50 is the amplitude on the high side / the amplitude on the low side, and the unit is mV.
  • Example 2 a second embodiment of the semiconductor device 1 in the present embodiment will be described with reference to FIGS. 2 and 4.
  • the signal transmitted from the transmission coil 30 arranged on the first substrate was received by the reception coil 50 arranged on the fifth substrate 15.
  • the transmission coil 30 and the reception coil 50 were set in the same manner as in the first embodiment.
  • the distance between the transmission coil 30 and the reception coil 50 was also set in the same manner as in the first embodiment.
  • the intermediate coil 60 was also set in the same manner as in the first embodiment.
  • the voltage amplitude of the receiving coil 50 was increased by arranging the intermediate coil 60 regardless of whether the current of the transmitting coil 30 was 360 ⁇ A, 500 ⁇ A, 640 ⁇ A, or 730 ⁇ A. rice field. Further, it was found that the voltage amplitude of the receiving coil 50 can be made larger by arranging a plurality of intermediate coils 60. That is, it was found that the voltage amplitude of the receiving coil 50 can be increased in the second embodiment as in the first embodiment.
  • the numerical value shown together with the voltage waveform of the receiving coil 50 is the amplitude on the high side / the amplitude on the low side, and the unit is mV.
  • a semiconductor device 1 including a plurality of semiconductor substrates 10 to be laminated, wherein a transmission coil 30 arranged on a transmission side substrate, which is one semiconductor substrate 10, and a semiconductor substrate 10 different from the transmission side substrate 10
  • the substrate includes an intermediate coil 60 arranged at a position where the transmitting coil 30 and the receiving coil 50 overlap in the stacking direction D, and the intermediate coils 60 having both ends electrically released.
  • the magnetic field generated by the transmission coil 30 generates a magnetic field in the direction of strengthening the signal by the intermediate coil 60. Therefore, the receiving coil can receive the magnetic field strengthened by the intermediate coil 60 and can increase the strength of the received signal as compared with the case where the intermediate coil 60 is not provided.
  • a plurality of intermediate coils 60 are arranged on one intermediate substrate. Thereby, on one intermediate substrate, the intermediate coil 60 can be arranged for each communication channel formed by one transmission coil 30 and one reception coil 50. Therefore, the range of design can be widened, and the variation of the semiconductor substrate 10 can be widened.
  • the intermediate coil 60 is a semiconductor substrate 10 of the semiconductor substrate 10 between the receiving side substrate and the transmitting side substrate, which is closer to the receiving side substrate than the intermediate point between the receiving side substrate and the transmitting side substrate. It may be placed in either.
  • the value of the transient current that charges the parasitic capacitance of the intermediate coil 60 is smaller than that of arranging the intermediate coil 60 on the semiconductor substrate 10 close to the transmitting side substrate, so that the ringing noise generated by this change in current is eliminated. It can be relatively suppressed. Therefore, improvement in communication quality can be expected.
  • the number of intermediate substrates in the stacking direction D is not limited to three.
  • the number of intermediate substrates is not limited as long as communication is possible between the transmission coil 30 and the reception coil 50.
  • the number of intermediate coils 60 in the stacking direction D is set to 1 or 2, but the number is not limited to this. Three or more intermediate coils 60 may be arranged. Further, a plurality of intermediate coils 60 may be arranged at overlapping positions in the stacking direction D in the same intermediate substrate.
  • a communication channel in which the intermediate coil 60 is not provided, a communication channel in which one is provided, and a communication channel in which a plurality of intermediate coils 60 are provided may be arranged so as to coexist.
  • the semiconductor device 1 can be flexibly configured according to the communication distance and cost of the transmission coil 30 and the reception coil 50, the diameter or the number of turns of the transmission coil 30 and the reception coil 50 that can be arranged. ..

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Near-Field Transmission Systems (AREA)

Abstract

Provided is a semiconductor device that enables the intensity of a reception signal to be increased.　A semiconductor device 1 comprising a plurality of laminated semiconductor substrates 10, is provided with: a transmission coil 30 disposed on a transmission-side substrate that is one of the semiconductor substrates 10; a reception coil 50 disposed on a reception-side substrate that is another one of the semiconductor substrates 10 different from the transmission-side substrate and disposed at a position overlapping with the transmission coil 30 in a lamination direction; and an intermediate coil 60 disposed at a position overlapping with the transmission coil 30 and the reception coil 50 in the lamination direction in an intermediate substrate that is at least one of the semiconductor substrates 10 between the transmission-side substrate and the reception-side substrate, the intermediate coil 60 having both ends that are electrically released.

Description

半導体装置Semiconductor device
　本発明は、半導体装置に関する。 The present invention relates to a semiconductor device.
　従来より、記憶装置としてＤＲＡＭ（Dynamic Random Access Memory）等の揮発性メモリ（ＲＡＭ）が知られている。ＤＲＡＭには、演算装置（以下、論理チップという）の高性能化やデータ量の増大に耐えうる大容量化が求められている。そこで、メモリ（メモリセルアレイ、メモリチップ）の微細化及びセルの平面的な増設による大容量化が図られてきた。一方で、微細化によるノイズへの惰弱性や、面積の増加等により、この種の大容量化は限界に達してきている。 Conventionally, volatile memory (RAM) such as DRAM (Dynamic Random Access Memory) has been known as a storage device. DRAMs are required to have higher performance of arithmetic units (hereinafter referred to as logic chips) and larger capacities that can withstand an increase in the amount of data. Therefore, the capacity has been increased by miniaturizing the memory (memory cell array, memory chip) and increasing the number of cells in a plane. On the other hand, this kind of large capacity has reached its limit due to the weakness to noise due to miniaturization and the increase in area.
　そこで、昨今では、平面的なメモリを複数積層して３次元化（３Ｄ化）して大容量化を実現する技術が開発されている。また、通信又は給電にコイルを用いる技術が提案されている（例えば、特許文献１及び２参照）。 Therefore, in recent years, a technology has been developed that realizes a large capacity by stacking a plurality of flat memories to make them three-dimensional (3D). Further, a technique using a coil for communication or power supply has been proposed (see, for example, Patent Documents 1 and 2).
特開２０１５－１６２９４８号公報JP 2015-162948 特開２００５－３４８２６４号公報Japanese Unexamined Patent Publication No. 2005-348264
　ところで、通信にコイルを用いる場合、信号強度が強い方が好ましい。特許文献１では、一次コイルから二次コイルに給電する際に、中継コイルを配置することで給電ロスの低下を図っている。しかしながら、特許文献１の中継コイルには、共振により電力を供給するために共振周波数を調整するための機構が採用されている。そのため、特許文献１に記載の技術は、種々の周波数の信号を伝送する非接触通信には適さない。 By the way, when a coil is used for communication, it is preferable that the signal strength is strong. In Patent Document 1, when power is supplied from the primary coil to the secondary coil, the power supply loss is reduced by arranging the relay coil. However, the relay coil of Patent Document 1 employs a mechanism for adjusting the resonance frequency in order to supply electric power by resonance. Therefore, the technique described in Patent Document 1 is not suitable for non-contact communication for transmitting signals of various frequencies.
　また、特許文献２には、同心円上に配置される送信コイル及び受信コイルの対について、同軸上に、順に３対配置した電子回路が開示されている。そして、特許文献２では、１つの送信コイルから他の２つの受信コイルに信号を送信する際に、他の２つの送信コイルの一端を解放することで、他の２つの送信コイルが通信に干渉することを抑制している。しかしながら、特許文献２では、受信信号の強度を増加させることまではできない。 Further, Patent Document 2 discloses an electronic circuit in which three pairs of transmitting coils and receiving coils arranged on concentric circles are arranged coaxially in order. Then, in Patent Document 2, when a signal is transmitted from one transmitting coil to the other two receiving coils, one end of the other two transmitting coils is released, so that the other two transmitting coils interfere with communication. It suppresses doing. However, in Patent Document 2, it is not possible to increase the strength of the received signal.
　本発明は、受信信号の強度を増加させることが可能な半導体装置を提供することを目的とする。 An object of the present invention is to provide a semiconductor device capable of increasing the strength of a received signal.
　本発明は、積層される複数の半導体基板を備える半導体装置であって、一の前記半導体基板である送信側基板に配置される送信用コイルと、前記送信側基板とは別の前記半導体基板である受信側基板に配置され、前記送信用コイルと積層方向で重なる位置に配置される受信用コイルと、前記送信側基板と前記受信側基板との間の少なくとも１つの前記半導体基板である中間基板において、前記送信用コイル及び前記受信用コイルに、積層方向で重なる位置に配置される中間コイルであって、両端が電気的に解放されている中間コイルと、を備える半導体装置に関する。 The present invention is a semiconductor device including a plurality of semiconductor substrates to be laminated, wherein a transmission coil arranged on the transmission side substrate, which is one of the semiconductor substrates, and the semiconductor substrate different from the transmission side substrate are used. An intermediate substrate which is at least one semiconductor substrate between a receiving coil arranged on a receiving side substrate and overlapping with the transmitting coil in a stacking direction and the transmitting side substrate and the receiving side substrate. The present invention relates to a semiconductor device including an intermediate coil arranged at a position where the transmitting coil and the receiving coil overlap in a stacking direction, and both ends of which are electrically open.
　また、前記中間コイルは、前記受信側基板及び前記送信側基板の間の前記半導体基板のうち、前記受信側基板と前記送信側基板との中間点よりも前記受信側基板に近い前記半導体基板のいずれかに配置されるのが好ましい。 Further, the intermediate coil is a semiconductor substrate between the receiving side substrate and the transmitting side substrate, which is closer to the receiving side substrate than the intermediate point between the receiving side substrate and the transmitting side substrate. It is preferably placed in either.
　また、前記中間コイルは、１つの前記中間基板に複数配置されるのが好ましい。 Further, it is preferable that a plurality of the intermediate coils are arranged on one intermediate substrate.
　本発明によれば、受信信号の強度を増加させることが可能な半導体装置を提供することができる。 According to the present invention, it is possible to provide a semiconductor device capable of increasing the strength of a received signal.
本発明の一実施形態に係る半導体装置に積層される半導体基板の平面図である。It is a top view of the semiconductor substrate laminated on the semiconductor device which concerns on one Embodiment of this invention. 一実施形態の半導体装置の断面図を示す。A cross-sectional view of the semiconductor device of one embodiment is shown. 一実施形態の半導体装置の第１実施例を示す。A first embodiment of the semiconductor device of one embodiment is shown. 一実施形態の半導体装置の第２実施例を示す。A second embodiment of the semiconductor device of one embodiment is shown.
　以下、本発明の一実施形態に係る半導体装置１について、図１から図４を参照して説明する。
　半導体装置１は、例えば、積層される複数の半導体基板１０を備える部材である。半導体装置１は、例えば、メモリチップ（ＤＲＡＭチップ）を有するメモリ部材である。半導体装置１は、積層される半導体基板１０の間で非接触な通信を実現する。半導体装置１は、例えば、磁界を用いて通信を実施することで、製造の容易性及び集積度の向上等を図ることができる。以下の実施形態に係る半導体装置１は、非接触通信における通信強度の向上を図るものである。半導体装置１は、図１及び図２に示すように、複数の半導体基板１０と、送信回路２０と、送信用コイル３０と、受信回路４０と、受信用コイル５０と、中間コイル６０と、を備える。 Hereinafter, the semiconductor device 1 according to the embodiment of the present invention will be described with reference to FIGS. 1 to 4.
The semiconductor device 1 is, for example, a member including a plurality of semiconductor substrates 10 to be laminated. The semiconductor device 1 is, for example, a memory member having a memory chip (DRAM chip). The semiconductor device 1 realizes non-contact communication between the laminated semiconductor substrates 10. The semiconductor device 1 can improve the ease of manufacture and the degree of integration by, for example, performing communication using a magnetic field. The semiconductor device 1 according to the following embodiment is intended to improve the communication strength in non-contact communication. As shown in FIGS. 1 and 2, the semiconductor device 1 includes a plurality of semiconductor substrates 10, a transmission circuit 20, a transmission coil 30, a reception circuit 40, a reception coil 50, and an intermediate coil 60. Be prepared.
　半導体基板１０は、例えば、シリコン基板である。半導体基板１０は、一方の面に配置される配線層を備える。本実施形態において、半導体基板１０は、図２に示すように、第１基板１１、第２基板１２、第３基板１３、第４基板１４、及び第５基板１５の５枚設けられる。ここで、第２基板１２及び第３基板１３は、配線層１１２，１１３を互いに対向させて接着される。また、第４基板１４及び第５基板１５は、配線層１１４，１１５を互いに対向させて接着される。そして、第３基板１３及び第４基板１４が配線層１１３，１１４とは逆の面を対向させて接着される。そして、第１基板１１及び第２基板１２が配線層１１１，１１２とは逆の面を対向させて接着される。 The semiconductor substrate 10 is, for example, a silicon substrate. The semiconductor substrate 10 includes a wiring layer arranged on one surface. In the present embodiment, as shown in FIG. 2, five semiconductor substrates 10 are provided: a first substrate 11, a second substrate 12, a third substrate 13, a fourth substrate 14, and a fifth substrate 15. Here, the second substrate 12 and the third substrate 13 are adhered with the wiring layers 112 and 113 facing each other. Further, the fourth substrate 14 and the fifth substrate 15 are adhered with the wiring layers 114 and 115 facing each other. Then, the third substrate 13 and the fourth substrate 14 are adhered so that the surfaces opposite to the wiring layers 113 and 114 face each other. Then, the first substrate 11 and the second substrate 12 are adhered so that the surfaces opposite to the wiring layers 111 and 112 face each other.
　送信用コイル３０は、半導体基板１０に配置される信号送信用のコイルである。送信用コイル３０は、一の半導体基板１０である送信側基板に配置される。本実施形態において、送信用コイル３０は、第１基板１１及び第５基板１５の配線層１１１,１１５に配置される。すなわち、第１基板１１の送信用コイル３０ａ，３０ｃ，３０ｅは、送信側基板となる第１基板１１の配線層１１１に配置される。また、第５基板１５の送信用コイル３０ｂ，３０ｄ，３０ｆは、送信側基板となる第５基板１５の配線層１１５に配置される。なお、第１基板１１の送信用コイル３０ａ，３０ｃ，３０ｅと、第５基板１５の送信用コイル３０ｂ，３０ｄ，３０ｆとは、積層方向Ｄで重ならない位置に配置される。 The transmission coil 30 is a signal transmission coil arranged on the semiconductor substrate 10. The transmission coil 30 is arranged on a transmission-side substrate, which is one semiconductor substrate 10. In the present embodiment, the transmission coil 30 is arranged in the wiring layers 111 and 115 of the first substrate 11 and the fifth substrate 15. That is, the transmission coils 30a, 30c, and 30e of the first substrate 11 are arranged on the wiring layer 111 of the first substrate 11 which is the transmission side substrate. Further, the transmission coils 30b, 30d, and 30f of the fifth substrate 15 are arranged on the wiring layer 115 of the fifth substrate 15 which is the transmission side substrate. The transmission coils 30a, 30c, 30e of the first substrate 11 and the transmission coils 30b, 30d, 30f of the fifth substrate 15 are arranged at positions where they do not overlap in the stacking direction D.
　送信回路２０は、例えば、電子回路である。送信回路２０は、送信用の信号を電気信号として送信コイルに印可する。これにより、送信回路２０は、送信用コイル３０に、送信用の信号に対応する磁束を発生させる。 The transmission circuit 20 is, for example, an electronic circuit. The transmission circuit 20 applies a transmission signal as an electric signal to the transmission coil. As a result, the transmission circuit 20 generates a magnetic flux corresponding to the transmission signal in the transmission coil 30.
　受信用コイル５０は、半導体基板１０に配置される信号受信用のコイルである。受信用コイル５０は、送信側基板とは別の半導体基板１０である受信側基板に配置される。また、受信用コイル５０は、送信用コイル３０と積層方向Ｄで重なる位置に配置される。本実施形態において、受信用コイル５０は、第１基板１１及び第５基板１５の配線層１１１，１１５に配置される。すなわち、第１基板１１の受信用コイル５０ｂ，５０ｄ，５０ｆは、受信側基板となる第１基板１１の配線層１１１に配置される。また、第５基板１５の受信用コイル５０ａ，５０ｃ，５０ｅは、受信側基板となる第５基板１５の配線層１１５に配置される。また、本実施形態において、第５基板１５の受信用コイル５０ａ，５０ｃ，５０ｅは、第１基板１１の送信用コイル３０ａ,３０ｃ,３０ｅと積層方向Ｄで重なる位置に配置される。そして、第１基板１１の受信用コイル５０ｂ，５０ｄ，５０ｆは、第５基板１５の送信用コイル３０ｂ，３０ｄ，３０ｆと積層方向Ｄで重なる位置に配置される。 The receiving coil 50 is a signal receiving coil arranged on the semiconductor substrate 10. The receiving coil 50 is arranged on a receiving side substrate, which is a semiconductor substrate 10 different from the transmitting side substrate. Further, the receiving coil 50 is arranged at a position where it overlaps with the transmitting coil 30 in the stacking direction D. In the present embodiment, the receiving coil 50 is arranged in the wiring layers 111 and 115 of the first substrate 11 and the fifth substrate 15. That is, the receiving coils 50b, 50d, and 50f of the first substrate 11 are arranged on the wiring layer 111 of the first substrate 11 which is the receiving side substrate. Further, the receiving coils 50a, 50c, 50e of the fifth substrate 15 are arranged on the wiring layer 115 of the fifth substrate 15 which is the receiving side substrate. Further, in the present embodiment, the receiving coils 50a, 50c, 50e of the fifth substrate 15 are arranged at positions where they overlap with the transmitting coils 30a, 30c, 30e of the first substrate 11 in the stacking direction D. The receiving coils 50b, 50d, 50f of the first substrate 11 are arranged at positions where they overlap with the transmitting coils 30b, 30d, 30f of the fifth substrate 15 in the stacking direction D.
　受信回路４０は、例えば、電子回路である。受信回路４０は、受信用コイル５０で受信した送信用の信号を受信信号として取得する。 The receiving circuit 40 is, for example, an electronic circuit. The reception circuit 40 acquires a transmission signal received by the reception coil 50 as a reception signal.
　中間コイル６０は、図１に示すように、両端が電気的に解放されているコイルである。中間コイル６０は、送信側基板と受信側基板との間の少なくとも１つの半導体基板１０である中間基板に配置される。中間コイル６０は、中間基板の配線層に配置される。本実施形態において、中間コイル６０は、少なくとも第２基板１２の配線層１１２に配置される。中間コイル６０は、例えば、第２基板１２及び第３基板１３の配線層１１２，１１３に配置される。中間コイル６０は、送信用コイル３０及び受信用コイル５０に、積層方向Ｄで重なる位置に配置される。具体的には、中間コイル６０ｃは、第１基板１１の送信用コイル３０ｃと、第５基板１５の受信用コイル５０ｃと積層方向Ｄで重なる位置に配置される。中間コイル６０ｄは、第５基板１５の送信用コイル３０ｄと、第１基板１１の受信用コイル５０ｄと積層方向Ｄで重なる位置に配置される。また、中間コイル６０ｅは、第１基板１１の送信用コイル３０ｅと、第５基板１５の受信用コイル５０ｅと積層方向Ｄで重なる位置に配置される。また、中間コイル６０ｆは、第５基板１５の送信用コイル３０ｆと、第１基板１１の受信用コイル５０ｆと積層方向Ｄで重なる位置に配置される。本実施形態において、中間コイル６０は、１つの中間基板に複数配置される。４つの中間コイル６０ｃ，６０ｄ，６０ｅ，６０ｆは、例えば、第２基板１２に配置される。 As shown in FIG. 1, the intermediate coil 60 is a coil in which both ends are electrically released. The intermediate coil 60 is arranged on an intermediate substrate, which is at least one semiconductor substrate 10 between the transmitting side substrate and the receiving side substrate. The intermediate coil 60 is arranged in the wiring layer of the intermediate substrate. In the present embodiment, the intermediate coil 60 is arranged at least in the wiring layer 112 of the second substrate 12. The intermediate coil 60 is arranged, for example, in the wiring layers 112 and 113 of the second substrate 12 and the third substrate 13. The intermediate coil 60 is arranged at a position where it overlaps the transmitting coil 30 and the receiving coil 50 in the stacking direction D. Specifically, the intermediate coil 60c is arranged at a position where the transmission coil 30c of the first substrate 11 and the reception coil 50c of the fifth substrate 15 overlap in the stacking direction D. The intermediate coil 60d is arranged at a position where the transmission coil 30d of the fifth substrate 15 and the reception coil 50d of the first substrate 11 overlap in the stacking direction D. Further, the intermediate coil 60e is arranged at a position where the transmission coil 30e of the first substrate 11 and the reception coil 50e of the fifth substrate 15 overlap in the stacking direction D. Further, the intermediate coil 60f is arranged at a position where the transmission coil 30f of the fifth substrate 15 and the reception coil 50f of the first substrate 11 overlap in the stacking direction D. In this embodiment, a plurality of intermediate coils 60 are arranged on one intermediate substrate. The four intermediate coils 60c, 60d, 60e, 60f are arranged on the second substrate 12, for example.
　次に、半導体装置１の動作について説明する。
　送信回路２０は、図１及び図２に示すように、送信用の電気信号を第５基板１５の送信用コイル３０に印可する。送信用コイル３０は、電気信号を磁界に変換する。 Next, the operation of the semiconductor device 1 will be described.
As shown in FIGS. 1 and 2, the transmission circuit 20 applies an electric signal for transmission to the transmission coil 30 of the fifth substrate 15. The transmission coil 30 converts an electric signal into a magnetic field.
　第１基板１１の受信用コイル５０は、第５基板１５の送信用コイル３０によって変換された磁界に基づいて電気信号を生成する。受信回路４０は、第１基板１１の受信用コイル５０によって生成される電気信号を取得することで、信号を受信する。これにより、１つの通信チャネルが形成される。 The receiving coil 50 of the first substrate 11 generates an electric signal based on the magnetic field converted by the transmitting coil 30 of the fifth substrate 15. The receiving circuit 40 receives the signal by acquiring the electric signal generated by the receiving coil 50 of the first substrate 11. As a result, one communication channel is formed.
　ここで、第２基板１２（及び第３基板１３）に配置されている中間コイル６０には、送信信号の送信開始に伴って、自己の寄生容量を充電するだけの過渡的な微小電流が流れる。これにより、中間コイル６０の両端には、送信用コイル３０との距離に応じた受信電圧が発生する。続いて、発生した受信電圧により流れる電流は、閉ループ（両端が解放されていないコイル）の場合と反対方向に変化する。したがって、中間コイル６０は、送信用コイル３０の磁界変化を強める方向の磁界を発生する。その結果、受信用コイル５０の位置における磁界変化は、中間コイル６０がない場合に比べてより大きくなる。すなわち、中間コイル６０がない場合に比べ、受信用コイル５０によって受信される受信信号の電圧値をより大きくすることができる。 Here, in the intermediate coil 60 arranged on the second substrate 12 (and the third substrate 13), a transient minute current sufficient to charge its own parasitic capacitance flows with the start of transmission of the transmission signal. .. As a result, a reception voltage corresponding to the distance from the transmission coil 30 is generated at both ends of the intermediate coil 60. Subsequently, the current flowing due to the generated reception voltage changes in the opposite direction to the case of the closed loop (coil whose ends are not released). Therefore, the intermediate coil 60 generates a magnetic field in a direction that strengthens the change in the magnetic field of the transmission coil 30. As a result, the change in the magnetic field at the position of the receiving coil 50 is larger than that without the intermediate coil 60. That is, the voltage value of the received signal received by the receiving coil 50 can be made larger than that in the case where the intermediate coil 60 is not provided.
（実施例１）
　次に、本実施形態における半導体装置１の実施例１について、図２及び図３を参照して説明する。第５基板に配置される送信用コイル３０から送信される信号について、第１基板に配置される受信用コイル５０で受信した。このとき、送信用コイル３０及び受信用コイル５０を以下のように設定した。
送信用コイル３０：巻き数１５回、直径７０μｍ、線幅１．４μｍ、線間０．３μｍ
受信用コイル５０：巻き数３０回、直径７０μｍ、線幅０．３μｍ、線間０．３μｍ (Example 1)
Next, the first embodiment of the semiconductor device 1 in the present embodiment will be described with reference to FIGS. 2 and 3. The signal transmitted from the transmission coil 30 arranged on the fifth substrate was received by the reception coil 50 arranged on the first substrate. At this time, the transmission coil 30 and the reception coil 50 were set as follows.
Transmission coil 30: 15 turns, diameter 70 μm, line width 1.4 μm, line spacing 0.3 μm
Receiving coil 50: 30 turns, diameter 70 μm, line width 0.3 μm, line spacing 0.3 μm
　そして、送信用コイル３０及び受信用コイル５０の間の距離を４０μｍとした。上記条件において、中間コイル６０無し、第２基板１２に中間コイル６０を配置（１つ）、第２基板１２及び第３基板１３に中間コイル６０を配置（２つ）の３つの態様で受信信号を取得した。中間コイル６０を以下のように設定した。
中間コイル６０ｃ，６０ｄ（第２基板のみ）：巻き数２５回、直径７０μｍ、線幅１．０μｍ、線間０．３μｍ
中間コイル６０ｅ，６０ｆ（第２基板及び第３基板）：巻き数２０回、直径５６μｍ、線幅１．０μｍ、線間０．３μｍ Then, the distance between the transmitting coil 30 and the receiving coil 50 was set to 40 μm. Under the above conditions, the received signal is received in three modes: no intermediate coil 60, the intermediate coil 60 is arranged on the second substrate 12 (1), and the intermediate coil 60 is arranged on the 2nd substrate 12 and the 3rd substrate 13 (2). Was acquired. The intermediate coil 60 was set as follows.
Intermediate coils 60c, 60d (second substrate only): 25 turns, diameter 70 μm, line width 1.0 μm, line spacing 0.3 μm
Intermediate coils 60e, 60f (second substrate and third substrate): 20 turns, diameter 56 μm, line width 1.0 μm, line spacing 0.3 μm
　その結果、図３に示すように、送信用コイル３０の電流が３６０μＡ、５００μＡ、６４０μＡ、７３０μＡのいずれにおいても、中間コイル６０を配置した方が受信用コイル５０の電圧振幅を大きくすることがわかった。また、中間コイル６０を複数配置する方が、より受信用コイル５０の電圧振幅を大きくできることがわかった。なお、図３において受信用コイル５０の電圧波形と共に示される数値はハイ側の振幅／ロー側の振幅で単位はｍＶである。 As a result, as shown in FIG. 3, it was found that the voltage amplitude of the receiving coil 50 was increased by arranging the intermediate coil 60 regardless of whether the current of the transmitting coil 30 was 360 μA, 500 μA, 640 μA, or 730 μA. rice field. Further, it was found that the voltage amplitude of the receiving coil 50 can be made larger by arranging a plurality of intermediate coils 60. In FIG. 3, the numerical value shown together with the voltage waveform of the receiving coil 50 is the amplitude on the high side / the amplitude on the low side, and the unit is mV.
（実施例２）
　次に、本実施形態における半導体装置１の実施例２について、図２及び図４を参照して説明する。第１基板に配置される送信用コイル３０から送信される信号について、第５基板１５に配置される受信用コイル５０で受信した。このとき、送信用コイル３０及び受信用コイル５０を実施例１と同様に設定した。また、送信用コイル３０及び受信用コイル５０の間の距離についても、実施例１と同様に設定した。そして、中間コイル６０についても実施例１と同様に設定した。 (Example 2)
Next, a second embodiment of the semiconductor device 1 in the present embodiment will be described with reference to FIGS. 2 and 4. The signal transmitted from the transmission coil 30 arranged on the first substrate was received by the reception coil 50 arranged on the fifth substrate 15. At this time, the transmission coil 30 and the reception coil 50 were set in the same manner as in the first embodiment. Further, the distance between the transmission coil 30 and the reception coil 50 was also set in the same manner as in the first embodiment. Then, the intermediate coil 60 was also set in the same manner as in the first embodiment.
　その結果、図４に示すように、送信用コイル３０の電流が３６０μＡ、５００μＡ、６４０μＡ、７３０μＡのいずれにおいても、中間コイル６０を配置した方が受信用コイル５０の電圧振幅を大きくすることがわかった。また、中間コイル６０を複数配置する方が、より受信用コイル５０の電圧振幅を大きくできることがわかった。すなわち、実施例２においても実施例１と同様に、受信用コイル５０の電圧振幅を大きくできることがわかった。なお、図４において受信用コイル５０の電圧波形と共に示される数値はハイ側の振幅／ロー側の振幅で単位はｍＶである。 As a result, as shown in FIG. 4, it was found that the voltage amplitude of the receiving coil 50 was increased by arranging the intermediate coil 60 regardless of whether the current of the transmitting coil 30 was 360 μA, 500 μA, 640 μA, or 730 μA. rice field. Further, it was found that the voltage amplitude of the receiving coil 50 can be made larger by arranging a plurality of intermediate coils 60. That is, it was found that the voltage amplitude of the receiving coil 50 can be increased in the second embodiment as in the first embodiment. In FIG. 4, the numerical value shown together with the voltage waveform of the receiving coil 50 is the amplitude on the high side / the amplitude on the low side, and the unit is mV.
　以上のような一実施形態に係る半導体装置１によれば、以下の効果を奏する。
（１）積層される複数の半導体基板１０を備える半導体装置１であって、一の半導体基板１０である送信側基板に配置される送信用コイル３０と、送信側基板とは別の半導体基板１０である受信側基板に配置され、送信用コイル３０と積層方向Ｄで重なる位置に配置される受信用コイル５０と、送信側基板と受信側基板との間の少なくとも１つの半導体基板１０である中間基板において、送信用コイル３０及び受信用コイル５０に、積層方向Ｄで重なる位置に配置される中間コイル６０であって、両端が電気的に解放されている中間コイル６０と、を備える。これにより、送信用コイル３０によって発生される磁界は、中間コイル６０によって信号を強める方向に磁界を発生させる。したがって、受信用コイルは、中間コイル６０がない場合に比べ、中間コイル６０によって強められた磁界を受信することができ、受信信号の強度を大きくすることができる。 According to the semiconductor device 1 according to the above-described embodiment, the following effects are obtained.
(1) A semiconductor device 1 including a plurality of semiconductor substrates 10 to be laminated, wherein a transmission coil 30 arranged on a transmission side substrate, which is one semiconductor substrate 10, and a semiconductor substrate 10 different from the transmission side substrate 10 The intermediate between the receiving coil 50, which is arranged on the receiving side substrate and overlaps the transmitting coil 30 in the stacking direction D, and at least one semiconductor substrate 10 between the transmitting side substrate and the receiving side substrate. The substrate includes an intermediate coil 60 arranged at a position where the transmitting coil 30 and the receiving coil 50 overlap in the stacking direction D, and the intermediate coils 60 having both ends electrically released. As a result, the magnetic field generated by the transmission coil 30 generates a magnetic field in the direction of strengthening the signal by the intermediate coil 60. Therefore, the receiving coil can receive the magnetic field strengthened by the intermediate coil 60 and can increase the strength of the received signal as compared with the case where the intermediate coil 60 is not provided.
（２）中間コイル６０は、１つの中間基板に複数配置される。これにより、１つの中間基板において、１つの送信用コイル３０及び１つの受信用コイル５０で形成される１つの通信チャネルごとに、中間コイル６０を配置することができる。したがって、設計の幅を広げることができ、半導体基板１０のバリエーションを広げることができる。 (2) A plurality of intermediate coils 60 are arranged on one intermediate substrate. Thereby, on one intermediate substrate, the intermediate coil 60 can be arranged for each communication channel formed by one transmission coil 30 and one reception coil 50. Therefore, the range of design can be widened, and the variation of the semiconductor substrate 10 can be widened.
　以上、本発明の半導体装置の好ましい各実施形態につき説明したが、本発明は、上述の実施形態に制限されるものではなく、適宜変更が可能である。 Although the preferred embodiments of the semiconductor device of the present invention have been described above, the present invention is not limited to the above-described embodiments and can be appropriately modified.
　例えば、上記実施形態において、中間コイル６０は、受信側基板及び送信側基板の間の半導体基板１０のうち、受信側基板と送信側基板との中間点よりも受信側基板に近い半導体基板１０のいずれかに配置されてもよい。これにより、中間コイル６０の寄生容量を充電する過渡的な電流の値が、中間コイル６０を送信側基板に近い半導体基板１０に配置するより少なくなるため、この電流の変化によって発生するリンギングノイズを比較的抑制することができる。したがって、通信品質の向上を期待することができる。 For example, in the above embodiment, the intermediate coil 60 is a semiconductor substrate 10 of the semiconductor substrate 10 between the receiving side substrate and the transmitting side substrate, which is closer to the receiving side substrate than the intermediate point between the receiving side substrate and the transmitting side substrate. It may be placed in either. As a result, the value of the transient current that charges the parasitic capacitance of the intermediate coil 60 is smaller than that of arranging the intermediate coil 60 on the semiconductor substrate 10 close to the transmitting side substrate, so that the ringing noise generated by this change in current is eliminated. It can be relatively suppressed. Therefore, improvement in communication quality can be expected.
　また、上記実施形態において、積層方向Ｄにおける中間基板の数は、３枚に限定されない。送信用コイル３０及び受信用コイル５０の間で通信が可能であれば、中間基板の枚数は制限されない。 Further, in the above embodiment, the number of intermediate substrates in the stacking direction D is not limited to three. The number of intermediate substrates is not limited as long as communication is possible between the transmission coil 30 and the reception coil 50.
　また、上記実施形態において、積層方向Ｄにおける中間コイル６０の数を１又は２つとしたが、これに制限されない。中間コイル６０は、３つ以上配置されてもよい。また、同じ中間基板内において、積層方向Ｄで重なる位置に複数の中間コイル６０を配置してもよい。 Further, in the above embodiment, the number of intermediate coils 60 in the stacking direction D is set to 1 or 2, but the number is not limited to this. Three or more intermediate coils 60 may be arranged. Further, a plurality of intermediate coils 60 may be arranged at overlapping positions in the stacking direction D in the same intermediate substrate.
　また、上記実施形態において、図２に示すように、中間コイル６０を設けない通信チャネル、１つ設ける通信チャネル、及び複数設ける通信チャネルが混在するように配置されてもよい。これにより、送信用コイル３０及び受信用コイル５０の通信距離、コスト、送信用コイル３０及び受信用コイル５０の配置可能な径又は巻き数に応じて、半導体装置１を柔軟に構成することができる。 Further, in the above embodiment, as shown in FIG. 2, a communication channel in which the intermediate coil 60 is not provided, a communication channel in which one is provided, and a communication channel in which a plurality of intermediate coils 60 are provided may be arranged so as to coexist. Thereby, the semiconductor device 1 can be flexibly configured according to the communication distance and cost of the transmission coil 30 and the reception coil 50, the diameter or the number of turns of the transmission coil 30 and the reception coil 50 that can be arranged. ..
　１　半導体装置
　１０　半導体基板
　２０　送信回路
　３０　送信用コイル
　４０　受信回路
　５０　受信用コイル
　６０　中間コイル
　Ｄ　積層方向 1 Semiconductor device 10 Semiconductor substrate 20 Transmission circuit 30 Transmission coil 40 Reception circuit 50 Reception coil 60 Intermediate coil D Stacking direction

Claims (3)

  1. 　積層される複数の半導体基板を備える半導体装置であって、
    　一の前記半導体基板である送信側基板に配置される送信用コイルと、
    　前記送信側基板とは別の前記半導体基板である受信側基板に配置され、前記送信用コイルと積層方向で重なる位置に配置される受信用コイルと、
    　前記送信側基板と前記受信側基板との間の少なくとも１つの前記半導体基板である中間基板において、前記送信用コイル及び前記受信用コイルに、積層方向で重なる位置に配置される中間コイルであって、両端が電気的に解放されている中間コイルと、
    を備える半導体装置。     A semiconductor device including a plurality of semiconductor substrates to be laminated.
    A transmission coil arranged on the transmission side substrate, which is the semiconductor substrate, and a transmission coil.
    A receiving coil which is arranged on a receiving side substrate which is a semiconductor substrate different from the transmitting side substrate and is arranged at a position where it overlaps with the transmitting coil in the stacking direction.
    An intermediate coil that is arranged at a position that overlaps the transmitting coil and the receiving coil in the stacking direction in the intermediate substrate that is at least one semiconductor substrate between the transmitting side substrate and the receiving side substrate. , An intermediate coil with both ends electrically open,
    A semiconductor device equipped with.
  2. 　前記中間コイルは、前記受信側基板及び前記送信側基板の間の前記半導体基板のうち、前記受信側基板と前記送信側基板との中間点よりも前記受信側基板に近い前記半導体基板のいずれかに配置される請求項１に記載の半導体装置。 The intermediate coil is any one of the semiconductor substrates between the receiving side substrate and the transmitting side substrate, which is closer to the receiving side substrate than the intermediate point between the receiving side substrate and the transmitting side substrate. The semiconductor device according to claim 1, which is arranged in.
  3. 　前記中間コイルは、１つの前記中間基板に複数配置される請求項１に記載の半導体装置。 The semiconductor device according to claim 1, wherein a plurality of the intermediate coils are arranged on one of the intermediate substrates.
PCT/JP2020/018638 2020-05-08 2020-05-08 Semiconductor device WO2021224982A1 (en)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010109112A (en) * 2008-10-30 2010-05-13 Hitachi Ltd Semiconductor integrated circuit
JP2012169513A (en) * 2011-02-16 2012-09-06 Keio Gijuku Electronic circuit
WO2017010012A1 (en) * 2015-07-16 2017-01-19 株式会社ＰＥＺＹ Ｃｏｍｐｕｔｉｎｇ Semiconductor device
WO2017126018A1 (en) * 2016-01-18 2017-07-27 ウルトラメモリ株式会社 Semiconductor device
WO2017138106A1 (en) * 2016-02-10 2017-08-17 ウルトラメモリ株式会社 Semiconductor device

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010109112A (en) * 2008-10-30 2010-05-13 Hitachi Ltd Semiconductor integrated circuit
JP2012169513A (en) * 2011-02-16 2012-09-06 Keio Gijuku Electronic circuit
WO2017010012A1 (en) * 2015-07-16 2017-01-19 株式会社ＰＥＺＹ Ｃｏｍｐｕｔｉｎｇ Semiconductor device
WO2017126018A1 (en) * 2016-01-18 2017-07-27 ウルトラメモリ株式会社 Semiconductor device
WO2017138106A1 (en) * 2016-02-10 2017-08-17 ウルトラメモリ株式会社 Semiconductor device

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