WO2017126018A1 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
WO2017126018A1
WO2017126018A1 PCT/JP2016/051321 JP2016051321W WO2017126018A1 WO 2017126018 A1 WO2017126018 A1 WO 2017126018A1 JP 2016051321 W JP2016051321 W JP 2016051321W WO 2017126018 A1 WO2017126018 A1 WO 2017126018A1
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Prior art keywords
transmission
reception coil
interposer
memory chips
memory chip
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PCT/JP2016/051321
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French (fr)
Japanese (ja)
Inventor
利次 上田
尚記 小川
隆治 瀧下
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ウルトラメモリ株式会社
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Priority to PCT/JP2016/051321 priority Critical patent/WO2017126018A1/en
Publication of WO2017126018A1 publication Critical patent/WO2017126018A1/en

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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00, e.g. assemblies of rectifier diodes
    • H01L25/04Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00, e.g. assemblies of rectifier diodes
    • H01L25/04Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L51/00
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04BTRANSMISSION
    • H04B5/00Near-field transmission systems, e.g. inductive loop type
    • H04B5/02Near-field transmission systems, e.g. inductive loop type using transceiver

Abstract

This semiconductor device has: a plurality of memory chips provided with a first transmission/reception coil for communication by inductive coupling; and an interposer which is disposed at one end in a stacking direction along which the plurality of memory chips are stacked and provided with, for each of the plurality of memory chips, a second transmission/reception coil coupled with the first transmission/reception coil by inductive coupling. The larger the communication distance between the memory chips and the interposer, the larger the sizes of the first transmission/reception coil and the second transmission/reception coil. The first transmission/reception coil and the second transmission/reception coil may have sizes determined such that an induced electromotive force, which is generated in each of the memory chips by communication between the interposer and the memory chips, has a value within a common prescribed range.

Description

Semiconductor device

The present invention relates to a semiconductor device, and more particularly to a stacked semiconductor device in which semiconductor chips are stacked.

In order to increase the degree of integration while reducing the size of a semiconductor integrated circuit, a method of stacking semiconductor chips in a vertical direction is known.

As a data communication method between stacked semiconductor chips, there are a wired method and a wireless method. Furthermore, the former includes micro-bump technology and through silicon via technology (Through-Silicon-Via, TSV), and the latter includes technology based on capacitive coupling and technology based on inductive coupling (ThruChip Interface, TCI).

In the technology using micro bumps and capacitive coupling, since it is not possible to communicate through the silicon chip, it is a face-to-face lamination in which circuits of chips to be communicated face each other and are bonded. On the other hand, according to TSV and TCI, since communication can be performed through a silicon chip, it can be stacked by a face-to-back method in which chips are stacked in the same direction and bonded together. Therefore, according to TSV or TCI, communication between three or more stacked chips is possible.

In TSV, through holes are formed by providing minute holes in a chip, and the chips are connected by wiring up and down. However, TSV requires a machining technique, so that the manufacturing cost per chip is high, and there are problems such as poor mechanical connection due to stress, heat, and the like.

On the other hand, in TCI, data communication is performed between stacked chips using inductive coupling between a transmission coil and a reception coil (see, for example, Patent Document 1). The inductive coupling interface between the stacked chips is configured by inductive coupling between communication coils and a transmission / reception circuit that processes data communication. The transmission circuit converts transmission data into current, and when the converted transmission current flows through the transmission coil, a reception voltage is induced in the reception coil in accordance with a change in the transmission current. Then, the induced voltage is detected by the receiving circuit, and the transmission data is restored.

The transmission coil and reception coil in TCI are created by metal wiring in the manufacturing process of a semiconductor integrated circuit and do not require machining techniques. For this reason, TCI is superior in cost compared with TSV, and can solve the problem of reliability caused by mechanical connection.

JP 2005-228981 A

Since the magnetic field can penetrate the silicon chip, as described above, according to TCI, communication between three or more stacked chips can be realized. At this time, if the transmission coil and the reception coil are enlarged, the communication distance can be extended. However, when these coils are enlarged, there arises a problem that the number of coils that can be mounted on a chip is reduced.

The present invention has been made in view of this point. That is, an object of the present invention is to provide a semiconductor device that enables interchip communication at a necessary distance while minimizing the decrease in the number of coils that can be mounted on a chip.

Other objects and advantages of the present invention will become apparent from the following description.

(1) According to one embodiment of the present invention, a plurality of memory chips including a first transmission / reception coil for communication by inductive coupling and one end in a stacking direction in which the plurality of memory chips are stacked are inductively coupled. The interposer includes a second transmission / reception coil coupled to the first transmission / reception coil for each of the plurality of memory chips, and the sizes of the first transmission / reception coil and the second transmission / reception coil are different between the memory chip and the interposer. The larger the communication distance is, the larger the semiconductor device is.

(2) In another aspect of the present invention, the first transmission / reception coil and the second transmission / reception coil are within a predetermined range in which the induced electromotive force generated in each of the memory chips by communication between the interposer and the memory chip is common. The present invention relates to the semiconductor device according to (1), which has a size determined to be a value.

(3) Another aspect of the present invention relates to the semiconductor device according to (1), wherein the interposer is a memory chip positioned at one end in the stacking direction among the plurality of stacked memory chips.

(4) In another aspect of the present invention, there are a plurality of memory chips having the same size of the first transmission / reception coil, and all the memory chips including these memory chips are identified differently from each other. An arithmetic circuit for outputting a number and a comparison circuit for comparing the identification number with an address for selecting a memory chip to detect whether or not they match, and a signal line for the address is common to all the memory chips The semiconductor device according to (1).

(5) Another aspect of the invention relates to the semiconductor device according to (4), wherein the interposer generates and outputs an address.

(6) Another aspect of the present invention relates to the semiconductor device according to (1), wherein the size index is a radius of the first transmission / reception coil and the second transmission / reception coil.

(7) According to one embodiment of the present invention, a plurality of memory chips including a first transmission / reception coil for communication by inductive coupling and one end in a stacking direction in which the plurality of memory chips are stacked are inductively coupled. And an interposer provided with a second transmitter / receiver coil coupled to the first transmitter / receiver coil for each of the plurality of memory chips, and the number of turns of the first transmitter / receiver coil and the second transmitter / receiver coil is such that the memory chip and the interposer The larger the communication distance is, the more the semiconductor device is.

(8) According to another aspect of the present invention, the first transmission / reception coil and the second transmission / reception coil are within a predetermined range in which induced electromotive force generated in each of the memory chips in communication between the interposer and the memory chip is common. The present invention relates to the semiconductor device according to (7), wherein the number of turns is determined to be a value.

(9) Another aspect of the present invention relates to the semiconductor device according to (7), wherein the interposer is a memory chip positioned at one end in the stacking direction among the plurality of stacked memory chips.

(10) In another aspect of the present invention, there are a plurality of memory chips having the same size of the first transmission / reception coil, and all the memory chips including these memory chips have different identification numbers, respectively. And a comparison circuit that detects whether or not the identification number matches the address for selecting the memory chip, and the signal line of the address is common to all the memory chips ( The semiconductor device according to 7).

(11) Another aspect of the invention relates to the semiconductor device according to (10), wherein the interposer generates and outputs an address.

According to one aspect of the present invention, since the size of the first transmission / reception coil and the second transmission / reception coil is larger as the communication distance between the memory chip and the interposer is larger, the number of coils that can be mounted on the memory chip is increased. There is provided a semiconductor device that enables chip-to-chip communication at a necessary distance while minimizing the decrease in the above.

According to one aspect of the present invention, since the number of turns of the first transmission / reception coil and the second transmission / reception coil is larger as the communication distance between the memory chip and the interposer is larger, the coil that can be mounted on the memory chip. Provided is a semiconductor device that enables chip-to-chip communication at a necessary distance while minimizing the decrease in the number.

1 is a partial cross-sectional view showing an example of a semiconductor device according to a first embodiment. FIG. 3 is a schematic cross-sectional view of the interposer and the stacked DRAM in the first embodiment. It is an example of the schematic top view of a transmission / reception coil. FIG. 6 is a partial cross-sectional view showing an example of a semiconductor device according to a second embodiment. 6 is a schematic cross-sectional view of a stacked DRAM in a second embodiment. FIG. 6 is a schematic cross-sectional view of an interposer and a stacked DRAM in a third embodiment. FIG. FIG. 10 is a configuration diagram of a chip selection circuit in a third embodiment.

Embodiment 1 FIG.
FIG. 1 is a partial cross-sectional view showing an example of a semiconductor device according to the present embodiment. In the semiconductor device 1 of FIG. 1, a processor 2 is mounted on a substrate 5 via solder balls 6. On the substrate 5, a stacked structure (stacked DRAM 4) in which memory chips of DRAM (Dynamic Random Access Memory) are stacked in a direction perpendicular to the substrate 5 is provided. An interposer 3 is disposed at one end in the stacking direction of the memory chips in the stacked DRAM 4. The processor 2 and each memory chip of the DRAM are electrically connected via the interposer 3. By providing the interposer 3, it is possible to prevent the heat generated by the processor 2 from adversely affecting the operation of the DRAM. For example, the semiconductor device 1 may have a structure in which a plurality of structures including the interposer 3 and the stacked DRAM 4 are arranged around the processor 2. Lamination is realized by fusion bonding. Lamination may use a technique using an adhesive or other techniques such as surface activated room temperature bonding.

FIG. 2 is a schematic cross-sectional view of the interposer 3 and the stacked DRAM 4. In this figure, the stacked DRAM 4 is formed by stacking four DRAM memory chips 11 to 14. Each of the memory chips 11 to 14 has transmission / reception coils C11 to C14, respectively. Further, the interposer 3 has transmission / reception coils C1 to C4 corresponding to the transmission / reception coils C11 to C14 of the memory chips 11 to 14. The transmission / reception coils C11 to C14 are suitable examples of the first transmission / reception coil of the present invention. The transmission / reception coils C1 to C4 are suitable examples of the second transmission / reception coil of the present invention. In the present embodiment, the number of stacked memory chips is not limited to the example shown in FIG.

In this specification, the transmission coil and the reception coil are collectively referred to as a transmission / reception coil. For example, the transmission / reception coil may have a structure in which the center of the transmission coil and the center of the reception coil are coaxially positioned. The number of turns of the transmission / reception coil can be set to an arbitrary value by using a plurality of wiring layers and connection vias. Note that the structure of the transmission / reception coil is not limited to this example. For example, a single transmission coil and a reception coil are formed by one layer of wiring, and these are connected, and the number of turns is reduced by a plurality of wiring layers and connection vias. It may be an increased structure. In an actual semiconductor device, for example, about 1000 transmission / reception coils are arranged per memory chip of a DRAM. The distance between each transmitting / receiving coil can be set to about one half of the size of the transmitting / receiving coil.

Returning to FIG. 1, the interposer 3 receives data sent from the chip of the processor 2 arranged above, and transmits the data to a desired memory chip in the stacked DRAM 4 arranged below. As a result, data is written. On the other hand, the data reading is performed by the interposer 3 receiving data sent from a desired memory chip in the stacked DRAM 4 disposed below and transmitting the data to the chip of the processor 2 disposed above. Done. In the semiconductor device 1, for example, data may be transmitted from the processor 2 to one or more other elements (not shown), and data may be transmitted from any of these elements to the interposer 3. Further, the interposer 3 may transmit the data received from the memory chips 11 to 14 to the processor 2 or may be transmitted to other elements not shown.

FIG. 3 is an example of a schematic plan view of the transmission / reception coil C 1 of the interposer 3 and the transmission / reception coil C 11 of the memory chip 11. Reference numerals in parentheses correspond to the transmission / reception coil C11. The other transmitting / receiving coils C2 to C4 of the interposer 3 and the transmitting / receiving coils C12 to C14 of the other memory chips 12 to 14 can also have the same structure. However, the planar shape of the transmission / reception coil in the present embodiment is not limited to a quadrangle as shown in FIG. 3, and may be another polygonal shape, a circular shape, an elliptical shape, or the like.

In the example of FIG. 3, transmission and reception coils C1, the transmission coil C1 reception coils C1 R outside the T are provided, further, arranged in a double coil with transmitting coil C1 T and receiver coils C1 R is arranged concentrically Yes. The same applies to the transmission / reception coil C11.

The transmission coil C1 T is electrically connected to the transmitter T1. The transmitter T1 is, for example, outputs a current superimposed according to data to be transmitted to the memory chip 11 to the transmitter coil C1 T. Flows transmission current to the transmitter coil C1 T is caused magnetic flux interlinking to the transmitter coil C1 T. Since the generated magnetic flux is also linked to the reception coil C11 R of the transmission / reception coil C11 in the memory chip 11, an induced electromotive force is generated in the reception coil C11 R , and a reception current flows. When the reception current receiving coil C11 R flows, the receiver R11 to be electrically connected to the receiving coil C11 R reproduces the data corresponding to the resulting induced electromotive force. As described above, the data output from the processor 2 is transmitted to the memory chip 11 of the stacked DRAM 4 via the interposer 3.

On the other hand, when reading data from the memory chip 11, the transmitter T11 of the memory chip 11, and outputs a current superimposed in accordance with data to be transmitted to the interposer 3 to the transmitter coil C11 T. When the transmission current to the transmitter coil C11 T flows, resulting magnetic flux interlinked with the transmit coil C11 T. The resulting magnetic flux for interlinked to receiving coil C1 R of the transmission and reception coils C1 in the interposer 3, receives current flow induced electromotive force generated in the receiving coil C1 R. When the reception current receiving coil C1 R flows, receivers R1 electrically connected to the receiving coil C1 R reproduces the data corresponding to the resulting induced electromotive force. As described above, the data output from the memory chip 11 of the stacked DRAM 4 is transmitted to the interposer 3.

Data transmission / reception is performed in the same manner as described above between the transmission / reception coil C2 and the transmission / reception coil 12, between the transmission / reception coil C3 and the transmission / reception coil 13, and between the transmission / reception coil C4 and the transmission / reception coil 14.

In general, the relationship of the equation (1) is established between the data communication distance x, the radius r of the coil, and the number n of turns of the coil. V RX is the received signal strength, r TX is the radius of the transmitting coil, r RX is the radius of the receiving coil, n TX is the number of turns of the transmitting coil, n RX is the number of turns of the receiving coil, and μ 0 is the magnetic permeability of vacuum. , J is an imaginary unit, I TX is a current flowing through the transmission coil, and ω is a frequency.

Figure JPOXMLDOC01-appb-I000001

From equation (1), if the received signal strength (V RX ) and the current (I TX ) flowing through the transmission coil are the same, the larger the coil radius (r TX , r RX ), the more the number of turns of the coil ( The communication distance (x) becomes longer as n TX , n RX ) increases. Here, the radius of the polygonal coil can be defined as the radius of a circle inscribed (or circumscribed) by the coil. For example, in FIG. 3, the radius of the rectangular transmission coil C1 T (C11 T ) can be the radius of a circle indicated by a dotted line.

Here, as an example for comparison, it is assumed that the radius and the number of turns of the transmission / reception coils C1 to C4 of the interposer 3 and the radius and the number of turns of the transmission / reception coils C11 to C14 of the memory chips 11 to 14 are all the same. Furthermore, it is assumed that the communication distance at this time is equal to the communication distance between the interposer 3 and the memory chip 11. In this case, in order to transfer data from the interposer 3 to the memory chip 12, the data is transferred from the interposer 3 to the memory chip 11, and then transferred from the memory chip 11 to the memory chip 12. The same applies to the case where data is transferred to the memory chips 13 and 14, and data is transferred to a desired chip by repeating the transfer to adjacent chips.

In the above comparative example, as the number of stacked memory chips constituting the stacked DRAM 4 increases, the number of data transfers increases and the power required for the transfer increases. If the radius of the coil is increased or the number of turns of the coil is increased, the communication distance can be increased, so that the number of data transfers can be reduced. However, in this case, the total number of coils provided per chip is reduced, causing a problem that the communication speed is reduced.

Therefore, in the present embodiment, the radius of the transmission / reception coil arranged in the interposer and the radius of the transmission / reception coil of the memory chip for transmission / reception are increased as the communication distance between the interposer and the memory chip increases. In this specification, “increasing the radius of the transmitting / receiving coil” means “increasing both the radius of the transmitting coil and the radius of the receiving coil”. Specifically, the radius of the transmission / reception coils C1, C11 having the smallest communication distance is made the smallest, and the radius is gradually increased in the order of the transmission / reception coils C2, C12, the transmission / reception coils C3, C13. The radius of the coils C4 and C14 is maximized. For example, the radius of the transmission / reception coils C1 and C11 can be 50 μm, the radius of the transmission / reception coils C2 and C12 can be 80 μm, the radius of the transmission / reception coils C3 and C13 can be 120 μm, and the radius of the transmission / reception coils C4 and C14 can be 150 μm.

In the present embodiment, the size of the transmission / reception coil disposed in the interposer and the size of the transmission / reception coil of the memory chip to be transmitted / received may be increased as the communication distance between the interposer and the memory chip increases. The size index is not limited to the coil radius. For example, the cross-sectional area of the coil may be used, and if the planar shape of the coil is a polygon, the length of a polygonal piece may be used. Whichever index is used, it can be considered in the same way as the radius.

Further, as shown in FIG. 2, the transmission / reception coil C1 of the interposer 3 is arranged such that the central axis thereof coincides with the transmission / reception coil C11 of the memory chip 11. Similarly, the transmission / reception coil C2 of the interposer 3 is also arranged so that the central axis coincides with the transmission / reception coil C12 of the memory chip 12. Further, the transmission / reception coil C3 of the interposer 3 is arranged so that the central axis thereof coincides with the transmission / reception coil C13 of the memory chip 13. Further, the transmission / reception coil C4 of the interposer 3 is arranged so that the central axis thereof coincides with the transmission / reception coil C14 of the memory chip 14. By doing in this way, between the transmission / reception coil C1 and the transmission / reception coil C11, between the transmission / reception coil C2 and the transmission / reception coil C12, between the transmission / reception coil C3 and the transmission / reception coil C13, between the transmission / reception coil C4 and the transmission / reception coil C14, respectively. Electromagnetic coupling is generated by magnetic flux as indicated by arrows M1 to M4.

In the present embodiment, the radius of each transmitting / receiving coil is substantially equal to the induced electromotive force generated in the transmitting / receiving coils C11 to C14 of each memory chip 11 to 14 when data is transferred from the interposer 3 to each memory chip 11 to 14. Are preferably the same. Specifically, the range of the induced electromotive force allowable in the specification is determined, and the radius of the coil is determined so that the induced electromotive force of each transmitting / receiving coil is within this range. That is, when data is transferred from the interposer 3 to each of the memory chips 11 to 14, the induced electromotive forces generated in the transmission / reception coils C11 to C14 are substantially the same, in other words, within a predetermined range. The radii of the transmitting / receiving coils C1 to C4 and C11 to C14 are determined so that In this way, for example, the threshold value of the on / off operation of the transmission circuit and the reception circuit in each memory chip can be made the same, and these circuits can be connected to a common power source between the memory chips. The power can be supplied by TSV. This is because the memory chips communicate with each other by TCI, so that the length of the via can be minimized, and the power source does not require processing as highly accurate as the signal line.

For example, in FIG. 2, according to the transmission / reception coil having a larger radius than the transmission / reception coils C1 and C11, data communication at a distance away from the distance between the interposer 3 and the memory chip 11 is possible. The distance from the interposer 3 to each of the memory chips 11 to 14 is determined by the specifications of the semiconductor device 1 and the like. In addition, the amplitude of the coil signal gradually attenuates as the distance from the interposer 3 increases. Therefore, for example, in order to be able to transmit data transmitted from the interposer 3 to the memory chip 12, it is necessary that the radii of the transmission / reception coils C2 and C12 be larger than a certain value. On the other hand, since the induced electromotive force increases as the coil radius increases, if the radius of the transmission / reception coil C12 becomes too large, the difference from the induced electromotive force generated in the transmission / reception coil C11 increases. Therefore, there is an optimum radius that allows the data transmitted from the interposer 3 to be transmitted to the memory chip 12 and generates an induced electromotive force equivalent to the induced electromotive force generated in the memory chip 11. The transmission / reception coils C2 and C12 are designed to have such a radius.

The transmission / reception coils C3 and C13 and the transmission / reception coils C4 and C14 are also designed in the same manner as described above.

According to the present embodiment, the size of the transmission / reception coil arranged in the interposer and the size of the transmission / reception coil of the memory chip to be transmitted / received are increased as the communication distance between the interposer and the memory chip increases. Since the number of data transfers can be reduced while minimizing the total number of coils provided per chip, the power required for the transfer can be reduced. According to the configuration of the present embodiment, a large number of transmission / reception coils can be efficiently arranged on an interposer or a memory chip. Further, the size of each transmission / reception coil is set so that the induced electromotive force generated in the transmission / reception coil of each memory chip is substantially the same when data is transferred from the interposer to each memory chip. The threshold values of the ON / OFF operations of the transmission circuit and the reception circuit can be made the same, and these circuits can be connected to a common power source between the memory chips.

In this embodiment, instead of the size of the transmission / reception coil, the number of turns of the transmission / reception coil arranged in the interposer and the number of turns of the transmission / reception coil of the memory chip to be transmitted / received are determined by the communication distance between the interposer and the memory chip. You may increase as it grows larger. In this case, the number of turns of each transmission / reception coil is preferably set so that the induced electromotive force generated in the transmission / reception coil of each memory chip is substantially the same when data is transferred from the interposer to each memory chip.

For example, an interposer is stacked on the first memory chip for a stacked DRAM in which a first memory chip, a second memory chip, a third memory chip, and a fourth memory chip are stacked in this order. Suppose that At this time, the data transmitted from the interposer can be transmitted to the second memory chip, and there is an optimum number of turns that generates an induced electromotive force equivalent to the induced electromotive force generated in the first memory chip. The number of turns of the transmission / reception coil of the second memory chip and the number of turns of the transmission / reception coil of the interposer transmitting / receiving to / from the second memory chip are designed so as to be the number of turns. The number of turns of the transmission / reception coil of the third memory chip and the transmission / reception coil of the interposer to / from the third memory chip, and the number of turns of the transmission / reception coil of the fourth memory chip and the transmission / reception coil of the interposer to / from the fourth memory chip are designed in the same manner. Is done. Note that the transmission / reception coils of the first memory chip, the second memory chip, the third memory chip, and the fourth memory chip are suitable examples of the first transmission / reception coil of the present invention. Moreover, each transmission / reception coil of an interposer is a suitable example of the 2nd transmission / reception coil of this invention.

Since the number of data transfers can be reduced also by changing the number of turns as described above, the power required for the transfer can be reduced. Further, by setting the number of turns of each transmission / reception coil so that the induced electromotive force generated in the transmission / reception coil of each memory chip is substantially the same when data is transferred from the interposer to each memory chip. The threshold values of the ON / OFF operations of the transmission circuit and the reception circuit in each memory chip can be made the same, and these circuits can be connected to a common power source among the memory chips.

Furthermore, in this embodiment, both the size and the number of turns of the transmission / reception coil may be adjusted. Also in this case, when the data is transferred from the interposer to each memory chip, the induced electromotive force generated in the transmission / reception coil of each memory chip is substantially the same as the radius and the number of turns of the transmission / reception coil of the interposer and each memory chip. Such a value is preferable. With this configuration, the same effect as described above can be obtained.

Embodiment 2. FIG.
FIG. 4 is a partial cross-sectional view showing an example of the semiconductor device according to the present embodiment. In the semiconductor device 101 of FIG. 4, a processor 102 is mounted on a substrate 105 via solder balls 106, and a DRAM (Dynamic Random Access Memory) memory chip is stacked in a direction perpendicular to the substrate 105. A stacked DRAM 104 is provided.

FIG. 5 is a schematic cross-sectional view of the stacked DRAM 104. In this figure, the same reference numerals as those in FIG. 2 indicate the same structure. The stacked DRAM 104 includes four memory chips 11 to 14 stacked below the memory chip 111, but the number of chips stacked below the memory chip 111 is not limited to this.

The memory chip 111 in the uppermost layer of the stacked DRAM 104 has both an original function as a memory chip and a function as an interposer. According to this structure, since it is not necessary to provide the interposer separately from the stacked DRAM, the thickness of the entire stacked body provided on the substrate 105 can be reduced.

In order for the memory chip 111 to function as an interposer, the memory chip 111 has transmission / reception coils C1 to C4 corresponding to the transmission / reception coils C11 to C14 of the memory chips 11 to 14 of each DRAM. Here, the transmission / reception coils C11 to C14 are suitable examples of the first transmission / reception coil of the present invention. The transmission / reception coils C1 to C4 are suitable examples of the second transmission / reception coil of the present invention.

The radius of the transmission / reception coils C1 to C4 arranged in the memory chip 111 and the radius of the transmission / reception coils C11 to C14 of the memory chips 11 to 14 that transmit / receive to / from the memory chip 111 are larger as the communication distance between the memory chips increases. According to such a configuration, since the number of data transfers can be reduced while minimizing the total number of coils provided per chip, it is possible to reduce the power required for the transfer. .

The radius of the transmission / reception coils (C1 to C4, C11 to C14) is such that when the data is transferred from the memory chip 111 to each of the memory chips 11 to 14, the induced electromotive force generated in the transmission / reception coils C11 to C14 is substantially between the coils. Are preferably set to the same value. That is, it is preferable that the radius of the transmitting / receiving coils (C1 to C4, C11 to C14) is determined so that the induced electromotive force becomes a value within a predetermined range between the coils.

By setting the radius of the transmission / reception coil so that the induced electromotive force generated in each memory chip has a value within a common predetermined range, for example, the threshold value of the ON / OFF operation of the transmission circuit and the reception circuit in each memory chip is the same. In addition, these circuits can be connected to a common power source among the memory chips. The power can be supplied by TSV. This is because the memory chips communicate with each other by TCI, so that the length of the via can be minimized, and the power source does not require processing as highly accurate as the signal line.

In addition, the planar shape of the transmission / reception coil can be a polygon such as a quadrangle, a circle, or an ellipse. In the case of a polygon, the radius of the coil can be defined as the radius of a circle that is inscribed (or circumscribed) with the coil, as in the first embodiment.

Further, in the present embodiment, the size of the transmission / reception coils C1 to C4 arranged in the memory chip 111 and the size of the transmission / reception coils C11 to C14 of the memory chips 11 to 14 that transmit / receive to / from the memory chip 111 are determined between the memory chips. The larger the communication distance, the larger the size, and the size index is not limited to the coil radius. For example, the cross-sectional area of the coil may be used, and if the planar shape of the coil is a polygon, the length of a polygonal piece may be used.

Furthermore, in this embodiment, the number of turns of the transmission / reception coil arranged in the memory chip functioning as the interposer and the number of turns of the transmission / reception coil of the memory chip to be transmitted / received are increased as the communication distance between the chips increases. Also good. In this case, the number of turns of each transmission / reception coil is preferably set so that the induced electromotive force generated in the transmission / reception coil of each memory chip is substantially the same when data is transferred to each memory chip.

For example, in a stacked DRAM in which a first memory chip, a second memory chip, a third memory chip, a fourth memory chip, and a fifth memory chip are stacked in this order, the uppermost first memory Assume that the chip also functions as an interposer. At this time, there is an optimal number of turns that enables transmission of data transmitted from the first memory chip to the third memory chip and generates an induced electromotive force equivalent to the induced electromotive force generated in the second memory chip. Therefore, the number of turns of the transmission / reception coil of the third memory chip and the number of turns of the transmission / reception coil of the first memory chip to be transmitted / received to / from the third memory chip are designed so that the number of turns becomes such. The number of turns of the transmission / reception coil of the fourth memory chip and the transmission / reception coil of the first memory chip to be transmitted / received thereto, and the number of turns of the transmission / reception coil of the first memory chip to / from the transmission / reception coil of the fifth memory chip. Is designed in the same manner. The transmission / reception coils of the second memory chip, the third memory chip, the fourth memory chip, and the fifth memory chip are suitable examples of the first transmission / reception coil of the present invention. Each transmission / reception coil of the first memory chip is a suitable example of the second transmission / reception coil of the present invention.

Also with the above configuration, a large number of transmission / reception coils can be efficiently arranged on the memory chip. In addition, since the number of times of data transfer can be reduced, the power required for the transfer can be reduced. Further, by setting the number of turns of each transmission / reception coil to be substantially the same as the induced electromotive force generated in the transmission / reception coil of each memory chip, the threshold value of the ON / OFF operation of the transmission circuit and reception circuit in each memory chip These circuits can be connected to a common power source among the memory chips.

Furthermore, in this embodiment, both the radius and the number of turns of the transmission / reception coil may be adjusted. For example, in FIG. 5, the radius and the number of turns of each of the transmission / reception coils (C1 to C4, C11 to C14) are the same as those of the memory chips 11 to 14 when data is transferred from the memory chip 111 to the memory chips 11 to 14. The induced electromotive force generated in the transmission / reception coils C11 to C14 is set to a value that is substantially the same. In this case, the same effect as described above can be obtained.

Embodiment 3 FIG.
The semiconductor device of this embodiment can have a structure similar to that of FIG. 1 described in Embodiment 1. That is, a processor is mounted on the substrate via solder balls. On the substrate, a stacked structure (stacked DRAM) in which memory chips of DRAM (Dynamic Random Access Memory) are stacked in a direction perpendicular to the substrate is provided. An interposer is disposed at one end in the stacking direction of the memory chips in the stacked DRAM. The processor and the DRAM are electrically connected via an interposer.

FIG. 6 is a schematic cross-sectional view of the interposer 20 and the memory chips 21 to 28. In this figure, the stacked DRAM 204 is composed of eight DRAM memory chips 21 to 28, but the number of stacked memory chips is not limited to this.

In FIG. 6, the interposer 20 has transmission / reception coils C21 to C24 corresponding to the transmission / reception coils C221 to C228 of the memory chips 21 to 28 of the respective DRAMs. The transmission / reception coils C221 to C228 are a suitable example of the first transmission / reception coil of the present invention. The transmission / reception coils C21 to C24 are a suitable example of the second transmission / reception coil of the present invention.

The transmission / reception coil C21 of the interposer 20 is arranged so that its central axis coincides with the central axes of the transmission / reception coil C221 of the memory chip 21 and the transmission / reception coil C222 of the memory chip 22.

Similarly, the central axis of the transmission / reception coil C22 of the interposer 20 coincides with the central axis of the transmission / reception coil C223 of the memory chip 23 and the transmission / reception coil C224 of the memory chip 24. The central axis of the transmission / reception coil C23 of the interposer 20 coincides with the central axis of the transmission / reception coil C225 of the memory chip 25 and the transmission / reception coil C226 of the memory chip 26. Further, the central axis of the transmission / reception coil C24 of the interposer 20 coincides with the central axes of the transmission / reception coil C227 of the memory chip 27 and the transmission / reception coil C228 of the memory chip 28.

By arranging each transmission / reception coil as described above, between the transmission / reception coil C21 and the transmission / reception coil C221, between the transmission / reception coil C21 and the transmission / reception coil C222, between the transmission / reception coil C22 and the transmission / reception coil C223, and between the transmission / reception coil C22 and the transmission / reception coil. 6 between C224, between transmission / reception coil C23 and transmission / reception coil C225, between transmission / reception coil C23 and transmission / reception coil C226, between transmission / reception coil C24 and transmission / reception coil C227, and between transmission / reception coil C24 and transmission / reception coil C228, respectively. Electromagnetic coupling can be generated by the magnetic fluxes M21 to M28 indicated by arrows.

The interposer 20 receives data sent from the processor chip and transmits the data to a desired memory chip. As a result, data is written. On the other hand, data reading is performed by the interposer 20 receiving data sent from a desired memory chip and transmitting the data to the processor chip. Note that data may be transmitted from the processor to one or more other elements, and the data may be transmitted from any of these elements to the interposer. Further, the interposer may transmit data received from the memory chip to the processor, or may transmit the data to another element.

Also in the present embodiment, as in the first embodiment, the communication distance between the interposer and the memory chip is increased by setting the radius of the transmission / reception coil arranged in the interposer and the radius of the transmission / reception coil of the memory chip to be transmitted / received. Make it bigger. Further, in the present embodiment, there are a plurality of memory chips having the same radius of the transmission / reception coil. These memory chips have the same capacity and configuration.

In FIG. 6, the radii of the transmission / reception coils C21, C221, C222 are all the same, and the value is the smallest compared to other transmission / reception coils. The radius of the transmission / reception coils C22, C223, C224 is the next largest value, and the radius of the transmission / reception coils C23, C225, C226 is the next largest value. The radius values of the transmission / reception coils C24, C227, and C228 are the maximum. For example, the radius of the transmitting / receiving coils C21, C221, C222 is 50 μm, the radius of the transmitting / receiving coils C22, C223, C224 is 80 μm, the radius of the transmitting / receiving coils C23, C225, C226 is 120 μm, and the radius of the transmitting / receiving coils C24, C227, C228 is 150 μm. can do.

In this embodiment, a specific memory chip is selected from a plurality of memory chips having transmission / reception coils having the same radius, and communication is performed with the interposer 20. Therefore, each of the memory chips 21 to 28 includes chip selection circuits 31 to 38 as shown in FIG. 7 in addition to the memory circuit.

As shown in FIG. 7, the chip selection circuits 31 to 38 are connected to each other, and each generates an identification number S1 assigned to the corresponding memory chip. The chip selection circuits 31 to 38 compare the chip selection address S2 input from the outside via the interposer 20 via the common signal line 60 with the chip identification number S1 and compare the chip selection signal S3. Is output. The interposer 20 may have a function of generating and outputting the address S2.

The chip selection circuits 31 to 38 output to the memory chips 21 to 28 an arithmetic circuit that outputs a different identification number S1, respectively, and comparison circuits 39 to 39 that compare the identification number S1 with the address S2 and output a chip selection signal S3. 46. In FIG. 7, the arithmetic circuits are 3-bit increment circuits 47 to 54 for performing an increment operation for adding 1 to an input value.

In the chip selection circuit 31, all three bits α1, α2, and α3 constituting the identification number SN are connected to the ground. Therefore, 0 is input to the increment circuit 47, and 0 is given as the identification number S1 of the memory chip 21. Since the value obtained by adding 1 to 0 is input from the increment circuit 47 to the chip selection circuit 32, the identification number of the memory chip 22 is 1. 1 is input to the increment circuit 48, and a number obtained by adding 1, that is, 2 is output. Hereinafter, similarly, identification numbers 2 to 7 are assigned to the memory chips 23 to 28, respectively.

Increment circuits 47 to 54 have three 1-bit increment circuits for performing a 3-bit increment operation. The 3 bits α1, α2, and α3 constituting the chip identification number are input to each 1-bit increment circuit, and 3 bits β1, β2, and β3 are output from each 1-bit increment circuit.

The comparison circuit 33 has three EXOR circuits and one AND circuit. One of the EXOR circuits receives bit α1 of identification number S1 and bit β1 of address S2. The other one of the EXOR circuits receives bit α2 of identification number S1 and bit β2 of address S2. The remaining one of the EXOR circuits receives bit α3 of identification number S1 and bit β3 of address S2. Each EXOR circuit outputs 0 when the input bits do not match, and outputs 1 when the bits match. Output values from the three EXOR circuits are input to the AND circuit. When the coincidence of all three EXOR circuits is detected, the AND circuit outputs 1 and the chip selection signal S3 becomes high. On the other hand, when a mismatch is detected in any of the three EXOR circuits, the AND circuit outputs 0 and the chip selection signal S3 becomes low.

According to the above configuration, even if there are a plurality of memory chips having transmission / reception coils with the same radius, it is possible to select a desired memory chip and perform data communication with the interposer. Note that the chip selection circuit is not limited to the configuration shown in FIG. 7, and may be another known configuration as long as a specific memory chip can be selected from memory chips having the same capacity and configuration.

According to the present embodiment, the radius of the transmission / reception coil arranged in the interposer and the radius of the transmission / reception coil of the memory chip that transmits and receives this are increased as the communication distance between the interposer and the memory chip increases. A reduction in the total number of coils provided per chip can be minimized, and a large number of transmission / reception coils can be efficiently arranged on the memory chip. According to this configuration, since the number of data transfers can be reduced, it is possible to reduce the power required for the transfer. Moreover, since the same radius is given to the transmission / reception coils of a plurality of memory chips, there is no need to provide transmission / reception coils having different radii for each memory chip. Therefore, switching between a product in which four memory chips of DRAM are stacked and a product in which eight memory chips are stacked is facilitated, and the manufacturing process of the semiconductor device can be simplified.

The radius of each transmitting / receiving coil (C21 to C24, C221 to C228) is an induced electromotive force generated in the transmitting / receiving coils C221 to C228 of each memory chip 21 to 28 when data is transferred from the interposer 20 to each memory chip 21 to 28. Are preferably substantially the same. Specifically, the range of the induced electromotive force allowable in the specification is determined, and the radius of the coil is determined so that the induced electromotive force of each transmitting / receiving coil is within this range.

More specifically, when data is transferred from the interposer 20 to the memory chips 21 to 28, the induced electromotive forces generated in the transmission / reception coils C221 to C228 are substantially the same, in other words, predetermined. The radii of the transmission / reception coils C21 to C24 and C221 to C228 are determined so that the values are within the predetermined range. In this way, for example, the threshold value of the on / off operation of the transmission circuit and the reception circuit in each memory chip can be made the same, and these circuits can be connected to a common power source between the memory chips. The power can be supplied by TSV. This is because the memory chips communicate with each other by TCI, so that the length of the via can be minimized, and the power source does not require processing as highly accurate as the signal line.

In addition, the planar shape of the transmission / reception coil can be a polygon such as a quadrangle, a circle, or an ellipse. In the case of a polygon, the radius of the coil can be defined as the radius of a circle that is inscribed (or circumscribed) with the coil, as in the first embodiment.

Further, in the present embodiment, the sizes of the transmission / reception coils C21 to C24 arranged in the interposer 20 and the sizes of the transmission / reception coils C221 to C228 of the memory chips 21 to 28 that transmit / receive to / from the interposer 20 are determined by the interposer 20 and the memory chip 21. The larger the communication distance between ˜28, the larger the distance, and the size index is not limited to the coil radius. For example, the cross-sectional area of the coil may be used, and if the planar shape of the coil is a polygon, the length of a polygonal piece may be used.

In the present embodiment, the number of turns of the transmission / reception coil arranged in the interposer and the number of turns of the transmission / reception coil of the memory chip to be transmitted / received may be increased as the communication distance between the interposer and the memory chip increases. In this case, the number of turns of each transmission / reception coil is preferably set so that the induced electromotive force generated in the transmission / reception coil of each memory chip is substantially the same when data is transferred from the interposer to each memory chip.

By changing the number of turns of the transmission / reception coil, it is possible to increase the communication distance and reduce the number of data transfers, so that it is possible to reduce the power required for the transfer. Further, by setting the number of turns of each transmission / reception coil to be substantially the same as the induced electromotive force generated in the transmission / reception coil of each memory chip, the threshold value of the ON / OFF operation of the transmission circuit and reception circuit in each memory chip These circuits can be connected to a common power source among the memory chips.

Furthermore, in this embodiment, both the radius and the number of turns of the transmission / reception coil may be adjusted. For example, in FIG. 6, the radius and the number of turns of each transmission / reception coil (C21 to C24, C221 to C228) are the same as the transmission / reception of each memory chip 21 to 28 when data is transferred from the interposer 20 to each memory chip 21 to 28. The values are such that the induced electromotive forces generated in the coils C221 to C228 are substantially the same. In this case, the same effect as described above can be obtained.

The present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention.

Further, in each of the above embodiments, description of parts that are not directly required for the description of the present invention, such as a device configuration and a control method, is omitted, but a device configuration and a control method required for the semiconductor device are appropriately selected. Needless to say, it can be used. In addition, all semiconductor devices that include the elements of the present invention and whose design can be changed as appropriate by those skilled in the art are included in the scope of the present invention.

DESCRIPTION OF SYMBOLS 1,101 Semiconductor device 2,102 Processor 3,20 Interposer 4,104,204 Stacked DRAM
5,105 Substrate 6,106 Solder ball 11-14, 21-28 Memory chip

Claims (11)

  1. A plurality of memory chips including a first transmission / reception coil for communication by inductive coupling;
    An interposer that is disposed at one end in the stacking direction in which the plurality of memory chips are stacked and includes a second transmission / reception coil coupled to the first transmission / reception coil by inductive coupling for each of the plurality of memory chips. ,
    The size of the first transmission / reception coil and the second transmission / reception coil is a semiconductor device having a larger communication distance between the memory chip and the interposer.
  2. The first transmission / reception coil and the second transmission / reception coil are determined so that the induced electromotive force generated in each of the memory chips by communication between the interposer and the memory chip is a value within a predetermined range. The semiconductor device according to claim 1, wherein the semiconductor device has a predetermined size.
  3. 2. The semiconductor device according to claim 1, wherein the interposer is a memory chip positioned at one end in the stacking direction among the plurality of stacked memory chips.
  4. There are a plurality of memory chips having the same size of the first transmission / reception coil, and all the memory chips including these memory chips each have an arithmetic circuit that outputs a different identification number; 2. The semiconductor according to claim 1, further comprising: a comparison circuit that detects whether or not the identification number matches with an address for selecting a memory chip, and the signal line of the address is common to all the memory chips. apparatus.
  5. The semiconductor device according to claim 4, wherein the interposer generates and outputs the address.
  6. 2. The semiconductor device according to claim 1, wherein the size index is a radius of the first transmission / reception coil and the second transmission / reception coil.
  7. A plurality of memory chips including a first transmission / reception coil for communication by inductive coupling;
    An interposer that is disposed at one end in the stacking direction in which the plurality of memory chips are stacked and includes a second transmission / reception coil coupled to the first transmission / reception coil by inductive coupling for each of the plurality of memory chips. ,
    The number of turns of the first transmission / reception coil and the second transmission / reception coil increases as the communication distance between the memory chip and the interposer increases.
  8. The first transmission / reception coil and the second transmission / reception coil are determined so that the induced electromotive force generated in each of the memory chips by communication between the interposer and the memory chip is a value within a predetermined range. The semiconductor device according to claim 7, wherein the number of turns is set.
  9. The semiconductor device according to claim 7, wherein the interposer is a memory chip located at one end in a stacking direction among the plurality of stacked memory chips.
  10. There are a plurality of memory chips having the same size of the first transmission / reception coil, and all the memory chips including these memory chips each have an arithmetic circuit that outputs a different identification number; 8. The semiconductor device according to claim 7, further comprising a comparison circuit that detects whether the identification number matches with an address for selecting a memory chip, and the signal line of the address is common to all the memory chips. apparatus.
  11. The semiconductor device according to claim 10, wherein the interposer generates and outputs the address.
PCT/JP2016/051321 2016-01-18 2016-01-18 Semiconductor device WO2017126018A1 (en)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2007029435A1 (en) * 2005-09-02 2007-03-15 Nec Corporation Transmission method, interface circuit, semiconductor device, semiconductor package, semiconductor module and memory module
JP2009026792A (en) * 2007-07-17 2009-02-05 Hitachi Ltd Semiconductor device
JP2011081883A (en) * 2009-10-09 2011-04-21 Elpida Memory Inc Semiconductor device, and information processing system including the same
JP2011086738A (en) * 2009-10-15 2011-04-28 Keio Gijuku Laminated semiconductor integrated circuit device
JP2011233842A (en) * 2010-04-30 2011-11-17 Toshiba Corp Nonvolatile semiconductor storage device

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2007029435A1 (en) * 2005-09-02 2007-03-15 Nec Corporation Transmission method, interface circuit, semiconductor device, semiconductor package, semiconductor module and memory module
JP2009026792A (en) * 2007-07-17 2009-02-05 Hitachi Ltd Semiconductor device
JP2011081883A (en) * 2009-10-09 2011-04-21 Elpida Memory Inc Semiconductor device, and information processing system including the same
JP2011086738A (en) * 2009-10-15 2011-04-28 Keio Gijuku Laminated semiconductor integrated circuit device
JP2011233842A (en) * 2010-04-30 2011-11-17 Toshiba Corp Nonvolatile semiconductor storage device

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