WO2021217482A1 - 一种瞬态电压抑制保护器件、制作工艺及电子产品 - Google Patents

一种瞬态电压抑制保护器件、制作工艺及电子产品 Download PDF

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WO2021217482A1
WO2021217482A1 PCT/CN2020/087729 CN2020087729W WO2021217482A1 WO 2021217482 A1 WO2021217482 A1 WO 2021217482A1 CN 2020087729 W CN2020087729 W CN 2020087729W WO 2021217482 A1 WO2021217482 A1 WO 2021217482A1
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well
type
protection device
substrate
transient voltage
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PCT/CN2020/087729
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English (en)
French (fr)
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张富生
许成宗
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上海韦尔半导体股份有限公司
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Priority to US17/424,003 priority Critical patent/US11990505B2/en
Priority to EP20911322.4A priority patent/EP3933919A4/en
Publication of WO2021217482A1 publication Critical patent/WO2021217482A1/zh

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    • H—ELECTRICITY
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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0259—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements
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    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
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    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
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    • H01L29/0642—Isolation within the component, i.e. internal isolation
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    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1058—Channel region of field-effect devices of field-effect transistors with PN junction gate
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66833—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a charge trapping gate insulator, e.g. MNOS transistors
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    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/07—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common
    • H01L27/0744—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common without components of the field effect type
    • H01L27/075—Bipolar transistors in combination with diodes, or capacitors, or resistors, e.g. lateral bipolar transistor, and vertical bipolar transistor and resistor
    • H01L27/0755—Vertical bipolar transistor in combination with diodes, or capacitors, or resistors
    • H01L27/0772—Vertical bipolar transistor in combination with resistors only

Definitions

  • the embodiment of the present invention relates to the technical field of integrated circuits, in particular to a transient voltage suppression protection device, a manufacturing process and an electronic product.
  • TVS The suppression protection device
  • One purpose of the embodiments provided by the present invention is to overcome the above-mentioned problems or to at least partially solve or alleviate the above-mentioned problems.
  • Another object of the embodiments provided by the present invention is to provide a transient voltage suppression protection device, a manufacturing process, and an electronic product, which can trigger the opening of the protection function at a lower voltage, and the device capacitance is small, and the manufacturing process is simple.
  • an embodiment of the present invention discloses a transient voltage suppression protection device, including a substrate, a first well, a second well, a first injection region and a second injection region;
  • the first well and the second well are sequentially arranged on the substrate at intervals from left to right, and the first well and the second well have the same doping type and are respectively opposite to the doping type of the substrate ,
  • the first well and the second well are respectively provided with a first implantation region and a second implantation region with opposite doping types;
  • the substrate serves as a common collector
  • the first well and the second well serve as bases respectively
  • the first injection region and the second injection region are respectively led out as emitters through metal connections.
  • the junction depth of the pn junction formed between the first well and the second well and the substrate is the same, and the first implantation region and the second implantation region are respectively the same as those of the pn junction.
  • the junction depth of the pn junction formed between the first well and the second well is the same.
  • the doping concentration of the first well and the second well are the same, and the doping concentration of the first implantation region and the second implantation region are the same.
  • the first implantation region and the second implantation region are respectively arranged at the central positions of the first well and the second well.
  • the separation distance between the first well and the second well is 5-20um.
  • the resistivity of the substrate as a collector is 30-1500 ⁇ cm.
  • the embodiment of the present invention provides a transient voltage suppression protection device, by forming a first well and a second well spaced from left to right on a substrate, wherein the first well and The second well has the same doping type and is opposite to the doping type of the substrate.
  • the first well and the second well are respectively provided with a first implantation region and a second implantation region with opposite doping types.
  • the first well and the second well share a substrate as a common collector, so that the semiconductor punch-through characteristics can be used to solve the problem that the unidirectional cut-off characteristics of the high-resistance substrate triode cause the device to be unable to be used normally.
  • the protection provided by the embodiment of the present invention is connected in series with two open base transistors sharing the collector, which can trigger the opening protection at a lower voltage, which can halve the device capacitance, obtain a smaller capacitance, and have higher anti-surge and static electricity capabilities.
  • embodiments of the present invention also provide a transient voltage suppression protection device, including a substrate, an epitaxial layer, a first well, a second well, a first injection region and a second injection region;
  • the epitaxial layer is disposed on the substrate, the first well and the second well are sequentially arranged on the epitaxial layer at intervals from left to right, and the first well and the second well have the same doping type, And respectively opposite to the doping type of the epitaxial layer, the first well and the second well are respectively provided with a first implantation region and a second implantation region with opposite doping types;
  • the epitaxial layer serves as a common collector, the first well and the second well respectively serve as bases, and the first injection region and the second injection region are respectively led out as emitters through metal connections.
  • the junction depth of the pn junction formed between the first well and the second well is the same as that of the epitaxial layer, and the first implantation region and the second implantation region are respectively the same as those of the pn junction.
  • the junction depth of the pn junction formed between the first well and the second well is the same.
  • the doping concentration of the first well and the second well are the same, and the doping concentration of the first implantation region and the second implantation region are the same.
  • the doping concentration of the epitaxial layer is less than that of the substrate.
  • the doping types of the epitaxial layer and the substrate are the same or different.
  • the first implantation region and the second implantation region are respectively arranged at the central positions of the first well and the second well.
  • the separation distance between the first well and the second well is 5-20um.
  • the resistivity of the epitaxial layer as a collector is 30-1500 ⁇ cm.
  • the embodiment of the present invention provides a transient voltage suppression protection device, by forming a first well and a second well spaced from left to right on an epitaxial layer, wherein the first well and The second well has the same doping type and is opposite to the doping type of the epitaxial layer.
  • the first well and the second well are respectively provided with a first implantation region and a second implantation region with opposite doping types.
  • the first well and the second well share an epitaxial layer as a common collector, so that the semiconductor punch-through characteristics can be used to solve the problem that the unidirectional cut-off characteristics of the high-resistance substrate triode cause the device to be unable to be used normally.
  • the protection provided by the embodiment of the present invention is connected in series with two open base transistors sharing the collector, which can trigger the opening protection at a lower voltage, which can halve the device capacitance, obtain a smaller capacitance, and have higher anti-surge and static electricity capabilities.
  • embodiments of the present invention also provide a manufacturing process of a transient voltage suppression protection device, including:
  • the substrate serves as a common collector, the first well and the second well serve as bases respectively, and the first injection region and the second injection region are respectively led out as emitters through metal connections;
  • An epitaxial layer with the same doping type as the substrate is formed on the substrate;
  • the epitaxial layer serves as a common collector, the first well and the second well respectively serve as bases, and the first injection region and the second injection region are respectively led out as emitters through metal connections.
  • the beneficial effects of the manufacturing process of the transient voltage suppression protection device provided by the embodiments of the present invention are comparable to those of the transient voltage suppression protection device according to any one of the technical solutions of the first aspect or the second aspect.
  • the effect is the same, so I won't repeat it here.
  • an embodiment of the present invention also provides an electronic product, including the transient voltage suppression protection device according to any one of the technical solutions disclosed in the first aspect and the second aspect.
  • the beneficial effects of the electronic products provided by the embodiments of the present invention are the same as those of the transient voltage suppression protection device described in any one of the technical solutions of the first aspect or the second aspect, and will not be repeated here.
  • Figure 1 is a cross-sectional view of a transient voltage suppression protection device disclosed in an embodiment of the present invention
  • FIG. 2 is an equivalent circuit diagram of a transient voltage suppression protection device disclosed in an embodiment of the present invention.
  • FIG. 3 is an equivalent circuit diagram of a transient voltage suppression protection device disclosed in another embodiment of the present invention.
  • Fig. 4 is a cross-sectional view of a transient voltage suppression protection device disclosed in another embodiment of the present invention.
  • first wells spaced from left to right are formed on the substrate or the epitaxial layer.
  • the second well, the first well and the second well are respectively provided with a first implantation region and a second implantation region with opposite doping types, wherein the first well and the second well have the same doping type, and are respectively connected to the substrate or the substrate.
  • the doping type of the epitaxial layer is opposite.
  • the substrate or the epitaxial layer is used as the common collector of the first well and the second well.
  • the technical solution provided by the embodiments of the present invention utilizes the semiconductor punch-through characteristics to solve the problem of unidirectional high-resistance substrate triode.
  • the cut-off characteristic leads to the problem that the device cannot be used normally.
  • the protection device provided by the embodiment of the present invention is formed by two open base transistors sharing the collector in series, which can trigger the turn-on protection at a lower voltage, and can reduce the device capacitance by half. Obtain a smaller capacitance, and at the same time have a higher anti-surge and electrostatic capacity.
  • the transient voltage suppression protection device provided by the embodiment of the present invention is a current-controlled device.
  • the output current is controlled by the input current. It has a current amplification function. It has two kinds of electrons and holes when it works. Carriers participate in the conduction process.
  • the semiconductor triode has three electrodes, namely the emitter, the base and the collector.
  • the semiconductor triode needs to be applied with a working voltage when it is working, so a current of each pole is generated.
  • the emitter current of the semiconductor triode is equal to the base and the collector during operation.
  • the sum of the electrode currents, the base current is the smallest, and the emitter current is the largest. Add a small current to the base to output a large current at the collector, so the triode has an amplifying effect.
  • an embodiment of the present invention provides a transient voltage suppression protection device, which includes an N-type substrate 1, a first P-type well 2, a second P-type well 7, and a first N-type implantation region 3. And the second N-type implanted region 8, in the protection device, also includes an interlayer dielectric 5 and a protection layer 6 above it.
  • the first P-type well 2 and the second P-type well 7 are arranged on the N-type substrate 1 at intervals from left to right, so that the first P-type well 2 and the second P-type well 7 are Keep a certain distance between the first P-type well 2 and the second P-type well 7 at a distance of 5-20um, and a preset distance must be set between the first P-type well 2 and the second P-type well 7
  • the size of the entire protection device can be effectively controlled, and the capacitance of the entire protection device can also be effectively controlled.
  • the first N-type implantation region 3 and the second N-type implantation region 8 are respectively arranged in the central positions of the first P-type well 2 and the second P-type well 7.
  • the first P-type well 2 and the second P-type well 7 are used as bases, and the bases are in a floating open state.
  • the first N-type implanted region 3 and the second N-type implanted region 8 are connected by metal 4 respectively.
  • the emitter is led out, and the N-type substrate 1 serves as a common collector.
  • the protection device provided by the embodiment of the present invention is connected in series with two open base transistors sharing the collector, which can halve the capacitance of the device and obtain a smaller capacitance.
  • the N-type substrate 1, the first P-type well 2, the second P-type well 7, the first N-type implantation region 3 and the second N-type implantation region 8 are heavily doped.
  • the N-type substrate 1 The doping concentration of the first P-type well 2 and the first N-type implanted region 3 increase sequentially, and the dopant concentrations of the N-type substrate 1, the second P-type well 7 and the second N-type implanted region 8 increase sequentially.
  • the doping concentration of the first P-type well 2 and the second P-type well 7 are the same, the doping concentration of the first N-type implantation region 3 and the second N-type implantation region 8 are the same, and the first N-type implantation region
  • the doping concentration of 3 and the second N-type implanted region 8 is 3 ⁇ 10 15 -8 ⁇ 10 15 /cm 2
  • the doping concentration of the first P-type well 2 and the second P-type well 7 is 1 ⁇ 10 13 ⁇ 3 ⁇ 10 14 /cm 2 .
  • the N-type substrate 1 as a collector is a high-resistance substrate with a resistivity of 30-1500 ⁇ cm, which can reduce the capacitance of the entire protection device.
  • the doping level of the collector is different.
  • the doping concentration of the emitter is much higher.
  • the pn junction of the collector and the base can withstand high reverse voltage, but the emitter The pn junction with the base is not used to carry high voltage, so if the emitter is used as the collector, it will cause the withstand voltage of the transistor to drop and it is easy to break down. This is also the reason why the doping level of the collector cannot be too high. .
  • the first P-type well 2 and the second P-type well 7 have the same junction depth as the pn junction formed between the N-type substrate 1, and the first N-type implanted region 3 and the second N-type
  • the junction depth of the pn junction formed between the first P-type well 2 and the second P-type well 7 is the same as the junction depth of the type implantation region 8 respectively, so that a completely symmetrical two transistors in series can be formed, and the two sides are completely symmetrical, which simplifies the manufacturing process .
  • the protection device provided by the embodiment of the present invention is connected in series by two open base transistors sharing the collector, which is equivalent to two transistors connected in series, and is a bidirectional transient voltage suppression protection device. Therefore, no matter which end is connected to the positive pole of the power supply, the final result The effect is the same.
  • the NPN is a vertical structure, with the emitter at the top, the base at the middle, and the collector at the bottom.
  • the protection device provided is composed of two open base transistors sharing the collector in series. The device capacitance can be halved to obtain a smaller capacitance.
  • FIG 2 it is an equivalent circuit diagram of the transient voltage suppression protection device disclosed in the first embodiment of the present invention.
  • Connect the positive pole of the power supply, the second P-type well 7, the second N-type injection region 8, and the N-type substrate 1 are connected to the negative pole of the power supply.
  • the internal resistance of the N-type substrate 1 can be defined as R NW .
  • the transistor When the transistor is turned on, the emitter current formed by the pn junction formed by the first N-type injection region and the first P-type well flows through the first P-type
  • the pn junction formed by the well and the N-type substrate, the pn junction formed by the second P-well and the N-type substrate, and the pn junction formed by the second N-type implanted region and the second P-type well reach the cathode of the power supply.
  • two open-base transistors sharing the collector are connected in series, which can halve the capacitance of the device and obtain a smaller capacitance.
  • the first N-type implantation area 3, and the N-type substrate 1 constitute a triode connected to the negative electrode of the power supply, then the second P-type well 7, the second N-type implantation area 8, and the N-type substrate 1
  • the composed transistor is connected to the positive pole of the power supply.
  • the internal resistance of the N-type substrate 1 can be defined as R NW .
  • the transistor When the transistor is turned on, the emitter current formed by the pn junction formed by the second N-type injection region and the second P-type well flows through the second P-type
  • the pn junction formed by the well and the N-type substrate, the pn junction formed by the first P-well and the N-type substrate, and the pn junction formed by the first N-type implanted region and the first P-type well reach the cathode of the power supply.
  • two open-base transistors sharing the collector are connected in series, which can halve the capacitance of the device and obtain a smaller capacitance.
  • the embodiment of the present invention provides a transient voltage suppression protection device by forming a first well and a second well spaced from left to right on a substrate, wherein the first well and the second well have the same doping type , And are respectively opposite to the doping type of the substrate, the first well and the second well are respectively provided with a first implantation region and a second implantation region with opposite doping types, by sharing the two first and second wells.
  • the substrate serves as a common collector, so that the semiconductor punch-through characteristics can be used to solve the problem that the unidirectional cut-off characteristics of the high-resistance substrate triode cause the device to be unable to be used independently.
  • the protection device provided by the embodiment of the present invention consists of two common collector bases Polar open-circuit transistors are connected in series, which can trigger the opening protection at a lower voltage, which can halve the capacitance of the device, obtain a smaller capacitance, and have a higher anti-surge and static electricity ability.
  • the embodiment of the present invention provides a transient voltage suppression protection device.
  • the difference from the first embodiment is that the substrate 1 is P-type, and the first well 2 and the second well 7 are N type, the first injection region 3 and the second injection region 8 are P type, and the protection device further includes an interlayer dielectric 5 and a protection layer 6 above it.
  • the first N-type well 2 and the second N-type well 7 are arranged on the P-type substrate 1 at intervals from left to right, so that the first N-type well 2 and the second N-type well 7 are Keep a certain distance between the first N-type well 2 and the second N-type well 7 at a distance of 5-20um, and a preset distance between the first N-type well 2 and the second N-type well 7 needs to be set.
  • the size of the entire protection device can be effectively controlled, and the capacitance of the entire protection device can also be effectively controlled.
  • the first P-type implantation region 3 and the second P-type implantation region 8 are respectively arranged in the central positions of the first N-type well 2 and the second N-type well 7.
  • the first N-type well 2 and the second N-type well 7 serve as bases, and the bases are in a floating open state.
  • the first P-type implantation region 3 and the second P-type implantation region 8 are respectively connected by metal 4 As an emitter lead, the P-type substrate 1 serves as a common collector.
  • the protection device provided by the embodiment of the present invention is connected in series with two open base transistors sharing the collector, which can halve the capacitance of the device and obtain a smaller capacitance. .
  • the P-type substrate 1, the first N-type well 2, the second N-type well 7, the first P-type implanted region 3 and the second P-type implanted region 8 are heavily doped.
  • the P-type substrate 1 The doping concentration of the first N-type well 2 and the first P-type implanted region 3 increases in sequence, and the doping concentration of the P-type substrate 1, the second N-type well 7 and the second P-type implanted region 8 increases in sequence.
  • the doping concentration of the first N-type well 2 and the second N-type well 7 are the same, the doping concentration of the first P-type implantation region 3 and the second P-type implantation region 8 are the same, and the first P-type implantation region
  • the doping concentration of 3 and the second P-type implanted region 8 is 3 ⁇ 10 15 -8 ⁇ 10 15 /cm 2
  • the doping concentration of the first N-type well 2 and the second N-type well 7 is 1 ⁇ 10 13 ⁇ 3 ⁇ 10 14 /cm 2 .
  • the P-type substrate 1 as a collector is a high-resistance substrate with a resistivity of 30-1500 ⁇ cm, which can reduce the capacitance of the entire protection device.
  • the first N-type well 2 and the second N-type well 7 have the same junction depth as the pn junction formed between the P-type substrate 1, and the first P-type implanted region 3 and the second P-type
  • the junction depth of the type injection region 8 is the same as that of the pn junction formed between the first N-type well 2 and the second N-type well 7, so that two transistors in series can be formed completely symmetrically, and the two sides are completely symmetrical, which simplifies the manufacturing process .
  • the protection device provided by the embodiment of the present invention is connected in series by two open base transistors sharing the collector, which is equivalent to two transistors connected in series, and is a bidirectional transient voltage suppression protection device. Therefore, no matter which end is connected to the positive pole of the power supply, the final result The effect is the same.
  • the PNP has a vertical structure, with the emitter on the upper side, the base electrode in the middle, and the collector electrode on the lower side.
  • the protection device provided is connected in series by two open base transistors sharing the collector. The device capacitance can be halved to obtain a smaller capacitance.
  • FIG. 3 it is the equivalent circuit diagram of the transient voltage suppression protection device disclosed in the second embodiment of the present invention.
  • Connect the positive pole of the power supply, the second N-type well 7, the second P-type injection region 8, and the P-type substrate 1 are connected to the negative pole of the power supply.
  • the internal resistance of the P-type substrate 1 can be defined as R pW .
  • the emitter current formed by the pn junction formed by the first P-type injection region and the first N-type well passes through the first N-type well.
  • the pn junction formed with the P-type substrate, the pn junction formed by the second N-type well and the P-type substrate, and the pn junction formed by the second P-type implanted region and the second N-type well reach the power cathode.
  • two open-base transistors sharing the collector are connected in series, which can halve the capacitance of the device and obtain a smaller capacitance.
  • the first P-type implanted region 3, and the P-type substrate 1 constitute a triode connected to the negative electrode of the power supply, then the second N-type well 7, the second P-type implanted region 8, and the P-type substrate 1
  • the composed transistor is connected to the positive pole of the power supply.
  • the internal resistance of the P-type substrate 1 can be defined as R PW .
  • the emitter current formed by the pn junction formed by the second P-type injection region and the second N-type well passes through the second N-type well.
  • the pn junction formed by the sum and the P-type substrate, the pn junction formed by the first N-type well and the P-type substrate, the pn junction formed by the first P-type implanted region and the first N-type well reaches the power cathode, this
  • two open base transistors sharing the collector are connected in series, which can halve the capacitance of the device and obtain a smaller capacitance.
  • the embodiment of the present invention provides a transient voltage suppression protection device by forming a first well and a second well spaced from left to right on a substrate, wherein the first well and the second well have the same doping type , And are respectively opposite to the doping type of the substrate, the first well and the second well are respectively provided with a first implantation region and a second implantation region with opposite doping types, by sharing the two first and second wells.
  • the substrate serves as a common collector, so that the semiconductor punch-through characteristics can be used to solve the problem that the unidirectional cut-off characteristics of the high-resistance substrate triode cause the device to be unable to be used independently.
  • the protection device provided by the embodiment of the present invention consists of two common collector bases Polar open-circuit transistors are connected in series, which can trigger the opening protection at a lower voltage, which can halve the capacitance of the device, obtain a smaller capacitance, and have a higher anti-surge and static electricity ability.
  • the embodiment of the present invention provides a transient voltage suppression protection device, which further includes an epitaxial layer 10 disposed on the substrate 1.
  • the epitaxial layer The doping type 10 is the same as or different from that of the substrate 1, the epitaxial layer 10 is N-type, the substrate 1 is N-type or P-type, and the first P-type well 2 and the second P-type well 7 are sequentially from left to right
  • the first P-type well 2 and the second P-type well 7 are separated from each other on the N-type epitaxial layer 10, and the distance between the first P-type well 2 and the second P-type well 7 is 5-20 um, and the first P-type well 2 and the second P-type well 7 It is necessary to set a preset distance between them, which can effectively control the size of the entire protection device, and at the same time, it can also effectively control the size of the entire protection device capacitance.
  • the first P-type well 2 and the second P-type well 7 are respectively provided with a first N-type implantation region 3 and a second N-type implantation region 8 with opposite doping types.
  • the first N-type implantation region 3 and the second N-type implantation region 8 are respectively arranged in the central positions of the first P-type well 2 and the second P-type well 7.
  • the epitaxial layer 10 serves as a common collector, the first P-type well 2 and the second P-type well 7 respectively serve as bases, and the bases are in a floating open state.
  • the first N-type implanted region 3 and the second The N-type implanted regions 8 are led out as emitters through metal connections, respectively.
  • the first P-type well 2 and the second P-type well 7 have the same junction depth as the pn junction formed between the N-type epitaxial layer 10, and the first N-type implanted region 3 and the second N-type implanted region 3 and the second N-type
  • the junction depth of the pn junction formed between the first P-type well 2 and the second P-type well 7 is the same as the junction depth of the type implantation region 8 respectively, so that a completely symmetrical two transistors in series can be formed, and the two sides are completely symmetrical, which simplifies the manufacturing process .
  • the doping concentration of the N-type epitaxial layer 10 is lower than that of the N-type or P-type substrate 1.
  • the doping concentration of the N-type epitaxial layer 10, the first P-type well 2 and the first N-type implanted region 3 increase sequentially, and the epitaxial layer 10, the second P-type well 7 and the second N-type implanted region 8 are doped
  • the impurity concentration increases sequentially.
  • the N-type epitaxial layer 10 is a high-resistance substrate with a resistivity of 30-1500 ⁇ cm, which can reduce the capacitance of the entire protection device.
  • the protection device provided by the embodiment of the present invention is connected in series by two open base transistors sharing the collector, which is equivalent to two transistors connected in series, and is a bidirectional transient voltage suppression protection device. Therefore, no matter which end is connected to the positive pole of the power supply, the final result The effect is the same.
  • the NPN is a vertical structure, with the emitter at the top, the base at the middle, and the collector at the bottom.
  • the protection device provided is composed of two open base transistors sharing the collector in series. The device capacitance can be halved to obtain a smaller capacitance.
  • the N-type epitaxial layer 10 constitutes a triode connected to the positive electrode of the power supply, then the second P-type well 7, the second N-type injection region 8 , The transistor composed of the N-type epitaxial layer 10 is connected to the negative electrode of the power supply.
  • the internal resistance of the N-type epitaxial layer 10 can be defined as R NW .
  • R NW The internal resistance of the N-type epitaxial layer 10
  • the transistor When the transistor is turned on, the emitter current formed by the pn junction formed by the first N-type injection region and the first P-type well flows through the first P-type
  • the pn junction formed by the well and the N-type epitaxial layer 10, the pn junction formed by the second P-well and the N-type epitaxial layer, and the pn junction formed by the second N-type implantation region and the second P-type well reach the power cathode.
  • two open-base transistors sharing the collector are connected in series, which can halve the capacitance of the device and obtain a smaller capacitance.
  • the first N-type injection region 3, and the N-type epitaxial layer 10 constitute a triode connected to the negative electrode of the power supply, then the second P-type well 7, the second N-type injection region 8, and the N-type epitaxial layer 10 The composed transistor is connected to the positive pole of the power supply.
  • the internal resistance of the N-type epitaxial layer 10 can be defined as R NW .
  • R NW The internal resistance of the N-type epitaxial layer 10
  • the transistor is turned on, the emitter current formed by the pn junction formed by the second N-type injection region and the second P-type well flows through the second P-type
  • the pn junction formed by the well and the N-type epitaxial layer 10, the pn junction formed by the first P-well and the N-type epitaxial layer 10, the pn junction formed by the first N-type implanted region and the first P-type well reach the power cathode,
  • two open-base transistors sharing the collector are connected in series, which can reduce the capacitance of the device by half and obtain a smaller capacitance.
  • the embodiment of the present invention provides a transient voltage suppression protection device, by forming a first well and a second well spaced from left to right on an epitaxial layer, wherein the first well and The second well has the same doping type and is opposite to the doping type of the epitaxial layer.
  • the first well and the second well are respectively provided with a first implantation region and a second implantation region with opposite doping types.
  • the first well and the second well share an epitaxial layer as a common collector, so that the semiconductor punch-through characteristics can be used to solve the problem that the unidirectional cut-off characteristics of the high-resistance substrate triode cause the device to be unable to be used normally.
  • the protection provided by the embodiment of the present invention is connected in series with two open base transistors sharing the collector, which can trigger the opening protection at a lower voltage, which can halve the device capacitance, obtain a smaller capacitance, and have higher anti-surge and static electricity capabilities.
  • the embodiment of the present invention provides a transient voltage suppression protection device, which further includes an epitaxial layer 10 disposed on the substrate 1.
  • the epitaxial layer The doping type 10 is the same as or different from that of the substrate 1, the epitaxial layer 10 is P-type, and the substrate is N-type or P-type.
  • the first N-type well 2 and the second N-type well 7 are mutually in turn from left to right.
  • the first N-type well 2 and the second N-type well 7 are separated by a distance of 5-20um, and the first N-type well 2 and the second N-type well 7 It is necessary to set a preset distance between them, which can effectively control the size of the entire protection device, and at the same time can effectively control the size of the entire protection device capacitance.
  • the first N-type well 2 and the second N-type well 7 are respectively provided with a first P-type implanted region 3 and a second P-type implanted region 8 with opposite doping types.
  • the first P-type implantation region 3 and the second P-type implantation region 8 are respectively arranged in the central positions of the first N-type well 2 and the second N-type well 7.
  • the P-type epitaxial layer 10 serves as a common collector, the first N-type well 2 and the second N-type well 7 respectively serve as bases, and the bases are in a floating open state.
  • the first P-type implanted region 3 and The second P-type implanted regions 8 are led out as emitters through metal connections, respectively.
  • the first N-type well 2 and the second N-type well 7 have the same junction depth as the pn junction formed between the P-type epitaxial layer 10, and the first P-type implanted region 3 and the second P-type
  • the junction depth of the type injection region 8 is the same as that of the pn junction formed between the first N-type well 2 and the second N-type well 7, so that two transistors in series can be formed completely symmetrically, and the two sides are completely symmetrical, which simplifies the manufacturing process .
  • the doping concentration of the P-type epitaxial layer 10 is lower than that of the N-type or P-type substrate 1.
  • the doping concentration of the P-type epitaxial layer 10, the first N-type well 2 and the first P-type implanted region 3 increase sequentially, and the P-type epitaxial layer 10, the second N-type well 7 and the second P-type implanted region 8 The doping concentration increases successively.
  • the P-type epitaxial layer 10 is a high-resistance substrate with a resistivity of 30-1500 ⁇ cm, which can reduce the capacitance of the entire protection device.
  • the protection device provided by the embodiment of the present invention is connected in series by two open base transistors sharing the collector, which is equivalent to two transistors connected in series, and is a bidirectional transient voltage suppression protection device. Therefore, no matter which end is connected to the positive pole of the power supply, the final result The effect is the same.
  • the PNP has a vertical structure, with the emitter on the upper side, the base electrode in the middle, and the collector electrode on the lower side.
  • the protection device provided is connected in series by two open base transistors sharing the collector. The device capacitance can be halved to obtain a smaller capacitance.
  • the first P-type injection region 3 and the P-type epitaxial layer 10 constitute a triode connected to the positive electrode of the power supply, then the second N-type well 7, the second P-type injection region 8 , The transistor composed of the P-type epitaxial layer 10 is connected to the negative pole of the power supply.
  • the internal resistance of the P-type epitaxial layer 10 can be defined as R PW .
  • the transistor When the transistor is turned on, the emitter current formed by the pn junction formed by the first P-type injection region and the first N-type well passes through the first N-type well. And the pn junction formed by the P-type epitaxial layer 10, the pn junction formed by the second N-type well and the P-type epitaxial layer 10, the pn junction formed by the second P-type implanted region and the second N-type well reaches the power cathode, In the embodiment of the present invention, two open-base transistors sharing the collector are connected in series, which can reduce the capacitance of the device by half and obtain a smaller capacitance.
  • the first P-type injection region 3, and the P-type epitaxial layer 10 constitute a triode connected to the negative electrode of the power supply, then the second N-type well 7, the second P-type injection region 8, and the P-type epitaxial layer 10 The composed transistor is connected to the positive pole of the power supply.
  • the internal resistance of the P-type epitaxial layer 10 can be defined as R NW .
  • R NW The internal resistance of the P-type epitaxial layer 10
  • the transistor is turned on, the emitter current formed by the pn junction formed by the second P-type injection region and the second N-type well flows through the second N-type
  • the pn junction formed by the well and the P-type epitaxial layer 10, the pn junction formed by the first N-well and the P-type epitaxial layer 10, and the pn junction formed by the first P-type implanted region and the first N-type well reach the power cathode,
  • two open-base transistors sharing the collector are connected in series, which can reduce the capacitance of the device by half and obtain a smaller capacitance.
  • the embodiment of the present invention provides a transient voltage suppression protection device, by forming a first well and a second well spaced from left to right on an epitaxial layer, wherein the first well and The second well has the same doping type and is opposite to the doping type of the epitaxial layer.
  • the first well and the second well are respectively provided with a first implantation region and a second implantation region with opposite doping types.
  • the first well and the second well share an epitaxial layer as a common collector, so that the semiconductor punch-through characteristics can be used to solve the problem that the unidirectional cut-off characteristics of the high-resistance substrate triode cause the device to be unable to be used normally.
  • the protection provided by the embodiment of the present invention is connected in series with two open base transistors sharing the collector, which can trigger the opening protection at a lower voltage, which can halve the device capacitance, obtain a smaller capacitance, and have higher anti-surge and static electricity capabilities.
  • the embodiments of the present invention provide a manufacturing process of a transient voltage suppression protection device, which can manufacture a transient voltage suppression protection device.
  • the transient voltage suppression protection device disclosed in Embodiment 1 to Embodiment 2 can be manufactured through the following steps, which specifically includes the following steps:
  • the substrate serves as a common collector, the first well and the second well serve as bases respectively, and the first injection region and the second injection region are respectively led out as emitters through metal connections;
  • the transient voltage suppression protection device disclosed in Embodiment 3 to Embodiment 4 can be manufactured through the following steps, which specifically includes the following steps:
  • An epitaxial layer with the same doping type as the substrate is formed on the substrate;
  • the epitaxial layer serves as a common collector, the first well and the second well serve as bases respectively, and the first injection region and the second injection region are respectively led out as emitters through metal connections.
  • the embodiment of the present invention provides a manufacturing process of a transient voltage suppression protection device.
  • the two first wells and the second well to share a substrate or epitaxial layer as the collector, it can be used
  • the semiconductor punch-through characteristic solves the problem that the unidirectional cut-off characteristic of the high-resistance substrate triode causes the device to be unable to be used normally.
  • the protection device provided by the embodiment of the present invention is connected in series with two open base transistors sharing the collectors, which can trigger the opening protection at a lower voltage, halve the device capacitance, obtain a smaller capacitance, and have a simple manufacturing process.
  • the embodiments of the present invention also provide an electronic product.
  • the electronic product includes the transient voltage suppression protection device described in Embodiment 1 to Embodiment 4.
  • the beneficial effects of the electronic products provided by the embodiments of the present invention are the same as the beneficial effects of the transient voltage suppression protection device described in the foregoing Embodiments 1 to 4, and will not be repeated here.
  • the above-mentioned electronic products may be display terminals, communication equipment, engineering equipment, etc., which are not listed here.

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Abstract

公开一种瞬态电压抑制保护器件、制作工艺及电子产品。瞬态电压抑制保护器件包括，衬底（1），作为共用集电极；第一阱（2）和第二阱（7）依次从左到右相互间隔设置在衬底（1）上作为基极，第一阱（2）和第二阱（7）掺杂类型相同，且分别与衬底（1）的掺杂类型相反；第一阱（2）和第二阱（7）中分别设置有掺杂类型相反的第一注入区（3）和第二注入区（8）作为发射极。电子产品包括该瞬态电压抑制保护器件。该瞬态电压抑制保护器件可以在较低电压下触发开启保护，且电容很小，制作工艺简单。

Description

一种瞬态电压抑制保护器件、制作工艺及电子产品 技术领域
本发明实施例涉及集成电路技术领域，具体涉及一种瞬态电压抑制保护器件、制作工艺及电子产品。
背景技术
随着电子产品信号传输速率不断增加，后端IC器件工艺制程越来越先进，电子产品对ESD(静电释放)和EOS(电气过应力)的承受能力越来弱，这就需要增加瞬态电压抑制保护器件(TVS)对电子产品后端IC进行防护，同时对TVS器件提出更高的要求。
现有低电容TVS产品存在工艺复杂，触发电压较高问题，对后端IC防护存在很大问题。
发明概述
技术问题
问题的解决方案
技术解决方案
本发明提供的实施例一个目的在于克服上述问题或者至少部分地解决或缓减上述问题。
本发明提供的实施例另一目的在于提供一种瞬态电压抑制保护器件、制作工艺及电子产品，可以在较低电压下触发开启保护功能，并且器件电容很小，制作工艺简单。
第一方面，本发明实施例公开了一种瞬态电压抑制保护器件，包括，衬底，第一阱，第二阱，第一注入区和第二注入区；
所述第一阱和第二阱依次从左到右相互间隔设置在所述衬底上，所述第一阱和第二阱掺杂类型相同，且分别与所述衬底的掺杂类型相反，所述第一阱和第二阱分别设置有掺杂类型相反的第一注入区和第二注入区；
所述衬底作为共用集电极，所述第一阱和第二阱分别作为基极，所述第一注入 区和第二注入区分别通过金属连接作为发射极引出。
作为本发明的优选实施例，所述第一阱和第二阱分别与所述衬底之间形成的pn结的结深相同，所述第一注入区和所述第二注入区分别与所述第一阱和第二阱之间形成的pn结的结深相同。
作为本发明的优选实施例，所述第一阱和第二阱掺杂浓度相同，所述第一注入区和第二注入区掺杂浓度相同。
作为本发明的优选实施例，所述第一注入区和第二注入区分别设置在所述第一阱和第二阱中央位置。
作为本发明的优选实施例，所述第一阱和第二阱之间间隔距离为5-20um。
作为本发明的优选实施例，所述衬底作为集电极的电阻率为30-1500Ω·cm。
与现有技术相比，本发明实施例提供了一种瞬态电压抑制保护器件，通过在衬底上形成从左到右相互间隔设置的第一阱和第二阱，其中，第一阱和第二阱掺杂类型相同，且分别与衬底的掺杂类型相反，所述第一阱和第二阱分别设置有掺杂类型相反的第一注入区和第二注入区，通过将两个第一阱和第二阱共用一个衬底作为共用集电极，这样可以利用半导体穿通特性，解决了高阻衬底三极管单向截止特性导致器件无法正常单独应用的问题，本发明实施例提供的保护器件由两个共用集电极的基极开路三极管串联，可以在较低电压下触发开启保护，可以使器件电容减半，获得更小的电容，同时有更高抗浪涌和静电能力。
第二方面，本发明实施例还提供了一种瞬态电压抑制保护器件，包括，衬底，外延层，第一阱，第二阱，第一注入区和第二注入区；
所述外延层设置在所述衬底上，所述第一阱和第二阱依次从左到右相互间隔设置在所述外延层上，所述第一阱和第二阱掺杂类型相同，且分别与所述外延层的掺杂类型相反，所述第一阱和第二阱分别设置有掺杂类型相反的第一注入区和第二注入区；
所述外延层作为共用集电极，所述第一阱和第二阱分别作为基极，所述第一注入区和第二注入区分别通过金属连接作为发射极引出。
作为本发明的优选实施例，所述第一阱和第二阱分别与所述外延层之间形成的pn结的结深相同，所述第一注入区和所述第二注入区分别与所述第一阱和第二 阱之间形成的pn结的结深相同。
作为本发明的优选实施例，所述第一阱和第二阱掺杂浓度相同，所述第一注入区和第二注入区掺杂浓度相同。
作为本发明的优选实施例，所述外延层的掺杂浓度小于所述衬底。
作为本发明的优选实施例，所述外延层与所述衬底的掺杂类型相同或者不同。
作为本发明的优选实施例，所述第一注入区和第二注入区分别设置在所述第一阱和第二阱中央位置。
作为本发明的优选实施例，所述第一阱和第二阱之间间隔距离为5-20um。
作为本发明的优选实施例，所述外延层作为集电极的电阻率为30-1500Ω·cm。
与现有技术相比，本发明实施例提供了一种瞬态电压抑制保护器件，通过在外延层上形成从左到右相互间隔设置的第一阱和第二阱，其中，第一阱和第二阱掺杂类型相同，且分别与外延层的掺杂类型相反，所述第一阱和第二阱分别设置有掺杂类型相反的第一注入区和第二注入区，通过将两个第一阱和第二阱共用一个外延层作为共用集电极，这样可以利用半导体穿通特性，解决了高阻衬底三极管单向截止特性导致器件无法正常单独应用的问题，本发明实施例提供的保护器件由两个共用集电极的基极开路三极管串联，可以在较低电压下触发开启保护，可以使器件电容减半，获得更小的电容，同时有更高抗浪涌和静电能力。
第二方面，本发明实施例还提供了一种瞬态电压抑制保护器件的制作工艺，包括，
在衬底上形成与所述衬底掺杂类型相反第一阱和第二阱；
在所述第一阱和第二阱内形成与所述第一阱和第二阱掺杂类型相反的第一注入区和第二注入区；
所述衬底作为共用集电极，所述第一阱和第二阱分别作为基极，所述第一注入区和第二注入区分别通过金属连接作为发射极引出；
或，
在衬底上形成与衬底掺杂类型相同的外延层；
在所述外延层上形成与所述外延层掺杂类型相反第一阱和第二阱；
在所述第一阱和第二阱内形成与所述第一阱和第二阱掺杂类型相反的第一注入区和第二注入区；
所述外延层作为共用集电极，所述第一阱和第二阱分别作为基极，所述第一注入区和第二注入区分别通过金属连接作为发射极引出。
与现有技术相比，本发明实施例提供的一种瞬态电压抑制保护器件的制作工艺的有益效果与上述第一方面或第二方面任一技术方案所述瞬态电压抑制保护器件的有益效果相同，在此不在赘述。
第三方面，本发明实施例还提供了一种电子产品，包括第一方面和第二方面公开的任一技术方案所述的瞬态电压抑制保护器件。
与现有技术相比，本发明实施例提供的电子产品的有益效果与上述第一方面或第二方面任一技术方案所述瞬态电压抑制保护器件的有益效果相同，在此不做赘述。
发明的有益效果
对附图的简要说明
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作一简单地介绍，显而易见地，下面描述中的附图是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。
图1为本发明一个实施例公开的瞬态电压抑制保护器件的剖面图；
图2为本发明一个实施例公开的瞬态电压抑制保护器件的等效电路图；
图3为本发明另一个实施例公开的瞬态电压抑制保护器件的等效电路图；
图4为本发明另一个实施例公开的瞬态电压抑制保护器件的剖面图。
发明实施例
本发明的实施方式
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所 描述的实施例是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
申请人经过研究发现，现有技术中存在后端IC器件工艺制程越来越先进，电子产品对ESD(静电释放)和EOS(电气过应力)的承受能力越来弱，这就需要增加瞬态电压抑制保护器件(TVS)对电子产品后端IC进行防护，同时对TVS器件提出更高的要求而现有的TVS产品存在工艺复杂，触发电压较高问题，对后端IC防护存在很大问题。
为了解决上述问题，在本发明实施例提供了瞬态电压抑制保护器件、制作工艺及电子产品，本发明实施例通过在衬底或外延层上形成的从左到右相互间隔设置的第一阱和第二阱，第一阱和第二阱分别设置有掺杂类型相反的第一注入区和第二注入区，其中，第一阱和第二阱掺杂类型相同，且分别与衬底或外延层的掺杂类型相反，将衬底或外延层作为第一阱和第二阱的共用集电极，通过本发明实施例提供的技术方案利用半导体穿通特性，解决了高阻衬底三极管单向截止特性导致器件无法正常单独应用的问题，本发明实施例提供的保护器件由两个共用集电极的基极开路三极管串联形成，可以在较低电压下触发开启保护，可以使器件电容减半，获得更小的电容，同时有更高抗浪涌和静电能力。
所以为了解决上述问题，以下通过实施例详细说明本发明。
下面结合附图，详细说明本发明的各种非限制性实施方式。
第一方面，本发明实施例提供的瞬态电压抑制保护器件，其是一种电流控制型器件，由输入电流控制输出电流，其本身具有电流放大作用，它工作时有电子和空穴两种载流子参与导电过程。
半导体三极管有三个电极，分别是发射极，基极和集电极，半导体三级管在工作时要加工作电压，于是就产生了各极电流，半导体三极管在工作时发射极电流等于基极和集电极电流之和，其中基极电流最小，发射极电流最大，在基极加一很小的电流，在集电极就能输出很大的电流，因此三极管有放大作用。
实施例1
如图1所示，本发明实施例提供了一种瞬态电压抑制保护器件，包括，N型衬底 1，第一P型阱2，第二P型阱7，第一N型注入区3和第二N型注入区8，在保护器件中还包括，层间介质5和其上方的保护层6。
所述第一P型阱2和第二P型阱7依次从左到右相互间隔设置在所述N型衬底1上，使第一P型阱2和第二P型阱7两者之间保持一定的距离，第一P型阱2和第二P型阱7之间间隔距离为5-20um，所述第一P型阱2和第二P型阱7之间需设置预设距离可以有效控制整个保护器件大小，同时也可有效控制了整个保护器件电容大小。
所述第一N型注入区3和第二N型注入区8分别设置在所述第一P型阱2和第二P型阱7中央位置。
所述第一P型阱2和第二P型阱7作为基极，基极处于浮空开路状态，所述第一N型注入区3和第二N型注入区8分别通过金属4连接作为发射极引出，所述N型衬底1作为共用集电极，本发明实施例提供的保护器件由两个共用集电极的基极开路三极管串联，可以使器件电容减半，获得更小的电容。
所述N型衬底1，第一P型阱2，第二P型阱7，第一N型注入区3和第二N型注入区8为重掺杂，所述N型衬底1，第一P型阱2和第一N型注入区3掺杂浓度依次增大，所述N型衬底1，第二P型阱7和第二N型注入区8掺杂浓度依次增大。
所述第一P型阱2和第二P型阱7掺杂浓度相同，所述第一N型注入区3和第二N型注入区8掺杂浓度相同，所述第一N型注入区3和第二N型注入区8掺杂浓度为3×10 15-8×10 15/cm 2，所述第一P型阱2和第二P型阱7掺杂浓度为1×10 13-3×10 14/cm 2。
所述N型衬底1作为集电极为高阻衬底，电阻率为30-1500Ω·cm，可以减少整个保护器件的电容。
需要说明的是，三极管集电极和发射极的重要区别是掺杂水平不一样，发射极的掺杂浓度要高得多，集电极和基极的pn结可以承受高的逆向电压，但是发射极和基极pn结并不是用来承载高电压的，所以如果把发射极做为集电极使用，会导致三极管的耐压下降，容易击穿，这也是集电极的掺杂水平不能太高的原因。
所述第一P型阱2和第二P型阱7分别与所述N型衬底1之间形成的pn结的结深相 同，所述第一N型注入区3和所述第二N型注入区8分别与所述第一P型阱2和第二P型阱7之间形成的pn结的结深相同，这样可以形成完全对称两个三极管串联，两边完全对称，简化了制作工艺。
本发明实施例提供的保护器件由两个共用集电极的基极开路三极管串联，相当于两个三极管串联，为双向瞬态电压抑制保护器件，所以无论从那一端连接电源的正极，最后达到的效果是一致的。
从NPN的工艺上来看，NPN是垂直结构，发射极在上边，基极在中间，集电极在下边，本发明实施例中，提供的保护器件由两个共用集电极的基极开路三极管串联，可以使器件电容减半，获得更小的电容。
如图2所示，为本发明实施例一公开的瞬态电压抑制保护器件的等效电路图，如果是在第一P型阱2，第一N型注入区3，N型衬底1组成三极管连接电源正极，则第二P型阱7，第二N型注入区8，N型衬底1组成的三极管连接电源负极。
可以定义N型衬底1的内阻为R NW，当三极管导通时，其中，第一N型注入区和第一P型阱所构成的pn结形成的发射极电流流经第一P型阱和N型衬底所构成的pn结，第二P阱和N型衬底所构成的pn结，第二N型注入区和第二P型阱所构成的pn结到达电源阴极，本发明实施例为由两个共用集电极的基极开路三极管串联，可以使器件电容减半，获得更小的电容。
如果是在第一P型阱2，第一N型注入区3，N型衬底1组成三极管连接电源负极，则第二P型阱7，第二N型注入区8，N型衬底1组成的三极管连接电源正极。
可以定义N型衬底1的内阻为R NW，当三极管导通时，其中，第二N型注入区和第二P型阱所构成的pn结形成的发射极电流流经第二P型阱和N型衬底所构成的pn结，第一P阱和N型衬底所构成的pn结，第一N型注入区和第一P型阱所构成的pn结到达电源阴极，本发明实施例为由两个共用集电极的基极开路三极管串联，可以使器件电容减半，获得更小的电容。
本发明实施例提供了一种瞬态电压抑制保护器件，通过在衬底上形成从左到右相互间隔设置的第一阱和第二阱，其中，第一阱和第二阱掺杂类型相同，且分别与衬底的掺杂类型相反，第一阱和第二阱分别设置有掺杂类型相反的第一注入区和第二注入区，通过将两个第一阱和第二阱共用一个衬底作为共用集电极 ，这样可以利用半导体穿通特性，解决了高阻衬底三极管单向截止特性导致器件无法正常单独应用的问题，本发明实施例提供的保护器件由两个共用集电极的基极开路三极管串联，可以在较低电压下触发开启保护，可以使器件电容减半，获得更小的电容，同时有更高抗浪涌和静电能力。
实施例二
如图1所示，本发明实施例提供了一种瞬态电压抑制保护器件，与实施例一不同的是，所述衬底1为P型，所述第一阱2和第二阱7为N型，所述第一注入区3和第二注入区8为P型，在保护器件中还包括，层间介质5和其上方的保护层6。
所述第一N型阱2和第二N型阱7依次从左到右相互间隔设置在所述P型衬底1上，使第一N型阱2和第二N型阱7两者之间保持一定的距离，第一N型阱2和第二N型阱7之间间隔距离为5-20um，所述第一N型阱2和第二N型阱7之间需设置预设距离可以有效控制整个保护器件大小，同时也可有效控制了整个保护器件电容大小。
所述第一P型注入区3和第二P型注入区8分别设置在所述第一N型阱2和第二N型阱7中央位置。
所述第一N型阱2和第二N型阱7通作为基极，基极处于浮空开路状态，所述第一P型注入区3和第二P型注入区8分别通过金属4连接作为发射极引出，所述P型衬底1作为共用集电极，本发明实施例提供的保护器件由两个共用集电极的基极开路三极管串联，可以使器件电容减半，获得更小的电容。
所述P型衬底1，第一N型阱2，第二N型阱7，第一P型注入区3和第二P型注入区8为重掺杂，所述P型衬底1，第一N型阱2和第一P型注入区3掺杂浓度依次增大，所述P型衬底1，第二N型阱7和第二P型注入区8掺杂浓度依次增大。
所述第一N型阱2和第二N型阱7掺杂浓度相同，所述第一P型注入区3和第二P型注入区8掺杂浓度相同，所述第一P型注入区3和第二P型注入区8掺杂浓度为3×10 15-8×10 15/cm 2，所述第一N型阱2和第二N型阱7掺杂浓度为1×10 13-3×10 14/cm 2。
所述P型衬底1作为集电极为高阻衬底，电阻率为30-1500Ω·cm，可以减少整个保护器件的电容。
所述第一N型阱2和第二N型阱7分别与所述P型衬底1之间形成的pn结的结深相 同，所述第一P型注入区3和所述第二P型注入区8分别与所述第一N型阱2和第二N型阱7之间形成的pn结的结深相同，这样可以形成完全对称两个三极管串联，两边完全对称，简化了制作工艺。
本发明实施例提供的保护器件由两个共用集电极的基极开路三极管串联，相当于两个三极管串联，为双向瞬态电压抑制保护器件，所以无论从那一端连接电源的正极，最后达到的效果是一致的。
从PNP的工艺上来看，PNP是垂直结构，发射极在上边，基极在中间，集电极在下边，本发明实施例中，提供的保护器件由两个共用集电极的基极开路三极管串联，可以使器件电容减半，获得更小的电容。
如图3所示，为本发明实施例二公开的瞬态电压抑制保护器件的等效电路图，如果是在第一N型阱2，第一P型注入区3，P型衬底1组成三极管连接电源正极，则第二N型阱7，第二P型注入区8，P型衬底1组成的三极管连接电源负极。
可以定义P型衬底1的内阻为R pW，当三极管导通时，其中，第一P型注入区和第一N型阱所构成的pn结形成的发射极电流经由第一N型阱和P型衬底所构成的pn结，第二N型阱和P型衬底所构成的pn结，第二P型注入区和第二N型阱所构成的pn结到达电源阴极，本发明实施例为由两个共用集电极的基极开路三极管串联，可以使器件电容减半，获得更小的电容。
如果是在第一N型阱2，第一P型注入区3，P型衬底1组成三极管连接电源负极，则第二N型阱7，第二P型注入区8，P型衬底1组成的三极管连接电源正极。
可以定义P型衬底1的内阻为R PW，当三极管导通时，其中，第二P型注入区和第二N型阱所构成的pn结形成的发射极电流经由第二N型阱和和P型衬底所构成的pn结，第一N型阱和P型衬底所构成的pn结，第一P型注入区和第一N型阱所构成的pn结到达电源阴极，本发明实施例为由两个共用集电极的基极开路三极管串联，可以使器件电容减半，获得更小的电容。
本发明实施例提供了一种瞬态电压抑制保护器件，通过在衬底上形成从左到右相互间隔设置的第一阱和第二阱，其中，第一阱和第二阱掺杂类型相同，且分别与衬底的掺杂类型相反，第一阱和第二阱分别设置有掺杂类型相反的第一注入区和第二注入区，通过将两个第一阱和第二阱共用一个衬底作为共用集电极 ，这样可以利用半导体穿通特性，解决了高阻衬底三极管单向截止特性导致器件无法正常单独应用的问题，本发明实施例提供的保护器件由两个共用集电极的基极开路三极管串联，可以在较低电压下触发开启保护，可以使器件电容减半，获得更小的电容，同时有更高抗浪涌和静电能力。
实施例三
如图4所示，与实施例一和实施例二不同的是，本发明实施例提供了一种瞬态电压抑制保护器件，还包括设置在衬底1上的外延层10，所述外延层10与衬底1的掺杂类型相同或不同，外延层10为N型，衬底1为N型或P型，所述第一P型阱2和第二P型阱7依次从左到右相互间隔设置在所述N型外延层10上，第一P型阱2和第二P型阱7之间间隔距离为5-20um，所述第一P型阱2和第二P型阱7之间需设置预设距离可以有效控制整个保护器件大小，同时也可有效控制了整个保护器件电容大小。
所述第一P型阱2和第二P型阱7分别设置有掺杂类型相反的第一N型注入区3和第二N型注入区8。
所述第一N型注入区3和第二N型注入区8分别设置在所述第一P型阱2和第二P型阱7中央位置。
所述外延层10作为共用集电极，所述第一P型阱2和第二P型阱7分别作为基极，基极处于浮空开路状态，所述第一N型注入区3和第二N型注入区8分别通过金属连接作为发射极引出。
所述第一P型阱2和第二P型阱7分别与所述N型外延层10之间形成的pn结的结深相同，所述第一N型注入区3和所述第二N型注入区8分别与所述第一P型阱2和第二P型阱7之间形成的pn结的结深相同，这样可以形成完全对称两个三极管串联，两边完全对称，简化了制作工艺。
所述N型外延层10掺杂浓度小于N型或P型衬底1。
所述N型外延层10，第一P型阱2和第一N型注入区3掺杂浓度依次增大，所述外延层10，第二P型阱7和第二N型注入区8掺杂浓度依次增大。
所述N型外延层10为高阻衬底，电阻率为30-1500Ω·cm，可以减少整个保护器件的电容。
本发明实施例提供的保护器件由两个共用集电极的基极开路三极管串联，相当于两个三极管串联，为双向瞬态电压抑制保护器件，所以无论从那一端连接电源的正极，最后达到的效果是一致的。
从NPN的工艺上来看，NPN是垂直结构，发射极在上边，基极在中间，集电极在下边，本发明实施例中，提供的保护器件由两个共用集电极的基极开路三极管串联，可以使器件电容减半，获得更小的电容。
如图2所示，如果是在第一P型阱2，第一N型注入区3，N型外延层10组成三极管连接电源正极，则第二P型阱7，第二N型注入区8，N型外延层10组成的三极管连接电源负极。
可以定义N型外延层10的内阻为R NW，当三极管导通时，其中，第一N型注入区和第一P型阱所构成的pn结形成的发射极电流流经第一P型阱和N型外延层10所构成的pn结，第二P阱和N型外延层所构成的pn结，第二N型注入区和第二P型阱所构成的pn结到达电源阴极，本发明实施例为由两个共用集电极的基极开路三极管串联，可以使器件电容减半，获得更小的电容。
如果是在第一P型阱2，第一N型注入区3，N型外延层10组成三极管连接电源负极，则第二P型阱7，第二N型注入区8，N型外延层10组成的三极管连接电源正极。
可以定义N型外延层10的内阻为R NW，当三极管导通时，其中，第二N型注入区和第二P型阱所构成的pn结形成的发射极电流流经第二P型阱和N型外延层10所构成的pn结，第一P阱和N型外延层10所构成的pn结，第一N型注入区和第一P型阱所构成的pn结到达电源阴极，本发明实施例为由两个共用集电极的基极开路三极管串联，可以使器件电容减半，获得更小的电容。
与现有技术相比，本发明实施例提供了一种瞬态电压抑制保护器件，通过在外延层上形成从左到右相互间隔设置的第一阱和第二阱，其中，第一阱和第二阱掺杂类型相同，且分别与外延层的掺杂类型相反，所述第一阱和第二阱分别设置有掺杂类型相反的第一注入区和第二注入区，通过将两个第一阱和第二阱共用一个外延层作为共用集电极，这样可以利用半导体穿通特性，解决了高阻衬底三极管单向截止特性导致器件无法正常单独应用的问题，本发明实施例提供 的保护器件由两个共用集电极的基极开路三极管串联，可以在较低电压下触发开启保护，可以使器件电容减半，获得更小的电容，同时有更高抗浪涌和静电能力。
实施例四
如图4所示，与实施例一和实施例二不同的是，本发明实施例提供了一种瞬态电压抑制保护器件，还包括设置在衬底1上的外延层10，所述外延层10与衬底1的掺杂类型相同或不同，外延层10为P型，衬底为N型或P型，所述第一N型阱2和第二N型阱7依次从左到右相互间隔设置在所述P型外延层10上，第一N型阱2和第二N型阱7之间间隔距离为5-20um，所述第一N型阱2和第二N型阱7之间需设置预设距离可以有效控制整个保护器件大小，同时也可有效控制了整个保护器件电容大小。
所述第一N型阱2和第二N型阱7分别设置有掺杂类型相反的第一P型注入区3和第二P型注入区8。
所述第一P型注入区3和第二P型注入区8分别设置在所述第一N型阱2和第二N型阱7中央位置。
所述P型外延层10作为共用集电极，所述第一N型阱2和第二N型阱7分别作为基极，基极处于浮空开路状态，所述第一P型注入区3和第二P型注入区8分别通过金属连接作为发射极引出。
所述第一N型阱2和第二N型阱7分别与所述P型外延层10之间形成的pn结的结深相同，所述第一P型注入区3和所述第二P型注入区8分别与所述第一N型阱2和第二N型阱7之间形成的pn结的结深相同，这样可以形成完全对称两个三极管串联，两边完全对称，简化了制作工艺。
所述P型外延层10掺杂浓度小于N型或P型衬底1。
所述P型外延层10，第一N型阱2和第一P型注入区3掺杂浓度依次增大，所述P型外延层10，第二N型阱7和第二P型注入区8掺杂浓度依次增大。
所述P型外延层10为高阻衬底，电阻率为30-1500Ω·cm，可以减少整个保护器件的电容。
本发明实施例提供的保护器件由两个共用集电极的基极开路三极管串联，相当 于两个三极管串联，为双向瞬态电压抑制保护器件，所以无论从那一端连接电源的正极，最后达到的效果是一致的。
从PNP的工艺上来看，PNP是垂直结构，发射极在上边，基极在中间，集电极在下边，本发明实施例中，提供的保护器件由两个共用集电极的基极开路三极管串联，可以使器件电容减半，获得更小的电容。
如图3所示，如果是在第一N型阱2，第一P型注入区3，P型外延层10组成三极管连接电源正极，则第二N型阱7，第二P型注入区8，P型外延层10组成的三极管连接电源负极。
可以定义P型外延层10的内阻为R PW，当三极管导通时，其中，第一P型注入区和第一N型阱所构成的pn结形成的发射极电流经由第一N型阱和P型外延层10所构成的pn结，第二N型阱和P型外延层10所构成的pn结，第二P型注入区和第二N型阱所构成的pn结到达电源阴极，本发明实施例为由两个共用集电极的基极开路三极管串联，可以使器件电容减半，获得更小的电容。
如果是在第一N型阱2，第一P型注入区3，P型外延层10组成三极管连接电源负极，则第二N型阱7，第二P型注入区8，P型外延层10组成的三极管连接电源正极。
可以定义P型外延层10的内阻为R NW，当三极管导通时，其中，第二P型注入区和第二N型阱所构成的pn结形成的发射极电流流经第二N型阱和P型外延层10所构成的pn结，第一N阱和P型外延层10所构成的pn结，第一P型注入区和第一N型阱所构成的pn结到达电源阴极，本发明实施例为由两个共用集电极的基极开路三极管串联，可以使器件电容减半，获得更小的电容。
与现有技术相比，本发明实施例提供了一种瞬态电压抑制保护器件，通过在外延层上形成从左到右相互间隔设置的第一阱和第二阱，其中，第一阱和第二阱掺杂类型相同，且分别与外延层的掺杂类型相反，所述第一阱和第二阱分别设置有掺杂类型相反的第一注入区和第二注入区，通过将两个第一阱和第二阱共用一个外延层作为共用集电极，这样可以利用半导体穿通特性，解决了高阻衬底三极管单向截止特性导致器件无法正常单独应用的问题，本发明实施例提供的保护器件由两个共用集电极的基极开路三极管串联，可以在较低电压下触发 开启保护，可以使器件电容减半，获得更小的电容，同时有更高抗浪涌和静电能力。
第二方面，本发明实施例提供了一种瞬态电压抑制保护器件的制作工艺，可以制作出瞬态电压抑制保护器件。
通过以下步骤可以制作出如实施例1至实施例2公开的瞬态电压抑制保护器件，具体包括以下步骤：
在衬底上形成与所述衬底掺杂类型相反第一阱和第二阱；
在所述第一阱和第二阱内形成与所述第一阱和第二阱掺杂类型相反的第一注入区和第二注入区；
所述衬底作为共用集电极，所述第一阱和第二阱分别作为基极，所述第一注入区和第二注入区分别通过金属连接作为发射极引出；
通过以下步骤可以制作出如实施例3至实施例4公开的瞬态电压抑制保护器件，具体包括以下步骤：
在衬底上形成与衬底掺杂类型相同的外延层；
在所述外延层上形成与所述外延层掺杂类型相反第一阱和第二阱；
在所述第一阱和第二阱内形成与所述第一阱和第二阱掺杂类型相反的第一注入区和第二注入区；
所述外延层作为共用集电极，所述第一阱和第二阱分别作为基极，所述第一注入区和第二注入区分别通过金属连接作为发射极引出。
与现有技术相比，本发明实施例提供了一种瞬态电压抑制保护器件的制作工艺，通过将两个第一阱和第二阱共用一个衬底或外延层作为集电极，这样可以利用半导体穿通特性，解决了高阻衬底三极管单向截止特性导致器件无法正常单独应用的问题。同时本发明实施例提供的保护器件由两个共用集电极的基极开路三极管串联，可以在较低电压下触发开启保护，可以使器件电容减半，获得更小的电容，同时制作工艺简单。
第三方面，本发明实施例还提供了一种电子产品。该电子产品包括实施例1至实施例4所述的瞬态电压抑制保护器件。
与现有技术相比，本发明实施例提供的电子产品的有益效果与上述实施例1至 实施例4所述的瞬态电压抑制保护器件有益效果相同，此处不做赘述。
其中，上述电子产品可以为显示终端、通讯设备、工程设备等，在此不一一列出。
在上述实施方式的描述中，具体特征、结构或者特点可以在任何的一个或多个实施例或示例中以合适的方式结合。
最后应说明的是：以上各实施例仅用以说明本发明的技术方案，而非对其限制；尽管参照前述各实施例对本发明进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本发明各实施例技术方案的范围。

Claims (16)

  1. 一种瞬态电压抑制保护器件，其特征在于，包括，衬底，第一阱，第二阱，第一注入区和第二注入区；
    所述第一阱和第二阱依次从左到右相互间隔设置在所述衬底上，所述第一阱和第二阱掺杂类型相同，且分别与所述衬底的掺杂类型相反，所述第一阱和第二阱分别设置有掺杂类型相反的第一注入区和第二注入区；
    所述衬底作为共用集电极，所述第一阱和第二阱分别作为基极，所述第一注入区和第二注入区分别通过金属连接作为发射极引出。
  2. 根据权利要求1所述的瞬态电压抑制保护器件，其特征在于，所述第一阱和第二阱分别与所述衬底之间形成的pn结的结深相同，所述第一注入区和所述第二注入区分别与所述第一阱和第二阱之间形成的pn结的结深相同。
  3. 根据权利要求1至2任一项所述的瞬态电压抑制保护器件，其特征在于，所述第一阱和第二阱掺杂浓度相同，所述第一注入区和第二注入区掺杂浓度相同。
  4. 根据权利要求1至2任一项所述的瞬态电压抑制保护器件，其特征在于，所述第一注入区和第二注入区分别设置在所述第一阱和第二阱中央位置。
  5. 根据权利要求1至2任一项所述的瞬态电压抑制保护器件，其特征在于，所述第一阱和第二阱之间间隔距离为5-20um。
  6. 根据权利要求1至2任一项所述的瞬态电压抑制保护器件，其特征在于，所述衬底作为集电极的电阻率为30-1500Ω·cm。
  7. 一种瞬态电压抑制保护器件，其特征在于，包括，衬底，外延层，第一阱，第二阱，第一注入区和第二注入区；
    所述外延层设置在所述衬底上，所述第一阱和第二阱依次从左到右相互间隔设置在所述外延层上，所述第一阱和第二阱掺杂类型 相同，且分别与所述外延层的掺杂类型相反，所述第一阱和第二阱分别设置有掺杂类型相反的第一注入区和第二注入区；
    所述外延层作为共用集电极，所述第一阱和第二阱分别作为基极，所述第一注入区和第二注入区分别通过金属连接作为发射极引出。
  8. 根据权利要求7所述的瞬态电压抑制保护器件，其特征在于，所述第一阱和第二阱分别与所述外延层之间形成的pn结的结深相同，所述第一注入区和所述第二注入区分别与所述第一阱和第二阱之间形成的pn结的结深相同。
  9. 根据权利要求7至8任一项所述的瞬态电压抑制保护器件，其特征在于，所述第一阱和第二阱掺杂浓度相同，所述第一注入区和第二注入区掺杂浓度相同。
  10. 根据权利要求9任一项所述的瞬态电压抑制保护器件，其特征在于，所述外延层的掺杂浓度小于所述衬底。
  11. 根据权利要求7至8任一项所述的瞬态电压抑制保护器件，其特征在于，所述外延层与所述衬底的掺杂类型相同或不同。
  12. 根据权利要求7至8任一项所述的瞬态电压抑制保护器件，其特征在于，所述第一注入区和第二注入区分别设置在所述第一阱和第二阱中央位置。
  13. 根据权利要求7至8任一项所述的瞬态电压抑制保护器件，其特征在于，所述第一阱和第二阱之间间隔距离为5-20um。
  14. 根据权利要求7至8任一项所述的瞬态电压抑制保护器件，其特征在于，所述外延层作为集电极的电阻率为30-1500Ω·cm。
  15. 一种瞬态电压抑制保护器件的制作工艺，其特征在于，包括，在衬底上形成与所述衬底掺杂类型相反第一阱和第二阱；
    在所述第一阱和第二阱内形成与所述第一阱和第二阱掺杂类型相反的第一注入区和第二注入区；
    所述衬底作为共用集电极，所述第一阱和第二阱分别作为基极，
    所述第一注入区和第二注入区分别通过金属连接作为发射极引出；
    或，
    在衬底上形成与衬底掺杂类型相同的外延层；
    在所述外延层上形成与所述外延层掺杂类型相反第一阱和第二阱；
    在所述第一阱和第二阱内形成与所述第一阱和第二阱掺杂类型相反的第一注入区和第二注入区；
    所述外延层作为共用集电极，所述第一阱和第二阱分别作为基极，所述第一注入区和第二注入区分别通过金属连接作为发射极引出。
  16. 一种电子产品，其特征在于，包括如权利要求1至14任一项所述瞬态电压抑制保护器件。
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