WO2021217301A1 - Procédé de fabrication de structure semi-conductrice et structure semi-conductrice - Google Patents

Procédé de fabrication de structure semi-conductrice et structure semi-conductrice Download PDF

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Publication number
WO2021217301A1
WO2021217301A1 PCT/CN2020/087039 CN2020087039W WO2021217301A1 WO 2021217301 A1 WO2021217301 A1 WO 2021217301A1 CN 2020087039 W CN2020087039 W CN 2020087039W WO 2021217301 A1 WO2021217301 A1 WO 2021217301A1
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Prior art keywords
layer
metal
substrate
semiconductor structure
metal nitride
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PCT/CN2020/087039
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English (en)
Chinese (zh)
Inventor
程凯
张丽旸
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苏州晶湛半导体有限公司
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Priority to PCT/CN2020/087039 priority Critical patent/WO2021217301A1/fr
Publication of WO2021217301A1 publication Critical patent/WO2021217301A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02387—Group 13/15 materials
    • H01L21/02389—Nitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/0242—Crystalline insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02491—Conductive materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02494—Structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02494—Structure
    • H01L21/02496—Layer structure
    • H01L21/02502—Layer structure consisting of two layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02494—Structure
    • H01L21/02513—Microstructure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
    • H01L21/0254—Nitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments

Definitions

  • the present invention relates to the field of semiconductors, in particular to a manufacturing method of a semiconductor structure and a semiconductor structure.
  • GaN As a wide bandgap semiconductor material, GaN has a wide range of application prospects, but the preparation of high-quality GaN epitaxial layers is quite difficult.
  • a GaN epitaxial layer is prepared on a commonly used Si substrate. Since Ga and Si substrates have a melting reaction at high temperatures and destroy the epitaxial layer, it is necessary to prepare a metal nitride layer of a certain thickness, such as an AlN layer, but the AlN layer and the There is a huge lattice mismatch between Si substrates, and the surface mobility of Al atoms is low. How to achieve a high-quality AlN epitaxial layer on the Si substrate is very important for the crystal quality of the subsequent epitaxial layer.
  • the invention provides a method for manufacturing a semiconductor structure with improved quality and a semiconductor structure.
  • the present invention provides a manufacturing method of a semiconductor structure, the manufacturing method includes: providing a substrate; forming a composite layer on the substrate, the composite layer including a plurality of patterns, the composite layer including the substrate formed on the substrate A metal layer on the bottom and an amorphous layer formed on the metal layer, the metal layer and the amorphous layer jointly form a plurality of patterns, so that part of the substrate is exposed; a metal nitride layer is formed on the composite layer; The amorphous layer is removed to form a plurality of cavities; the substrate is removed to form a semiconductor structure.
  • the pattern is a convex pattern, and a gap is formed between two adjacent patterns; after a metal nitride layer is formed on the composite layer, the metal nitride layer passes through the gap and connects to the substrate. touch.
  • the step of forming a composite layer on the substrate includes: depositing a metal film layer on the substrate; depositing an amorphous film layer on the metal film layer; The layer is etched to form the metal layer and the amorphous layer.
  • the step of forming a metal nitride layer on the composite layer includes: forming a metal nitride film layer on the composite layer, the metal nitride film layer including a single crystal film layer in contact with the substrate And a polycrystalline film layer in contact with the composite layer; converting the polycrystalline film layer of the metal nitride film layer into a single crystal film layer to form the metal nitride layer.
  • the manufacturing method includes: before removing the composite layer, annealing the metal nitride layer.
  • the metal nitride layer is formed by a physical vapor deposition process or a metal organic compound chemical vapor deposition process.
  • the step of removing at least a part of the composite layer includes: removing the amorphous layer, and forming the cavity between the metal layer and the metal nitride layer.
  • the step of removing the amorphous layer includes: removing the amorphous layer through an etching process, and the amorphous layer is separated from the metal layer and the metal nitride layer in a lateral direction; and the lateral direction is perpendicular to the metal nitride layer.
  • the arrangement direction of the substrate and the metal nitride layer is not limited to: etching process, and the amorphous layer is separated from the metal layer and the metal nitride layer in a lateral direction; and the lateral direction is perpendicular to the metal nitride layer.
  • the material of the metal nitride layer includes aluminum nitride.
  • the material of the amorphous layer includes at least one of silicon dioxide, silicon nitride, and aluminum oxide.
  • the present invention also provides a semiconductor structure, including a metal layer and a metal nitride layer, the metal layer includes a plurality of electrodes, and the metal nitride layer includes a plurality of body portions and a plurality of support portions;
  • the supporting part connects two adjacent main body parts, and the main body part and the two adjacent supporting parts are arranged along the circumferential direction of the electrode.
  • the composite layer by forming a composite layer on the substrate and forming a metal nitride layer on the composite layer, the composite layer can inhibit slippage or dislocation during epitaxial growth, thereby improving the quality of the metal nitride layer and improving the semiconductor structure Performance.
  • FIG. 1 is a schematic flow chart of an embodiment of a method for fabricating a semiconductor structure of the present invention.
  • FIG. 2 is a schematic diagram after a metal film layer is formed on a substrate in the manufacturing method shown in FIG. 1.
  • FIG. 3 is a schematic diagram after an amorphous film layer is formed on a metal film layer in the manufacturing method shown in FIG. 1.
  • FIG. 4 is a schematic diagram of the metal film layer and the amorphous film layer after patterning in the manufacturing method shown in FIG. 1.
  • FIG. 5 is a schematic diagram after forming a metal nitride layer on the composite layer in the manufacturing method shown in FIG. 1.
  • Fig. 6 is a schematic diagram after removing the composite layer in the manufacturing method shown in Fig. 1.
  • FIG. 7 is a schematic diagram after removing the substrate in the manufacturing method shown in FIG. 1, that is, a schematic diagram of the semiconductor structure.
  • the present invention provides a manufacturing method of a semiconductor structure.
  • the manufacturing method includes: providing a substrate; forming a composite layer on the substrate, the composite layer including a plurality of patterns, the composite layer including the substrate formed on the substrate Forming a metal layer on the metal layer and an amorphous layer formed on the metal layer, the metal layer and the amorphous layer together form a plurality of patterns; forming a metal nitride layer on the composite layer; removing the amorphous layer, Forming a plurality of cavities; removing the substrate to form a semiconductor structure.
  • the manufacturing method of the semiconductor structure of this embodiment includes:
  • Step S10 Provide the substrate 1.
  • Step S20 forming a composite layer 2 on the substrate 1, and the composite layer 2 includes a plurality of patterns 201 (refer to FIG. 4) to expose part of the substrate;
  • Step S30 forming a metal nitride layer 3 on the composite layer 2 (refer to FIG. 5);
  • Step S40 Remove at least a part of the composite layer 2, such as the amorphous layer 22, to form a plurality of cavities 203, the cavities being located between the metal nitride layer 3 and the substrate 1 (see FIG. 6 );
  • Step S50 removing the substrate 1 to form a partially suspended semiconductor structure (refer to FIG. 7).
  • the composite layer 2 includes a metal layer 21 formed on the substrate 1 and an amorphous layer 22 formed on the metal layer 21, and the pattern 20 is composed of the metal layer 21 and the amorphous layer 22. Form together.
  • the substrate 1 can be a sapphire substrate or an aluminum nitride (AlN) substrate for supporting the structure formed thereon.
  • step S20 further includes:
  • Step S21 depositing a metal film layer 21A on the substrate 1;
  • Step S22 depositing an amorphous film layer 22A on the metal film layer 21A;
  • Step S23 patterning the metal film layer 21A and the amorphous film layer 22A to form the metal layer 21 and the amorphous layer 22.
  • the material of the metal film layer 21A is a high temperature resistant metal material.
  • molybdenum Mo
  • any metal material with a melting point higher than Mo can be used for the metal film layer 21A.
  • the high melting point can ensure that the metal film layer 21A will not melt in the subsequent process.
  • the material of the amorphous film layer 22A may include at least one of silicon dioxide, silicon nitride, and aluminum oxide, and silicon dioxide is selected in this embodiment.
  • the patterning process is an etching process, and in other embodiments, the patterning process may also be a photolithography process.
  • the pattern 201 is a convex pattern.
  • the projection of the pattern 201 on the substrate 1 may be a rectangle, a triangle, a polygon (which can be understood as a pentagon and a closed pattern with more sides) or a circle.
  • the pattern 20 can suppress slippage or dislocations of the metal nitride layer 3 during growth, thereby reducing the dislocation density, thereby improving the quality of the metal nitride layer 3.
  • the pattern 20 is a convex pattern, that is, the pattern 20 is formed by extending upward.
  • the substrate 1 can be etched to form a plurality of upward notches, and the pattern 20 is formed in the notches. At this time, the pattern 20 corresponds to a recessed pattern.
  • step S20 after step S20 is completed, a gap 202 is formed between adjacent patterns 201, and the substrate 1 is partially exposed through the gap 202.
  • step S30 after step S30 is completed, the metal nitride layer 3 contacts the substrate 1 through the gap 202.
  • the metal nitride layer 3 is formed by a physical vapor deposition (Physical Vapor Deposition, PVD) process or a metal organic chemical vapor deposition (Metal Organic Chemical Vapor Deposition, MOCVD) process.
  • the material of the metal nitride layer 3 includes AlN-based materials, and the AlN-based materials may be AlN, AlGaN, InAlN, ScAlN, and other materials.
  • the material of the metal nitride layer 3 is aluminum nitride doped with scandium, that is, Al(Sc)N.
  • the step S30 includes: forming a metal nitride film layer on the composite layer 2, and the part of the metal nitride film layer in direct contact with the substrate 1 is a single crystal film layer, The part directly in contact with the composite layer 2 is a polycrystalline film layer; the polycrystalline film layer of the metal nitride film layer is converted into a single crystal film layer to form the metal nitride layer. Since part of the metal nitride film layer is single crystal, the single crystal structure can be conducted to the polycrystalline structure part through the annealing process, so that the polycrystalline structure gradually becomes a single crystal structure, that is to say, the metal nitride film layer finally All become a single crystal structure. Through the patterned composite layer 2 and the annealing process, a high-quality single crystal metal nitride film can be obtained.
  • a part of the composite layer 2, such as the amorphous layer 22, is removed by an etching process, and the amorphous layer 22 is horizontally aligned with the metal layer after etching. 21 and the metal nitride layer 3 are separated. After etching, the cavity 203 is formed between the metal nitride layer 3 and the metal layer 21. The lateral direction is perpendicular to the arrangement direction of the substrate 1 and the metal nitride layer 3.
  • the metal layer 21 remains and can be directly used as an electrode without additional electrode manufacturing process, which is beneficial to simplify the manufacturing process of the semiconductor device.
  • the amorphous layer 22 is an amorphous layer, for example made of amorphous SiO2.
  • the composite layer 2 is completely removed by an etching process, and the cavity 203 is formed between the metal nitride layer 3 and the substrate 1.
  • the composite layer 2 is laterally separated from the substrate 1 and the metal nitride layer 3 after etching, so the metal nitride layer will not be damaged during the etching process.
  • the lateral direction is perpendicular to the arrangement direction of the substrate 1 and the metal nitride layer 3.
  • the composite layer 2 can be etched completely or partially, and the corresponding manufacturing process can be selected according to the final required semiconductor structure.
  • step S50 the substrate 1 is removed by a lift-off technology. Since the step of removing the substrate 1 is after the step of removing the composite layer 2, the substrate 1 can still support the metal nitride layer 3 well when the composite layer 2 is removed, so as to prevent the metal nitride layer 3 from being in step S40. Deformation occurred in.
  • the manufacturing method further includes: before removing the composite layer 2, annealing the metal nitride layer 3 to improve the crystal quality of the metal nitride layer.
  • high temperature annealing is performed on the metal nitride layer 3.
  • a semiconductor structure (actually, a metal nitride layer 3 and a metal layer) manufactured by the manufacturing method described in any of the foregoing embodiments, the semiconductor structure including a metal layer 21 and a metal nitride layer 3
  • the metal layer 21 includes a plurality of electrodes 211
  • the metal nitride layer 3 includes a plurality of body portions 31 and a plurality of support portions 32
  • the support portions 32 connect two adjacent body portions 31.
  • the portion 31 and the two adjacent support portions 32 are arranged along the circumferential direction of the electrode 211, and the main body portion 31 and the two adjacent support portions 32 and the electrode 211 jointly enclose a cavity 203.
  • the cavity 203 is closed.
  • the figure only illustrates a part of the semiconductor structure, which results in the cavities on both sides being different from the cavity in the middle, and the actual structure is the same.
  • the semiconductor structure can be self-supporting, and self-supporting can be understood as: being able to maintain its own shape without causing defects in processing.
  • the metal nitride layer of the semiconductor structure has a low dislocation density and a high quality, which is conducive to further production of a high-quality GaN structure.
  • the semiconductor structure does not require an additional electrode manufacturing process, which is beneficial to simplify the manufacturing process of the semiconductor device.
  • the present invention also provides a resonator, which includes the semiconductor structure described in any one of the foregoing embodiments.
  • the resonator needs to form a cavity structure on its substrate, and the semiconductor structure manufactured by the aforementioned manufacturing method has a plurality of cavities 203.
  • the cavities 203 can replace the cavity structure of the substrate, so the semiconductor structure can be directly used To manufacture the resonator, there is no need to form a cavity on the substrate of the resonator through other processes, which is beneficial to simplify the manufacturing process and reduce the manufacturing cost.
  • the semiconductor structure can also be used in other semiconductor devices, such as LED devices.
  • the composite layer can inhibit slippage or dislocation during epitaxial growth, thereby improving the quality of the metal nitride layer and improving the semiconductor structure
  • the metal nitride layer can be self-supporting.
  • the semiconductor structure can be directly used to fabricate the resonator, which is beneficial to simplify the fabrication process of the resonator.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Materials Engineering (AREA)
  • Recrystallisation Techniques (AREA)

Abstract

L'invention concerne un procédé de formation de structure semi-conductrice, ainsi qu'un structure semi-conductrice. L'invention concerne un procédé de fabrication de structure semi-conductrice consistant : à obtenir un substrat (1) ; à former une couche composite (2) sur le substrat (1), la couche composite (2) comprenant une pluralité de motifs (201), la couche composite (2) comprenant une couche métallique (21) formée sur le substrat (1) et une couche amorphe (22) formée sur la couche métallique (21), la couche métallique (21) et la couche amorphe (22) formant ensemble la pluralité de motifs (201), de sorte qu'une partie du substrat (1) soit découvert ; à former une couche de nitrure métallique (3) sur la couche composite (2) ; à retirer la couche amorphe (22) pour former une pluralité de cavités ; et à retirer le substrat (1) pour former une structure semi-conductrice. La formation de la couche composite (2) sur le substrat (1) et la formation de la couche de nitrure métallique (3) sur la couche composite (2) permettent à la couche composite (2) d'inhiber le glissement ou la dislocation pendant la croissance épitaxiale, ce qui améliore la qualité de la couche de nitrure métallique (3) ainsi que les performances de la structure semi-conductrice.
PCT/CN2020/087039 2020-04-26 2020-04-26 Procédé de fabrication de structure semi-conductrice et structure semi-conductrice WO2021217301A1 (fr)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1441982A (zh) * 2000-06-19 2003-09-10 日亚化学工业株式会社 氮化物半导体基板及制法和使用该基板的氮化物半导体装置
US7008839B2 (en) * 2002-03-08 2006-03-07 Matsushita Electric Industrial Co., Ltd. Method for manufacturing semiconductor thin film
CN101055895A (zh) * 2007-05-11 2007-10-17 北京工业大学 钙钛矿结构镧锰氧化物/氧化锌异质p－n结及制备方法
CN102644050A (zh) * 2012-04-16 2012-08-22 西安理工大学 一种多孔AlN/GaN薄膜的制备方法
CN103219361B (zh) * 2012-01-18 2017-05-10 精工爱普生株式会社 半导体基板及半导体基板的制造方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1441982A (zh) * 2000-06-19 2003-09-10 日亚化学工业株式会社 氮化物半导体基板及制法和使用该基板的氮化物半导体装置
US7008839B2 (en) * 2002-03-08 2006-03-07 Matsushita Electric Industrial Co., Ltd. Method for manufacturing semiconductor thin film
CN101055895A (zh) * 2007-05-11 2007-10-17 北京工业大学 钙钛矿结构镧锰氧化物/氧化锌异质p－n结及制备方法
CN103219361B (zh) * 2012-01-18 2017-05-10 精工爱普生株式会社 半导体基板及半导体基板的制造方法
CN102644050A (zh) * 2012-04-16 2012-08-22 西安理工大学 一种多孔AlN/GaN薄膜的制备方法

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