WO2021212818A1 - Amplificateur doherty à large bande - Google Patents

Amplificateur doherty à large bande Download PDF

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Publication number
WO2021212818A1
WO2021212818A1 PCT/CN2020/129805 CN2020129805W WO2021212818A1 WO 2021212818 A1 WO2021212818 A1 WO 2021212818A1 CN 2020129805 W CN2020129805 W CN 2020129805W WO 2021212818 A1 WO2021212818 A1 WO 2021212818A1
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Prior art keywords
amplifier
output
auxiliary
modulation circuit
main
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PCT/CN2020/129805
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English (en)
Chinese (zh)
Inventor
张勇
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苏州远创达科技有限公司
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Publication of WO2021212818A1 publication Critical patent/WO2021212818A1/fr

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
    • H03F1/04—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in discharge-tube amplifiers
    • H03F1/06—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in discharge-tube amplifiers to raise the efficiency of amplifying modulated radio frequency waves; to raise the efficiency of amplifiers acting also as modulators
    • H03F1/07—Doherty-type amplifiers

Definitions

  • the invention relates to a high-performance Doherty amplifier, in particular to a wideband Doherty amplifier.
  • the power amplifier has a vital influence on the overall performance of the communication system.
  • the system's demand for fast data transmission is increasing. This requires the use of more complex modulation methods, which in turn requires the communication signal to have a higher peak-to-average ratio, so the linearity of the power amplifier is proposed higher requirement.
  • the power fallback method is usually used to meet its linearity requirements, but this will sacrifice a large amount of efficiency, which not only increases the operating cost of wireless communication, but also worsens the instability of the system due to heat dissipation and other issues. sex.
  • the Doherty amplifier technology has the advantages of simple structure and easy implementation, especially the advantages of maintaining a high level of efficiency in the case of power back-off, and a good balance between efficiency and linearity. But the price is: Doherty amplifier development requires very precise design.
  • the electrical parameters of the components contained in the Doherty amplifier for example, ceramic capacitors and their position on the printed circuit board (PCB)
  • PCB printed circuit board
  • the ground contact of the main-level and peak-level packages and their position between the input microchip and output microchip of the PCB cannot be reproduced accurately enough, and the gap between the two amplification branches is increased.
  • the phase is inconsistent. As a result, it has an adverse effect on the accuracy of the Doherty amplifier parameter values, which leads to a lower production yield.
  • the traditional Doherty amplifier has a large circuit area due to the large number of components involved in the matching, which is not easy to integrate, and the loss is also large.
  • the Doherty amplifier architecture has the following shortcomings:
  • the input has no phase fitting network, which affects the Doherty synthesis effect. It will cause the deterioration of the AMAM curve within a certain bandwidth.
  • the purpose of the present invention is to provide a wideband Doherty amplifier, the main amplifier and the auxiliary amplifier are integrated with a harmonic modulation circuit connected to the main amplifier or the auxiliary amplifier on the chip, which saves the circuit area and simplifies the circuit.
  • the design also solves the difficult problem of harmonic circuits in high-power and high-frequency applications, and improves the efficiency of high-power and high-frequency power amplifier transistors.
  • a wideband Doherty amplifier including:
  • the chips of the main amplifier and the auxiliary amplifier are respectively integrated with a harmonic modulation circuit connected to the main amplifier or the auxiliary amplifier;
  • the output node of the main amplifier and the output node of the auxiliary amplifier are connected through a series inductor, and the amplifiers are connected through at least one series inductor;
  • the output node of the main amplifier and/or the auxiliary amplifier and/or the intermediate node of the series inductor is connected to a parasitic parameter balancing network
  • the harmonic modulation circuit includes an input harmonic modulation circuit connected to the output terminal of the amplifier and/or an output harmonic modulation circuit connected to the output terminal of the amplifier.
  • the input harmonic modulation circuit is an input series resonance trap circuit
  • the output harmonic modulation circuit is an output low-pass harmonic impedance modulation circuit
  • the input harmonic modulation circuit includes a first inductor, and a grounding capacitor connected to the first inductor.
  • the output harmonic modulation circuit includes a second inductor, and a grounding capacitor connected to the second inductor.
  • the parasitic parameter balance network includes a grounded balance inductance, and the output node of the main amplifier and the output node of the auxiliary amplifier are connected to a DC blocking capacitor and then connected through a series inductor.
  • the parasitic parameter balance network includes a balance inductance and a grounded DC blocking capacitor connected in series with the balance inductance.
  • the output node of the first auxiliary amplifier or the last auxiliary amplifier is connected to an impedance converter as an output.
  • the main transistor amplifier and the auxiliary transistor amplifier integrate the on-chip harmonic modulation circuit, which saves the circuit area and simplifies the circuit design. At the same time, it solves the problem that the harmonic circuit in high-power and high-frequency applications is difficult to realize. Improve the efficiency of high-power and high-frequency power amplifier transistors.
  • Three groups of parasitic parameter balancing networks, main circuit, auxiliary circuit, and inter-stage, are adopted to absorb and balance transistor parasitic parameters together, which can maximize the working bandwidth and efficiency of the Doherty circuit.
  • the matching components of the circuit are reduced, the area is saved, the integration is easy, and the loss of the entire circuit can be reduced, and the performance of the Doherty circuit can be improved.
  • This kind of Doherty amplifier can be equipped with a phase matching network (PBN) at the input to fit the output phase curve, making the combined AMAM characteristics better and suitable for broadband applications.
  • PBN phase matching network
  • Fig. 1 is a circuit structure diagram of an existing Doherty amplifier
  • Figure 2 is a schematic block diagram of a Doherty amplifier according to a preferred embodiment of the present invention.
  • Fig. 3 is a schematic block diagram of a transistor amplifier with an integrated harmonic modulation circuit on a chip according to the present invention
  • FIG. 4 is a schematic block diagram of a Doherty amplifier according to another embodiment of the present invention.
  • Fig. 5 is a schematic block diagram of a Doherty amplifier according to another embodiment of the present invention.
  • Fig. 6 is a schematic block diagram of a Doherty amplifier according to another embodiment of the present invention.
  • Fig. 7 is a schematic block diagram of a Doherty amplifier according to another embodiment of the present invention.
  • Fig. 8 is a schematic block diagram of a Doherty amplifier according to another embodiment of the present invention.
  • Fig. 9 is a schematic block diagram of a Doherty amplifier according to another embodiment of the present invention.
  • FIG. 10 is a schematic diagram of a design example of a transistor amplifier with an integrated harmonic modulation circuit on a chip according to the present invention.
  • FIG. 11 is the comparison result of the amplitude simulation value of the input end harmonic impedance between the architecture of the present invention and the existing architecture;
  • FIG. 12 is a comparison value of S parameters between the Smith chart of the architecture of the present invention and the existing architecture
  • FIG. 13 is a schematic diagram of the optimal impedance matching degree between the architecture of the present invention and the existing architecture.
  • a wideband Doherty amplifier includes: input (RF in), output (RF out), a main transistor amplifier M, and an auxiliary transistor amplifier P.
  • input (RF in), output (RF out), a main transistor amplifier M, and an auxiliary transistor amplifier P input (RF in), output (RF out), a main transistor amplifier M, and an auxiliary transistor amplifier P.
  • auxiliary transistor amplifier P input (RF in), output (RF out), a main transistor amplifier M, and an auxiliary transistor amplifier P.
  • the main transistor amplifier and the auxiliary transistor amplifier chip integrate the input harmonic modulation circuit HTi and the output harmonic modulation circuit HTo, that is, the transistor amplifier, the input harmonic modulation circuit HTi and the output harmonic modulation circuit HTo are integrated on the same substrate, as shown in the figure 9 shown.
  • the gate input ends of the main transistor amplifier and the auxiliary transistor amplifier are connected to the input harmonic modulation circuit HTi, and the drain output ends of the main transistor amplifier and the auxiliary transistor amplifier are connected to the output harmonic modulation circuit HTo, as shown in FIG. 3.
  • the input harmonic modulation circuit may be an input series resonance trap circuit, and the output harmonic modulation circuit is an output low-pass harmonic impedance modulation circuit.
  • the input harmonic modulation circuit HTi includes a first inductor 10 and a grounding capacitor 11 connected to the first inductor 10.
  • the inductance and capacitance of the input harmonic modulation circuit HTi are calculated by the following formula:
  • f 0 is the frequency of the second harmonic
  • L is the series inductance
  • C is the series capacitance
  • the output harmonic modulation circuit HTo includes a second inductor 20 and a grounding capacitor 21 connected to the second inductor 20.
  • the output harmonic modulation circuit HTo maximizes the output impedance of the transistor amplifier at the second harmonic.
  • the comparison result of the amplitude simulation value of the harmonic impedance of the input end of the present invention and the input end of the original architecture is shown in Fig. 11, and the comparison value of the S-parameter of the Smith chart is shown in Fig. 12.
  • the present invention well reduces the harmonic impedance in a wider bandwidth, and better realizes the short-circuit effect of the second harmonic, thereby improving the efficiency of the power amplifier.
  • the output node of the main transistor amplifier M is connected to the output node of the auxiliary transistor amplifier P through the inter-stage series inductances Lh1 and Lh2. Of course, it can also be connected through one inter-stage series inductance, or more than one, generally two.
  • the output node of the main amplifier and/or the intermediate node of the auxiliary amplifier and/or the series inductance is connected to the parasitic parameter balance network, which includes the main transistor amplifier parasitic parameter balance network, the auxiliary transistor parasitic parameter balance network, and the inter-stage parasitic parameter balance The internet.
  • the parasitic parameter balance network which includes the main transistor amplifier parasitic parameter balance network, the auxiliary transistor parasitic parameter balance network, and the inter-stage parasitic parameter balance The internet.
  • the intermediate point of the inter-stage series inductances Lh1 and Lh2 is connected to the parasitic parameter balancing network 010, the output of the main transistor amplifier is connected to the parasitic parameter balancing network 100 at the same time, the output of the auxiliary transistor amplifier is connected to the parasitic parameter balancing network 001, and the auxiliary transistor amplifier
  • the output node of P is connected to an output impedance transformer (AIT) as the output (RF out).
  • the characteristic impedance of the impedance converter (AIT) can be selected according to the principle of symmetry between the main and auxiliary circuits, or according to the principle of asymmetrical between the main and auxiliary circuits.
  • the parasitic parameter balance network 100, 010, 001 all include a balance inductance and a grounded DC blocking capacitor in series with the balance inductance.
  • the output terminal of the main transistor amplifier M is connected to the balancing inductance Lsm of the parasitic parameter balancing network 100, and the other end of the balancing inductance Lsm forms a series circuit with the grounded DC blocking capacitor Csm.
  • the output terminal of the auxiliary transistor amplifier P is connected to the balancing inductance Lsp of the parasitic parameter balancing network 001, and the other end of the balancing inductance Lsp forms a series circuit with the grounded DC blocking capacitor Csp.
  • the intermediate point of the inter-stage series inductances Lh1 and Lh2 is connected to the balancing inductance Lsc of the parasitic parameter balancing network 010, and the other end of the balancing inductance Lsc forms a series circuit with the grounded DC blocking capacitor Csc.
  • the balance inductance in the parasitic parameter balance network and the inter-stage series inductances Lh1 and Lh2 can be realized by bonding wire inductance, planar inductance, or alternatively by distributed high-resistance wire or discrete wire wound inductance.
  • the output node of the auxiliary transistor amplifier P is connected to the output impedance converter AIT as an output.
  • the output impedance converter AIT is used to transform the impedance of the doherty circuit to a certain value, for example, 50 Ohm.
  • the inter-stage series inductances Lh1 and Lh2, the three parasitic parameter balancing networks 100, 010, and 001, and the parasitic parameters of the main transistor amplifier and the auxiliary transistor amplifier together form a Doherty inverter circuit, which plays a role of high impedance traction in the Doherty circuit.
  • the principle of high resistance traction is based on the following formula:
  • n is the coefficient
  • Ropt is the impedance at the best output performance of the transistor
  • X L is the load reactance.
  • the input (RF in) is connected to the power distribution unit PD.
  • the two output ends of the power distribution unit PD are respectively connected to the input ends of the main input matching network IMM and the auxiliary input matching network IMP, and the power is distributed to the main and auxiliary branches. road.
  • the output end of the main input matching network IMM is connected to the main transistor M to form impedance matching.
  • the output end of the auxiliary input matching network IMP is connected to the input end of the phase equalization network PBN to form impedance matching, and the output end of the phase equalization network PBN is connected to the input end of the auxiliary transistor to form impedance matching while realizing balanced phase shift.
  • the present invention can better realize the optimal impedance matching of the Doherty power amplifier, thereby improving the power and efficiency of the Doherty circuit.
  • the output terminal of the main transistor amplifier M is first connected to the DC blocking capacitor Csm, and the output terminal of the auxiliary transistor amplifier P is first connected to the DC blocking capacitor Csp, and then connected through the inter-stage series inductors Lh1 and Lh2.
  • the three parasitic parameter balance networks 100, 010, and 001 can be simplified into a single grounding inductance Lsm, Lsc, Lsp, and then grounded respectively.
  • the three parasitic parameter networks 100, 010, and 001 can also be combined and applied appropriately according to the actual situation. These three parasitic parameter balance networks can be flexibly selected according to the needs of the design.
  • Three kinds As shown in Figure 5, two parasitic parameter balancing networks are connected, including the auxiliary transistor parasitic parameter balancing network 010 and the inter-stage parasitic parameter balancing network 001.
  • As shown in Figure 6 connect a parasitic parameter balancing network, such as an inter-stage parasitic parameter balancing network.
  • Figure 7 connect a parasitic parameter balancing network and an auxiliary transistor parasitic parameter balancing network 010.
  • the three-way Doherty circuit includes two auxiliary amplifiers; the chips of each main amplifier M and auxiliary amplifier (P1, P2) are respectively integrated with a harmonic modulation circuit connected to the main amplifier M or auxiliary amplifier (P1, P2); The gate input ends of the main amplifier M and the auxiliary amplifiers (P1, P2) are connected to the input harmonic modulation circuit HTi, and the drain output ends of the main amplifier M and the auxiliary amplifiers (P1, P2) are connected to the output harmonic modulation circuit HTo.
  • the output node of the main amplifier M and the output node of the auxiliary amplifier P1 are connected through two inter-stage series inductances Lh1 and Lh2, and the output node of the auxiliary amplifier P1 and the output node of the auxiliary amplifier P2 are connected through the inter-stage series inductance Lh3 and the inter-stage series inductance Lh4 connect.
  • the output node of the main amplifier M and/or the auxiliary amplifier (P1, P2) and/or the intermediate node of the series inductance are connected to the parasitic parameter balancing network. 8 and 9, the output node of the main amplifier M is connected to the parasitic parameter balancing network 100, the output node of the auxiliary amplifier P1 is connected to the parasitic parameter balancing network 001, the output node of the auxiliary amplifier P2 is connected to the parasitic parameter balancing network 002, the main amplifier M and The intermediate node of the series inductance of the auxiliary amplifier P1 is connected to the parasitic parameter balancing network 010, and the intermediate node of the series inductance of the auxiliary amplifier P1 and the auxiliary amplifier P2 is connected to the parasitic parameter balancing network 020.
  • the output impedance converter AIT can be connected to the output node of the second auxiliary amplifier P2 to form a three-way Doherty circuit.
  • the output impedance converter AIT can be connected to the output terminal of the first auxiliary amplifier P1 to form another three-way Doherty circuit.
  • the transistor amplifier T is integrated with the input harmonic modulation circuit HTi and the output harmonic modulation circuit HTo on the same active substrate.
  • the active substrate such as GaN, GaAs, LDMOS, etc. forms a monolithic integrated circuit (MMIC).
  • the input passive integrated device (IPD1) and output passive integrated device (IPD2) can be integrated on a low-cost substrate, such as GaAs, high-resistance silicon, PCB, ceramic wafers, etc.
  • Integrated passive components (IPD1, IPD2) and monolithic integrated circuits (MMIC) are mounted on the heat sink flange (Flange) together.
  • the input terminal is connected to the outside through the bonding wire BW1, and the output terminal is connected to the outside through the bonding wire BW4.
  • the input passive integrated circuit IPD1 is connected to the monolithic integrated circuit MMIC through the bonding wire BW2, and the output passive integrated circuit IPD2 is connected to the monolithic integrated circuit MMIC through BW3 and BW5.
  • MMIC monolithic integrated circuit
  • the assembling method of the architecture of the present invention can adopt the form of i-Module.
  • Traditional packaging forms such as ceramic, OMP, cavity plastic, etc., can also be used.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Amplifiers (AREA)

Abstract

L'invention concerne un amplificateur Doherty à large bande, comprenant : une entrée, une sortie, un amplificateur principal et au moins un amplificateur auxiliaire, un circuit de modulation harmonique connecté à l'amplificateur principal ou à l'amplificateur auxiliaire étant respectivement intégré sur des puces de l'amplificateur principal et de l'amplificateur auxiliaire ; un nœud de sortie de l'amplificateur principal et un nœud de sortie de l'amplificateur auxiliaire sont connectés au moyen d'un inducteur en série, et les amplificateurs sont connectés au moyen d'au moins un inducteur en série ; le nœud de sortie de l'amplificateur principal et/ou un nœud intermédiaire de l'amplificateur auxiliaire et/ou de l'inducteur en série sont connectés à un réseau d'équilibrage de paramètres parasites ; et le nœud de sortie du premier amplificateur auxiliaire ou du dernier amplificateur auxiliaire est pris comme sortie. Des éléments d'adaptation d'un circuit de Doherty peuvent être réduits à l'étendue maximale ; une meilleure performance de circuit est également obtenue ; la zone est économisée ; l'intégration est facile ; la perte de l'ensemble du circuit peut être réduite ; et la performance du circuit de Doherty est améliorée.
PCT/CN2020/129805 2020-04-24 2020-11-18 Amplificateur doherty à large bande WO2021212818A1 (fr)

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CN202010330438.1 2020-04-24
CN202010330438.1A CN111510077A (zh) 2020-04-24 2020-04-24 一种宽带多赫蒂放大器

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Cited By (1)

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CN116131778A (zh) * 2023-02-13 2023-05-16 优镓科技(北京)有限公司 一种宽带分布式功率放大器和集成电路

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* Cited by examiner, † Cited by third party
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CN111510077A (zh) * 2020-04-24 2020-08-07 苏州远创达科技有限公司 一种宽带多赫蒂放大器
CN113556091B (zh) * 2021-09-16 2021-12-07 中兴通讯股份有限公司 输出匹配模块、多尔蒂功率放大器
CN116648851A (zh) * 2021-12-22 2023-08-25 苏州华太电子技术股份有限公司 多赫蒂放大器及其输出网络、多赫蒂放大器的设计方法
CN116388699B (zh) * 2021-12-24 2024-04-30 苏州华太电子技术股份有限公司 Doherty功放装置以及功率放大系统
CN117240236A (zh) * 2022-06-08 2023-12-15 苏州华太电子技术股份有限公司 功率放大器模块及其制作方法

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US9496837B2 (en) * 2013-06-26 2016-11-15 Ampleon Netherlands B.V. Doherty amplifier
CN107332518A (zh) * 2017-06-28 2017-11-07 苏州远创达科技有限公司 一种宽带多赫蒂功率放大器
CN109818582A (zh) * 2017-12-05 2019-05-28 恩智浦美国有限公司 具有谐波陷波器的宽带功率放大器
CN110138350A (zh) * 2019-04-30 2019-08-16 杭州中科微电子有限公司 一种带谐波抑制电路的功率放大器
CN110417357A (zh) * 2018-04-26 2019-11-05 苏州远创达科技有限公司 一种紧凑型集成多赫蒂放大器
CN110417356A (zh) * 2018-04-26 2019-11-05 苏州远创达科技有限公司 一种宽带高效率多赫蒂放大器
CN111510077A (zh) * 2020-04-24 2020-08-07 苏州远创达科技有限公司 一种宽带多赫蒂放大器

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US9496837B2 (en) * 2013-06-26 2016-11-15 Ampleon Netherlands B.V. Doherty amplifier
CN107332518A (zh) * 2017-06-28 2017-11-07 苏州远创达科技有限公司 一种宽带多赫蒂功率放大器
CN109818582A (zh) * 2017-12-05 2019-05-28 恩智浦美国有限公司 具有谐波陷波器的宽带功率放大器
CN110417357A (zh) * 2018-04-26 2019-11-05 苏州远创达科技有限公司 一种紧凑型集成多赫蒂放大器
CN110417356A (zh) * 2018-04-26 2019-11-05 苏州远创达科技有限公司 一种宽带高效率多赫蒂放大器
CN110138350A (zh) * 2019-04-30 2019-08-16 杭州中科微电子有限公司 一种带谐波抑制电路的功率放大器
CN111510077A (zh) * 2020-04-24 2020-08-07 苏州远创达科技有限公司 一种宽带多赫蒂放大器

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Publication number Priority date Publication date Assignee Title
CN116131778A (zh) * 2023-02-13 2023-05-16 优镓科技(北京)有限公司 一种宽带分布式功率放大器和集成电路

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