WO2021212547A1 - 平坦化方法 - Google Patents

平坦化方法 Download PDF

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Publication number
WO2021212547A1
WO2021212547A1 PCT/CN2020/088780 CN2020088780W WO2021212547A1 WO 2021212547 A1 WO2021212547 A1 WO 2021212547A1 CN 2020088780 W CN2020088780 W CN 2020088780W WO 2021212547 A1 WO2021212547 A1 WO 2021212547A1
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layer
electrode layer
surface portion
cavity
inclined surface
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PCT/CN2020/088780
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English (en)
French (fr)
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吕丽英
黎家健
吴一雷
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瑞声声学科技(深圳)有限公司
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Publication of WO2021212547A1 publication Critical patent/WO2021212547A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H3/00—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators
    • H03H3/007—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks
    • H03H3/02—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of piezoelectric or electrostrictive resonators or networks
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
    • H03H9/15—Constructional features of resonators consisting of piezoelectric or electrostrictive material
    • H03H9/17—Constructional features of resonators consisting of piezoelectric or electrostrictive material having a single resonator
    • H03H9/171—Constructional features of resonators consisting of piezoelectric or electrostrictive material having a single resonator implemented with thin-film techniques, i.e. of the film bulk acoustic resonator [FBAR] type
    • H03H9/172—Means for mounting on a substrate, i.e. means constituting the material interface confining the waves to a volume
    • H03H9/173—Air-gaps
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
    • H03H9/46—Filters
    • H03H9/54—Filters comprising resonators of piezoelectric or electrostrictive material
    • H03H9/56—Monolithic crystal filters
    • H03H9/564—Monolithic crystal filters implemented with thin-film techniques
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N30/00—Piezoelectric or electrostrictive devices
    • H10N30/01—Manufacture or treatment
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H3/00—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators
    • H03H3/007—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks
    • H03H3/02—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of piezoelectric or electrostrictive resonators or networks
    • H03H2003/021—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of piezoelectric or electrostrictive resonators or networks the resonators or networks being of the air-gap type
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/42—Piezoelectric device making
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49005—Acoustic transducer

Definitions

  • the present invention relates to the technical field of planarization processing methods, in particular to a planarization method.
  • the CMP process has the following problems:
  • the CMP process has requirements for materials, and many materials are not suitable for the CMP process.
  • materials are not suitable for the CMP process.
  • aluminum nitride is not a common material for the CMP process, while silicon nitride is difficult to process for the CMP process.
  • the conventional CMP process planarizes the entire product to be processed during the planarization process.
  • the object of the present invention is to provide a flattening method, which is used to locally flatten products to be processed that need to be flattened, the processing process is easier to control, and the local flatness of the products to be processed can be improved.
  • a flattening method is used to flatten the surface of a product to be processed, the product to be processed is provided with a cavity filled with oxide, and the product to be processed includes a first electrode layer stacked on the cavity, A piezoelectric layer and a second electrode layer, the first electrode layer covers the cavity and includes a first inclined portion located at the periphery of the first electrode layer, the piezoelectric layer covers the first electrode layer, and Due to the first inclined portion, the piezoelectric layer forms a second inclined portion on its surface, and the second electrode layer covers part of the piezoelectric layer and includes a third inclined portion located at the periphery of the second electrode layer ,
  • the flattening method includes:
  • a passivation layer is deposited on the second electrode layer, the passivation layer covers the second electrode layer and the piezoelectric layer, and the passivation layer has a first plane portion and is disposed on the first plane portion
  • the orthographic projection in the straight direction falls outside the cavity;
  • the passivation layer is fully etched until the thickness of the passivation layer is reduced to a desired thickness.
  • the passivation layer forms the fourth inclined surface portion, and due to the existence of the second inclined surface portion, the passivation layer also forms a design A fifth inclined surface at the periphery of the second flat surface.
  • the oxide in the cavity is released to obtain a finished product.
  • the overall etching of the passivation layer is full-scale dry etching or full-scale wet etching.
  • the passivation layer is made of aluminum nitride.
  • the orthographic projection of the second electrode layer in the vertical direction falls within the cavity.
  • the product to be processed further includes a seed layer arranged between the first electrode layer and the cavity.
  • the seed layer is made of aluminum nitride.
  • the product to be processed is a filter.
  • the flattening method provided by the present invention is simple to operate, has strong practicability, is easier to control in the implementation process, can achieve better local flatness, and the flattening method is not limited to the processing to be processed.
  • the material of the product has a wide range of applications.
  • FIG. 1 is a flowchart of a planarization method according to an embodiment of the present invention
  • FIG. 2 is a schematic process diagram of a planarization method according to an embodiment of the present invention.
  • the embodiment of the present invention provides a planarization method, which is used to planarize a product 100 to be processed, such as a filter.
  • the product 100 to be processed is provided with a cavity 11 filled with oxide 15.
  • the product to be processed 100 includes a first electrode layer 12, a piezoelectric layer 13, and a second electrode layer 14 stacked on a cavity 11.
  • the first electrode layer 12 covers the cavity 11 and includes a first electrode layer 12 located at the periphery of the first electrode layer 12.
  • a slope portion 121, the piezoelectric layer 13 covers the first electrode layer 12, and due to the first slope portion 121, the piezoelectric layer 13 forms a second slope portion 131 on its surface, the second electrode layer 14 covers a part of the piezoelectric layer 13 and It includes a third inclined surface portion 141 located on the periphery of the second electrode layer 14.
  • the orthographic projection of the second electrode layer 14 in the vertical direction falls in the cavity 11, and the flattening method includes:
  • the passivation layer 17 is deposited on the second electrode layer 14.
  • the deposition method may be a PVD deposition method or a CVD deposition method. Which deposition method is used depends on the required film type and applicability.
  • the passivation layer 17 covers the second electrode layer 14 and the piezoelectric layer 13.
  • the passivation layer 17 has a first flat surface portion 171, a fourth inclined surface portion 172 provided on the periphery of the first flat surface portion 171, and extends from the fourth inclined surface portion 172
  • the formation layer 17 forms a fourth inclined surface 172, and the orthographic projection of the fourth inclined surface portion 172 in the vertical direction falls outside the cavity 11.
  • the passivation layer 17 forms a fifth inclined surface ⁇ 174.
  • the passivation layer 17 needs to be thick enough so that the orthographic projection of the fourth inclined surface portion 172 in the vertical direction falls outside the cavity 11.
  • the final thickness of the typical passivation layer 17 is generally in the range of 100nm-300nm
  • the initial thickness of the passivation layer 17 deposited by this method may be in the range of 300-1000 nm, and the specific thickness depends on the thickness of the stack (in this embodiment, the first electrode layer 12, the piezoelectric layer 13 and the second electrode
  • the overall thickness of layer 14), and the thickness of the laminated layer is determined according to actual needs.
  • the passivation layer 17 is fully etched until the thickness of the passivation layer 17 is reduced to the required thickness.
  • the required thickness of the typical passivation layer 17 is in the range of 100nm-300nm, and the passivation layer 17 is finally required
  • the thickness depends on the thickness of the laminate (in this embodiment, the overall thickness of the first electrode layer 12, the piezoelectric layer 13 and the second electrode layer 14), and the thickness of the laminate is determined according to actual needs.
  • the implementation of the overall etching of the passivation layer 17 is overall dry etching or overall wet etching.
  • the overall etching here refers to etching the passivation layer 17 at the same etching rate from top to bottom, that is, Before and after etching, the shape of the passivation layer 17 has not changed, but the thickness has changed. In this way, compared with the CMP process, the planarization area is smaller, and better uniformity control can be achieved during the planarization process.
  • the full-scale etching method does not have too many restrictions on the etching materials.
  • aluminum nitride and silicon nitride materials are not suitable for the CMP process, while the full-scale etching method does not have this limitation. Therefore, the passivation layer 17 can be made of aluminum nitride.
  • step S300 the oxide 15 in the cavity 11 is released to obtain a finished product.
  • the processed product further includes a seed layer 16 provided between the first electrode layer 12 and the cavity 11.
  • the seed layer 16 may be made of aluminum nitride.
  • the flattening method provided in this embodiment is simple to operate, has strong practicability, is easier to control during implementation, and can achieve better local flatness, and the flattening method is not limited to the material of the product 100 to be processed. wide range.

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Acoustics & Sound (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Piezo-Electric Or Mechanical Vibrators, Or Delay Or Filter Circuits (AREA)
  • Drying Of Semiconductors (AREA)
  • Weting (AREA)

Abstract

本发明提供了一种平坦化方法，能够使得待加工产品的局部平坦度更均匀，待加工产品开设有填充氧化物的腔体且包括叠设在腔体上的第一电极层、压电层和第二电极层，第一电极层覆盖腔体且包括位于第一电极层周边的第一斜面部，压电层覆盖第一电极层且在其表面形成第二斜面部，第二电极层覆盖部分压电层且包括位于第二电极层周边的第三斜面部，平坦化方法包括：在第二电极层沉积钝化层，钝化层覆盖住第二电极层和压电层，钝化层具有第一平面部、设于第一平面部外围的第四斜面部和自第四斜面部延伸的第二平面部，第一平面部沿竖直方向上的投影覆盖腔体，第四斜面部沿竖直方向的正投影落在腔体外；对钝化层全面刻蚀，直至钝化层的厚度减薄至所需厚度。

Description

平坦化方法 技术领域
本发明涉及平坦化加工方法技术领域，尤其涉及一种平坦化方法。
背景技术
现有技术中，对需要平坦化加工的产品通常是通过CMP工艺来实现。
发明概述
技术问题
CMP工艺存在以下问题：
1、CMP工艺比较复杂，成本较高。
2、CMP工艺对材料有要求，很多材料不适用CMP工艺，例如，氮化铝不是CMP工艺的常见材料，而氮化硅则对于CMP工艺来说是难以加工处理的。
3、常规CMP工艺在平坦化处理过程中是将待加工产品整个平坦化。
因此，有必要提供一种新的平坦化方法以解决以上问题。
问题的解决方案
技术解决方案
本发明的目的在于提供一种平坦化方法，其用于局部平坦化需要平坦化的待加工产品，加工过程更容易控制，能给提高待加工产品的局部平坦度。
本发明的技术方案如下：
一种平坦化方法，用于使得待加工产品的表面部分平坦化，所述待加工产品开设有填充氧化物的腔体，所述待加工产品包括叠设在腔体上的第一电极层、压电层以及第二电极层，所述第一电极层覆盖所述腔体且包括位于所述第一电极层周边的第一斜面部，所述压电层覆盖所述第一电极层，且由于所述第一斜面部，所述压电层在其表面形成第二斜面部，所述第二电极层覆盖部分所述压电层且包括位于所述第二电极层周边的第三斜面部，所述平坦化方法包括：
在所述第二电极层沉积钝化层，所述钝化层覆盖住所述第二电极层和所述压电层，所述钝化层具有第一平面部、设于所述第一平面部外围的第四斜面部、以 及自所述第四斜面部延伸的第二平面部，所述第一平面部沿竖直方向上的投影覆盖所述腔体，且所述第四斜面部沿竖直方向的正投影落在所述腔体外；
对所述钝化层全面刻蚀，直至所述钝化层的厚度减薄至所需厚度。
作为一种改进方式，由于所述第三斜面部的存在，所述钝化层形成了所述第四斜面部，且由于所述第二斜面部的存在，所述钝化层还形成了设于所述第二平面部外围的第五斜面部。
作为一种改进方式，对所述钝化层全面刻蚀之后，进行以下工序：
释放所述腔体内的氧化物，得到成品。
作为一种改进方式，所述对所述钝化层全面刻蚀的实施方式为全面干刻蚀或全面湿刻蚀。
作为一种改进方式，所述钝化层采用氮化铝材料。
作为一种改进方式，所述第二电极层沿竖直方向的正投影落在所述腔体内。
作为一种改进方式，所述待加工产品还包括设于所述第一电极层与所述腔体之间的种子层。
作为一种改进方式，所述种子层采用氮化铝材料。
作为一种改进方式，所述待加工产品为滤波器。
发明的有益效果
有益效果
本发明的有益效果在于：本发明提供的平坦化方法操作简单，实用性强，在实施过程中更容易控制，能够实现更好的局部平坦度，而且该平坦化方法还不受限于待加工产品的材料，应用范围广。
对附图的简要说明
附图说明
图1为本发明实施例的平坦化方法的流程图；
图2为本发明实施例的平坦化方法的工艺示意图。
附图说明：
100、待加工产品；11、腔体；12、第一电极层；121、第一斜面部；13、压电层；131、第二斜面部；14、第二电极层；141、第三斜面部；15、氧化物；16 、种子层；17、钝化层；171、第一平面部；172、第四斜面部；175、第二平面部；174、第五斜面部。
发明实施例
本发明的实施方式
下面结合附图和实施方式对本发明作进一步说明。
需要说明的是，本发明实施例中所有方向性指示(诸如上、下、左、右、前、后、内、外、顶部、底部......)仅用于解释在某一特定姿态(如附图所示)下各部件之间的相对位置关系等，如果该特定姿态发生改变时，则该方向性指示也相应地随之改变。
还需要说明的是，当元件被称为“固定于”或“设置于”另一个元件上时，该元件可以直接在另一个元件上或者可能同时存在居中元件。当一个元件被称为“连接”另一个元件，它可以是直接连接另一个元件或者可能同时存在居中元件。
实施例
如图1和图2所示，本发明实施例提供了一种平坦化方法，其用于平坦化待加工产品100，例如滤波器，待加工产品100开设有填充氧化物15的腔体11，待加工产品100包括叠设在腔体11上的第一电极层12、压电层13以及第二电极层14，第一电极层12覆盖腔体11且包括位于第一电极层12周边的第一斜面部121，压电层13覆盖第一电极层12，且由于第一斜面部121，压电层13在其表面形成第二斜面部131，第二电极层14覆盖部分压电层13且包括位于第二电极层14周边的第三斜面部141，第二电极层14沿竖直方向的正投影落在腔体11内，平坦化方法包括：
步骤S100，在第二电极层14沉积钝化层17，沉积方式可采用PVD沉积法或CVD沉积法，采用哪种沉积方式取决于所需的薄膜类型和适用性。钝化层17覆盖住第二电极层14和压电层13，钝化层17具有第一平面部171、设于第一平面部171外围的第四斜面部172、自第四斜面部172延伸的第二平面部175、以及设于第二平面部175外围的第五斜面部174，第一平面部171沿竖直方向上的投影覆盖腔体11，由于第三斜面部141的存在，钝化层17形成了第四斜面部172，第四斜面部172沿竖直方向的正投影落在腔体11外，而且，由于第二斜面部131的存在，钝化层17形成了第五斜面部174。在此工序中，钝化层17需要足够厚的厚度才可以使 得第四斜面部172沿竖直方向的正投影落在腔体11外，典型钝化层17的最终厚度一般是100nm-300nm范围内，本方法沉积的钝化层17初始厚度可能在300-1000nm范围内，具体的厚度取决于叠层厚度(在本实施例中即为第一电极层12、压电层13和第二电极层14整体厚度)，而叠层的厚度根据实际需要决定。
步骤S200，对钝化层17全面刻蚀，直至钝化层17的厚度减薄至所需厚度，例如典型钝化层17所需厚度是100nm-300nm范围内，钝化层17最终所需的厚度取决于叠层厚度(在本实施例中即为第一电极层12、压电层13和第二电极层14整体厚度)，而叠层的厚度根据实际需要决定。对钝化层17全面刻蚀的实施方式为全面干刻蚀或全面湿刻蚀，此处所说全面刻蚀，指的是从上到下对钝化层17以同样的蚀刻速率进行蚀刻，即蚀刻前后，钝化层17的形状并没有改变，只是厚度改变了。如此，与CMP工艺相比，平坦化面积更小，在平坦化过程中能够实现更好的均匀性控制。
进一步地，全面刻蚀的方法对蚀刻材料没有太多的限制，例如，氮化铝材料和氮化硅材料对于CMP工艺来说是不太合适的，而全面刻蚀的方法则没有这个限制，因此钝化层17可采用氮化铝材料。
步骤S300，释放腔体11内的氧化物15，得到成品。
进一步地，加工产品还包括设于第一电极层12与腔体11之间的种子层16，本实施例中，种子层16可采用氮化铝材料。
本实施例提供的平坦化方法操作简单，实用性强，在实施过程中更容易控制，能够实现更好的局部平坦度，而且该平坦化方法还不受限于待加工产品100的材料，应用范围广。
以上所述的仅是本发明的实施方式，在此应当指出，对于本领域的普通技术人员来说，在不脱离本发明创造构思的前提下，还可以做出改进，但这些均属于本发明的保护范围。

Claims (9)

  1. 一种平坦化方法，用于使得待加工产品的表面部分平坦化，所述待加工产品开设有填充氧化物的腔体，所述待加工产品包括叠设在腔体上的第一电极层、压电层以及第二电极层，所述第一电极层覆盖所述腔体且包括位于所述第一电极层周边的第一斜面部，所述压电层覆盖所述第一电极层，且由于所述第一斜面部，所述压电层在其表面形成第二斜面部，所述第二电极层覆盖部分所述压电层且包括位于所述第二电极层周边的第三斜面部，其特征在于，所述平坦化方法包括：
    在所述第二电极层沉积钝化层，所述钝化层覆盖住所述第二电极层和所述压电层，所述钝化层具有第一平面部、设于所述第一平面部外围的第四斜面部、以及自所述第四斜面部延伸的第二平面部，所述第一平面部沿竖直方向上的投影覆盖所述腔体，且所述第四斜面部沿竖直方向的正投影落在所述腔体外；
    对所述钝化层全面刻蚀，直至所述钝化层的厚度减薄至所需厚度。
  2. 根据权利要求1所述的平坦化方法，其特征在于，由于所述第三斜面部的存在，所述钝化层形成了所述第四斜面部，且由于所述第二斜面部的存在，所述钝化层还形成了设于所述第二平面部外围的第五斜面部。
  3. 根据权利要求1所述的平坦化方法，其特征在于，对所述钝化层全面刻蚀之后，进行以下工序：
    释放所述腔体内的氧化物，得到成品。
  4. 根据权利要求1所述的平坦化方法，其特征在于，所述对所述钝化层全面刻蚀的实施方式为全面干刻蚀或全面湿刻蚀。
  5. 根据权利要求1所述的平坦化方法，其特征在于，所述钝化层采用氮化铝材料。
  6. 根据权利要求1所述的平坦化方法，其特征在于，所述第二电极层 沿竖直方向的正投影落在所述腔体内。
  7. 根据权利要求1所述的平坦化方法，其特征在于，所述待加工产品还包括设于所述第一电极层与所述腔体之间的种子层。
  8. 根据权利要求7所述的平坦化方法，其特征在于，所述种子层采用氮化铝材料。
  9. 根据权利要求1所述的平坦化方法，其特征在于，所述待加工产品为滤波器。
PCT/CN2020/088780 2020-04-23 2020-05-06 平坦化方法 WO2021212547A1 (zh)

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Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1472884A (zh) * 2002-07-30 2004-02-04 ƽ 具有晶种层的改进的谐振器
US20080174389A1 (en) * 2005-06-02 2008-07-24 Yuka Mori Piezoelectric Resonator and Piezoelectric Thin-Film Filter
CN105262456A (zh) * 2015-10-09 2016-01-20 锐迪科微电子（上海）有限公司 一种高性能薄膜体声波谐振器及其制造方法
US20190199319A1 (en) * 2015-05-21 2019-06-27 Samsung Electro-Mechanics Co., Ltd. Resonator package and method of manufacturing the same
CN110912528A (zh) * 2018-09-18 2020-03-24 三星电机株式会社 体声波谐振器及制造体声波谐振器的方法
CN110957413A (zh) * 2018-09-26 2020-04-03 台湾积体电路制造股份有限公司 用于压电装置的击穿电压增强的结构与方法
CN111554800A (zh) * 2020-04-23 2020-08-18 瑞声声学科技(深圳)有限公司 平坦化方法

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001075985A1 (fr) * 2000-03-30 2001-10-11 Fujitsu Limited Actionneur piezoelectrique, son procede de fabrication et tete a jet d'encre dotee de cet actionneur
JP3945486B2 (ja) * 2004-02-18 2007-07-18 ソニー株式会社 薄膜バルク音響共振子およびその製造方法
JP2007295280A (ja) * 2006-04-25 2007-11-08 Toshiba Corp 電子素子
KR20170122539A (ko) * 2016-04-27 2017-11-06 삼성전기주식회사 체적 음향 공진기 및 이의 제조 방법

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1472884A (zh) * 2002-07-30 2004-02-04 ƽ 具有晶种层的改进的谐振器
US20080174389A1 (en) * 2005-06-02 2008-07-24 Yuka Mori Piezoelectric Resonator and Piezoelectric Thin-Film Filter
US20190199319A1 (en) * 2015-05-21 2019-06-27 Samsung Electro-Mechanics Co., Ltd. Resonator package and method of manufacturing the same
CN105262456A (zh) * 2015-10-09 2016-01-20 锐迪科微电子（上海）有限公司 一种高性能薄膜体声波谐振器及其制造方法
CN110912528A (zh) * 2018-09-18 2020-03-24 三星电机株式会社 体声波谐振器及制造体声波谐振器的方法
CN110957413A (zh) * 2018-09-26 2020-04-03 台湾积体电路制造股份有限公司 用于压电装置的击穿电压增强的结构与方法
CN111554800A (zh) * 2020-04-23 2020-08-18 瑞声声学科技(深圳)有限公司 平坦化方法

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