WO2021205882A1 - スイッチング回路、スイッチング電源、スイッチング電源のゲートドライバ回路、スイッチング電源の制御回路 - Google Patents

スイッチング回路、スイッチング電源、スイッチング電源のゲートドライバ回路、スイッチング電源の制御回路 Download PDF

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Publication number
WO2021205882A1
WO2021205882A1 PCT/JP2021/012286 JP2021012286W WO2021205882A1 WO 2021205882 A1 WO2021205882 A1 WO 2021205882A1 JP 2021012286 W JP2021012286 W JP 2021012286W WO 2021205882 A1 WO2021205882 A1 WO 2021205882A1
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Prior art keywords
transistor
switching
voltage
capacitor
control
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PCT/JP2021/012286
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English (en)
French (fr)
Japanese (ja)
Inventor
伸也 柄澤
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Rohm Co Ltd
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Rohm Co Ltd
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Priority to JP2022514392A priority Critical patent/JP7606511B2/ja
Priority to CN202180021202.2A priority patent/CN115280655A/zh
Publication of WO2021205882A1 publication Critical patent/WO2021205882A1/ja
Priority to US17/960,528 priority patent/US12512751B2/en
Anticipated expiration legal-status Critical
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—ELECTRIC POWER NETWORKS; CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J1/00—Circuit arrangements for DC mains or DC distribution networks
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/32—Means for protecting converters other than automatic disconnection
    • H02M1/322—Means for rapidly discharging a capacitor of the converter for protecting electrical components or for preventing electrical shock
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/32—Means for protecting converters other than automatic disconnection
    • H02M1/34—Snubber circuits
    • H02M1/342—Active non-dissipative snubbers
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/38—Means for preventing simultaneous conduction of switches
    • H02M1/385—Means for preventing simultaneous conduction of switches with means for correcting output voltage deviations introduced by the dead time
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of DC power input into DC power output
    • H02M3/01—Resonant DC/DC converters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of DC power input into DC power output
    • H02M3/02—Conversion of DC power input into DC power output without intermediate conversion into AC
    • H02M3/04—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters
    • H02M3/10—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of DC power input into DC power output
    • H02M3/02—Conversion of DC power input into DC power output without intermediate conversion into AC
    • H02M3/04—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters
    • H02M3/10—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
    • H02M3/158—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of DC power input into DC power output
    • H02M3/22—Conversion of DC power input into DC power output with intermediate conversion into AC
    • H02M3/24—Conversion of DC power input into DC power output with intermediate conversion into AC by static converters
    • H02M3/28—Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC
    • H02M3/325—Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC using devices of a triode or a transistor type requiring continuous application of a control signal
    • H02M3/335—Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/33569—Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only having several active switching elements
    • H02M3/33573—Full-bridge at primary side of an isolation transformer
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of DC power input into DC power output
    • H02M3/22—Conversion of DC power input into DC power output with intermediate conversion into AC
    • H02M3/24—Conversion of DC power input into DC power output with intermediate conversion into AC by static converters
    • H02M3/28—Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC
    • H02M3/325—Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC using devices of a triode or a transistor type requiring continuous application of a control signal
    • H02M3/335—Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/33569—Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only having several active switching elements
    • H02M3/33576—Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only having several active switching elements having at least one active switching element at the secondary side of an isolation transformer
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/04—Modifications for accelerating switching
    • H03K17/042—Modifications for accelerating switching by feedback from the output circuit to the control circuit
    • H03K17/04206—Modifications for accelerating switching by feedback from the output circuit to the control circuit in field-effect transistor switches
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K2217/00—Indexing scheme related to electronic switching or gating, i.e. not by contact-making or -breaking covered by H03K17/00
    • H03K2217/0036—Means reducing energy consumption
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Definitions

  • the present disclosure relates to switching circuits.
  • Switching circuits such as half-bridge circuits and full-bridge circuits are used in the field of power electronics such as DC / DC converters, AC / DC converters, and inverters.
  • a dead time is inserted to prevent a through current.
  • the longer the dead time the lower the risk of through current, but during the dead time, the current flows through the body diode or freewheeling diode (fly wheel diode) of the transistor, resulting in lower efficiency.
  • the switching transistor may be composed of a discrete element different from the control circuit that generates the pulse signal that controls the switching transistor.
  • the gate driver that drives the switching transistor may be an IC (Integrated Circuit) separate from the control circuit.
  • a transformer may be inserted between the control circuit and the switching transistor. In such a case, it is necessary to determine the dead time in consideration of the gate capacitance of the switching transistor, the delay time of the gate driver, and the delay time of the transformer. In the past, the designer of a switching circuit had to determine the dead time empirically or by trial and error in consideration of the characteristics of the peripheral circuit.
  • the present disclosure has been made in such circumstances, and one of the exemplary purposes of that aspect is to provide a switching circuit capable of optimizing dead time.
  • One aspect of the present disclosure relates to a switching circuit.
  • the switching circuit the first transistor and the second transistor, the first transistor is on, the second transistor is off, a high level voltage is generated, the second transistor is off, the second transistor is on, the low level.
  • a constant voltage is applied to the switching node where a voltage is generated and a negative voltage is generated while both the first transistor and the second transistor are off, the capacitor whose first end is connected to the switching node, and the second end of the capacitor.
  • the rectifying element to be applied, the switching controller that generates the first control pulse and the second control pulse that instruct the on / off of the first transistor and the second transistor, and the first transistor that drives the first transistor according to the first control pulse.
  • the 1-gate driver the 2nd gate driver that drives the 2nd transistor according to the 2nd control pulse, and the adjacent edges of the 1st control pulse and the 2nd control pulse according to the sense voltage between both ends of the capacitor. It includes a dead time controller that controls the delay time.
  • Another aspect of the present disclosure also relates to a switching circuit.
  • the switching circuit the first transistor and the second transistor, the first transistor is on, the second transistor is off, a high level voltage is generated, the second transistor is off, the second transistor is on, the low level.
  • a constant voltage is applied to the switching node where a voltage is generated and a negative voltage is generated while both the first transistor and the second transistor are off, the capacitor whose first end is connected to the switching node, and the second end of the capacitor.
  • the rectifying element to be applied, the switching controller that generates the first control pulse and the second control pulse that instruct the on / off of the first transistor and the second transistor, and the first transistor that drives the first transistor according to the first control pulse.
  • the delay time of at least one of the 1st gate driver, the 2nd gate driver that drives the 2nd transistor in response to the 2nd control pulse, and the 1st gate driver and the 2nd gate driver depending on the sense voltage between both ends of the capacitor is equipped with a dead time controller that controls.
  • the switching power supply is a low level during the period when the first transistor and the second transistor and the first transistor are on and the second transistor is off, a high level voltage is generated, the second transistor is off, and the second transistor is on.
  • a constant voltage is applied to the switching node where a voltage is generated and a negative voltage is generated while both the first transistor and the second transistor are off, the capacitor whose first end is connected to the switching node, and the second end of the capacitor. It includes a rectifying element to be applied, a first gate driver that drives the first transistor in response to a first control pulse, and a second gate driver that drives the second transistor in response to a second control pulse.
  • the control circuit includes a switching controller that generates a first control pulse and a second control pulse that indicate on / off of the first transistor and the second transistor, and a first control pulse according to a sense voltage between both ends of the capacitor.
  • a dead time controller for controlling the delay time between adjacent edges of the second control pulse is provided.
  • the switching power supply is a low level during the period when the first transistor and the second transistor and the first transistor are on and the second transistor is off, a high level voltage is generated, the second transistor is off, and the second transistor is on.
  • a constant voltage is applied to the switching node where a voltage is generated and a negative voltage is generated while both the first transistor and the second transistor are off, the capacitor whose first end is connected to the switching node, and the second end of the capacitor.
  • It includes a rectifying element to be applied and a switching controller that generates a control signal instructing the duty cycle of the first transistor and the second transistor so that the electric state of the switching power supply approaches a predetermined target state.
  • the gate driver circuit includes a pulse generator that generates a first control pulse and a second control pulse having a duty cycle corresponding to a control signal, a first gate driver that drives a first transistor in response to the first control pulse, and a first gate driver.
  • the delay time between the second gate driver that drives the second transistor according to the second control pulse and the adjacent edges of the first control pulse and the second control pulse is controlled according to the sense voltage between both ends of the capacitor. It is equipped with a dead time controller.
  • the length of the dead time when both transistors are turned off can be optimized.
  • FIG. 1 is a circuit diagram of a switching circuit according to the first embodiment.
  • FIG. 2 is an operation waveform diagram of the switching circuit of FIG.
  • FIG. 3 is a diagram illustrating charging of the sense capacitors Cs.
  • Figure 4 is a diagram showing the length of the dead time tau D, the relationship between the sense voltage Vs. 5 (a) to 5 (c) are diagrams for explaining the advantages of the switching circuit.
  • FIG. 6 is a flowchart of the control delay Td optimization process by the dead time controller of FIG.
  • FIG. 7 is a circuit diagram of a switching power supply according to the first embodiment.
  • FIG. 8 is an operation waveform diagram of the switching power supply of FIG. 7.
  • FIG. 9 is a switching power supply circuit according to the second embodiment.
  • FIG. 10 is a block diagram of a switching power supply according to a third embodiment.
  • FIG. 11 is an operation waveform diagram of the switching power supply of FIG.
  • FIG. 12 is a block diagram of a switching power supply according to a fourth embodiment.
  • FIG. 13 is an operation waveform diagram of the switching power supply of FIG.
  • FIG. 14 is a circuit diagram of the switching circuit according to the second embodiment.
  • FIG. 15 is a circuit diagram of the switching circuit according to the third embodiment.
  • 16 (a) to 16 (f) are diagrams showing variations of switching power supplies.
  • a high level voltage is generated during a period in which the first transistor and the second transistor are on and the second transistor is off, the second transistor is off, and the second transistor is on.
  • the switching node where the low level voltage is generated and the negative voltage is generated during the period when both the first transistor and the second transistor are off, the capacitor whose first end is connected to the switching node, and the second end of the capacitor.
  • the switching controller that generates the first control pulse and the second control pulse that instruct the on / off of the first transistor and the second transistor, and the sense voltage between both ends of the capacitor.
  • a dead time controller that controls the delay time between adjacent edges of the first control pulse and the second control pulse, a first gate driver that drives the first transistor in response to the first control pulse, and a second control pulse.
  • a second gate driver that drives the second transistor according to the above is provided.
  • the length of the dead time (also called the high impedance period) in which both the first transistor and the second transistor are turned off has a positive correlation with the voltage across the capacitor. Therefore, by monitoring the sense voltage between both ends of the capacitor, the actual length of the dead time can be detected. Then, by optimizing the delay time between the edges of the control pulse according to the detected sense voltage (that is, the length of the dead time), the length of the dead time when the first transistor and the second transistor are actually turned off. Can be optimized.
  • the first transistor and the second transistor the first transistor is on, the second transistor is off, a high level voltage is generated, the second transistor is off, and the second transistor is off.
  • a switching node that generates a low level voltage during the on period and a negative voltage during the period when both the first and second transistors are off, a capacitor whose first end is connected to the switching node, and a second of the capacitors.
  • a rectifying element that applies a constant voltage
  • a switching controller that generates a first control pulse and a second control pulse that instruct the on / off of the first transistor and the second transistor, and a first control pulse according to the first control pulse.
  • the first gate driver that drives one transistor, the second gate driver that drives the second transistor in response to the second control pulse, and the first gate driver and second gate driver according to the sense voltage between both ends of the capacitor.
  • the dead time controller includes a comparator that compares the voltage across the capacitor with a predetermined target voltage, and the delay time between edges may be increased or decreased according to the output of the comparator.
  • the comparator may be a digital comparator or an analog comparator.
  • the dead time controller may feedback control the delay time between edges so that the voltage across the capacitor approaches a predetermined target voltage.
  • the dead time controller may be configured by a digital circuit including a PI controller and a PID controller, or may be configured by an analog circuit including an error amplifier.
  • the dead time controller may independently control the delay time when the first transistor turns on and the delay time when the second transistor turns on.
  • the switching circuit may further include a discharge circuit that is connected to the capacitor and discharges the charge of the capacitor while the first transistor is on.
  • the switching power supply may further include a transformer including a primary winding and a secondary winding.
  • the first transistor may be connected to the primary winding
  • the second transistor may be connected to the secondary winding
  • the switching node may be the connection node between the secondary winding and the second transistor.
  • the first transistor and the second transistor are connected in series, and the switching node may be a connection node between the first transistor and the second transistor.
  • the "state in which the member A is connected to the member B” means that the member A and the member B are physically directly connected, and that the member A and the member B are electrically connected to each other. It also includes the case of being indirectly connected via other members, which does not substantially affect the connection state, or does not impair the functions and effects performed by the combination thereof.
  • a state in which the member C is provided between the member A and the member B means that the member A and the member C, or the member B and the member C are directly connected, and their electricity. It also includes the case of being indirectly connected via other members, which does not substantially affect the connection state, or does not impair the functions and effects produced by the combination thereof.
  • FIG. 1 is a circuit diagram of the switching circuit 100 according to the first embodiment.
  • the switching circuit 100 includes a main circuit 110, a sense capacitor Cs, a rectifier element Ds, a dead time controller 120, a switching controller 130, and gate drivers 140_1 and 140_2.
  • the main circuit 110 includes a first transistor M1 and a second transistor M2.
  • a load 2 is connected to the main circuit 110, and power is supplied to the load 2 according to whether the first transistor M1 and the second transistor M2 are turned on or off.
  • the main circuit 110 can be part of a switching power supply such as a DC / DC converter, an inverter, or a converter.
  • a switching power supply such as a DC / DC converter, an inverter, or a converter.
  • the first transistor M1 and the second transistor M2 may be directly connected or may be connected via a transformer.
  • the switching controller 130 targets at least one of the voltage, current or power, or load state supplied to the load 2, and turns on the first transistor M1 and the second transistor M2 so that the control target approaches the target value. , Off is generated as control pulses Sp1 and Sp2.
  • the gate driver 140_1 drives the first transistor M1 in response to the first control pulse Sp1. Further, the gate driver 140_2 drives the second transistor M2 in response to the second control pulse Sp2.
  • an intentional control delay Td is set between the edges of the first control pulse Sp1 and the second control pulse Sp2.
  • This control delay (this control delay may be referred to as a dead time) Td is provided to insert a period (dead time ⁇ D) in which both the first transistor M1 and the second transistor M2 are off.
  • the control delay Td is a design dead time, the actual length of the dead time ⁇ D does not always match the control delay Td. This is because the delay times for the two control pulses Sp1 and Sp2 to reach the corresponding gates are not always the same, and if the gate capacitances of the first transistor M1 and the second transistor M2 are different, the turn-on delay (turn-off delay) ) Is also different.
  • a high level voltage VH is generated during the period when the first transistor M1 is on and the second transistor M2 is off, and the low level level voltage is generated during the period when the second transistor M2 is on and the first transistor M1 is off.
  • It includes a switching node Nsw in which a negative voltage ⁇ V NEG is generated during a dead time (also referred to as a high impedance section) ⁇ D in which VL is generated and both the first transistor M1 and the second transistor M2 are turned off.
  • a positive constant voltage VREG is applied to the other end of the sense capacitor Cs via the rectifying element Ds.
  • a diode can be typically used as the rectifying element Ds, but a transistor may be used instead.
  • the constant voltage VREG may be a power supply voltage or a reference voltage.
  • the dead time controller 120 detects and optimizes the dead time ⁇ D in the switching controller 130 based on the sense voltage Vs between both ends of the sense capacitor Cs.
  • the discharge circuit 122 is connected to the sense capacitor Cs. When the discharge circuit 122 is enabled, the discharge circuit 122 discharges the electric charge of the sense capacitors Cs.
  • the discharge circuit 122 may include a switch connected in parallel with the sense capacitor Cs.
  • the switching controller 130 may control the discharge circuit 122 to enable (active) / disable (inactive) in synchronization with the on / off of the control pulses Sp1 and Sp2.
  • the discharge circuit 122 may enable the discharge circuit 122 during the on period of the first transistor M1, in other words, the period when the switching voltage Vsw becomes the high level voltage VH, and disable the discharge circuit 122 for the remaining period. ..
  • FIG. 2 is an operation waveform diagram of the switching circuit 100 of FIG.
  • Period of the first transistor M1 is turned on, the switching voltage Vsw is high-level voltage V H, the period of the second transistor M2 is turned on, the switching voltage Vsw is low level voltage V L (0V), both off dead during the time tau D, the switching voltage Vsw is a negative voltage -V NEG.
  • the magnitude of the negative voltage ⁇ V NEG depends on the type of the second transistor M2. For example, when the second transistor M2 is a Si-MOSFET, the forward voltage Vf of the body diode becomes the magnitude of the negative voltage V NEG , which is about 0.5 to 1 V.
  • the drain-source voltage V DS is a negative voltage magnitude V NEG next, the number of V.
  • V REG -V F the switching voltage
  • V F is the forward voltage of the rectifier diode Ds. Therefore, (V REG -V F)> period Vsw, is across the sense capacitor Cs, (V REG -V F) -Vsw is applied.
  • FIG. 3 is a diagram illustrating charging of the sense capacitors Cs.
  • Vsw low (0V)
  • the low level voltage to one end of the sense capacitor Cs V L (0V) is, at the other end V REG -V F is applied, so that its two ends between the voltage Vs, V the REG -V F.
  • the sense capacitor Cs is further charged and the voltage Vc between both ends thereof further rises.
  • the increase width ⁇ V at this time increases as the dead time ⁇ D becomes longer, and decreases as the dead time ⁇ D becomes shorter. That is, the sense voltage Vs becomes higher as the dead time ⁇ D becomes longer, and becomes lower as the dead time ⁇ D becomes shorter.
  • Figure 4 is a diagram showing the length of the dead time tau D, the relationship between the sense voltage Vs.
  • the sense voltage Vs increases monotonically with respect to the dead time ⁇ D , and the sense voltage Vs and the actual dead time ⁇ D are associated with each other on a one-to-one basis.
  • the dead time controller 120 determines the target value Vs (REF) to the sense voltage Vs, short control delay Td when the sense voltage Vs is higher than the target value Vs (REF), the sense voltage Vs is the target value Vs (REF ) ,
  • the length of the dead time ⁇ D can be optimized to the length ⁇ D (REF) according to the target value Vs (REF) by performing the control so as to lengthen the control delay Td when it is lower than the target value Vs (REF). ..
  • 5 (a) to 5 (c) are diagrams for explaining the advantages of the switching circuit 100.
  • 5 (a) to 5 (c) show the control pulses Sp1 and Sp2, and the actual on / off states of the first transistor M1 and the second transistor M2.
  • the second transistor M2 turns off after the off delay time ⁇ 2 elapses.
  • the control pulse Sp1 transitions from low (OFF level) to the high (on-level)
  • the first transistor M1 is turned on.
  • the delay times ⁇ 1 and ⁇ 2 are affected by the ability of the gate driver, the element sizes of the first transistor M1 and the second transistor M2, the parasitic impedance of the wiring, and the like. 5 (a) to 5 (c) show that the delay times ⁇ 1 and ⁇ 2 are different.
  • the length of the dead time ⁇ D at which both the first transistor M1 and the second transistor M2 are turned off is the target value ⁇ D (in other words, so that the sense voltage Vs approaches the target voltage Vs (REF).
  • the control delay Td which is the delay time of the level transition of the control pulses Sp1 and Sp2, is adjusted so as to approach REF).
  • FIG. 5B shows a case where ⁇ 1 > ⁇ 2.
  • feedback is applied so that the length of the dead time ⁇ D approaches the target value, and the control delay Td becomes long.
  • FIG. 5C shows a case where ⁇ 1 ⁇ 2.
  • feedback is applied so that the length of the dead time ⁇ D approaches the target value, and the control delay Td becomes short.
  • FIG. 6 is a flowchart of the control delay Td optimization process by the dead time controller 120 of FIG.
  • the dead time ⁇ D includes a dead time ⁇ D1 immediately after the turn-off of the second transistor M2 (immediately before the turn-on of the first transistor M1) and immediately after the turn-off of the first transistor M1 (of the second transistor M2).
  • the control delay Td1 is the delay time of the negative edge of the control pulse Sp2 and the positive edge of the control pulse Sp2
  • the control delay Td2 is the delay time of the negative edge of the control pulse Sp1 and the positive edge of the control pulse Sp2.
  • the initial values Td1_init and Td2_init are set in the two dead times Td1 and Td2 (S100).
  • V S sense voltage V S due to perturbation
  • fluctuation width [Delta]
  • V S sense voltage V S due to perturbation
  • is calculated (S108). In this state, the perturbation is released (S110).
  • Td1 Td1 + ⁇ td1
  • the dead time tau D (i.e. dead time Td1, Td2) is a small area, the sensitivity of the sense voltage V S for the dead time Td1, Td2 is reduced.
  • This region has a high risk of penetrating current flowing. To avoid this risk, it compares the fluctuation width [Delta] V S by perturbation with small threshold A (S112). When it is ⁇ V S ⁇ A (S112 of Y), since the through current is likely to flow, increasing the dead time Td1 (S116).
  • the dead times Td1 and Td2 may be optimized at all times during the operation of the switching circuit 100, or may be performed intermittently. Alternatively, the dead times Td1 and Td2 obtained by executing the final product including the switching circuit 100 before shipment are stored in the non-volatile memory, and the dead times Td1 and Td2 loaded from the non-volatile memory are used during operation. You may try to do so.
  • the present invention covers various devices and methods that are grasped as the block diagram or circuit diagram of FIG. 1 or derived from the above description, and are not limited to a specific configuration.
  • more specific configuration examples and examples will be described not for narrowing the scope of the present invention but for helping to understand the essence and operation of the invention and clarifying them.
  • FIG. 7 is a circuit diagram of the switching power supply 300A according to the first embodiment.
  • the switching power supply 300A is a forward converter, and the architecture of the switching circuit 100 described above is implemented.
  • the switching power supply 300A includes a transformer TRN1, four transistors MA to MD, gate drivers 340A to 340D, isolators 342A and 342B, a dead time controller 320, and a switching controller 330.
  • the primary side and the secondary side of the switching power supply 300A are insulated by a transformer TRN1 and isolators 342A and 342B.
  • the dead time controller 320 and the switching controller 330 may be integrated in a single control circuit 310A.
  • the discharge circuit 122 may also be integrated in the control circuit 310A.
  • the switching controller 330 generates control pulses SpA to SpD so that the output voltage V OUT (or another electrical state) of the switching power supply 300A approaches the target value.
  • the configuration and control method of the switching controller 330 are not particularly limited, and a known technique may be used.
  • the switching controller 330 generates a duty cycle command value in which the duty cycle, frequency, etc. are adjusted so that the output voltage V OUT approaches the target value, and generates an internal pulse dpwm according to the duty cycle command value. It is also good.
  • the control pulses SpA to SpD may be generated by giving an appropriate control delay to the positive edge and the negative edge of the internal pulse dpwm.
  • the duty cycle command value may be directly converted into control pulses SpA to SpD.
  • the gate drivers 340A and 340B receive control pulses SpA and Sp2 via the isolators 342A and 342B and drive the transistors MA and MB on the primary side.
  • the gate drivers 340C and 340D receive the control pulses SpC and SpD and drive the transistors MC and MD on the secondary side.
  • the pair of the transistor MB on the primary side and the transistor MD on the secondary side corresponds to the above-mentioned first transistor M1 and second transistor M2, and the secondary winding Ws of the transformer TRN2 and the transistor M2.
  • the connection node of is the above-mentioned switching node Nsw.
  • One end of the sense capacitor Cs is connected to this switching node Nsw.
  • the dead time controller 320 optimizes the control delay Td between the control pulses SpA and SpD based on the sense voltage Vs between both ends of the sense capacitor Cs.
  • FIG. 8 is an operation waveform diagram of the switching power supply 300A of FIG. A to D indicate the actual on / off states of the transistors MA to MD.
  • the high level of the switching voltage Vsw is V IN / N.
  • N is the winding ratio of the transformer TRN1, and the low level is the ground voltage.
  • the switching voltage Vsw becomes a negative voltage. According to the switching power supply 300A, it is possible to optimize the dead time tau D.
  • FIG. 9 is a circuit diagram of the switching power supply 300B according to the second embodiment.
  • the switching power supply 300B is a non-isolated DC / DC converter (step-down converter).
  • the buck converter includes a high-side transistor MB (switching transistor), a low-side transistor (synchronous rectifier transistor) MA, an inductor L1, a capacitor C1, a sense capacitor Cs, a rectifier element Ds, a dead time controller 320, a switching controller 330, and a gate driver 340A, 340B. To be equipped.
  • the dead time controller 320 and the switching controller 330 may be integrated in a single control circuit 210B. Further, the gate drivers 340A and 340B and the discharge circuit 122 may also be integrated in the control circuit 210B.
  • the switching controller 330 generates control pulses SpA and SpB so that the output voltage V OUT (or another electrical state) of the switching power supply 300B approaches the target value.
  • the configuration and control method of the switching controller 330 are not particularly limited, and a known technique may be used.
  • the switching controller 330 generates a duty cycle command value in which the duty cycle, frequency, etc. are adjusted so that the output voltage V OUT approaches the target value, and generates an internal pulse dpwm according to the duty cycle command value. It is also good.
  • the control pulses SpA and SpB may be generated by giving an appropriate control delay to the positive edge and the negative edge of the internal pulse dpwm.
  • the duty cycle command value may be directly converted into control pulses SpA and SpB.
  • the gate drivers 340A and 340B drive the transistors MA and MB according to the control pulses SpA and Sp2.
  • the high-side transistor MB and the low-side transistor MA correspond to the above-mentioned first transistor M1 and second transistor M2, and the connection node of the two transistors is the switching node Nsw.
  • One end of the sense capacitor Cs is connected to this switching node Nsw.
  • the dead time controller 320 optimizes the control delay Td between the control pulses SpA and SpB based on the sense voltage Vs between both ends of the sense capacitor Cs.
  • FIG. 10 is a block diagram of the switching power supply 400 according to the third embodiment.
  • This switching power supply 400 is a half-bridge converter and includes transformers TRN1, transistors MA to MD, capacitors C1 to C3, a control circuit 410, gate drivers 422A to 422D, sense capacitors Cs1, Cs2, and rectifier elements Ds1 and Ds2.
  • the control circuit 410 includes a switching controller 412 and a dead time controller 414.
  • the switching controller 412 generates control pulses SpA to SpD so that the output voltage V OUT (or another electrical state) of the switching power supply 400 approaches the target value.
  • the control pulses SpA and SpB are input to the gate drivers 422A and 422B.
  • an isolator is added between the gate drivers 422A and 422B and the control circuit 410.
  • the pair of transistors MA and MC is switched in a complementary manner, and the pair of transistors MB and MD is switched in a complementary manner. Therefore, the first control delay Td AC is introduced between the control pulses SpA and SpC, and the second control delay Td BD is introduced between the control pulses SpB and SpD.
  • the drain of the transistor MC is the first switching node Nsw1, and the capacitor Cs1 and the diode Ds1 are connected to it.
  • the dead time controller 414 adjusts the first control delay Td AC based on the sense voltage Vs1 generated in the capacitor Cs1.
  • the drain of the transistor MD is the second switching node Nsw2, and the capacitor Cs2 and the diode Ds2 are connected to each other.
  • the dead time controller 414 adjusts the second control delay Td BD based on the sense voltage Vs2 generated in the capacitor Cs2.
  • the switching controller 412 includes a pulse width modulator 416 and a pulse generator 418.
  • the pulse width modulator 416 feedback-controls the duty cycle Don so that the feedback signal corresponding to the output voltage V OUT (or another electrical state) of the switching power supply 400 approaches the target value.
  • a signal corresponding to the duty cycle Don is supplied from the pulse width modulator 416 to the pulse generation unit 418.
  • the pulse generation unit 418 generates control pulses SpA to SpD based on the duty cycle Don generated by the pulse width modulator 416 and the control delays Td AC and Td BD.
  • the configuration and control method of the switching controller 412 are not particularly limited, and a known technique may be used.
  • FIG. 11 is an operation waveform diagram of the switching power supply of FIG.
  • the duty cycle Don is feedback controlled by the pulse width modulator 416.
  • pwm_p1 and pwm_p2 represent pulse signals having a duty cycle Don.
  • ⁇ 12 represents the delay time from the occurrence of the edge of the control pulse SpB (or SpA) to the occurrence of the change in the switching voltage Vsw2 (or Vsw1) based on the edge.
  • This delay time may include a driver 422B (422A) delay, a transistor MB turn-on time, a transformer TRN delay, and the like.
  • the dead time ⁇ BD1 at which the switching voltage Vsw2 becomes a negative voltage is the total time of the control delay Td BD1 and the delay time ⁇ 12.
  • ⁇ BD1 Td BD1 + ⁇ 12
  • the dead time ⁇ BD2 is the time obtained by subtracting the delay time ⁇ 12 from the control delay Td BD2.
  • ⁇ BD2 Td BD2- ⁇ 12
  • the dead time controller 414 optimizes the control delay Td BD1 based on the sense voltage Vs2 according to the length of ⁇ BD1. Further, the dead time controller 414 optimizes the control delay Td BD2 based on the sense voltage Vs2 according to the length of ⁇ BD2.
  • the dead time ⁇ AC1 at which the switching voltage Vsw1 becomes a negative voltage is the total time of the control delay Td AC1 and the delay time ⁇ 12.
  • ⁇ AC1 Td AC1 + ⁇ 12
  • the dead time ⁇ AC2 is the time obtained by subtracting the delay time ⁇ 12 from the control delay Td AC2.
  • ⁇ AC2 Td AC2- ⁇ 12
  • the dead time controller 414 optimizes the control delay Td AC1 based on the sense voltage Vs1 according to the length of ⁇ AC1. Further, the dead time controller 414 optimizes the control delay Td AC2 based on the sense voltage Vs1 according to the length of ⁇ AC2.
  • FIG. 12 is a block diagram of the switching power supply 400A according to the fourth embodiment.
  • the switching power supply 400A is a half-bridge converter, and the locations of the switching nodes are different.
  • the tap of the secondary winding of the transformer TRN and the connection node of the inductor L1 are switching nodes.
  • the switching power supply 400A includes a capacitor Cs and a rectifying element Ds connected to the switching node Nsw.
  • the dead time controller 414 of the control circuit 410A controls the control delays Td AC and Td BD based on the sense voltage Vs generated in the capacitor Cs.
  • FIG. 13 is an operation waveform diagram of the switching power supply 400A of FIG.
  • the switching voltage Vsw is a combined voltage of the two switching voltages Vsw1 and Vsw2 shown in FIG. Therefore, the control delay Td BD1 is optimized based on the sense voltage Vs according to the length of ⁇ BD1 , and the control delay Td BD2 is optimized based on the sense voltage Vs according to the length of ⁇ BD2.
  • dead time controller 414 based on the sense voltage Vs corresponding to the length of the tau AC1, to optimize the control delay Td AC1, based on the sense voltage Vs corresponding to the length of the tau AC2, control delay Td AC2 Optimize.
  • the number of parts and the number of pins of the control circuit 410A can be reduced.
  • FIG. 14 is a circuit diagram of the switching circuit 200 according to the second embodiment.
  • the optimized delay time between two control pulses Sp1, Sp2 of the edge in the second embodiment, by controlling the delay time Td of the gate driver, the optimum dead time tau D To be.
  • the switching circuit 200 includes a main circuit 110, a dead time controller 120, a controller 130, a gate driver 140_1, and a gate driver 140_2. At least one of the gate driver 140_1 and the gate driver 140_2 has a variable delay time Td.
  • the gate driver 140_1 may be able to individually control the delay time for the positive edge of the control pulse Sp1 and the delay time for the negative edge of the control pulse Sp1.
  • the gate driver 140_2 may be able to individually control the delay time of the control pulse Sp2 with respect to the positive edge and the delay time of the control pulse Sp2 with respect to the negative edge.
  • the above is the configuration of the switching circuit 200. According to the switching circuit 200, by controlling the delay time of the gate driver, it is possible to optimize the dead time tau D.
  • FIG. 15 is a circuit diagram of a switching circuit 200 including the gate driver circuit 500 according to the third embodiment.
  • the gate driver circuit 500 includes a dead time controller 510, a pulse generation unit 520, a first gate driver 530_1, and a second gate driver 530_2.
  • the switching controller 130 includes a pulse width modulator, generates a control signal indicating the duty cycle Don of the first transistor M1 and the second transistor M2, and supplies the control signal to the gate driver circuit 500.
  • This control signal may be a pulse signal, a digital value, or an analog signal.
  • the pulse generation unit 520 generates a first control pulse Sp1 and a second control pulse Sp2 having a duty cycle corresponding to a control signal from the switching controller 130.
  • the dead time controller 510 controls the delay time between adjacent edges of the first control pulse Sp1 and the second control pulse Sp2 according to the sense voltage Vs between both ends of the capacitor Cs.
  • the first gate driver 530_1 drives the first transistor M1 in response to the first control pulse Sp1.
  • the second gate driver 530_2 drives the second transistor M2 in response to the second control pulse Sp2.
  • the topology of the switching power supply is not limited to that described in the embodiment.
  • 16 (a) to 16 (f) are diagrams showing variations of switching power supplies.
  • FIG. 16A shows a step-down converter, which was described in Example 2.
  • the architecture of the second embodiment or the third embodiment may be applied to the buck converter.
  • the delay time of the gate driver of the transistors A and B may be changed by using the connection node of the transistors A and B as a switching node.
  • FIG. 16B shows a forward converter, which has been described in Example 1.
  • the control of the dead time between the transistors A and D has been described in the first embodiment, the dead time between the transistors A and C (control delay TAC ) may be controlled instead of or in addition to the control. ..
  • the architecture of Embodiment 2 or Embodiment 3 may be applied to this forward converter.
  • FIG. 16C shows a half-bridge converter, which has been described in Examples 3 and 4.
  • the architecture of Embodiment 2 or Embodiment 3 may be applied to this half-bridge converter.
  • FIG. 16 (d) is a full bridge bridge converter.
  • This full bridge converter has the same configuration on the secondary side as the half bridge converter. On the primary side, the transistor pairs A1 and A2 are turned on at the same time, and the pairs of the transistor pairs B1 and B2 are turned on at the same time.
  • the dead time optimization can be performed in the same manner as the half-bridge converter of Example 3 or Example 4.
  • the operation of the transistor A may be read as the transistor pairs A1 and A2
  • the operation of the transistor B may be read as the transistor pairs B1 and B2.
  • Either the architecture of the first embodiment or the architecture of the second embodiment may be used for the optimization.
  • FIG. 15 (e) is a current doubler synchronous rectifier.
  • the pairs of transistors A and C operate complementarily, and the control delay Td AC between them can be optimized by using the drain of the transistor C as a switching terminal.
  • the pair of transistors B and D operates in a complementary manner, and the control delay Td BD between them can be optimized by using the drain of the transistor D as a switching terminal.
  • FIG. 15 (f) is a secondary side full bridge synchronous rectifier.
  • the transistor pairs A and C are turned on and off at the same time, and the transistor pairs B and D are turned on and off at the same time.
  • the transistor pairs E and G are turned on and off at the same time, and the transistor pairs F and H are turned on and off at the same time.
  • the drain of the transistor E is set as the switching node Nsw1
  • the control delay (dead time) Td AE between the transistor pairs A and C and the transistor pairs E and G is based on the sense voltage Vs1 corresponding to the switching voltage Vsw1. Can be optimized.
  • the drain of the transistor H is set as the switching node Nsw2, and the control delay Td BF (dead time) between the transistor pairs B and D and the transistor pairs F and H is optimized based on the sense voltage Vs2 corresponding to the switching voltage Vsw2. Can be transformed into.
  • control delays Td AE and Td BF may be optimized based on the voltage of the switching node Nsw as the connection node between the secondary side full bridge circuit and the secondary side inductor.
  • the switching circuit is used in various applications such as a motor drive circuit in addition to a power supply, and the present invention can be applied to applications other than the power supply.
  • the present invention relates to a switching circuit.
  • Switching circuit M1 1st transistor M2 2nd transistor Cs Capacitor Ds Rectifier 110 Main circuit 120 Dead time controller 122 Discharge circuit 130 Switching controller 140, 142 Gate driver 200 Switching circuit 300 Switching power supply 310 Control circuit 320 Dead time controller 330 Switching controller 340 gate driver

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