WO2021203355A1 - 一种发光二极管器件及其制备方法 - Google Patents

一种发光二极管器件及其制备方法 Download PDF

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Publication number
WO2021203355A1
WO2021203355A1 PCT/CN2020/083931 CN2020083931W WO2021203355A1 WO 2021203355 A1 WO2021203355 A1 WO 2021203355A1 CN 2020083931 W CN2020083931 W CN 2020083931W WO 2021203355 A1 WO2021203355 A1 WO 2021203355A1
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Prior art keywords
layer
light
emitting diode
area
substrate
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PCT/CN2020/083931
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English (en)
French (fr)
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蔡琳榕
杨力勋
曾信义
朱立钦
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厦门市三安光电科技有限公司
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Priority to PCT/CN2020/083931 priority Critical patent/WO2021203355A1/zh
Priority to CN202080003192.5A priority patent/CN112335060B/zh
Priority to CN202310806090.2A priority patent/CN116936702A/zh
Publication of WO2021203355A1 publication Critical patent/WO2021203355A1/zh
Priority to US17/819,693 priority patent/US20220392949A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/20—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission
    • H01L27/153—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars
    • H01L27/156—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars two-dimensional arrays
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0095—Post-treatment of devices, e.g. annealing, recrystallisation or short-circuit elimination
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/12—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a stress relaxation structure, e.g. buffer layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/44—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0016—Processes relating to electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0093—Wafer bonding; Removal of the growth substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/38—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
    • H01L33/382—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape the electrode extending partially in or entirely through the semiconductor body

Definitions

  • the present invention relates to the related technical field of light-emitting diodes, in particular to a light-emitting diode device and a preparation method thereof.
  • the light-emitting diode devices are widely used in many fields due to their high luminous efficiency.
  • the light-emitting diode devices generally include an epitaxial substrate, a semiconductor epitaxial layer, a sacrificial layer, an insulating layer, a metal layer, and a substrate.
  • the existing light-emitting diode devices have differences in the thermal expansion coefficient of the semiconductor epitaxial layer and the metal layer and the substrate, the thickness and growth temperature of the semiconductor epitaxial layer, and the thickness of the metal layer.
  • the present invention provides a light-emitting diode device and a preparation method thereof, which are used to solve the problems of stress lines and semiconductor epitaxial layer cracking caused by stress accumulation of the existing light-emitting diode devices.
  • a light-emitting diode device includes:
  • a substrate, the upper surface of the substrate includes a light-emitting area and a cutting area between the light-emitting areas;
  • the mesa structure includes a light emitting diode mesa in the light emitting area and a cutting area mesa in the cutting area.
  • the light emitting diode mesa and the cutting area mesa are arranged at intervals, and the mesa structure includes a semiconductor epitaxial layer and a semiconductor epitaxial layer. It includes a first semiconductor layer, an active layer, and a second semiconductor layer arranged in sequence.
  • the size of the light emitting diode device is not less than 24 inches ⁇ 24 inches.
  • the substrate is a permanent substrate, and the substrate is used to transfer a plurality of mesa structures grown on the epitaxial substrate.
  • a metal layer and a first insulating layer are formed between the upper surface of the substrate and the mesa structure.
  • the cutting area includes a cutting lane and a spacer area between the cutting lane and the light-emitting area, and the cutting lane is formed as a boss on the upper surface of the substrate.
  • the boss includes at least a metal layer and a first insulating layer.
  • the height of the boss in the semiconductor epitaxial layer is between 0.6 ⁇ m and 1.5 ⁇ m.
  • the cutting area further includes a semiconductor epitaxial layer, and the semiconductor epitaxial layer covers the boss and at least a part of the spacer region.
  • the cutting area further includes a semiconductor epitaxial layer located between the boss and the light emitting area and at least partially covering the spacer area.
  • a conductive layer and a sacrificial layer on the first insulating layer are further included between the mesa structure and the upper surface of the substrate.
  • the sacrificial layer of the spacer area between the scribe line and the light-emitting area is intermittently arranged, and the first insulating layer and the metal layer are distributed in a convex shape.
  • the light-emitting diode mesa further includes a conductive pillar formed in the semiconductor epitaxial layer, the conductive pillar penetrates the first semiconductor layer, the active layer and a part of the second semiconductor layer, and the conductive pillar is connected to the second semiconductor layer and the metal layer.
  • a first insulating layer is formed on the sidewall of the pillar.
  • it further includes a first electrode electrically connected to the first semiconductor layer of the light-emitting diode mesa.
  • the distance between the center of the conductive pillar and the center of the boss is between 40 ⁇ m and 120 ⁇ m.
  • a method for preparing a light emitting diode device includes the following steps:
  • a scribe line is formed at the first groove, and a spacer is formed between the scribe line and the light-emitting area;
  • the epitaxial substrate is removed, and the semiconductor epitaxial layer is etched to form a plurality of mesa structures.
  • forming a semiconductor epitaxial layer on the epitaxial substrate includes sequentially forming a second semiconductor layer, an active layer, and a first semiconductor layer on the epitaxial substrate.
  • forming a cutting line at the position of the first groove further includes the following steps:
  • a metal layer is filled in the first trench.
  • forming the conductive pillar at the second trench further includes the following steps:
  • the second trench is filled with a metal layer to form a conductive pillar connected to the second semiconductor layer.
  • the fourth trench is etched on the sacrificial layer in the spacer area between the scribe line and the light-emitting area, and the fourth trench cuts off the sacrificial layer, and the first insulating layer and the metal layer are distributed in a convex shape.
  • the mesa structure on the substrate includes the light emitting diode mesa located in the light emitting area and the cutting area mesa located in the cutting area, and the cutting area mesa and the light emitting diode mesa are arranged at intervals, which effectively reduces the area of the continuous epitaxial layer of the semiconductor and reduces the stress.
  • the continuous accumulation of light-emitting diodes reduces or eliminates the stress lines and the abnormalities that the semiconductor epitaxial layer is easy to peel and fall off, which can effectively improve the appearance yield of the light-emitting diode device and improve the product quality of the light-emitting diode device.
  • the cutting area retains the semiconductor epitaxial layer or the semiconductor epitaxial layer between the cutting area and the light-emitting area, which effectively improves the thickness of the sacrificial layer caused by the thinner sacrificial layer at the cutting channel and the spacer between the cutting channel and the light-emitting area
  • the problem that the etching solution easily penetrates and corrodes the metal layer in the subsequent process effectively reduces the possibility of damage to the cutting line.
  • the sacrificial layer of the spacer between the cutting channel and the light-emitting area is disconnected, and the first insulating layer and the metal layer are distributed in a convex shape; this convex distribution method can effectively improve the continuous direction of stress at the first insulating layer.
  • the continuous accumulation of stress at the first insulating layer is reduced, the appearance yield of the light emitting diode device is further improved, and the product quality of the light emitting diode device is improved.
  • Fig. 1 is a flow chart of a method for manufacturing a light emitting diode device in the first embodiment
  • 2-9 are schematic cross-sectional views of the manufacturing process of a light-emitting diode device in the first embodiment
  • FIG. 10 is a schematic cross-sectional view of a cutting area of the light emitting diode device in FIG. 9;
  • FIG. 11 is a schematic cross-sectional view of a light-emitting diode device in the fifth embodiment (there is a semiconductor epitaxial layer at the dicing channel);
  • FIG. 12 is a schematic cross-sectional view of a light-emitting diode device in the fifth embodiment (the space between the cutting channel and the light-emitting area has a semiconductor epitaxial layer);
  • FIG. 13 is a schematic cross-sectional view of a cutting area of a light emitting diode device in FIG. 11;
  • FIG. 14 is a schematic cross-sectional view of a cutting area of the light emitting diode device in FIG. 12.
  • the first semiconductor layer 210.
  • This embodiment provides a method for manufacturing a light emitting diode device. Referring to FIG. 1 to FIG. 9, the method includes the following steps:
  • An epitaxial substrate 100 is provided; the epitaxial substrate 100 includes a sapphire patterned substrate, a sapphire substrate, a gallium nitride substrate, an aluminum nitride substrate, a silicon carbide substrate or a silicon substrate, etc., in this embodiment Wherein, the epitaxial substrate 100 is specifically a sapphire patterned substrate or a sapphire flat substrate;
  • a semiconductor epitaxial layer 200 is formed on the epitaxial substrate 100; the semiconductor epitaxial layer 100 includes a first type semiconductor layer 210, an active region 220, and a second type semiconductor layer 230 from top to bottom.
  • the first type semiconductor layer 210 is a P-type semiconductor layer
  • the second type semiconductor layer 230 is an N-type semiconductor layer
  • the active region 220 is a multilayer quantum well layer;
  • the semiconductor epitaxial layer 200 is etched.
  • the semiconductor epitaxial layer 200 includes a light-emitting area and a cutting area between the light-emitting areas.
  • the first trench 240 is etched in the cutting area of the semiconductor epitaxial layer 200.
  • the light-emitting area of the epitaxial layer 200 etches the second trench 250, and both the first trench 240 and the second trench 250 penetrate the first semiconductor layer 210, the active layer 220 and a part of the second semiconductor layer 230.
  • a scribe line 241 is formed at the first trench 240, and a spacer is formed between the scribe line 241 and the light-emitting region; on the sidewall and bottom of the first trench 240 and the semiconductor epitaxial layer A reflective metal layer, a sacrificial layer 300, and a first insulating layer 500 are formed on the surface of the cutting area 200, and then the surface of the first insulating layer 500 inside the first trench 240 is filled with the metal layer 600; the sacrificial layer 300 inside the scribe line 241 And the first insulating layer 500 are distributed in a trapezoid shape; the first insulating layer 500 includes silicon oxide, silicon nitride, silicon oxynitride, titanium dioxide, aluminum oxide, or any combination of the foregoing.
  • the material of the metal layer 600 includes Au or an alloy of Au .
  • a conductive pillar 251 is formed in the second trench 250; a reflective metal layer, a sacrificial layer 300, and a conductive layer 400 are formed on the surface of the light-emitting area of the semiconductor epitaxial layer 200, and the second trench A first insulating layer 500 is formed on the sidewalls of 250 and the conductive layer 400, and then a metal layer 600 is filled inside the second trench 250 to form a conductive pillar 251 connected to the second semiconductor layer 230.
  • the conductive pillar 251 is a second electrode.
  • a substrate 700 is provided.
  • the preparation material of the substrate 700 is selected from GaAs, Ge, Si, Cu, Mo, WCu or MoCu; a metal layer 600 is formed on the surface of the light-emitting area and the cutting area, and the substrate 700 is combined with The semiconductor epitaxial layer 200 is bonded through the metal layer 600 using eutectic bonding.
  • the epitaxial substrate 100 is removed, and a third trench 260 penetrating the semiconductor epitaxial layer 200 is etched between the light-emitting area and the cutting area of the semiconductor epitaxial layer 200, and the third trench 260 epitaxial the semiconductor
  • the layer 200 is separately divided into a light emitting diode mesa 280 located in the light emitting area and a cutting area mesa 270 located in the cutting area, and the light emitting diode mesa 280 and the cutting area mesa 270 are arranged at intervals (as shown in Figure a); all the mesa of the cutting area is etched
  • the semiconductor epitaxial layer 200 exposes the scribe line 241 (as shown in figure b).
  • the first electrode 800 and the second insulating layer 900 are formed, and the sacrificial layer 300 between the mesa 270 of the cutting area and the mesa 280 of the light emitting diode is etched to expose the conductive layer 400.
  • a first electrode 800 is formed on 400, and then a second insulating layer 900 is formed on the surface of the light emitting diode mesa 280, the cutting area mesa 270, the first electrode 800, and the sacrificial layer 300.
  • the second insulating layer 900 covers part of the light emitting diode mesa 280 and part of the First electrode 800.
  • the material of the first electrode 800 includes Au or an alloy of Au; the material of the second insulating layer 900 includes silicon oxide, specifically including silicon oxide, silicon nitride, or silicon oxynitride.
  • a plurality of openings are etched on the sacrificial layer 300, the openings penetrate through the sacrificial layer 300, exposing the semiconductor epitaxial layer 200, and the conductive layer 400 is filled in the openings.
  • At least one opening is provided on the sacrificial layer 300 on the side of the light emitting diode mesa 280 close to the first electrode 800, and the first semiconductor layer 210 is in ohmic contact with the conductive layer 400 through the opening to realize the conduction between the conductive layer 400 and the first electrode 800.
  • the semiconductor epitaxial layer 200 is etched.
  • the semiconductor epitaxial layer 200 includes a light-emitting area and a cutting area between the light-emitting areas.
  • the first trench is etched in the cutting area of the semiconductor epitaxial layer 200 240.
  • the second trench 250 is etched in the light-emitting region of the semiconductor epitaxial layer 200.
  • the first trench 240 penetrates the semiconductor epitaxial layer 200, and the second trench 250 penetrates the first semiconductor layer 210, the active layer 220 and a part of the second semiconductor. ⁇ 230.
  • the method for manufacturing a light-emitting diode device proposed in this embodiment is mainly to simultaneously etch the first trench 240 and the second trench 250 on the light-emitting area and the cutting area, and etch the first trench 240 and the second trench at the same time.
  • the cutting lane 241 and the conductive pillar 251 are respectively formed at the positions 250, and the reflective metal layer, the sacrificial layer 300, and the first insulating layer 500 inside the cutting lane 241 are distributed in a trapezoid shape.
  • This trapezoidal distribution method can effectively improve the continuous direction of stress and reduce
  • the continuous accumulation of small stress reduces or eliminates the stress lines and the easy peeling and falling off abnormalities of the semiconductor epitaxial layer, which can effectively improve the appearance yield of the light-emitting diode device and improve the product quality of the light-emitting diode device.
  • this embodiment provides a method for manufacturing a light-emitting diode device: in step S4, a fourth trench is etched in the spacer region between the cutting line 241 and the light-emitting region, and the fourth trench penetrates The sacrificial layer 300 and the semiconductor epitaxial layer 200 are exposed; the first insulating layer 500 is filled at the fourth trench, and the first insulating layer 500 at the fourth trench is etched to the inside of the first insulating layer 500; The inside of the first insulating layer 500 is filled with the metal layer 600; so far, the sacrificial layer 300 in the spacer area between the scribe line 241 and the light-emitting area is disconnected, and the first insulating layer 500 and the metal layer 600 are distributed in a convex shape.
  • the first insulating layer 500 and the metal layer 600 are distributed in a convex shape, and the sacrificial layer 300 is disconnected.
  • This convex distribution method can effectively improve the continuous direction of stress at the first insulating layer 500 and reduce the number of stress on the first insulating layer 500.
  • the continuous accumulation of stress further improves the appearance yield of the light-emitting diode device and improves the product quality of the light-emitting diode device.
  • the same embodiment of this embodiment provides a method for manufacturing a light-emitting diode device.
  • the similarities between this embodiment and the first embodiment will not be repeated.
  • the difference is that the first trench 240, the second trench 250, and the third trench
  • the etching sequence of the groove 260 is different, specifically:
  • step S3 the semiconductor epitaxial layer 200 is etched.
  • the semiconductor epitaxial layer 200 includes a light-emitting area and a cutting area between the light-emitting areas.
  • the semiconductor epitaxial layer 200 is etched between the light-emitting area and the cutting area of the semiconductor epitaxial layer 200.
  • the third trench 260 separates the semiconductor epitaxial layer 200 into the light emitting diode mesa 280 in the light emitting area and the cutting area mesa 270 in the cutting area, and the light emitting diode mesa 280 and the cutting area mesa 270 are arranged at intervals
  • the first trench 240 is etched in the cutting area mesa 270 in the cutting area
  • the second trench 250 is etched in the light emitting diode mesa 280 in the light-emitting area.
  • the epitaxial substrate 100 is removed, and the metal layer 600, the first insulating layer 500, the conductive layer 400 and the sacrificial layer 300 are sequentially filled on the substrate 700 between the light emitting diode mesa 280 and the cutting area mesa 270, and all the cutting area mesa is etched
  • the semiconductor epitaxial layer 200 is exposed, and the scribe line 241 is exposed.
  • Steps S1, S2, S4, S5, S6, and S8 in this embodiment are the same as steps S1, S2, S4, S5, S6, and S8 in the first embodiment.
  • This embodiment has many of the same features as the first or second embodiment. The difference between this embodiment and the first or second embodiment is:
  • Step S7 The semiconductor epitaxial layer 200 on the mesa 270 of the cutting area is not etched or partially etched, and the semiconductor epitaxial layer 200 is retained at the scribe lane 241 or the space between the scribe lane 241 and the light-emitting area.
  • the semiconductor epitaxial layer 200 on the mesa 270 of the cutting area is not etched or partially etched, and the semiconductor epitaxial layer 200 is retained at the scribe lane 241 or the space between the scribe lane 241 and the light-emitting area.
  • the embodiment of the present invention provides a method for manufacturing a light-emitting diode device.
  • step S7 the epitaxial substrate 100 is removed, and the third layer penetrating the semiconductor epitaxial layer 200 is etched between the light-emitting area and the cutting area of the semiconductor epitaxial layer 200.
  • the trench 260, the third trench separates the semiconductor epitaxial layer 200 into the light emitting diode mesa 280 in the light emitting area and the cutting area mesa 270 in the cutting area, and the light emitting diode mesa 280 and the cutting area mesa 270 are arranged at intervals; for the cutting area
  • the semiconductor epitaxial layer 200 of the mesa 270 is not etched, and the semiconductor epitaxial layer 200 at the scribe line 241 remains.
  • step S7 the semiconductor epitaxial layer 200 of the mesa 270 in the cutting area is partially etched so that the semiconductor epitaxial layer 200 of the mesa 270 in the cutting area covers the cutting line 241 and at least a part of the spacer area.
  • step S7 the semiconductor epitaxial layer 200 of the mesa 270 of the cutting area is partially etched.
  • the semiconductor epitaxial layer 200 of the mesa 270 of the cutting area is located in the spacer area between the cutting channel 241 and the light emitting area, and covers At least part of the spacer.
  • the beneficial effects of the embodiments provided above are as follows: since the thickness of the sacrificial layer 300 at the scribe lane 241 and the spacer area between the scribe lane 241 and the light-emitting area is relatively thin, the thickness of the sacrificial layer 300 at the scribe lane 241 or the scribe lane 241 The semiconductor epitaxial layer 200 is still retained in the spacer between the regions, which effectively improves the problem that the etching solution easily penetrates and corrodes the metal layer 600 in the subsequent process, and reduces the possibility of damage to the cutting line 241.
  • This embodiment provides a light-emitting diode device, which can be manufactured using the manufacturing method provided in the first embodiment or the second embodiment.
  • the light emitting diode device includes:
  • a substrate 700, the upper surface of the substrate 700 includes a light-emitting area and a cutting area between the light-emitting areas;
  • the mesa structure includes a light emitting diode mesa 280 in the light emitting area and a cutting area mesa 270 in the cutting area.
  • the light emitting diode mesa 280 and the cutting area mesa 270 are arranged at intervals; the light emitting diode mesa 280 includes
  • the semiconductor epitaxial layer 200 includes a first semiconductor layer 210, an active layer 220, and a second semiconductor layer 230 arranged in sequence.
  • the substrate 700 is a permanent substrate, and the substrate 700 is used to transfer a plurality of mesa structures grown on the epitaxial substrate 100.
  • a metal layer 600 and a first insulating layer 500 are also formed between the upper surface of the substrate 700 and the mesa structure.
  • the cutting area includes a cutting line 241 and a space between the cutting line 241 and the light-emitting area.
  • the cutting line 241 is formed as a boss on the upper surface of the substrate 700, and the boss includes at least a metal layer 600 and a first insulating layer 500.
  • the height of the bump is different from the height of the semiconductor epitaxial layer 200.
  • the bump penetrates the first semiconductor layer 210, the active layer 220 and part of the second semiconductor layer 230; the light emitting diode mesa 280 includes the semiconductor epitaxial layer 200
  • the conductive pillar 251 penetrates through the first semiconductor layer 210, the active layer 220 and a part of the second semiconductor layer 230; the conductive pillar 251 is connected to the second semiconductor layer 230 and the metal layer 600, and the conductive pillar 251 is formed on the sidewall There is a first insulating layer 500.
  • the light emitting diode device further includes a first electrode 800 electrically connected to the first semiconductor layer 210 of the light emitting diode mesa 280, and a conductive layer 400 on the first insulating layer 500 is formed between the upper surface of the substrate 700 and the mesa structure.
  • the sacrificial layer 300 and the reflective metal layer, and the sacrificial layer 300 is intermittently arranged; the sacrificial layer 300 is provided with a plurality of openings penetrating the sacrificial layer 300, and the openings are filled with a conductive layer 400; at least one opening is provided near the light emitting diode mesa 280 On the sacrificial layer 300 on the side of the first electrode 800, the first semiconductor layer 210 is in ohmic contact with the conductive layer 400 through the opening to realize the conduction between the conductive layer 400 and the first electrode 800.
  • the semiconductor epitaxial layer 200 includes a III/V compound semiconductor material or a II/V compound semiconductor material.
  • the semiconductor epitaxial layer 200 is specifically a III/V compound semiconductor material, and the III/V compound semiconductor material includes a III/V compound semiconductor material.
  • Nitride compound semiconductor materials and Group III phosphide compound semiconductor materials such as GaN, GaAs, and InGaAlP.
  • the height of the semiconductor epitaxial layer 200 is between 4.5 ⁇ m and 7 ⁇ m, and the height of the conductive pillar 251 in the semiconductor epitaxial layer 200 is between 0.6 ⁇ m and 1.5 ⁇ m.
  • the cutting lane 241 and the conductive pillar 251 are both a circle structure surrounding the light emitting diode device, and the sidewalls of the cutting lane 241 are vertical sidewalls or inclined sidewalls.
  • the height of the scribe line 241 in the semiconductor epitaxial layer 200 is the same as or different from the height of the conductive pillar 251 in the semiconductor epitaxial layer 200. In this embodiment, the height of the scribe line 241 in the semiconductor epitaxial layer 200 is between 0.6 ⁇ m and 1.5 ⁇ m.
  • the distance from the center of the boss to the center of the conductive pillar 251 is between 40 ⁇ m and 120 ⁇ m. The smaller the distance between the boss and the conductive pillar 251 is, the more beneficial it is to improve the phenomenon of continuous accumulation of stress at the cutting lane 241.
  • the material of the reflective metal layer is Ag, Al, Cr and alloys thereof, and the material of the conductive layer 400 is Ag, Au, Ti, Al, Cr, Pt, TiW alloy, Ni, or any combination thereof.
  • the conductive layer 400 is Ti, Au, Cr, Pt, TiW alloys with relatively stable properties.
  • the reflective metal layer, the sacrificial layer 300 and the first insulating layer 500 inside the cutting channel 241 are distributed in a trapezoidal shape; this trapezoidal distribution method can effectively improve the continuous direction of stress, reduce the continuous accumulation of stress, and thereby reduce or eliminate the stress pattern And the abnormality that the semiconductor epitaxial layer is easy to peel and fall off; it can effectively improve the appearance yield of the light-emitting diode device, and improve the product quality of the light-emitting diode device.
  • the height of the bump is the same as the height of the semiconductor epitaxial layer 200, and the bump penetrates the entire semiconductor epitaxial layer 200; the height of the scribe line 241 is the same as the height of the semiconductor epitaxial layer 200.
  • the sacrificial layer 300 in the spacer region between the scribe line 241 and the light-emitting region is intermittently arranged, and the first insulating layer 500 and the metal layer 600 are distributed in a convex shape.
  • This convex-shaped distribution method effectively improves the continuous direction of the stress at the first insulating layer 500 and reduces the continuous accumulation of stress at the first insulating layer 500.
  • This embodiment provides a light-emitting diode device, and the light-emitting diode device can be manufactured using the manufacturing method provided in the third embodiment.
  • This embodiment has many of the same features as the fourth embodiment, and the difference between this embodiment and the fourth embodiment is:
  • the cutting area also includes a semiconductor epitaxial layer 200, which is located at the scribe lane 241 or the space between the scribe lane 241 and the light-emitting area.
  • a semiconductor epitaxial layer 200 which is located at the scribe lane 241 or the space between the scribe lane 241 and the light-emitting area.
  • the cutting area further includes a semiconductor epitaxial layer 200 covering the cutting lane 241 and the spacer area between the cutting lane 241 and the light emitting area.
  • the dicing area further includes a semiconductor epitaxial layer 200 covering the dicing lane 241 and at least part of the spacer area.
  • the cutting area further includes a semiconductor epitaxial layer 200, which is located in the spacer area between the cutting channel 241 and the light emitting area and covers at least part of the spacer area.
  • the beneficial effects of the above embodiments since the thickness of the sacrificial layer 300 at the scribe lane 241 and the interval between the scribe lane 241 and the light-emitting area is relatively thin, the distance between the scribe lane 241 or the interval between the scribe lane 241 and the light-emitting area is relatively thin.
  • the semiconductor epitaxial layer 200 is still retained in the region, which effectively improves the problem that the etching solution easily penetrates and corrodes the metal layer 600 in the subsequent process, and reduces the possibility of damage to the cutting line 241.
  • the sacrificial layer 300 in the spacer region between the scribe line 241 and the light-emitting region is disconnected, and the first insulating layer 500 and the metal layer 600 are distributed in a convex shape.
  • This convex-shaped distribution method effectively improves the continuous direction of the stress at the first insulating layer 500 and reduces the continuous accumulation of stress at the first insulating layer 500.
  • the light-emitting diode device with the semiconductor epitaxial layer 200 remaining in the space between the scribe lane 241 and the light-emitting region has some advantages compared to the light-emitting diode device with the semiconductor epitaxial layer 200 remaining at the cut 241 (FIG. 13)
  • the light-emitting diode device exposes the reflective metal layer, so it is easier to be identified by the inspection equipment.
  • the type of the second insulating layer 900 can be changed according to actual needs, and is not limited to the type described in the present invention.
  • the light-emitting diode device and the preparation method thereof provided in all the embodiments of the present invention are not only applicable to light-emitting diode devices with a vertical structure, but also applicable to other series of light-emitting diode devices such as a horizontal structure and a high-voltage structure.
  • the light emitting diode provided by the present invention has achieved the following beneficial effects:
  • the mesa structure on the substrate 700 includes a light emitting diode mesa located in the light emitting area and a cutting area mesa located in the cutting area, and the cutting area mesa and the light emitting diode mesa are arranged at intervals, which effectively reduces the area of the continuous semiconductor epitaxial layer 200 and reduces The continuous accumulation of stress is reduced, thereby reducing or eliminating the stress lines and the abnormalities of easy peeling and falling off of the semiconductor epitaxial layer 200, which can effectively improve the appearance yield of the light emitting diode device and improve the product quality of the light emitting diode device.
  • the semiconductor epitaxial layer 200 is retained in the cutting area or the semiconductor epitaxial layer 200 is retained between the cutting area and the light-emitting area, which effectively improves the thickness of the sacrificial layer due to the thinner thickness of the sacrificial layer at the cutting line 241 and the spacer between the cutting line 241 and the light-emitting area
  • the resulting problem that the etching solution easily penetrates and corrodes the metal layer 600 in the subsequent process effectively reduces the possibility of damage to the cutting channel 241.
  • the sacrificial layer 300 in the spacer area between the cutting channel 241 and the light-emitting area is disconnected, and the first insulating layer 500 and the metal layer 600 are distributed in a convex shape; this convex distribution method can effectively improve the position of the first insulating layer 500
  • the continuous direction of the stress reduces the continuous accumulation of stress at the first insulating layer 500, further improves the appearance yield of the light-emitting diode device, and improves the product quality of the light-emitting diode device.

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Abstract

本发明公开了一种发光二极管器件及其制备方法，不仅适用于垂直结构的发光二极管器件，还适用于水平结构、高压结构等其他系列的发光二极管器件。该发光二极管器件包括基板以及位于基板的上表面的多个台面结构，该台面结构包括位于发光区域的发光二极管台面和位于切割区域的切割区台面，发光二极管台面与切割区台面间隔排列，切割区域包括切割道以及间隔区，切割道内部的反射金属层、牺牲层和第一绝缘层呈梯形分布，这种梯形分布的方式有效改善了切割道处应力的连续方向，减小了应力的持续累积，进而减少或者消除了应力纹及半导体外延层易剥离、易脱落的异常，能够有效改善发光二极管器件的外观良率，提高发光二极管器件的产品品质。

Description

一种发光二极管器件及其制备方法 技术领域
本发明涉及发光二极管相关技术领域，尤其涉及一种发光二极管器件及其制备方法。
背景技术
现有的发光二极管器件由于其较高的发光效率在很多领域均有广泛的应用，发光二极管器件一般包括外延衬底、半导体外延层、牺牲层、绝缘层、金属层和基板。但是，现有的发光二极管器件存在半导体外延层与金属层及基板的热膨胀系数差异、半导体外延层厚度及生长温度差异、金属层厚度差异，这些发光二极管器件中存在的差异均会使发光二极管器件结构中产生大小不一的应力；另外，发光二极管切割区域上半导体外延层面积大，易产生持续的应力累积，从而导致在后续工艺中易出现应力纹及半导体外延层易破损、易脱落的现象，从而影响了发光二极管器件的外观良率和产品品质。
发明概述
技术问题
问题的解决方案
技术解决方案
本发明提供了一种发光二极管器件及其制备方法，用于解决现有的发光二极管器件的应力累积所导致的出现应力纹和半导体外延层破裂的问题。
为了解决上述问题，本发明采用如下的技术方案：一种发光二极管器件，包括：
基板，该基板的上表面包括发光区域以及位于发光区域之间的切割区域；
位于基板的上表面的多个台面结构，台面结构包括位于发光区域的发光二极管台面和位于切割区域的切割区台面，发光二极管台面与切割区台面间隔排列，台面结构包括半导体外延层，半导体外延层包括依次排列的第一半导体层、有源层以及第二半导体层。
可选地，发光二极管器件的尺寸不小于24英寸×24英寸。
可选地，基板为永久基板，该基板用于转移生长在外延衬底上的多个台面结构。
可选地，基板的上表面与台面结构之间还形成有金属层以及第一绝缘层。
可选地，切割区域包括切割道以及位于切割道与发光区域之间的间隔区，切割道形成为位于基板的上表面的凸台。
可选地，凸台至少包括金属层和第一绝缘层。
可选地，凸台在半导体外延层内的高度介于0.6μm～1.5μm。
可选地，切割区域还包括半导体外延层，该半导体外延层覆盖凸台及至少部分间隔区。
可选地，切割区域还包括半导体外延层，该半导体外延层位于凸台与发光区域之间并且至少部分覆盖间隔区。
可选地，台面结构与基板的上表面之间还包括位于第一绝缘层上的导电层和牺牲层。
可选地，切割道与发光区域之间的间隔区的牺牲层间断设置，且第一绝缘层和金属层呈凸字形分布。
可选地，发光二极管台面还包括形成在半导体外延层中的导电柱，导电柱贯穿第一半导体层、有源层以及部分第二半导体层，导电柱与第二半导体层和金属层连接，导电柱的侧壁上形成有第一绝缘层。
可选地，还包括与发光二极管台面的第一半导体层电性连接的第一电极。
可选地，导电柱的中心距凸台的中心的距离介于40μm～120μm。
一种发光二极管器件的制备方法，包括以下步骤：
提供外延衬底，
在外延衬底上形成半导体外延层；
刻蚀半导体外延层，半导体外延层包括发光区域和位于发光区域之间的切割区域；在切割区域刻蚀第一沟槽，在发光区域刻蚀第二沟槽；
在第一沟槽处形成切割道，切割道与发光区域之间形成间隔区；
在第二沟槽处形成导电柱；
提供基板，将基板与半导体外延层键合；
去除外延衬底，刻蚀半导体外延层，形成多个台面结构。
可选地，在外延衬底上形成半导体外延层，包括在外延衬底上依次形成第二半导体层、有源层以及第一半导体层。
可选地，在第一沟槽位置处形成切割道还包括以下步骤：
在第一沟槽的侧壁和底部以及半导体外延层的切割区域的表面依次形成反射金属层、牺牲层及第一绝缘层；
在第一沟槽中填充金属层。
可选地，在第二沟槽处形成导电柱还包括以下步骤：
在半导体外延层的发光区域形成反射金属层、牺牲层和导电层；
在导电层和第二沟槽的侧壁上形成第一绝缘层；
在第二沟槽中填充金属层，形成与第二半导体层导通的导电柱。
可选地，还包括以下步骤：
在切割道与发光区域之间的间隔区的牺牲层刻蚀第四沟槽，第四沟槽将牺牲层切断，且第一绝缘层和金属层呈凸字形分布。
发明的有益效果
有益效果
本发明的有益效果：
1、基板上的台面结构包括位于发光区域的发光二极管台面和位于切割区域的切割区台面，且切割区台面与发光二极管台面间隔排列，这有效减少了半导体连续的外延层面积，减小了应力的持续累积，进而减小或者消除了应力纹及半导体外延层易剥离、易脱落的异常，能够有效改善发光二极管器件的外观良率，提高发光二极管器件的产品品质。
2、切割区域保留半导体外延层或者且切割区域与发光区域之间保留半导体外延层，有效改善了由于切割道处和切割道与发光区域之间的间隔区的牺牲层厚度均比较薄所导致的后续工艺中刻蚀溶液易渗透腐蚀金属层的问题，有效减小了切割道破损的可能性。
3、切割道与发光区域之间的间隔区的牺牲层断开，第一绝缘层和金属层呈凸 字形分布；这种凸字形分布的方式可以有效改善第一绝缘层处应力的连续方向，减少了第一绝缘层处应力的连续累积，进一步改善了发光二极管器件的外观良率，提高了发光二极管器件的产品品质。
对附图的简要说明
附图说明
图1是实施例一中的一种发光二极管器件的制备方法的流程图；
图2～图9是实施例一中的一种发光二极管器件的制备过程的截面示意图；
图10是图9中的一种发光二极管器件的切割区域的截面示意图；
图11是实施例五中的一种发光二极管器件的截面示意图(切割道处有半导体外延层)；
图12是实施例五中的一种发光二极管器件的截面示意图(切割道与发光区域之间的间隔区有半导体外延层)；
图13是图11中的一种发光二极管器件的切割区域的截面示意图；
图14是图12中的一种发光二极管器件的切割区域的截面示意图。
图示说明：
100、外延衬底
200、半导体外延层
210、第一半导体层
220、有源层
250、第二半导体层
240、第一沟槽
250、第二沟槽
260、第三沟槽
270、切割区台面
280、发光二极管台面
241、切割道
251、导电柱
500、牺牲层
400、导电层
500、第一绝缘层
600、金属层
700、基板
800、第一电极
900、第二绝缘层
发明实施例
本发明的实施方式
下面结合附图对本发明具体实施方式的技术方案作进一步详细说明，这些实施方式仅用于说明本发明，而非对本发明的限制。
实施例一
本实施例提供了一种发光二极管器件的制备方法，参照图1～图9，该方法包括如下步骤：
S1、提供一外延衬底100；外延衬底100包括蓝宝石图形化衬底、蓝宝石衬底、氮化镓衬底、氮化铝衬底、碳化硅衬底或硅衬底等，在本实施例中，外延衬底100具体为蓝宝石图形化衬底或者蓝宝石平底衬底；
S2、如图2所示，在外延衬底100上形成半导体外延层200；该半导体外延层100自上至下包括第一类型半导体层210、有源区220和第二类型半导体层230，在本实施例中，第一类型半导体层210为P型半导体层，第二类型半导体层230为N型半导体层，有源区220为多层量子阱层；
S3、如图3所示，刻蚀半导体外延层200，半导体外延层200包括发光区域以及位于发光区域之间的切割区域，在半导体外延层200的切割区域刻蚀第一沟槽240，在半导体外延层200的发光区域刻蚀第二沟槽250，第一沟槽240和第二沟槽250均贯穿第一半导体层210、有源层220及部分第二半导体层230。
S4、如图4～图6所示，在第一沟槽240处形成切割道241，切割道241与发光区域之间形成间隔区；在第一沟槽240的侧壁和底部以及半导体外延层200的切割区域的表面形成反射金属层、牺牲层300和第一绝缘层500，然后在第一沟槽240内部的第一绝缘层500的表面填充金属层600；切割道241内部的牺牲层300和第一 绝缘层500呈梯形分布；第一绝缘层500包括氧化硅、氮化硅、氮氧化硅、二氧化钛、氧化铝或前述的任意组合之一，金属层600的材料包括Au或Au的合金。
S5、如图4～图6所示，在第二沟槽250形成导电柱251；在半导体外延层200的发光区域的表面形成反射金属层、牺牲层300和导电层400，在第二沟槽250的侧壁和导电层400上形成第一绝缘层500，然后在第二沟槽250内部填充金属层600，形成与第二半导体层230导通的导电柱251。该导电柱251为第二电极。
S6、如图7所示，提供基板700，基板700的制备材料选自GaAs、Ge、Si、Cu、Mo、WCu或MoCu；在发光区域及且切割区域的表面形成金属层600，基板700与半导体外延层200采用共晶键合方式通过金属层600键合。
S7、如图8所示，去除外延衬底100，在半导体外延层200的发光区域和切割区域之间刻蚀贯穿该半导体外延层200的第三沟槽260，第三沟槽260将半导体外延层200独立分割成位于发光区域的发光二极管台面280和位于切割区域的切割区台面270，且发光二极管台面280和切割区台面270间隔排列(如a图所示)；全部刻蚀切割区台面的半导体外延层200，暴露出切割道241(如b图所示)。
S8、如图9所示，形成第一电极800和第二绝缘层900，刻蚀切割区台面270与发光二极管台面280之间的牺牲层300，暴露出导电层400，在所暴露的导电层400上形成第一电极800，然后在发光二极管台面280、切割区台面270、第一电极800以及牺牲层300的表面形成第二绝缘层900，第二绝缘层900覆盖部分发光二极管台面280和部分第一电极800。第一电极800的材料包括Au或Au的合金；第二绝缘层900的制备材料包括硅的氧化物，具体包括氧化硅、氮化硅或氮氧化硅等。
上述牺牲层300上刻蚀多个开口，该开口贯穿牺牲层300，暴露出半导体外延层200，且开口处填充导电层400。至少一个开口设在发光二极管台面280靠近第一电极800一侧的牺牲层300上，第一半导体层210通过开口与导电层400欧姆接触，实现导电层400与第一电极800的导电。
作为可替换的实施方式，在S3步骤中，刻蚀半导体外延层200，半导体外延层200包括发光区域以及位于发光区域之间的切割区域，在半导体外延层200的切割区域刻蚀第一沟槽240，在半导体外延层200的发光区域刻蚀第二沟槽250，第一沟槽240贯穿半导体外延层200，第二沟槽250贯穿第一半导体层210、有源层220 及部分第二半导体层230。
本实施例所提出的一种发光二极管器件的制备方法主要是在发光区域和切割区域上同时刻蚀第一沟槽240和第二沟槽250，并在第一沟槽240和第二沟槽250处分别形成切割道241和导电柱251，且切割道241内部的反射金属层、牺牲层300和第一绝缘层500呈梯形分布，这种梯形分布的方式可以有效改善应力的连续方向，减小应力的持续累积，进而减小或者消除了应力纹及半导体外延层易剥离、易脱落的异常，能够有效改善发光二极管器件的外观良率，提高发光二极管器件的产品品质。
作为可替换的实施方式，本实施例提供了一种发光二极管器件的制备方法：在S4步骤中，在切割道241与发光区域之间的间隔区刻蚀第四沟槽，第四沟槽贯穿牺牲层300，并暴露出半导体外延层200；在第四沟槽处填充第一绝缘层500，并刻蚀第四沟槽处的第一绝缘层500至第一绝缘层500内部；在所暴露的第一绝缘层500的内部填充金属层600；至此，切割道241与发光区域之间的间隔区的牺牲层300断开，第一绝缘层500和金属层600呈凸字形分布。第一绝缘层500和金属层600呈凸字形分布，且牺牲层300断开，这种凸字形分布的方式可以有效改善第一绝缘层500处应力的连续方向，减少了第一绝缘层500处应力的连续累积，进一步改善了发光二极管器件的外观良率，提高了发光二极管器件的产品品质。
实施例二
本实施同样例提供了一种发光二极管器件的制备方法，本实施例与实施例一的相同之处不再赘述，不同之处在于，第一沟槽240、第二沟槽250与第三沟槽260的刻蚀顺序不同，具体地：
在步骤S3中，刻蚀半导体外延层200，半导体外延层200包括发光区域以及位于发光区域之间的切割区域，在半导体外延层200的发光区域和切割区域之间刻蚀贯穿该半导体外延层200的第三沟槽260，第三沟槽260将半导体外延层200独立分割成位于发光区域的发光二极管台面280和位于切割区域的切割区台面270，且发光二极管台面280和切割区台面270间隔排列；在切割区域的切割区台面270刻蚀第一沟槽240，在发光区域的发光二极管台面280刻蚀第二沟槽250。
S7、去除外延衬底100，在发光二极管台面280和切割区台面270之间的基板700上依次填充金属层600、第一绝缘层500、导电层400和牺牲层300，全部刻蚀切割区台面的半导体外延层200，暴露出切割道241。
本实施例的步骤S1、S2、S4、S5、S6和S8均与实施例一的步骤S1、S2、S4、S5、S6和S8相同。
实施例三
本实施例与实施例一或实施例二具有多个相同的特征，本实施例与实施例一或实施例二的区别在于：
步骤S7：对切割区台面270的半导体外延层200不进行刻蚀或部分刻蚀，在切割道241处或切割道241与发光区域之间的间隔区保留半导体外延层200，在这里，对于相同的特征就不再一一叙述，仅对区别进行叙述。
本发明实施例提供了一种发光二极管器件的制备方法，在步骤S7中，去除外延衬底100，在半导体外延层200的发光区域和切割区域之间刻蚀贯穿该半导体外延层200的第三沟槽260，第三沟槽将半导体外延层200独立分割成位于发光区域的发光二极管台面280和位于切割区域的切割区台面270，且发光二极管台面280和切割区台面270间隔排列；对切割区台面270的半导体外延层200不进行刻蚀，保留有切割道241处的半导体外延层200。
可替换的实施方式，在步骤S7中，对切割区台面270的半导体外延层200进行部分刻蚀，使切割区台面270的半导体外延层200覆盖切割道241及至少部分间隔区。
可替换的实施方式，在步骤S7中，对切割区台面270的半导体外延层200进行部分刻蚀，切割区台面270的半导体外延层200位于切割道241与发光区域之间的间隔区，且覆盖至少部分间隔区。
以上所提供的的实施方式的有益效果：由于切割道241处和切割道241与发光区域之间的间隔区的牺牲层300厚度均比较薄，因此，在切割道241处或切割道241与发光区域之间的间隔区依然保留有半导体外延层200，有效改善了后续工艺中刻蚀溶液易渗透腐蚀金属层600的问题，减小了切割道241破损的可能性。
实施例四
本实施例提供了一种发光二极管器件，该发光二极管器件可以利用实施例一或实施例二所提供的制备方法制备。
如图9所示，该发光二极管器件包括：
基板700，该基板700的上表面包括发光区域以及位于发光区域之间的切割区域；
位于基板700的上表面的多个台面结构，台面结构包括位于发光区域的发光二极管台面280和位于切割区域的切割区台面270，发光二极管台面280与切割区台面270间隔排列；发光二极管台面280包括半导体外延层200，半导体外延层200包括依次排列的第一半导体层210、有源层220以及第二半导体层230。
基板700为永久基板，该基板700用于转移生长在外延衬底100上的多个台面结构。基板700的上表面与台面结构之间还形成有金属层600和第一绝缘层500。切割区域包括切割道241以及位于切割道241与发光区域之间的间隔区，该切割道241形成为自基板700的上表面的凸台，该凸台至少包括金属层600和第一绝缘层500；该凸台的高度与半导体外延层200的高度不相同，该凸台贯穿第一半导体层210、有源层220以及部分第二半导体层230；发光二极管台面280包括形成在半导体外延层200中的导电柱251，导电柱251贯穿第一半导体层210、有源层220以及部分第二半导体层230；导电柱251与第二半导体层230以及金属层连接600，导电柱251的侧壁上形成有第一绝缘层500。
该发光二极管器件还包括与发光二极管台面280的第一半导体层210电性连接的第一电极800，基板700的上表面与台面结构之间还形成有位于第一绝缘层500上的导电层400、牺牲层300和反射金属层，且牺牲层300间断设置；牺牲层300上设有多个贯穿牺牲层300的开口，且开口处填充有导电层400；至少一个开口设在发光二极管台面280靠近第一电极800一侧的牺牲层300上，第一半导体层210通过开口与导电层400欧姆接触，实现导电层400与第一电极800的导电。
在本实施例中，该发光二极管器件的尺寸不小于24英寸×24英寸。半导体外延层200包括III/V化合物半导体材料或者基于II/V化合物半导体材料，在本实施例中，半导体外延层200具体为III/V化合物半导体材料，该III/V化合物半导体材料包括第III族氮化物化合物半导体材料和第III族磷化物化合物半导体材料，例如G aN、GaAs和InGaAlP。另外，考虑到工艺性能，该半导体外延层200的高度为4.5μm～7μm，导电柱251在半导体外延层200内的高度介于0.6μm～1.5μm。
切割道241和导电柱251均为环绕该发光二极管器件的一圈结构，切割道241的侧壁为垂直侧壁或倾斜侧壁。切割道241在半导体外延层200内的高度与导电柱251在半导体外延层200内的高度相同或不相同。在本实施例中，切割道241在半导体外延层200内的高度介于0.6μm～1.5μm。凸台的中心到导电柱251的中心的距离介于40μm～120μm。凸台与导电柱251之间的距离越小，越有利于改善切割道241处应力的连续累积的现象。
反射金属层的材料为Ag、Al、Cr及其合金等，导电层400的材料为Ag、Au、Ti、Al、Cr、Pt、TiW合金、Ni或以上任意组合。具体来说，在本实施例中，导电层400为性能较为稳定的Ti、Au、Cr、Pt、TiW合金。
切割道241内部的反射金属层、牺牲层300和第一绝缘层500梯形分布；这种梯形分布的方式可以有效改善应力的连续方向，减小应力的持续累积，进而减小或者消除了应力纹及半导体外延层易剥离、易脱落的异常；能够有效改善发光二极管器件的外观良率，提高发光二极管器件的产品品质。
作为可替换的实施方式，凸台的高度与半导体外延层200的高度相同，该凸台贯穿包括整个半导体外延层200；切割道241的高度与半导体外延层200的高度相同。
作为可替换的实施方式，如图10所示，切割道241与发光区域之间的间隔区的牺牲层300间断设置，且第一绝缘层500和金属层600呈凸字形分布。这种凸字形分布的方式有效改善第一绝缘层500处应力的连续方向，减少了第一绝缘层500处应力的连续累积。
实施例五
本实施例提供了一种发光二极管器件，该发光二极管器件可以利用实施例三所提供的制备方法制备。本实施例与实施例四具有多个相同的特征，本实施例与实施例四的区别在于：
切割区域还包括半导体外延层200，该半导体外延层200位于切割道241处或切割道241与发光区域之间的间隔区，在这里，对于相同的特征就不再一一叙述， 仅对区别进行叙述。
如图11所示，切割区域还包括半导体外延层200，该半导体外延层200覆盖切割道241和切割道241与发光区域之间的间隔区。
可替换的实施方式，切割区域还包括半导体外延层200，该半导体外延层200覆盖切割道241及至少部分间隔区。
可替换的实施方式，如图12所示，切割区域还包括半导体外延层200，该半导体外延层200位于切割道241与发光区域之间的间隔区，且覆盖至少部分间隔区。
以上实施方式的有益效果：由于切割道241处和切割道241与发光区域之间间隔区的牺牲层300厚度均比较薄，因此，在切割道241处或切割道241与发光区域之间的间隔区依然保留有半导体外延层200，有效改善了后续工艺中刻蚀溶液易渗透腐蚀金属层600的问题，减小了切割道241破损的可能性。
作为可替换的实施方式，如图13～图14所示，切割道241与发光区域之间的间隔区的牺牲层300断开，且第一绝缘层500和金属层600呈凸字形分布。这种凸字形分布的方式有效改善第一绝缘层500处应力的连续方向，减少了第一绝缘层500处应力的连续累积。
在切割道241与发光区域之间的间隔区保留有半导体外延层200的发光二极管器件(图14)相比于在切割到241处保留有半导体外延层200的发光二极管器件(图13)具有一些优势，在切割道240与发光区域之间的间隔区保留有半导体外延层200的发光二极管器件在划裂时，该发光二极管器件露出了反射金属层，因此，其更易被检测设备识别。
在本发明所有实施例中，外延衬底100、半导体外延层200、反射金属层、牺牲层300、电流阻挡层400、第一绝缘层500、金属层600、基板700、第一电极800和第二绝缘层900的种类可以根据实际需求去改变，并不仅限于本发明所描述的种类。
本发明所有实施例中所提供的发光二极管器件及其制备方法不仅适用于垂直结构的发光二极管器件，还适用于水平结构、高压结构等其他系列的发光二极管器件。本发明所提供的发光二极管取得了以下有益效果：
1、基板700上的台面结构包括位于发光区域的发光二极管台面和位于切割区域的切割区台面，且切割区台面与发光二极管台面间隔排列，这有效减少了连续的半导体外延层200的面积，减小了应力的持续累积，进而减小或者消除了应力纹及半导体外延层200易剥离、易脱落的异常，能够有效改善发光二极管器件的外观良率，提高发光二极管器件的产品品质。
2、切割区域保留半导体外延层200或者切割区域与发光区域之间保留半导体外延层200，有效改善了由于切割道241处和切割道241与发光区域之间的间隔区的牺牲层厚度均比较薄所导致的后续工艺中刻蚀溶液易渗透腐蚀金属层600的问题，有效减小了切割道241破损的可能性。
3、切割道241与发光区域之间的间隔区的牺牲层300断开，第一绝缘层500和金属层600呈凸字形分布；这种凸字形分布的方式可以有效改善第一绝缘层500处应力的连续方向，减少了第一绝缘层500处应力的连续累积，进一步改善了发光二极管器件的外观良率，提高了发光二极管器件的产品品质。
以上所述仅是本发明的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本发明技术原理的前提下，还可以做出若干改进和替换，这些改进和替换也应视为本发明的保护范围。

Claims (19)

  1. 一种发光二极管器件，其特征在于，包括：
    基板，所述基板的上表面包括发光区域以及位于所述发光区域之间的切割区域；
    位于所述基板的上表面的多个台面结构，所述台面结构包括位于所述发光区域的发光二极管台面和位于所述切割区域的切割区台面，所述发光二极管台面与所述切割区台面间隔排列，所述发光二极管台面包括半导体外延层，所述半导体外延层包括依次排列的第一半导体层、有源层以及第二半导体层。
  2. 根据权利要求1所述的发光二极管器件，其特征在于，所述发光二极管器件的尺寸不小于24英寸×24英寸。
  3. 根据权利要求1所述的发光二极管器件，其特征在于，所述基板为永久基板，所述基板用于转移生长在外延衬底上的所述多个台面结构。
  4. 根据权利要求1所述的发光二极管器件，其特征在于，所述基板的上表面与所述台面结构之间还形成有金属层以及第一绝缘层。
  5. 根据权利要求1所述的发光二极管器件，其特征在于，所述切割区域包括切割道以及位于所述切割道与发光区域之间的间隔区，所述切割道形成为位于所述基板的上表面的凸台。
  6. 根据权利要求5所述的发光二极管器件，其特征在于，所述凸台至少包括所述金属层和第一绝缘层。
  7. 根据权利要求5所述的发光二极管器件，其特征在于，所述凸台在所述半导体外延层内的高度介于0.6μm～1.5μm。
  8. 根据权利要求5所述的发光二极管器件，其特征在于，所述切割区域还包括所述半导体外延层，所述半导体外延层覆盖所述凸台及至少部分所述间隔区。
  9. 根据权利要求5所述的发光二极管器件，其特征在于，所述切割区域还包括所述半导体外延层，所述半导体外延层位于所述凸台与 发光区域之间并且至少部分覆盖所述间隔区。
  10. 根据权利要求4所述的发光二极管器件，其特征在于，所述台面结构与所述基板的上表面之间还包括位于第一绝缘层上的导电层和牺牲层。
  11. 根据权利要求10所述的发光二极管器件，其特征在于，切割道与发光区域之间的间隔区的所述牺牲层间断设置，且所述第一绝缘层和金属层呈凸字形分布。
  12. 根据权利要求11所述的发光二极管器件，其特征在于，所述发光二极管台面还包括形成在所述半导体外延层中的导电柱，所述导电柱贯穿所述第一半导体层、有源层以及部分第二半导体层，所述导电柱与所述第二半导体层和金属层连接，所述导电柱的侧壁上形成有所述第一绝缘层。
  13. 根据权利要求12所述的发光二极管器件，其特征在于，还包括与所述发光二极管台面的所述第一半导体层电性连接的第一电极。
  14. 根据权利要求12所述的发光二极管器件，其特征在于，所述导电柱的中心距凸台的中心的距离介于40μm～120μm。
  15. 一种发光二极管器件的制备方法，其特征在于，包括以下步骤：
    提供外延衬底，
    在所述外延衬底上形成半导体外延层；
    刻蚀所述半导体外延层，所述半导体外延层包括发光区域和位于发光区域之间切割区域；在切割区域刻蚀第一沟槽，在发光区域刻蚀第二沟槽；
    在所述第一沟槽处形成切割道，所述切割道与发光区域之间形成间隔区；
    在所述第二沟槽处形成导电柱；
    提供基板，将所述基板与半导体外延层键合；
    去除所述外延衬底，刻蚀所述半导体外延层，形成多个台面结构。
  16. 根据权利要求15所述的制备方法，其特征在于，在所述外延衬底上形成半导体外延层，包括在所述外延衬底上依次形成第二半导体层、有源层以及第一半导体层。
  17. 根据权利要求15所述的制备方法，其特征在于，在所述第一沟槽位置处形成切割道还包括以下步骤：
    在所述第一沟槽的侧壁和底部以及所述半导体外延层的切割区域的表面依次形成反射金属层、牺牲层及第一绝缘层；
    在所述第一沟槽中填充金属层。
  18. 根据权利要求15所述的制备方法，其特征在于，在所述第二沟槽处形成导电柱还包括以下步骤：
    在所述半导体外延层的发光区域形成反射金属层、牺牲层和导电层；
    在所述导电层和所述第二沟槽的侧壁上形成第一绝缘层；
    在所述第二沟槽中填充金属层，形成与所述第二半导体层导通的导电柱。
  19. 根据权利要求17所述的制备方法，其特征在于，还包括以下步骤：
    在所述切割道与发光区域之间的间隔区的牺牲层刻蚀第四沟槽，
    所述第四沟槽将所述牺牲层切断，且所述第一绝缘层和金属层呈凸字形分布。
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