WO2021201290A1 - Procédé de fabrication de boîtier de semi-conducteur optique, et boîtier de semi-conducteur optique - Google Patents

Procédé de fabrication de boîtier de semi-conducteur optique, et boîtier de semi-conducteur optique Download PDF

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Publication number
WO2021201290A1
WO2021201290A1 PCT/JP2021/014392 JP2021014392W WO2021201290A1 WO 2021201290 A1 WO2021201290 A1 WO 2021201290A1 JP 2021014392 W JP2021014392 W JP 2021014392W WO 2021201290 A1 WO2021201290 A1 WO 2021201290A1
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WIPO (PCT)
Prior art keywords
solder
optical semiconductor
metal layer
package substrate
surface electrode
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PCT/JP2021/014392
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English (en)
Japanese (ja)
Inventor
丸山　司
隆司 新木
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Ｄｏｗａエレクトロニクス株式会社
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Publication of WO2021201290A1 publication Critical patent/WO2021201290A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/02—Structural details or components not essential to laser action
    • H01S5/022—Mountings; Housings
    • H01S5/02208—Mountings; Housings characterised by the shape of the housings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/02—Structural details or components not essential to laser action
    • H01S5/022—Mountings; Housings
    • H01S5/0233—Mounting configuration of laser chips
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/02—Structural details or components not essential to laser action
    • H01S5/022—Mountings; Housings
    • H01S5/0235—Method for mounting laser chips
    • H01S5/02355—Fixing laser chips on mounts
    • H01S5/0237—Fixing laser chips on mounts by soldering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/04—Processes or apparatus for excitation, e.g. pumping, e.g. by electron beams
    • H01S5/042—Electrical excitation ; Circuits therefor

Definitions

  • the present invention relates to an optical semiconductor package manufacturing method and an optical semiconductor package.
  • Optical semiconductor chips are roughly classified into light emitting elements and light receiving elements.
  • examples of the optical semiconductor device using a light emitting element include a light emitting diode and a semiconductor laser.
  • the light emitting element is used in various applications depending on the wavelength of the emitted light.
  • infrared light emitting elements are used in various sensors
  • visible light emitting elements are used as lighting
  • display light sources of electronic devices and ultraviolet light emitting elements are used for sterilization, resin curing, and the like.
  • Any optical semiconductor chip is required to have a structure capable of maintaining its performance for a long period of time in various usage environments.
  • a transparent window that sufficiently transmits light matching the wavelength of the optical semiconductor chip is used to achieve high reliability for a long period of time.
  • the optical semiconductor chip is sealed by a lid made of a material (hereinafter, referred to as a translucent lid). That is, the optical semiconductor device accommodates the optical semiconductor chip in a closed space (hereinafter, referred to as a closed space) where there is no inflow of outside air.
  • a closed space where there is no inflow of outside air.
  • the structure for accommodating the optical semiconductor chip is often more complicated than that of other wavelengths.
  • Patent Document 1 when the package substrate in which the optical semiconductor element is housed in the recess and the window member are sealed, the first metal layer on the upper surface of the package substrate, the bonding material (solder), and the window member are provided. A preferable arrangement relationship with the second metal layer is disclosed.
  • Patent Document 2 shows an example of sealing a package substrate on which an optical semiconductor element is mounted and a window member (cap) having a concave shape, and describes providing a resin portion in the concave shape.
  • the present inventors focused on the joining conditions and tested by changing the solder thickness and the load on the solder in order to obtain sufficient joining strength. As a result, leakage current was generated due to the lateral spread of the solder and reliable joining was performed. The present inventors have confirmed that there is a contradictory relationship with obtaining strength. In order to suppress the leakage current while obtaining a reliable joint strength, it is necessary to increase the width of the non-conducting region between the joint and the surface electrode where there is no conductive material to reduce the area of the surface electrode. However, the merit of increasing the area of the surface electrode cannot be enjoyed.
  • an object of the present invention is to provide an optical semiconductor package capable of increasing the area of the surface electrode while suppressing current leakage and a method for manufacturing the same.
  • the present inventors have diligently studied to solve the above problems, and made it possible to provide a step in the non-conducting region surrounding the surface electrode in the package substrate and use this step to prevent the solder from spreading when the solder melts. I was inspired.
  • the present invention has been made based on such findings, and has the following configuration.
  • An optical semiconductor package in which an optical semiconductor chip mounted on a surface electrode on a package substrate is sealed in a closed space formed between the optical semiconductor chip and a translucent lid having a recess.
  • a first metal layer located at a position not in contact with the surface electrode via a non-conducting region surrounding the surface electrode on the package substrate, and a second metal layer located at a joint surface of the mouth edge portion of the translucent lid. Face to face, The first metal layer and the second metal layer are joined by solder.
  • An optical semiconductor package characterized in that the package substrate has a step in the non-conducting region.
  • solder is AuSn solder or AgSn solder.
  • an optical semiconductor device capable of increasing the area of a surface electrode while suppressing current leakage, and a method for manufacturing the same.
  • FIG. 1 It is a schematic diagram of an example of the optical semiconductor package which concerns on this invention. It is a schematic diagram of an example of an optical semiconductor package according to a conventional example. It is a schematic diagram which considered the lateral protrusion of solder at the time of bonding in the optical semiconductor package which concerns on the prior arts.
  • (A) to (C) are examples of steps of the package substrate in the optical semiconductor package according to the present invention, respectively.
  • (A) to (C) are different examples of the steps of the package substrate in the optical semiconductor package according to the present invention, respectively. It is a schematic cross-sectional view for demonstrating an example of the manufacturing method of the optical semiconductor package which concerns on this invention.
  • FIG. 1 It is a schematic view of the package substrate in an Example, (A) is an enlarged schematic sectional view of the end portion of the package substrate, and (B) is the top view of the package substrate. It is sectional drawing of the optical semiconductor package which concerns on Example of this invention, (A) is the schematic sectional view of Example 1, and (B) is the schematic sectional view of Example 2.
  • FIG. 1 is an exploded schematic cross-sectional view of an optical semiconductor package 100 which is an example according to the present invention
  • FIG. 2 is an exploded schematic sectional view of an example of an optical semiconductor package 900 according to a conventional example.
  • FIG. 3 is an enlarged schematic cross-sectional view for explaining the problems in the conventional example.
  • the optical semiconductor package 100, which is an example of the present invention, and the optical semiconductor package 900 according to the conventional example are particularly different depending on whether or not there is a step in the non-conducting region of the package substrate to prevent the spread of solder during the sealing process. .. Specific examples of such steps are illustrated in FIGS. 4 (A) to 4 (C) and FIGS.
  • FIG. 6 illustrates an example of a method for manufacturing an optical semiconductor package.
  • the numbers after the last two digits and the alphabetic code refer to the same type of configuration, and duplicate explanations will be omitted.
  • the optical semiconductor package 100 includes at least a package substrate 110, an optical semiconductor chip 120, and a translucent lid 130 having a recess. Then, the optical semiconductor chip 120 mounted on the surface electrodes 151 and 152 on the package substrate 110 is sealed between the optical semiconductor chip 120 and the translucent lid 130 to form a closed space 180. Since FIG. 1 is an exploded schematic view, a closed space is not originally formed in this figure, but since it becomes a closed space after the sealing step, a convenience code for explanation is added. Hereinafter, details of each configuration will be described in sequence.
  • the optical semiconductor chip 120 may be any light emitting element or light receiving element as long as it is enclosed in the closed space 180 by the package substrate 110 to be installed and the translucent lid 130.
  • Examples of the optical semiconductor chip 120 used in such a state include those having a emission wavelength or a reception wavelength of deep ultraviolet light (wavelength 200 to 350 nm).
  • a light emitting element of deep ultraviolet light (wavelength 200 to 350 nm) generates a large amount of heat during driving, and is therefore suitable for use in the optical semiconductor chip 120.
  • a flip-chip type optical semiconductor chip is described as an example, but a vertical type optical semiconductor chip may also be used.
  • the chip size (outer shape when viewed from a bird's-eye view) of the optical semiconductor chip may be a square or a rectangle having a side of 300 to 2000 ⁇ m.
  • the package substrate 110 is preferably made of a material having high insulating properties and heat dissipation, and is preferably made of, for example, ceramics.
  • the ceramics may be either low temperature co-fired ceramics (LTCC) or high temperature co-fired ceramics (HTCC).
  • Examples of the ceramic material include aluminum nitride (AlN), alumina (Al 2 O 3 ), silica (SiO 2 ), titanium dioxide (TiO 2 ) and the like.
  • the package substrate 110 may contain a known insulating material, metal compound, plasticizer, organic binder or solvent, if necessary.
  • the electrode formed at the position where the optical semiconductor chip 120 is installed on the upper surface of the package substrate 110 is called a surface electrode.
  • surface electrodes 151 and 152 are provided in the central portion of the package substrate 110 through a predetermined gap 112 in order to ensure electrical insulation. When simply referred to as a "surface electrode", it is assumed that the gap 112 is included.
  • the surface electrodes 151 and 152 are electrodes for electrically connecting to the p-type electrode and the n-type electrode of the optical semiconductor chip 120, respectively.
  • the package substrate 110 there is a first metal layer 141 that is separated from the surface electrodes 151 and 152 and is not in contact with each other via a non-conducting region 111 that surrounds the outside of the surface electrodes.
  • the first metal layer 141 is formed so as to surround the surface electrodes 151 and 152 while sandwiching a non-conducting region 111 which is a region without a conductive material between the surface electrodes 151 and 152 and the first metal layer 141. It is used for joining with the translucent lid 130, which will be described later. Since the surface electrode includes the gap 112 as described above, the non-conducting region 111 does not include the gap 112. It can be said that the non-conducting region 111 corresponds to the peripheral edge portion between the outer edge portion from the outer edge thereof to the first metal layer 141 and the central portion where the surface electrodes 151, 152 and the gap 112 are located.
  • the package substrate 110 has a step 113 between the surface electrodes 151 and 152 and the first metal layer 141.
  • the example shown in FIG. 1 is an example in which a step is provided on the convex portion by providing a wall surface at the boundary between the first metal layer 141 and the non-conducting region 111, and this is merely an example. May be good.
  • the maximum height of the convex or concave portion due to the step is, for example, preferably larger than 0.02 mm, more preferably 0.05 mm or more, and preferably 0.4 mm or less. It is preferable that the surface electrodes 151 and 152 and the first metal layer 141 are provided on a flat surface, respectively, except for the portion where the step is provided.
  • the angle of the step may be vertical or sloping, and the elevation angle of the convex portion is preferably 45 to 90 degrees, and the depression angle of the concave portion is preferably 45 to 90 degrees.
  • the step may have a forward mesa structure or a reverse mesa structure.
  • the shape of the step is preferably a shape having an elevation angle at least partially.
  • between the first metal layer and the surface electrode means from the end point on the surface electrode side of the ground plane between the first metal layer 141 and the package substrate 110 to the ground plane between the surface electrode and the package substrate 110. It refers to the distance to the end point on the first metal layer 141 side, and if there is a step, the distance shall include the step height accompanying the step.
  • the shortest distance in the non-conducting region 111 is called the separation distance.
  • the width of the non-conducting region that does not include the step when viewed from a bird's-eye view is referred to as a separation width SW.
  • the non-conducting region 111 is the entire region surrounded by the region where the first metal layer 141 exists and the region where the surface electrode exists. If a step is included between the region where the first metal layer 111 exists and the region where the surface electrode exists, the non-conducting region has a step. For example, as in one example of FIG. 1, even when the step 113 of the package substrate 110 and the end point of the first metal layer 141 on the surface electrode side are at the same position when viewed from a bird's-eye view, the step 113 exists in the non-conducting region 111. Will be done.
  • the step is preferably a step that acts to prevent the spread of solder in the sealing step described later.
  • steps are illustrated in FIGS. 4 (A) to (C) and FIGS. 5 (A) to 5 (C).
  • FIGS. 4 (A) to 4 (C) are examples in which steps 413a, 413b, and 413c are provided by recesses (excavations), and the cross-sectional shape of each step is triangular, rectangular, or semicircular. In order to provide a step, these cross-sectional shapes may be arbitrarily combined.
  • FIG. 5A is an example in which a step 513a is formed by further providing a convex portion 514a in the concave portion (excavation portion).
  • FIG. 5B is an example in which the convex portion 514b is provided on the end surface of the surface electrode 551b to provide the step 513b.
  • FIG. 5C shows an example in which a step 513c is provided by providing a convex portion on the central portion side of the package substrate.
  • the separation width SW and the step height SH SH1 and SH2 in FIG. 5A are shown.
  • FIG. 5C shows that the position where the surface electrode is provided and the optical semiconductor chip is mounted is on the convex portion of the package substrate 510c, and the position (ground plane) of the surface electrode 551c in the height direction is the first electrode 541c.
  • the position is higher than the position in the height direction (ground contact surface) of the above through a step 513c of the convex portion.
  • the thickness of the first electrode 541c is thinner than that of the step 513c, and the position of the surface electrode 551c (grounding surface) is higher than the upper surface of the first electrode 541c. More preferred.
  • the area of the surface electrode can be maximized, and the proportion of the light emitted laterally from the optical semiconductor chip that directly reaches the translucent lid increases, so that the output is output. Improvement can also be expected.
  • the translucent lid 130 may be a transparent window material that sufficiently transmits light with respect to the wavelength of the optical semiconductor chip 120.
  • the material has a transmittance of 80% or more with respect to the wavelength, for example, quartz or molten. Quartz, calcium fluoride (CaF 2 ), and sapphire (Al 2 O 3 ) can be exemplified.
  • a known AR coat (light antireflection film) or photonic crystal may be provided on the outer surface, inner surface or both outer and inner surfaces of the translucent lid 130.
  • the translucent lid 130 preferably has a recess so as to accommodate the above-mentioned optical semiconductor chip 120, and the recess is preferably a recess having a depth larger than the thickness of the optical semiconductor chip 120.
  • the translucent lid 130 has a shape capable of forming a closed space 180 for accommodating the optical semiconductor chip 120 with the package substrate 110 having a substantially flat plate shape.
  • the translucent lid is also called a cavity lens.
  • the cross-sectional shape in the recess of the translucent lid 130 may be a rectangular shape or an excavation shape having a curved surface such as a hemisphere.
  • the outer shape of the translucent lid 130 on the light extraction side may have a curved surface such as a hemisphere in addition to a flat plate.
  • the translucent lid 130 has a joint surface with the package substrate 110 on the rim portion 131, and has a second metal layer 142 on the joint surface.
  • the mouth edge portion 131 refers to a portion of a tip around the mouth edge portion 131 as viewed from the bottom of the recess of the translucent lid, such as the surface on which the second metal layer 142 is located as shown in FIG.
  • the second metal layer 142 is formed to ensure the adhesion between the translucent lid 130 and the solder 143.
  • the position of the joint surface on the rim portion 131 is such that it can face the position of the first metal layer 141 described above, and the second metal layer 142 covers the entire circumference of the joint surface of the rim portion 131 surrounding the outer periphery of the recess. It is preferably formed over.
  • the second metal layer 142 is formed at a position facing the first metal layer 141 with the solder 143 sandwiched between them.
  • the solder 143 may be any material as long as it spreads in the lateral direction when the solder 143 is pushed down in the sealing step is about the same as that of AuSn solder.
  • AuSn solder for example, AgSn solder may be used. You may.
  • Various composition of AuSn solder can be used, and for example, one having a eutectic composition can be used.
  • the first metal layer 141 and the second metal layer 142 are generally produced by a vapor deposition method, a sputtering method, or a plating method, but the waviness of the surfaces of the package substrate 110 and the translucent lid 130 themselves also has an effect.
  • the surface of each metal layer is usually not a perfectly flat surface.
  • the Rz on the surface of the first metal layer 141 is 1 ⁇ m to 5 ⁇ m
  • the Rz on the surface of the second metal layer 142 is 4 ⁇ m to 10 ⁇ m.
  • the solder 143 When there are irregularities or waviness on the surface in this way, the solder 143 is sandwiched between the first metal layer 141 and the second metal layer 142, and the solder 143 is melted while being pressurized and cooled and solidified to cool and solidify the first metal layer 141.
  • the load applied to the solder 143 is weak, air bubbles (voids) are left between the first metal layer 141 and the second metal layer 142, and the bonding strength of the solder is increased. It doesn't go up.
  • the load applied to the solder 143 is less than 0.1 kgf / cm 2 , bubbles (voids) are left between the first metal layer 141 and the second metal layer 142, and sufficient strength cannot be obtained.
  • the load applied to the solder is preferably 0.1 kgf / cm 2 or more, and the upper limit of the load applied to the solder is preferably 2 kgf / cm 2 . This is because even if a load larger than 2 kgf / cm 2 is applied, the amount of crushing of the solder 143 increases and the bonding strength does not change much.
  • the thickness of the melted solder 143 is reduced to less than 1/2 of the original thickness.
  • the behavior of the solder 943 in the optical semiconductor package 900 according to the prior art will be described with reference to FIGS. 2 and 3.
  • FIGS. 2 and 3 when the optical semiconductor chip 920 is sealed, when the solder 943 corresponding to 1/2 or more of the average thickness before pressurization is melted while being pressurized as described above. , A part of the solder 943 is extruded to the surface electrode side in the closed space 980.
  • the step that prevents the spread of the solder as illustrated in FIGS. 1, 4 (A) to (C), 5 (A) to (C), and 7 is the solder that protrudes to the surface electrode side. It is a step that forces vertical movement to the end of the surface electrode side.
  • the space created by the vertical step height SH between the first metal layer 741 and the surface electrode 751 moves toward the surface electrode of the solder that protrudes due to the step that prevents the spread of the solder.
  • the step height SH may be appropriately set according to the volume of the solder that protrudes and the separation width SW, but if the step height SH exceeds the thickness of the solder before the load is applied, the surface electrode of the solder that protrudes. It is possible to reliably force the side edge to move in the vertical direction.
  • the step height SH is preferably larger than 0.02 mm, and more preferably 0.05 mm or more, which is 2.5 times the solder thickness.
  • the step height SH depends on the thickness of the green sheet used for the package, but is preferably 0.4 mm or less.
  • the optical semiconductor package according to the present invention can increase the area of the surface electrode while suppressing the leakage of current.
  • the manufacturing method according to the present invention includes at least a mounting step and a sealing step. Each step will be described in detail with reference to FIG. 6 for one of the embodiments.
  • the mounting process for mounting the optical semiconductor chip 620 on the package substrate 610 is optional, and a known method can be used.
  • the surfaces (installation portions) of the surface electrodes 651 and 652 on the package substrate 610 are opposed to the bonding metals 623 and 624 provided on the surfaces of the electrode layers 621 and 622 of the optical semiconductor chip 620, respectively. While adhering, ultrasonic bonding is performed while heating the package substrate 610 and applying an appropriate load to the optical semiconductor chip 620.
  • the front surface electrodes 651 and 652 are connected to the back surface electrodes 661 and 662 provided on the back surface of the package substrate 610 via wiring electrodes 618 penetrating the inside of the package substrate, respectively.
  • Au bumps are previously attached to the surface electrodes 651 and 652 of the installation portion provided on the package substrate 610, or the Au bumps are previously attached.
  • a method of adhering a solder piece to the surface electrodes 651 and 652 of the installation portion provided on the package substrate 610 may be adopted.
  • a method of applying the solder paste to the surface electrodes 651 and 652 of the installation portion provided on the package substrate 610 in advance may be used.
  • solder layer such as AuSn may be formed (deposited or the like) on the surfaces of the electrode layers 621 and 622 of the optical semiconductor chip 620, and solder such as AuSn may be formed on the surface of the electrode layers 621 and 622 of the optical semiconductor chip 620 in advance.
  • a layer may be formed (deposited or the like), and flux may be applied to the surface electrodes 651 and 652 of the installation portion provided on the package substrate 610.
  • the first metal layer 641 is formed so as to surround the surface electrode via the non-conducting region 611.
  • a second metal layer 642 is also formed on the joint surface of the rim portion 631 on the translucent lid 630.
  • the solder 643 may be attached to either side of the first metal layer 641 or the second metal layer 642 first. It is also preferable to temporarily hold the transparent lid 630 by applying a load so that the translucent lid 630 can be maintained on the package substrate 610.
  • the first metal layer 641 and the second metal layer 642 are brought into contact with each other via the solder 643 as described above, and then fused and sealed using the solder 643.
  • This is a step of forming a closed space 680 created by the package substrate 610 containing the optical semiconductor chip 620 and the translucent lid 630.
  • the first metal layer 641 and the second metal layer 642 are not particularly limited as long as they can easily adhere to the package substrate 610 and the translucent lid 630, respectively, and can be metallized with the solder 643 described later. ..
  • the solder used in the sealing step is preferably AuSn-based solder, AgSn-based solder, or the like, and it is preferable to use solder bonding by heating.
  • the heating temperature in the sealing step to a temperature at which the solder melts (e.g. 220 ⁇ 360 °C), it is preferable to 0.1 kgf / cm 2 or more 2 kgf / cm 2 or less load applied to the solder.
  • an inert atmosphere such as nitrogen gas.
  • the optical semiconductor chip (LED (DoUVLEDs (registered trademark), trade name DF8XC-00001)) used in this embodiment is an LED chip made of an AlGaN crystal that emits a wavelength of 280 nm.
  • the size of the LED chip was 1 mm ⁇ 1 mm and the thickness was 0.43 mm.
  • the package substrate used in this example used high-temperature co-fired ceramics (HTCC, thermal conductivity 170-200 W / m ⁇ K). With reference to FIGS. 7 (A) and 7 (B), this ceramic was produced according to the procedure described below.
  • HTCC high-temperature co-fired ceramics
  • AlN powder is used as a raw material for ceramics, a known binder and a plasticizer are mixed to form a slurry, and the slurry is subjected to a first sheet 710A having a thickness of 0.44 mm by a known doctor blade method.
  • a second sheet 710B having a thickness of 0.22 mm was prepared.
  • Each of these two sheets (hereinafter, also referred to as a green sheet) is provided with two or more through holes 718 penetrating the substrate.
  • a conductive paste containing tungsten powder is used to fill the through holes 718, and the through holes 718 are printed and dried by printing on the electrode pattern regions for the front and back electrodes and the region forming the first metal layer, which will be described later. bottom.
  • the second sheet 710B is cut into a predetermined shape, the second sheet 710B is arranged on the first sheet 710A so that the fillings of the respective through holes 718 are connected, and the second sheet 710B is heated to about 50 to 80 ° C. by a press machine. However, the pressure of 10 MPa was thermocompression bonded over 20 minutes. Then, after the temporary firing at 600 ° C., it was fired at 1800 ° C. while pressurizing. By superimposing and firing the two green sheets 710A and 710B in this way, the first sheet 710A and the second sheet 710B were bonded to each other to produce an integrated ceramic base material. Both green sheets were shrunk by firing, and the thickness D 1 of the portion of the first sheet 710A became 0.38 mm, and the thickness D 2 of the portion of the second sheet 710B became 0.19 mm.
  • the front surface electrodes 751 and 752 are placed on the upper surface of the second sheet 710B, and the back surface electrodes 761 and 762 (however, the back surface electrodes) are placed on the back surface of the first sheet 710A according to the positions of the electrode patterns formed by using the above conductive paste. 762 is not shown for the sake of simplification of the drawings).
  • the frame-shaped first metal layer 741 is a portion of the upper surface of the first sheet 710A where the second sheet 710B is not arranged and the first sheet 710A is exposed, and is one of the wall surfaces of the second sheet 710B. It was formed without a gap so as to cover the portion.
  • the package substrate 710 has a convex portion composed of the second sheet 710B portion, and the ground contact surface of the surface electrodes 751 and 752 with the second sheet 710B is with the first sheet 710A of the first metal layer 741. It is located at a high position through a vertical step of 0.19 mm (D 2) from the ground plane.
  • the front electrode 751, 752, the back electrode 761, 762, and the first metal layer 741 are formed by forming copper Cu (30 ⁇ m) by a plating method, and then palladium Pd (75 nm), nickel Ni (4.5 ⁇ m), and gold Au. Lamination was performed in the order of (0.1 ⁇ m). Further, the first sheet 710A was cut into individual pieces to obtain the package substrate 710 of this example.
  • the back electrode 762 is not shown for simplification of the drawings.
  • the outer size of the first sheet 710A portion of the package substrate 710 is 3.5 mm ⁇ 3.5 mm (length L 4 ), and the outer size of the second sheet 710B portion (elevation portion) is 2.39 mm ⁇ 2. It was .39 mm (length L 2 ).
  • the frame-shaped first metal layer 741 as viewed from a bird's-eye view has an outer shape of 3.35 mm ⁇ 3.35 mm (length L 3 ) and an inner shape of 2.39 mm ⁇ 2.39 mm (length L 2 ), and has a surface electrode.
  • the outer shape of the quadrangular surface of 751 and 752 including the portion on the p-type electrode side and the portion on the n-type electrode side is 2.29 mm ⁇ 2.29 mm (length L 1 ), and the surface from the first metal layer 741.
  • the value of the separation width SW between the electrodes 751 and 752 without considering the step when viewed from a bird's-eye view was 0.05 mm. Since there is no gap between the first metal layer 741 and the side surface of the second sheet 710B, from the upper surface end of the first metal layer 741 in which the side surface of the first metal layer 741 and the side surface of the second sheet 710B forming the step are in contact with each other.
  • Quartz glass was used for the translucent lid used in this example.
  • the shape of the translucent lid is shown in the schematic cross-sectional view of FIG. 8 (A).
  • the outer size of the translucent lid is 3.50 mm ⁇ 3.50 mm (L 1 ) with a height of 1.28 mm (D 4 ), has recesses, and the recesses are trapezoidal caldera-shaped.
  • the depth of the recess was 0.88 mm
  • the width on the opening side of the recess was 2.8 mm
  • the width on the bottom of the recess was 1.74 mm.
  • the second metal layer located at the rim portion had an outer shape of 3.3 mm ⁇ 3.3 mm and an inner shape of 2.8 mm ⁇ 2.8 mm.
  • titanium (Ti), panadium (Pd), copper (Cu), and nickel (Ni) are vapor-deposited on quartz glass in this order, and gold (Au) is vapor-deposited on the quartz glass by 0.5 ⁇ m. The total thickness was 3 ⁇ m.
  • a total of 25 Au bumps were attached to the above LED chip in advance, and a chip with Au bumps was prepared.
  • the chips with Au bumps were placed on the surface electrodes 851a and 852a of the package substrate, the package substrate was placed on a hot plate at 200 ° C., heated, and ultrasonically bonded while crushing the Au bumps by pressurization.
  • the environment during the mounting process is the atmosphere.
  • the translucent lid 830a was loaded on the package substrate 810a.
  • both were moved into a glove box having a nitrogen atmosphere, and the surface electrodes 851a and 852a of the package substrate 810a and the electrodes of the LED chip 820a were placed so as to face each other.
  • AuSn preform solder manufactured by Tanaka Kikinzoku, Au78at%, Sn22at% is placed on the first metal layer of the package substrate 810a as solder, and the position is set so as to sandwich the solder between the first metal layer and the second metal layer.
  • a translucent lid 830a was placed together.
  • AuSn preform solder is made by punching a sheet having a thickness of 0.020 mm with an outer shape of 3.2 mm ⁇ 3.2 mm and an inner shape of 2.5 mm ⁇ 2.5 mm. Then, the arm and the weight of the temporary holding jig were used to fix the translucent lid 830a so that the position did not shift. At this time, a load of 33 gf was applied by the weight. At this time, the pressure exerted on the solder AuSn preform was 1.08 kg / cm 2 is calculated based on the area of the second metal layer (0.0305cm 2).
  • the temporary holding jig containing the package board equipped with the LED chip was moved to an area filled with nitrogen. While applying a load by the weight, it is heated to a temperature (300 to 310 ° C.) equal to or higher than the melting point of the solder sheet, and when the solder is melted, it is cooled to join the first metal layer and the second metal layer to form a closed space.
  • the LED chip was sealed inside to complete the sealing process. In this way, the optical semiconductor package according to the first embodiment in which the LED chip is housed in the closed space is produced. From the thickness of the distance between the translucent lid and the package substrate after the sealing process, the thickness of the solder after fusion is calculated to be 2.0 ⁇ m on average, which is 10 minutes from the original thickness (20 ⁇ m). It was found that the thickness was 1.
  • Example 2 The optical semiconductor package according to Example 2 was produced in the same manner as in Example 1 except that the translucent lid was replaced with the dome-shaped one shown in FIG. 8 (B).
  • the dome shape has an outer size of 3.50 mm ⁇ 3.50 mm (L 1 ) and a height of 2.1 mm (D 4 ), has a recess, and the recess is a dome shape with a radius of 1.3 mm (R). rice field.
  • the second metal layer located at the rim portion had an outer shape of 3.3 mm ⁇ 3.3 mm and an inner shape of 2.7 mm ⁇ 2.7 mm.
  • AuSn preform pressure on the solder when a load of 33gf by weight was 0.917kg / cm 2 when calculated area of the second metal layer (0.036 cm 2) in the group.
  • Example 3 An optical semiconductor device according to Example 3 was produced in the same manner as in Example 1 except that a load of 16 gf was applied by the weight.
  • the pressure exerted on the solder AuSn preform was 0.525kg / cm 2 is calculated based on the area (0.0305cm 2) of the second metal layer.
  • the average thickness of the solder after fusion is 4.0 ⁇ m from the thickness of the distance between the translucent lid and the package substrate after the sealing process, which is 5 minutes from the original thickness (20 ⁇ m). It was found that the thickness was 1.
  • Example 4 An optical semiconductor package according to Example 4 was produced in the same manner as in Example 2 except that a load of 16 gf was applied by the weight. The pressure exerted on the solder AuSn preform was 0.444kg / cm 2 is calculated based on the area (0.036 cm 2) of the second metal layer.
  • Comparative Example 1 In the first embodiment, the second sheet was laminated on the first sheet in order to provide a step in the production of the package substrate. In Comparative Example 1, the second sheet was not used in the package substrate, and the surface electrode and the first sheet were on the first sheet. One metal layer was formed.
  • the frame-shaped first metal layer seen from a bird's-eye view has an outer shape of 3.3 mm ⁇ 3.3 mm and an inner shape of 2.6 mm ⁇ 2.6 mm, and the surface electrodes are the part on the p-type electrode side and the part on the n-type electrode side.
  • the outer shape of the circumscribed quadrangle including it is 1.94 mm ⁇ 1.94 mm, there is no step in the non-conducting region between the first metal layer and the surface electrode, and the value of the separation width (and separation distance) is 0.33 mm. Is.
  • the optical semiconductor package according to Comparative Example 1 was produced in the same manner as in Example 1 under other conditions.
  • Example 2 In Example 1, the second sheet was laminated on the first sheet in order to provide a step in the production of the package substrate. In Comparative Example 2, the second sheet was not used in the package substrate, and the surface electrode and the first sheet were on the first sheet. One metal layer was formed.
  • the frame-shaped first metal layer viewed from a bird's-eye view has an outer shape of 3.35 mm ⁇ 3.35 mm and an inner shape of 2.39 mm ⁇ 2.39 mm (same as in Example 1), and the surface electrode is on the p-type electrode side.
  • the outer shape of the quadrangle circumscribing including the part on the n-type electrode side is 2.11 mm ⁇ 2.11 mm, there is no step in the non-conducting region between the first metal layer and the surface electrode, and the separation width (separation width) And the separation distance) was set to 0.14 mm.
  • the optical semiconductor package according to Comparative Example 2 was produced in the same manner as in Example 1 under other conditions.
  • Comparative Example 3 An optical semiconductor package according to Comparative Example 3 was produced in the same manner as in Comparative Example 1 except that a load of 16 gf was applied by the weight.
  • Comparative Example 4 An optical semiconductor package according to Comparative Example 4 was produced in the same manner as in Comparative Example 2 except that a load of 16 gf was applied by the weight.
  • Examples 2 to 4 and Comparative Examples 1 to 4 were also evaluated by the above-mentioned evaluations 1 and 2 in the same manner as in Example 1. The results are shown in Table 1 below.
  • Optical semiconductor package 110 Package substrate 111 Non-conducting area 112 Gap 113 Step 118 Through hole 120 Optical semiconductor chip (LED) 130 Translucent lid 131 Mouth edge 141 First metal layer 142 Second metal layer 143 Solder 151, 152 Front electrode 161, 162 Back electrode 180 Closed space

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Optics & Photonics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Led Device Packages (AREA)
  • Light Receiving Elements (AREA)

Abstract

La présente invention concerne un boîtier de semi-conducteur optique permettant d'augmenter la surface d'une électrode de surface tout en réduisant au minimum la fuite de courant, et son procédé de fabrication. Un procédé de fabrication d'un boîtier de semi-conducteur optique selon la présente invention comprend : un processus de montage d'une puce semi-conductrice optique sur une électrode de surface sur un substrat de boîtier ; et un processus d'agencement de brasure entre une première couche métallique qui est dans un emplacement n'entrant pas en contact avec l'électrode de surface et une seconde couche métallique située sur une surface de jonction d'une section bord d'ouverture d'un couvercle transparent ayant un évidement, avec une région non conductrice entourant l'électrode de surface entre celles-ci, amenant la première couche de métal et la seconde couche de métal face l'une à l'autre, et à appliquer une pression sur le substrat de boîtier et le couvercle transparent tout en faisant fondre la brasure pour loger la puce semi-conductrice optique dans un espace fermé entre le substrat d'emballage et le couvercle transparent, le substrat de boîtier ayant une étape qui arrête l'étalement de la brasure dans la région non conductrice.
PCT/JP2021/014392 2020-04-03 2021-04-02 Procédé de fabrication de boîtier de semi-conducteur optique, et boîtier de semi-conducteur optique WO2021201290A1 (fr)

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JP7194249B1 (ja) 2021-11-15 2022-12-21 星和電機株式会社 光源装置
WO2023199744A1 (fr) * 2022-04-11 2023-10-19 日本電気硝子株式会社 Élément de couvercle, boîtier et substrat de verre

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JPS61199001U (fr) * 1985-05-31 1986-12-12
JP3159412U (ja) * 2009-04-20 2010-05-20 馨意科技股▲分▼有限公司 Ｌｅｄパッケージ構造
JP2016127254A (ja) * 2014-12-26 2016-07-11 パナソニックＩｐマネジメント株式会社 発光装置及びその製造方法
US20160285232A1 (en) * 2013-12-03 2016-09-29 Fraunhofer-Gesellschaft Zur Foerderung Der Angewandten Forschung E.V. Method of producing a cap substrate, and packaged radiation-emitting device
JP6305668B1 (ja) * 2016-08-10 2018-04-04 京セラ株式会社 電気素子搭載用パッケージ、アレイ型パッケージおよび電気装置

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US20040217451A1 (en) * 2002-11-14 2004-11-04 Sai-Mun Lee Semiconductor packaging structure
JP5968674B2 (ja) * 2011-05-13 2016-08-10 エルジー イノテック カンパニー リミテッド 発光素子パッケージ及びこれを備える紫外線ランプ
JP2014027179A (ja) * 2012-07-27 2014-02-06 Harison Toshiba Lighting Corp 発光装置およびその製造方法、並びにパッケージ部材
JP6128938B2 (ja) * 2013-04-26 2017-05-17 株式会社トクヤマ 半導体発光素子パッケージ

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JPS61199001U (fr) * 1985-05-31 1986-12-12
JP3159412U (ja) * 2009-04-20 2010-05-20 馨意科技股▲分▼有限公司 Ｌｅｄパッケージ構造
US20160285232A1 (en) * 2013-12-03 2016-09-29 Fraunhofer-Gesellschaft Zur Foerderung Der Angewandten Forschung E.V. Method of producing a cap substrate, and packaged radiation-emitting device
JP2016127254A (ja) * 2014-12-26 2016-07-11 パナソニックＩｐマネジメント株式会社 発光装置及びその製造方法
JP6305668B1 (ja) * 2016-08-10 2018-04-04 京セラ株式会社 電気素子搭載用パッケージ、アレイ型パッケージおよび電気装置

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