WO2021196328A1 - 阵列基板及液晶显示面板 - Google Patents

阵列基板及液晶显示面板 Download PDF

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Publication number
WO2021196328A1
WO2021196328A1 PCT/CN2020/087670 CN2020087670W WO2021196328A1 WO 2021196328 A1 WO2021196328 A1 WO 2021196328A1 CN 2020087670 W CN2020087670 W CN 2020087670W WO 2021196328 A1 WO2021196328 A1 WO 2021196328A1
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Prior art keywords
fan
lines
auxiliary
line
out lines
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PCT/CN2020/087670
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English (en)
French (fr)
Inventor
奚苏萍
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Publication of WO2021196328A1 publication Critical patent/WO2021196328A1/zh
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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13452—Conductors connecting driver circuitry and terminals of panels
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line

Definitions

  • This application relates to the field of display technology, in particular to an array substrate and a liquid crystal display panel.
  • Gate Driver On Array is to use the Array process in the existing thin film transistor liquid crystal display to fabricate the Gate row scan driving signal circuit on the array substrate to realize the gate progressive scan driving method.
  • the left GOA and the right GOA drive the display panel at the same time, which results in the same gate routing.
  • the gate waveform in the middle area will be inconsistent with the edge gate waveform, which means that the flip chip film
  • the charging time of different areas in the panel will be inconsistent, that is, the intermediate charging time is short and the edge charging time is long. Due to the difference in charging time, the charging rate of different areas in the plane will be different, which will cause uneven display of the screen.
  • the purpose of the embodiments of the present application is to provide an array substrate and a liquid crystal display panel, which have the beneficial effect of improving the charging uniformity of each pixel unit.
  • an array substrate including:
  • a substrate having a display area and a non-display area
  • a plurality of pixel units, the plurality of pixel units are arranged in the display area;
  • a plurality of flip chip thin film chips are arranged in the non-display area, each of the flip chip thin film chips is connected to a plurality of the pixel units through a plurality of fan-out lines, and the plurality of fan The length of the outgoing line is not the same;
  • connection auxiliary lines are arranged in the non-display area, each of the connection auxiliary lines is set to a different first preset length, and each of the plurality of connection auxiliary lines is connected to the One of the plurality of fan-out lines is connected in parallel, thereby adjusting the equivalent resistance of each of the fan-out lines, so that the charging time of the plurality of the pixel units by the plurality of fan-out lines is equalized.
  • a plurality of auxiliary connection lines are provided, and each auxiliary connection line of the plurality of auxiliary connection lines is connected in parallel with one of the plurality of fan-out lines, thereby adjusting the equivalent of each fan-out line.
  • the resistance makes the charging time of the plurality of fan-out lines equal to the plurality of pixel units, which can improve the display balance and improve the display quality
  • a first metal layer, a second metal layer, and a first insulating layer located between the first metal layer and the second metal layer are provided on the substrate; the first metal layer A plurality of fan-out lines are formed, and the second metal layer forms a plurality of connection auxiliary lines.
  • the plurality of auxiliary connection lines correspond to part of the fan-out lines of the plurality of fan-out lines
  • the first insulating layer is provided with a plurality of metallized holes, and each of the auxiliary connecting lines is connected in parallel with the corresponding fan-out line through the plurality of metallized holes.
  • the plurality of fan-out lines include at least one first fan-out line of a first length and a plurality of second fan-out lines, and the lengths of the plurality of second fan-out lines are uneven, and the The lengths of the plurality of second fan-out lines are all greater than the length of the first fan-out line;
  • connection auxiliary lines are connected in parallel with the plurality of second fan-out lines in a one-to-one correspondence, so that the parallel equivalent resistance of each second fan-out line and the corresponding connection auxiliary line is equal to that of the first fan-out line. Effective resistance.
  • the plurality of auxiliary connection lines correspond to one of the plurality of fan-out lines
  • the first insulating layer is provided with a plurality of metallized holes, and each of the auxiliary connecting lines is connected in parallel with the corresponding fan-out line through the plurality of metallized holes.
  • the lengths of the plurality of fan-out lines are not uniform;
  • the plurality of fan-out lines and the plurality of connection auxiliary lines are connected in parallel in a one-to-one correspondence to form a plurality of sets of parallel wires, and the equivalent resistances of the plurality of sets of parallel wires are the same.
  • each auxiliary connection line is the same as the length of the corresponding fan-out line; the thickness of the plurality of fan-out lines is the same and the width is different; the longer the length of the plurality of fan-out lines is The longer the fan-out line corresponds to the larger the width of the auxiliary connection line.
  • connecting auxiliary lines of different widths are connected in parallel with fan-out lines of different lengths, so as to adjust the balance of the fan-out lines to ensure the equalization of the charging time of each pixel unit and improve the uniformity of display.
  • the width of each of the connection auxiliary lines is the same as the width of the corresponding fan-out line; the thickness of the plurality of fan-out lines is the same and the length is different; the longer the length of the plurality of fan-out lines is The longer the fan-out line corresponds to the longer the length of the auxiliary connection line.
  • the length of each of the auxiliary connection lines is the same as the length of the corresponding fan-out line; the widths of the plurality of fan-out lines are the same and the thicknesses are different; the longer the length of the plurality of fan-out lines is The longer the fan-out line corresponds to the larger the thickness of the auxiliary connection line.
  • connecting auxiliary lines of different thicknesses are connected in parallel with fan-out lines of different lengths, so as to adjust the balance of the fan-out lines to ensure that the charging time of each pixel unit is balanced, and the display uniformity can be improved.
  • an embodiment of the present application provides a liquid crystal display panel, which includes an array substrate, and the array substrate includes:
  • a substrate having a display area and a non-display area
  • a plurality of pixel units, the plurality of pixel units are arranged in the display area;
  • a plurality of flip chip thin film chips are arranged in the non-display area, each of the flip chip thin film chips is connected to a plurality of the pixel units through a plurality of fan-out lines, and the plurality of fan The length of the outgoing line is not the same;
  • connection auxiliary lines are arranged in the non-display area, each of the connection auxiliary lines is set to a different first preset length, and each of the plurality of connection auxiliary lines is connected to the One of the plurality of fan-out lines is connected in parallel, thereby adjusting the equivalent resistance of each of the fan-out lines, so that the charging time of the plurality of the pixel units by the plurality of fan-out lines is equalized.
  • a first metal layer, a second metal layer, and a first insulating layer located between the first metal layer and the second metal layer are provided on the substrate; the first metal layer The layer forms a plurality of fan-out lines, and the second metal layer forms a plurality of connection auxiliary lines.
  • the plurality of auxiliary connection lines correspond to part of the fan-out lines of the plurality of fan-out lines
  • the first insulating layer is provided with a plurality of metallized holes, and each of the auxiliary connecting lines is connected in parallel with the corresponding fan-out line through the plurality of metallized holes.
  • the plurality of fan-out lines include at least one first fan-out line with a first length and a plurality of second fan-out lines, and the lengths of the plurality of second fan-out lines are not uniform, so The lengths of the plurality of second fan-out lines are all greater than the length of the first fan-out line;
  • connection auxiliary lines are connected in parallel with the plurality of second fan-out lines in a one-to-one correspondence, so that the parallel equivalent resistance of each second fan-out line and the corresponding connection auxiliary line is equal to that of the first fan-out line. Effective resistance.
  • the plurality of auxiliary connection lines correspond to one of the plurality of fan-out lines
  • the first insulating layer is provided with a plurality of metallized holes, and each of the auxiliary connecting lines is connected in parallel with the corresponding fan-out line through the plurality of metallized holes.
  • the lengths of the plurality of fan-out lines are not uniform;
  • the plurality of fan-out lines and the plurality of connection auxiliary lines are connected in parallel in a one-to-one correspondence to form a plurality of sets of parallel wires, and the equivalent resistances of the plurality of sets of parallel wires are the same.
  • the length of each of the auxiliary connection lines is the same as the length of the corresponding fan-out line; the thickness of the plurality of fan-out lines is the same and the width is different; the length of the plurality of fan-out lines The longer the fan-out line corresponds to the larger the width of the auxiliary connection line.
  • each auxiliary connection line is the same as the width of the corresponding fan-out line; the thickness of the plurality of fan-out lines is the same and the length is different; the length of the plurality of fan-out lines The longer the fan-out line corresponds to the longer the length of the auxiliary connection line.
  • the length of each of the auxiliary connection lines is the same as the length of the corresponding fan-out line; the widths of the plurality of fan-out lines are the same and the thickness is different; the length of the plurality of fan-out lines The longer the fan-out line corresponds to the larger the thickness of the auxiliary connection line.
  • connection auxiliary lines are set in the non-display area, each of the connection auxiliary lines is set to a first preset length, and each connection auxiliary line of the multiple connection auxiliary lines They are respectively connected in parallel with one of the plurality of fan-out lines, thereby adjusting the equivalent resistance of each fan-out line, so that the charging time of the plurality of fan-out lines to the plurality of pixel units is equalized, and the display balance can be improved , Improve the display quality.
  • FIG. 1 is a schematic diagram of the structure of an array substrate provided by an embodiment of the application.
  • FIG. 2 is a schematic diagram of a partial structure of an array substrate provided by an embodiment of the application.
  • FIG. 3 is a schematic partial cross-sectional structure diagram of an array substrate provided by an embodiment of the application.
  • FIG. 4 is a schematic diagram of another partial structure of an array substrate provided by an embodiment of the application.
  • first and second are only used for description purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined with “first” and “second” may explicitly or implicitly include one or more of the features. In the description of this application, “multiple articles” means two or more than two unless otherwise specifically defined.
  • FIG. 1 is a schematic diagram of a structure of an array substrate provided by an embodiment of the application
  • FIG. 2 is a schematic diagram of a partial structure of the array substrate.
  • the array substrate includes: a substrate 10, a plurality of pixel units 20, a plurality of flip chip thin film chips 30, a plurality of fan-out lines 40a, a plurality of connection auxiliary lines 40b, a GOA driving circuit 60, a plurality of scan lines 70, and a plurality of data lines 80.
  • the substrate 10 has a display area 11 and a non-display area 12; the plurality of pixel units 20 are arranged in a uniform array in the display area 11; the GOA driving circuit 60 and a plurality of flip chip thin film chips 30 are arranged in the non-display area 12 .
  • the plurality of data lines 80 and the plurality of scan lines 70 are criss-crossed to define a plurality of pixel regions, and the plurality of pixel units 20 are respectively disposed in the plurality of pixel regions.
  • the GOA driving circuit 60 is connected to a plurality of scan lines 70, and the plurality of flip-chip thin film chips 30 are connected to the plurality of data lines 80 through the plurality of fan-out lines 40 a in a one-to-one correspondence, so as to charge the corresponding pixel unit 20.
  • each connection auxiliary line 40b is set to a first preset length, and each of the plurality of connection auxiliary lines 40b is connected to the plurality of fan-out lines 40a.
  • One of them is connected in parallel, thereby adjusting the equivalent resistance of each fan-out line 40a, so that the charging time of the plurality of fan-out lines 40a to the plurality of pixel units 20 is equalized.
  • the substrate 10 is provided with a first metal layer 401a, a second metal layer 401b, and a first insulating layer 402 located between the first metal layer 401a and the second metal layer 401b;
  • the layer 401a forms a plurality of fan-out lines 40a
  • the second metal layer 401b forms a plurality of connection auxiliary lines 40b.
  • the plurality of auxiliary connection lines 40b correspond to part of the fan-out lines 40a of the plurality of fan-out lines 40a; that is, the number of auxiliary connection lines 40b is less than the number of the fan-out lines 40a.
  • the first insulating layer 402 is provided with a plurality of metallized holes 4021, and each of the auxiliary connecting lines 40b is connected in parallel with the corresponding fan-out line 40a through the plurality of metallized holes 4021.
  • the plurality of fan-out lines 40a include at least one first fan-out line of a first length and a plurality of second fan-out lines.
  • the multiple connection auxiliary lines 40b are connected in parallel with the multiple second fan-out lines in a one-to-one correspondence, so that the parallel equivalent resistance of each second fan-out line and the corresponding connection auxiliary line is equal to the equivalent of the first fan-out line resistance.
  • Connecting auxiliary lines of different lengths are connected in parallel with fan-out lines of different lengths, so as to adjust the balance of the fan-out lines to ensure that the charging time of each pixel unit is balanced, and the uniformity of display can be improved.
  • the plurality of auxiliary connecting lines 40b correspond to one of the plurality of fan-out lines 40a, that is, the number of the two auxiliary connecting lines 40b is the same.
  • each auxiliary connecting line 40b is directly opposite to a part or the whole of the corresponding fan-out line 40a.
  • the first insulating layer 402 is provided with a plurality of metallized holes 4021, and each of the auxiliary connecting lines is connected in parallel with the corresponding fan-out line 40a through the plurality of metallized holes 4021.
  • the lengths of the multiple fan-out lines 40a are not uniform; the multiple fan-out lines 40a and the multiple connection auxiliary lines 40b are connected in parallel to form multiple sets of parallel lines in one-to-one correspondence, and the multiple sets of parallel lines have the same equivalent resistance.
  • Connecting auxiliary lines of different lengths are connected in parallel with fan-out lines of different lengths, so as to adjust the balance of the fan-out lines to ensure that the charging time of each pixel unit is balanced, and the uniformity of display can be improved.
  • the length of each auxiliary connection line 40b is the same as the length of the corresponding fan-out line 40a; the thickness of the plurality of fan-out lines 40a is the same and the width is different; the longer the length of the plurality of fan-out lines 40a is The width of the auxiliary connection line corresponding to the long fan-out line 40a is larger.
  • the equivalent resistances of the connecting auxiliary lines 40b are different, and connecting auxiliary lines of different widths are connected in parallel with fan-out lines of different lengths to adjust the balance of the fan-out lines to ensure each pixel unit The charging time is balanced, which can improve the uniformity of the display.
  • each auxiliary connection line 40b is the same as the length of the corresponding fan-out line 40a; the widths and thicknesses of the plurality of fan-out lines 40a are the same, so that their equivalent resistances are different; Among the plurality of fan-out lines 40a, the longer the length of the fan-out line 40a corresponds to the larger the thickness of the connection auxiliary line 40b.
  • the connection auxiliary lines 40b of different thicknesses are connected in parallel with the fan-out lines 40a of different lengths, so as to adjust the balance of the fan-out lines to ensure that the charging time of each pixel unit is balanced, and the display uniformity can be improved.
  • each auxiliary connection line 40b are different or partially different, so as to achieve the purpose of better setting the resistance of each auxiliary connection line, thereby achieving the The precise control of the equivalent resistance of each fan-out line realizes the balanced adjustment of the charging time of each pixel unit, which can improve the display quality.
  • FIG. 4 is a schematic diagram of another partial structure of the array substrate provided by an embodiment of the application.
  • the difference between the array substrate shown in FIG. 4 and the array substrate shown in FIG. 2 is that, in the array substrate shown in FIG. The longer the length of 40b is.
  • each auxiliary connection line 40b is the same as the width of the corresponding fan-out line 40a; the thickness of the plurality of fan-out lines 40a is the same and the length is different; the fan with the longer length among the plurality of fan-out lines 40a The longer the length of the auxiliary connection line 40b corresponding to the outlet line 40a is.
  • the connection auxiliary lines 40b of different lengths are connected in parallel with the fan-out lines 40a of different lengths, so as to adjust the balance of the fan-out lines to ensure that the charging time of each pixel unit is balanced, and the display uniformity can be improved.
  • connection auxiliary lines are set in the non-display area, each of the connection auxiliary lines is set to a first preset length, and each of the multiple connection auxiliary lines A connection auxiliary line is respectively connected in parallel with one of the plurality of fan-out lines, thereby adjusting the equivalent resistance of each fan-out line, so that the charging time of the plurality of fan-out lines to the plurality of pixel units is equalized, and Improve display balance and improve display quality.
  • the present application also provides a liquid crystal display panel.
  • the liquid crystal display panel includes the array substrate in any of the foregoing embodiments.
  • the liquid crystal display panel further includes a color film substrate and a liquid crystal molecular layer.
  • the array substrate and the color filter substrate are directly opposite and arranged at intervals, and the liquid crystal molecule layer is sandwiched between the array substrate and the color filter substrate.

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  • Nonlinear Science (AREA)
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  • Crystallography & Structural Chemistry (AREA)
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Abstract

本申请实施例提供的阵列基板包括：基板；多个像素单元；多个覆晶薄膜芯片，每一覆晶薄膜芯片通过多条扇出线与多个像素单元连接，多条扇出线的长度不相同；多条连接辅助线，每一连接辅助线设置为第一预设长度，多条连接辅助线中的每一连接辅助线分别与多条扇出线中的一条并联。

Description

阵列基板及液晶显示面板 技术领域
本申请涉及显示技术领域，具体涉及一种阵列基板及液晶显示面板。
 背景技术
Gate Driver On Array，简称GOA，也就是利用现有薄膜晶体管液晶显示器中的Array制程将Gate行扫描驱动信号电路制作在阵列基板上，实现对Gate逐行扫描的驱动方式。
对于GOA产品，通常为双驱产品，即左边GOA和右边GOA同时驱动显示面板,这就造成同样的gate走线，中间区域的gate波形会与边缘gate波形不一致，这就意味着在覆晶薄膜芯片处设定好时序信号以及数据电压信号的时间后，由于GOA驱动设定的原因，会造成面板内不同区域的充电时间不一致，即中间充电时间短，边缘充电时间长。由于充电时间的不同会造成面内不同区域充电率的不同，即会造成画面显示不均。
 技术问题
本申请实施例的目的在于提供一种阵列基板及液晶显示面板，具有提高各个像素单元充电均匀性的有益效果。
 技术解决方案
第一方面，本申请实施例提供了一种阵列基板，包括：
基板，其具有显示区域以及非显示区域；
多个像素单元，所述多个像素单元设置于所述显示区域；
多个覆晶薄膜芯片，所述多个覆晶薄膜芯片设置于所述非显示区域，每一所述覆晶薄膜芯片通过多条扇出线与多个所述像素单元连接，所述多条扇出线的长度不相同；
多条连接辅助线，其设置于所述非显示区域，每一所述连接辅助线设置为不同的第一预设长度，所述多条连接辅助线中的每一连接辅助线分别与所述多条扇出线中的一条并联，从而调节每一所述扇出线的等效电阻，使得所述多条扇出线对多个所述像素单元的充电时间均衡。
本申请实施例通过设置多条连接辅助线，所述多条连接辅助线中的每一连接辅助线分别与所述多条扇出线中的一条并联，从而调节每一所述扇出线的等效电阻，使得所述多条扇出线对多个所述像素单元的充电时间均衡，可以提高显示均衡性，提高显示质量
在本申请所述的阵列基板中，所述基板上设置有第一金属层、第二金属层以及位于第一金属层和第二金属层之间的第一绝缘层；所述第一金属层形成多条扇出线，所述第二金属层形成多条连接辅助线。
在本申请所述的阵列基板中，所述多条辅助连接线与所述多条扇出线中的部分扇出线相对应；
所述第一绝缘层开设有多个金属化孔，每一所述辅助连接线通过多个金属化孔与对应扇出线并联。
在本申请所述的阵列基板中，所述多条扇出线包括至少一条第一长度的第一扇出线以及多条第二扇出线，所述多条第二扇出线的长度不均，所述多条第二扇出线的长度均大于所述第一扇出线；
所述多条连接辅助线与所述多条第二扇出线一一对应地并联，使得每一所述第二扇出线与对应连接辅助线的并联等效电阻等于所述第一扇出线的等效电阻。
在本申请所述的阵列基板中，所述多条辅助连接线与所述多条扇出线中的一一对应；
所述第一绝缘层开设有多个金属化孔，每一所述辅助连接线通过多个金属化孔与对应扇出线并联。
在本申请所述的阵列基板中，所述多条扇出线的长度不均；
所述多条扇出线与所述多条连接辅助线一一对应地并联形成多组并联线，所述多组并联线具的等效电阻相同。
在本申请所述的阵列基板中，每一所述连接辅助线的长度与对应的扇出线的长度相同；所述多个扇出线的厚度相同且宽度不同；所述多条扇出线中长度越长的扇出线所对应的连接辅助线的宽度越大。
本申请实施例通过不同宽度的连接辅助线来与不同长度的扇出线并联，从而调整该扇出线的均衡性，以保证各个像素单元的充电的时间均衡，可以提高显示的均匀性。
在本申请所述的阵列基板中，每一所述连接辅助线的宽度与对应的扇出线的宽度相同；所述多个扇出线的厚度相同且长度不同；所述多条扇出线中长度越长的扇出线所对应的连接辅助线的长度越长。
在本申请所述的阵列基板中，每一所述连接辅助线的长度与对应的扇出线的长度相同；所述多个扇出线的宽度相同且厚度不同；所述多条扇出线中长度越长的扇出线所对应的连接辅助线的厚度越大。
本申请实施例通过不同厚的连接辅助线来与不同长度的扇出线并联，从而调整该扇出线的均衡性，以保证各个像素单元的充电的时间均衡，可以提高显示的均匀性。
第二方面，本申请实施例提供了一种液晶显示面板，其包括阵列基板，所述阵列基板包括：
基板，其具有显示区域以及非显示区域；
多个像素单元，所述多个像素单元设置于所述显示区域；
多个覆晶薄膜芯片，所述多个覆晶薄膜芯片设置于所述非显示区域，每一所述覆晶薄膜芯片通过多条扇出线与多个所述像素单元连接，所述多条扇出线的长度不相同；
多条连接辅助线，其设置于所述非显示区域，每一所述连接辅助线设置为不同的第一预设长度，所述多条连接辅助线中的每一连接辅助线分别与所述多条扇出线中的一条并联，从而调节每一所述扇出线的等效电阻，使得所述多条扇出线对多个所述像素单元的充电时间均衡。
在本申请所述的液晶显示面板中，所述基板上设置有第一金属层、第二金属层以及位于第一金属层和第二金属层之间的第一绝缘层；所述第一金属层形成多条扇出线，所述第二金属层形成多条连接辅助线。
在本申请所述的液晶显示面板中，所述多条辅助连接线与所述多条扇出线中的部分扇出线相对应；
所述第一绝缘层开设有多个金属化孔，每一所述辅助连接线通过多个金属化孔与对应扇出线并联。
在本申请所述的液晶显示面板中，所述多条扇出线包括至少一条第一长度的第一扇出线以及多条第二扇出线，所述多条第二扇出线的长度不均，所述多条第二扇出线的长度均大于所述第一扇出线；
所述多条连接辅助线与所述多条第二扇出线一一对应地并联，使得每一所述第二扇出线与对应连接辅助线的并联等效电阻等于所述第一扇出线的等效电阻。
在本申请所述的液晶显示面板中，所述多条辅助连接线与所述多条扇出线中的一一对应；
所述第一绝缘层开设有多个金属化孔，每一所述辅助连接线通过多个金属化孔与对应扇出线并联。
在本申请所述的液晶显示面板中，所述多条扇出线的长度不均；
所述多条扇出线与所述多条连接辅助线一一对应地并联形成多组并联线，所述多组并联线具的等效电阻相同。
在本申请所述的液晶显示面板中，每一所述连接辅助线的长度与对应的扇出线的长度相同；所述多个扇出线的厚度相同且宽度不同；所述多条扇出线中长度越长的扇出线所对应的连接辅助线的宽度越大。
在本申请所述的液晶显示面板中，每一所述连接辅助线的宽度与对应的扇出线的宽度相同；所述多个扇出线的厚度相同且长度不同；所述多条扇出线中长度越长的扇出线所对应的连接辅助线的长度越长。
在本申请所述的液晶显示面板中，每一所述连接辅助线的长度与对应的扇出线的长度相同；所述多个扇出线的宽度相同且厚度不同；所述多条扇出线中长度越长的扇出线所对应的连接辅助线的厚度越大。
 有益效果
本申请实施例通过设置多条连接辅助线，其设置于所述非显示区域，每一所述连接辅助线设置为第一预设长度，所述多条连接辅助线中的每一连接辅助线分别与所述多条扇出线中的一条并联，从而调节每一所述扇出线的等效电阻，使得所述多条扇出线对多个所述像素单元的充电时间均衡，可以提高显示均衡性，提高显示质量。
 附图说明
为了更清楚地说明本申请实施例的技术方案，下面将对本申请实施例中所需要使用的附图作简单地介绍，应当理解，以下附图仅示出了本申请的某些实施例，因此不应被看作是对范围的限定，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他相关的附图。
图1为本申请实施例提供的阵列基板的结构示意图；
图2为本申请实施例提供的阵列基板的局部结构示意图；
图3为本申请实施例提供的阵列基板的局部剖视结构示意图；以及
图4为本申请实施例提供的阵列基板的另一局部结构示意图。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
在本申请的描述中，需要理解的是，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个所述特征。在本申请的描述中，“多条”的含义是两条或两条以上，除非另有明确具体的限定。
请参照图1以及图2，该图1为本申请实施例提供的一种阵列基板的结构示意图，图2为该阵列基板的局部结构示意图。该阵列基板包括：基板10、多个像素单元20、多个覆晶薄膜芯片30、多条扇出线40a、多条连接辅助线40b、GOA驱动电路60、多条扫描线70以及多条数据线80。
其中，该基板10具有显示区域11以及非显示区域12；该多个像素单元20呈均匀阵列设置于显示区域11；该GOA驱动电路60以及多个覆晶薄膜芯片30设置于该非显示区域12。该多条数据线80以及多条扫描线70纵横交错，界定出多个像素区域，该多个像素单元20分别设置于该多个像素区域。GOA驱动电路60与多条扫描线70连接，该多个覆晶薄膜芯片30通过该多条扇出线40a与该多条数据线80一一对应地连接，从而给对应的像素单元20充电。
其中，该多条扇出线40a的长度不相同；每一连接辅助线40b设置为第一预设长度，多条连接辅助线40b中的每一连接辅助线40b分别与所述多条扇出线40a中的一条并联，从而调节每一所述扇出线40a的等效电阻，使得所述多条扇出线40a对多个所述像素单元20的充电时间均衡。
请同时参照图3，该基板10上设置有第一金属层401a、第二金属层401b以及位于第一金属层401a和第二金属层401b之间的第一绝缘层402；所述第一金属层401a形成多条扇出线40a，所述第二金属层401b形成多条连接辅助线40b。
在一些实施例中，该多条辅助连接线40b与多条扇出线40a中的部分扇出线40a相对应；也即是辅助连接线40b的数量少于该扇出线40a的数量。其中，该第一绝缘层402开设有多个金属化孔4021，每一所述辅助连接线40b通过多个金属化孔4021与对应扇出线40a并联。
具体地，该多条扇出线40a包括至少一条第一长度的第一扇出线以及多条第二扇出线，多条第二扇出线的长度不均，多条第二扇出线的长度均大于所述第一扇出线。多条连接辅助线40b与所述多条第二扇出线一一对应地并联，使得每一所述第二扇出线与对应连接辅助线的并联等效电阻等于所述第一扇出线的等效电阻。通过不同长度的连接辅助线来与不同长度的扇出线并联，从而调整该扇出线的均衡性，以保证各个像素单元的充电的时间均衡，可以提高显示的均匀性。
在一些实施例中，该多条辅助连接线40b与所述多条扇出线40a中的一一对应，也即是二者数量相同。并且，每一条辅助连接线40b与对应的扇出线40a的局部或整体正对。该第一绝缘层402开设有多个金属化孔4021，每一所述辅助连接线通过多个金属化孔4021与对应扇出线40a并联。多条扇出线40a的长度不均；多条扇出线40a与所述多条连接辅助线40b一一对应地并联形成多组并联线，所述多组并联线具的等效电阻相同。通过不同长度的连接辅助线来与不同长度的扇出线并联，从而调整该扇出线的均衡性，以保证各个像素单元的充电的时间均衡，可以提高显示的均匀性。
在一些实施例中，每一所述连接辅助线40b的长度与对应的扇出线40a的长度相同；所述多个扇出线40a的厚度相同且宽度不同；所述多条扇出线40a中长度越长的扇出线40a所对应的连接辅助线的宽度越大。通过设置不同的宽度，从而使得连接辅助线40b的等效电阻各不相同，通过不同宽度的连接辅助线来与不同长度的扇出线并联，从而调整该扇出线的均衡性，以保证各个像素单元的充电的时间均衡，可以提高显示的均匀性。
在一些实施例中，每一所述连接辅助线40b的长度与对应的扇出线40a的长度相同；所述多个扇出线40a的宽度相同且厚度不同，从而使得其等效电阻不同；所述多条扇出线40a中长度越长的扇出线40a所对应的连接辅助线40b的厚度越大。通过不同厚的连接辅助线40b来与不同长度的扇出线40a并联，从而调整该扇出线的均衡性，以保证各个像素单元的充电的时间均衡，可以提高显示的均匀性。
可以理解地，在一些实施例中，每一连接辅助线40b的长度、宽度以及厚度均各不相同或者部分不相同，从而达到更好的设置每一连接辅助线的电阻的目的，进而实现对每一扇出线的等效电阻的精确控制，实现对于各个像素单元的充电时间的均衡调整，可以提高显示质量。
另外，请参阅图4，图4为本申请实施例提供的阵列基板的另一局部结构示意图。图4所示的阵列基板与图2所示的阵列基板的区别在于，在图4所示的阵列基板中，所述多条扇出线40a中长度越长的扇出线40a所对应的连接辅助线40b的长度越长。
具体的，每一所述连接辅助线40b的宽度与对应的扇出线40a的宽度相同；所述多个扇出线40a的厚度相同且长度不同；所述多条扇出线40a中长度越长的扇出线40a所对应的连接辅助线40b的长度越长。通过不同长度的连接辅助线40b来与不同长度的扇出线40a并联，从而调整该扇出线的均衡性，以保证各个像素单元的充电的时间均衡，可以提高显示的均匀性。
由上可知，本申请实施例通过设置多条连接辅助线，其设置于所述非显示区域，每一所述连接辅助线设置为第一预设长度，所述多条连接辅助线中的每一连接辅助线分别与所述多条扇出线中的一条并联，从而调节每一所述扇出线的等效电阻，使得所述多条扇出线对多个所述像素单元的充电时间均衡，可以提高显示均衡性，提高显示质量。
本申请还提供了一种液晶显示面板，该液晶显示面板包括上述任意实施例中的阵列基板，当然该液晶显示面板还包括彩膜基板以及液晶分子层。该阵列基板与该彩膜基板正对且间隔设置，该液晶分子层夹设在该阵列基板与彩膜基板之间。
以上仅为本申请的实施例，并非因此限制本申请的专利范围，凡是利用本申请说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本申请的专利保护范围内。

Claims (18)

  1. 一种阵列基板，其包括：
    基板，其具有显示区域以及非显示区域；
    多个像素单元，所述多个像素单元设置于所述显示区域；
    多个覆晶薄膜芯片，所述多个覆晶薄膜芯片设置于所述非显示区域，每一所述覆晶薄膜芯片通过多条扇出线与多个所述像素单元连接，所述多条扇出线的长度不相同；
    多条连接辅助线，其设置于所述非显示区域，每一所述连接辅助线设置为不同的第一预设长度，所述多条连接辅助线中的每一连接辅助线分别与所述多条扇出线中的一条并联，从而调节每一所述扇出线的等效电阻，使得所述多条扇出线对多个所述像素单元的充电时间均衡。
  2. 根据权利要求1所述的阵列基板，其中，所述基板上设置有第一金属层、第二金属层以及位于第一金属层和第二金属层之间的第一绝缘层；所述第一金属层形成多条扇出线，所述第二金属层形成多条连接辅助线。
  3. 根据权利要求2所述的阵列基板，其中，所述多条辅助连接线与所述多条扇出线中的部分扇出线相对应；
    所述第一绝缘层开设有多个金属化孔，每一所述辅助连接线通过多个金属化孔与对应扇出线并联。
  4. 根据权利要求3所述的阵列基板，其中，所述多条扇出线包括至少一条第一长度的第一扇出线以及多条第二扇出线，所述多条第二扇出线的长度不均，所述多条第二扇出线的长度均大于所述第一扇出线；
    所述多条连接辅助线与所述多条第二扇出线一一对应地并联，使得每一所述第二扇出线与对应连接辅助线的并联等效电阻等于所述第一扇出线的等效电阻。
  5. 根据权利要求2所述的阵列基板，其中，所述多条辅助连接线与所述多条扇出线中的一一对应；
    所述第一绝缘层开设有多个金属化孔，每一所述辅助连接线通过多个金属化孔与对应扇出线并联。
  6. 根据权利要求5所述的阵列基板，其中，所述多条扇出线的长度不均；
    所述多条扇出线与所述多条连接辅助线一一对应地并联形成多组并联线，所述多组并联线具的等效电阻相同。
  7. 根据权利要求1所述的阵列基板，其中，每一所述连接辅助线的长度与对应的扇出线的长度相同；所述多个扇出线的厚度相同且宽度不同；所述多条扇出线中长度越长的扇出线所对应的连接辅助线的宽度越大。
  8. 根据权利要求1所述的阵列基板，其中，每一所述连接辅助线的宽度与对应的扇出线的宽度相同；所述多个扇出线的厚度相同且长度不同；所述多条扇出线中长度越长的扇出线所对应的连接辅助线的长度越长。
  9. 根据权利要求1所述的阵列基板，其中，每一所述连接辅助线的长度与对应的扇出线的长度相同；所述多个扇出线的宽度相同且厚度不同；所述多条扇出线中长度越长的扇出线所对应的连接辅助线的厚度越大。
  10. 一种液晶显示面板，其包括阵列基板，所述阵列基板包括：
    基板，其具有显示区域以及非显示区域；
    多个像素单元，所述多个像素单元设置于所述显示区域；
    多个覆晶薄膜芯片，所述多个覆晶薄膜芯片设置于所述非显示区域，每一所述覆晶薄膜芯片通过多条扇出线与多个所述像素单元连接，所述多条扇出线的长度不相同；
    多条连接辅助线，其设置于所述非显示区域，每一所述连接辅助线设置为不同的第一预设长度，所述多条连接辅助线中的每一连接辅助线分别与所述多条扇出线中的一条并联，从而调节每一所述扇出线的等效电阻，使得所述多条扇出线对多个所述像素单元的充电时间均衡。
  11. 根据权利要求10所述的液晶显示面板，其中，所述基板上设置有第一金属层、第二金属层以及位于第一金属层和第二金属层之间的第一绝缘层；所述第一金属层形成多条扇出线，所述第二金属层形成多条连接辅助线。
  12. 根据权利要求11所述的液晶显示面板，其中，所述多条辅助连接线与所述多条扇出线中的部分扇出线相对应；
    所述第一绝缘层开设有多个金属化孔，每一所述辅助连接线通过多个金属化孔与对应扇出线并联。
  13. 根据权利要求12所述的液晶显示面板，其中，所述多条扇出线包括至少一条第一长度的第一扇出线以及多条第二扇出线，所述多条第二扇出线的长度不均，所述多条第二扇出线的长度均大于所述第一扇出线；
    所述多条连接辅助线与所述多条第二扇出线一一对应地并联，使得每一所述第二扇出线与对应连接辅助线的并联等效电阻等于所述第一扇出线的等效电阻。
  14. 根据权利要求11所述的液晶显示面板，其中，所述多条辅助连接线与所述多条扇出线中的一一对应；
    所述第一绝缘层开设有多个金属化孔，每一所述辅助连接线通过多个金属化孔与对应扇出线并联。
  15. 根据权利要求14所述的液晶显示面板，其中，所述多条扇出线的长度不均；
    所述多条扇出线与所述多条连接辅助线一一对应地并联形成多组并联线，所述多组并联线具的等效电阻相同。
  16. 根据权利要求10所述的液晶显示面板，其中，每一所述连接辅助线的长度与对应的扇出线的长度相同；所述多个扇出线的厚度相同且宽度不同；所述多条扇出线中长度越长的扇出线所对应的连接辅助线的宽度越大。
  17. 根据权利要求10所述的液晶显示面板，其中，每一所述连接辅助线的宽度与对应的扇出线的宽度相同；所述多个扇出线的厚度相同且长度不同；所述多条扇出线中长度越长的扇出线所对应的连接辅助线的长度越长。
  18. 根据权利要求10所述的液晶显示面板，其中，每一所述连接辅助线的长度与对应的扇出线的长度相同；所述多个扇出线的宽度相同且厚度不同；所述多条扇出线中长度越长的扇出线所对应的连接辅助线的厚度越大。
PCT/CN2020/087670 2020-03-31 2020-04-29 阵列基板及液晶显示面板 Ceased WO2021196328A1 (zh)

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CN116009312A (zh) * 2022-12-08 2023-04-25 合肥京东方显示技术有限公司 显示面板和显示装置

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