WO2021184432A1 - 一种像素电路及其驱动方法、显示面板 - Google Patents

一种像素电路及其驱动方法、显示面板 Download PDF

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Publication number
WO2021184432A1
WO2021184432A1 PCT/CN2020/083158 CN2020083158W WO2021184432A1 WO 2021184432 A1 WO2021184432 A1 WO 2021184432A1 CN 2020083158 W CN2020083158 W CN 2020083158W WO 2021184432 A1 WO2021184432 A1 WO 2021184432A1
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Prior art keywords
thin film
film transistor
storage capacitor
pixel circuit
electrically connected
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PCT/CN2020/083158
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English (en)
French (fr)
Inventor
陈勇
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Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Priority to US16/760,041 priority Critical patent/US20220044627A1/en
Publication of WO2021184432A1 publication Critical patent/WO2021184432A1/zh
Anticipated expiration legal-status Critical
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0852—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor being a dynamic memory with more than one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0238—Improving the black level
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation

Definitions

  • This application relates to the field of display technology, and in particular to a pixel circuit and a driving method thereof, and a display panel.
  • FIG. 1 it is a schematic diagram of the structure of an existing under-screen camera display panel.
  • the under-screen camera display panel 90 includes a flexible substrate layer 91, an array substrate 92, a light-emitting layer 93, and an encapsulation layer which are sequentially stacked from bottom to top. 94.
  • Polarizer 95 and cover 96 Polarizer 95 and cover 96.
  • a through hole is provided at the corresponding position of the array substrate 92 and the polarizer 95 to form a blind hole 97.
  • the lens can be hidden below the displayable area of the screen. Finish shooting.
  • the under-screen camera solution in order to increase the light transmittance of the under-screen camera area, when using the classic 7T1C circuit of an organic light-emitting diode (OLED) display, in order to increase the light transmittance of the under-screen camera area, the pixel design needs to be optimized to reduce The pixel density of the camera area under the screen is partially transparent.
  • the 2T1C pixel circuit Mounting the 2T1C pixel circuit above the under-screen camera area can well reduce the pixel density. Because the camera area is small, the 2T1C pixel circuit has less impact on the display screen, but the current 2T1C pixel circuit working voltage is not given by the driving circuit. Within the normal data voltage range, it is not advisable to carry traditional 2T1C pixel circuits in the camera area under the screen.
  • the purpose of the present invention is to provide a pixel circuit, a driving method thereof, and a display panel, which can achieve the effect of improving light transmittance by changing the circuit structure of the camera area under the screen.
  • the present invention provides a pixel circuit, including: a first thin film transistor, a second thin film transistor, a first storage capacitor, a second storage capacitor, and an organic light emitting diode;
  • the scan signal is connected, the source of the first thin film transistor is electrically connected to the data signal, and the drain is electrically connected to the gate of the second thin film transistor, the first end of the first storage capacitor, and the first end of the second storage capacitor;
  • the source of the second thin film transistor is electrically connected to the positive voltage of the power source, and the drain is electrically connected to the anode of the organic light emitting diode;
  • the cathode of the organic light emitting diode is electrically connected to the negative voltage of the power source;
  • the first end of the first storage capacitor is electrically connected
  • the drain of the first thin film transistor and the second terminal are electrically connected to the source of the second thin film transistor;
  • the first terminal of the second storage capacitor is electrically connected to the drain of the first thin film transistor, and the second terminal is
  • the capacitance value of the second storage capacitor is 1/7 of the capacitance value of the first storage capacitor.
  • first thin film transistor and the second thin film transistor are any one of a low temperature polysilicon thin film transistor, an oxide semiconductor thin film transistor, or an amorphous silicon thin film transistor.
  • control signal is provided by an external timing controller.
  • the first thin film transistor provides a constant driving current for the organic light emitting diode.
  • the present invention also provides a driving method, which includes the following steps: a scan signal controls the first thin film transistor to turn on, and the data signal enters the gate of the second thin film transistor through the first thin film transistor, and the first thin film transistor.
  • the storage capacitor and the second storage capacitor, and then the first thin film transistor is closed. Due to the storage effect of the first storage capacitor and the second storage capacitor, the gate voltage of the second thin film transistor can still maintain the data signal voltage, so that the second thin film transistor In the on state, the driving current enters the organic light emitting diode through the second thin film transistor to drive the organic light emitting diode to emit light.
  • the gate voltage of the second thin film transistor is less than the threshold voltage of the second thin film transistor.
  • control signal is provided by an external timing controller.
  • the present invention also provides a display panel including the pixel circuit described above.
  • the display panel includes an under-screen camera area and a display area arranged around the under-screen camera area, and the pixel circuit is arranged in the under-screen camera area.
  • the technical effect of the present invention is to provide a pixel circuit, a driving method thereof, and a display panel.
  • a storage capacitor is added to the 2T1C pixel circuit and electrically connected to the control signal, thereby lowering the gate voltage of the second thin film transistor.
  • the current of the pixel circuit under the same data signal voltage is greatly increased. Setting the modified pixel circuit in the camera area under the screen can reduce the pixel density and increase the light transmittance of the camera area under the screen.
  • FIG. 1 is a schematic diagram of the structure of an existing under-screen camera display panel
  • Figure 2 is a schematic diagram of the structure of a 2T1C pixel circuit
  • FIG. 3 is a timing diagram of the scan signal Scan in the 2T1C pixel circuit shown in FIG. 2;
  • FIG. 4 is a simulation result diagram of the 2T1C pixel circuit shown in FIG. 2;
  • FIG. 5 is a schematic structural diagram of a 7T1C pixel circuit
  • FIG. 6 is a timing diagram of the 7T1C pixel circuit shown in FIG. 5;
  • FIG. 7 is a simulation result diagram of the 7T1C pixel circuit shown in FIG. 5;
  • FIG. 8 is a schematic structural diagram of a 2T2C pixel circuit provided by an embodiment of the present invention.
  • FIG. 9 is a schematic diagram of a partial structure of the display panel.
  • FIG. 10 is a timing diagram of the 2T2C pixel circuit shown in FIG. 8;
  • FIG. 11 is a simulation result diagram of the 2T2C pixel circuit shown in FIG. 8.
  • connection should be understood in a broad sense, unless otherwise clearly specified and limited.
  • it can be a fixed connection or a detachable connection.
  • Connected or integrally connected it can be mechanically connected, or electrically connected or can communicate with each other; it can be directly connected or indirectly connected through an intermediate medium, it can be the internal communication of two components or the interaction of two components relation.
  • an intermediate medium it can be the internal communication of two components or the interaction of two components relation.
  • the 2T1C pixel circuit includes a first thin film transistor T10, a second thin film transistor T20, a storage capacitor Cst, and an organic light emitting element OLED.
  • the gate of the first thin film transistor T10 is electrically connected to the scan signal Scan.
  • the timing diagram of the scan signal Scan is shown in FIG.
  • the gate of the thin film transistor T20 and one end of the storage capacitor Cst are electrically connected; the drain of the second thin film transistor T20 is electrically connected to the positive power supply voltage VDD, and the source is electrically connected to the anode of the organic light emitting diode OLED; and the organic light emitting diode OLED
  • the cathode of the storage capacitor Cst is electrically connected to the negative power supply voltage VSS; one end of the storage capacitor Cst is electrically connected to the drain of the first thin film transistor T10, and the other end is electrically connected to the source of the second thin film transistor T20.
  • the scan signal Scan controls the first thin film transistor T10 to turn on, and the data signal Data enters the gate of the second thin film transistor T20 and the storage capacitor Cst through the first thin film transistor T10, and then the first thin film transistor T10 is turned off.
  • the gate voltage of the second thin film transistor T20 can still maintain the data signal voltage, so that the second thin film transistor T20 is in the on state, and the driving current enters the organic light emitting diode OLED through the second thin film transistor T20 to drive organic light emission The diode OLED emits light.
  • the 2T1C pixel circuit does not capture the threshold voltage Vth, keeping the size of the thin film transistor and the storage capacitor consistent with the classic 7T1C.
  • the voltage of the data signal Data written by the first thin film transistor T10 is 3.0V, according to the simulation result of Figure 4, it can be seen that The gate voltage Q point of the second thin film transistor T20 will reach 3.4V due to the connection with the drain of the first thin film transistor T10, so there is no Vth capture of the 7T1C circuit.
  • the 7T1C pixel circuit includes: a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, and a sixth transistor.
  • M6 a seventh transistor M7, a storage capacitor Cst, and an organic light-emitting element OLED.
  • the gate of the first transistor M1 is connected to the first segment of the storage capacitor Cst, the first electrode of the first transistor M1 is connected to the first electrode of the second transistor M2, and the first transistor M1
  • the second electrode of is connected to the first electrode of the third transistor M3.
  • the gate of the second transistor M2 is connected to the second scan signal terminal Scan(n), and the second electrode of the second transistor M2 is connected to the data signal terminal Vdata.
  • the gate of the third transistor M3 is connected to the second scan signal terminal Scan(n), and the second electrode of the third transistor M3 is connected to the first terminal of the storage capacitor Cst.
  • the second terminal of the storage capacitor Cst is connected to the first voltage signal terminal VDD.
  • the gate of the fourth transistor M4 is connected to the first scan signal terminal Scan(n-1), the first electrode of the fourth transistor M4 is connected to the first terminal of the storage capacitor Cst, and the fourth transistor The second electrode of M4 is connected to the initialization signal terminal Vi.
  • the gate of the fifth transistor M5 is connected to the control signal terminal EM, the first electrode of the fifth transistor M5 is connected to the first voltage signal terminal VDD, and the second electrode of the fifth transistor M5 is connected to the The first electrode of the first transistor M1 is connected.
  • the gate of the sixth transistor M6 is connected to the control signal terminal EM, the first electrode of the sixth transistor M6 is connected to the second electrode of the first transistor M1, and the second electrode of the sixth transistor M6 is The electrode is connected to the anode of the organic light emitting element OLED.
  • the cathode of the organic light emitting element OLED is connected to the second voltage signal terminal VSS.
  • the gate of the seventh transistor M7 is connected to the second scan signal terminal Scan(n), the first electrode of the seventh transistor M7 is connected to the initialization signal terminal Vi, and the first electrode of the seventh transistor M7 The two electrodes are connected with the anode of the organic light emitting element OLED.
  • the third transistor M3 includes two sub-transistors connected in series, the gate of the first sub-transistor M31 is connected to the second scan signal terminal Scan(n), and the first electrode of the first sub-transistor M31 Is connected to the second electrode of the second sub-transistor M32, the second electrode of the first sub-transistor M31 is connected to the first end of the storage capacitor Cst; the gate of the second sub-transistor M32 is connected to the second scan signal The terminal Scan(n) is connected, and the first electrode of the second sub-transistor M32 is connected to the second electrode of the first transistor M1.
  • the fourth transistor M4 includes two sub-transistors connected in series, the gate of the third sub-transistor M41 is connected to the first scan signal terminal Scan(n-1), and the third sub-transistor M41 A Tina is connected to the first terminal of the storage capacitor Cst, the second electrode of the third sub-transistor M41 is connected to the first electrode of the fourth sub-transistor M42; the gate of the fourth sub-transistor M42 is connected to The first scan signal terminal Scan(n-1) is connected, and the second electrode of the fourth sub-transistor M42 is connected to the initialization signal terminal Vi.
  • the first terminal of the storage capacitor Cst, the gate of the first transistor M1, the second electrode of the third transistor M3, and the first electrode of the fourth transistor M4 are electrically connected to each other.
  • the timing diagram of the 7T1C pixel circuit is shown in FIG. 6.
  • the first scan signal terminal Scan(n-1) provides a low-level signal
  • the fourth transistor M4 is turned on
  • the initialization signal Vi passes
  • the fourth transistor M4 initializes the storage capacitor Cst.
  • the second scan signal terminal Scan(n) provides a low-level signal
  • the second transistor M2 and the third transistor M3 are turned on
  • the signal provided by the data signal terminal Data affects the storage capacitor Cst.
  • the first end of the battery is charged until the first transistor M1 is turned off. Maintain the conventional thin film transistor size and storage capacitor size in the 7T1C pixel circuit.
  • the simulation result is shown in Figure 7.
  • the gate voltage of the first transistor M1 reaches 1.4V due to its Vth extraction, and the written VDD voltage in the 7T1C pixel circuit is 4.6V.
  • VSS is -4.0V.
  • the current flowing through the OLED in the 2T1C pixel circuit is at least 3 orders of magnitude different from the current flowing through the OLED in the 7T1C pixel circuit. That is, for the 2T1C pixel circuit, to achieve the same current value as the 7T1C pixel circuit, Write a smaller Data voltage.
  • the Data value range of the 7T1C pixel circuit is about 3.0V-6.0V; the Data value range corresponding to the 2T1C pixel circuit is about 0.5V-3.5V, and the working voltage of the 2T1C pixel circuit is not the normal data voltage given by the drive circuit. Therefore, it is not advisable to carry 2T1C pixel circuits in the camera area under the screen.
  • the applicant has conducted research to provide a pixel circuit and a display panel, and a capacitor is introduced on the 2T1C pixel circuit to improve the light transmittance.
  • the 2T2C pixel circuit includes a first thin film transistor T10, a second thin film transistor T20, a first storage capacitor C10, a second storage capacitor C20, and an organic light emitting element OLED.
  • the gate of the first thin film transistor T10 is electrically connected to the scan signal Scan, the source of the first thin film transistor T10 is electrically connected to the data signal Data, and the drain is connected to the gate of the second thin film transistor T20 and the first storage capacitor C10.
  • the first terminal of the second storage capacitor C20 is electrically connected to the first terminal; the source of the second thin film transistor T20 is electrically connected to the positive power supply voltage VDD, and the drain is electrically connected to the anode of the organic light emitting diode OLED; The cathode of the diode OLED is electrically connected to the negative power supply voltage VSS; the first end of the first storage capacitor C10 is electrically connected to the drain of the first thin film transistor T10, and the second end is electrically connected to the source of the second thin film transistor T20; The first terminal of the storage capacitor C20 is electrically connected to the drain of the first thin film transistor T10, and the second terminal is electrically connected to the control signal EM.
  • FIG. 9 is a schematic diagram of a partial structure of the display panel, including a control signal EM11, a scan signal Scan12, an active layer 13, a source and drain layer 14, a capacitor 15, a first gate layer 16, and a second gate layer 17.
  • the timing diagram of the scan signal Scan and the control signal EM is shown in FIG. 10.
  • the scan signal Scan controls the first thin film transistor T10 to turn on, and the data signal Data enters the gate of the second thin film transistor T20 through the first thin film transistor T10 , The first storage capacitor C10 and the second storage capacitor C20, and then the first thin film transistor T10 is closed, due to the storage effect of the first storage capacitor C10 and the second storage capacitor C20, the gate voltage of the second thin film transistor T20 can still be maintained
  • the data signal voltage causes the second thin film transistor T20 to be in an on state, and the driving current enters the organic light emitting diode OLED through the second thin film transistor T20, and drives the organic light emitting diode OLED to emit light.
  • a second storage capacitor C20 is introduced into the gate of the second thin film transistor T20, and the second storage capacitor C20 is 10 fF (about the first storage capacitor C10). 1/7 of the capacitance value).
  • the gate voltage Q point of the second thin film transistor T20 will be connected to the first end of the second storage capacitor C20, and the EM control signal pulls down the Q point
  • This embodiment also provides a display panel including the 2T2C pixel circuit involved in this example.
  • the display panel includes an under-screen camera area and a display area arranged around the under-screen camera area, and the 2T2C pixel circuit is arranged in the under-screen camera area.
  • the technical effect of the present invention is to provide a pixel circuit, a driving method thereof, and a display panel.
  • a storage capacitor is added to the 2T1C pixel circuit and electrically connected to the control signal, thereby lowering the gate voltage of the second thin film transistor.
  • the current of the pixel circuit under the same data signal voltage is greatly increased. Setting the modified pixel circuit in the camera area under the screen can reduce the pixel density and increase the light transmittance of the camera area under the screen.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of El Displays (AREA)
  • Electroluminescent Light Sources (AREA)

Abstract

一种像素电路及其驱动方法、显示面板，所述像素电路包括第一薄膜晶体管（T10）、第二薄膜晶体管(T20)、第一存储电容(C10)、第二存储电容（C20）以及有机发光二极管(OLED)。通过在2T1C像素电路上增加一个存储电容，和控制信号电性连接，进而拉低第二薄膜晶体管（T20）的栅极电压，使得相同数据信号电压下的像素电路的电流大幅提高。

Description

一种像素电路及其驱动方法、显示面板 技术领域
本申请涉及显示技术领域，尤其涉及一种像素电路及其驱动方法、显示面板。
 背景技术
随着科技的不断发展，人们对显示器件的要求越来越高、显示屏技术发展也突飞猛进。现如今“全面屏”的设计成为时代的主流，各屏幕供应商都专注于研发屏占比较高的全面屏产品，提升显示屏屏占比成为一种产品发展的趋势。
目前市面上较多的提高屏占比方案通常将前置摄像头设计在显示屏外侧，通过异形切割设计使显示屏避让一定尺寸来容纳前置摄像头，不论切割设计如何变化，与全面屏概念相差甚远。近期兴起的发光型盲孔屏下摄像头（CUP）处理方案可使显示屏几乎趋近于全面屏效果。
如图1所示，为现有的一种屏下摄像头显示面板的结构示意图，屏下摄像头显示面板90包括从下至上依次层叠设置的柔性衬底层91、阵列基板92、发光层93、封装层94、偏光片95及盖板96。在阵列基板92和偏光片95对应位置设置通孔，形成盲孔97。将摄像头98置于屏幕下方并对应盲孔97设置，即盲孔97和摄像头98所在区域为屏下摄像头区域，通过面板设计与镜头设计的优化，使得镜头隐藏至屏幕的可显示区域下方也能完成拍摄。采用屏下摄像头方案时，为提高屏下摄像头区域的透光率，采用有机发光二极管（OLED）显示屏经典的7T1C电路时，为提高屏下摄像头区域的透光率，需要优化像素设计以降低屏下摄像头区域的像素密度实现局部透明。
在屏下摄像头区域上方搭载2T1C像素电路可以很好地降低像素密度，因摄像头区域面积较小，搭载2T1C像素电路对显示画面影响较小，但目前的2T1C像素电路工作电压不在驱动电路给定的正常数据电压范围内，故屏下摄像头区域搭载传统2T1C像素电路不可取。
屏下摄像头技术中，最影响成像的因素是屏幕的透光率，因此，提高屏下摄像头区域的透光率成为亟需解决的问题。
 技术问题
本发明的目的在于，提供一种像素电路及其驱动方法、显示面板，通过改变屏下摄像头区域的电路结构，实现提高透光率的效果。
 技术解决方案
为实现上述目的，本发明提供一种像素电路，包括：第一薄膜晶体管、第二薄膜晶体管、第一存储电容、第二存储电容以及有机发光二极管；所述第一薄膜晶体管的栅极电性连接扫描信号，第一薄膜晶体管的源极电性连接数据信号，其漏极与第二薄膜晶体管的栅极、第一存储电容的第一端、第二存储电容的第一端电性连接；所述第二薄膜晶体管的源极电性连接电源正电压，漏极电性连接有机发光二极管的阳极；有机发光二极管的阴极电性连接电源负电压；第一存储电容的第一端电性连接第一薄膜晶体管的漏极，第二端电性连接第二薄膜晶体管的源极；第二存储电容的第一端电性连接第一薄膜晶体管的漏极，第二端电性连接控制信号。
进一步地，所述第二存储电容的电容值为所述第一存储电容的电容值的1/7。
进一步地，所述第一薄膜晶体管、第二薄膜晶体管为低温多晶硅薄膜晶体管、氧化物半导体薄膜晶体管或非晶硅薄膜晶体管中的任一种。
进一步地，所述控制信号由外部时序控制器提供。
进一步地，所述第一薄膜晶体管为所述有机发光二极管提供恒定的驱动电流。
为实现上述目的，本发明还提供一种驱动方法，所述驱动方法包括如下步骤：扫描信号控制第一薄膜晶体管打开，数据信号经过第一薄膜晶体管进入到第二薄膜晶体管的栅极、第一存储电容和第二存储电容，然后第一薄膜晶体管闭合，由于第一存储电容和第二存储电容的存储作用，第二薄膜晶体管的栅极电压仍可继续保持数据信号电压，使得第二薄膜晶体管处于导通状态，驱动电流通过第二薄膜晶体管进入有机发光二极管，驱动有机发光二极管发光。
进一步地，第二薄膜晶体管的栅极电压小于所述第二薄膜晶体管的阈值电压。
进一步地，所述控制信号由外部时序控制器提供。
本发明还提供一种显示面板，包括如前文所述的像素电路。
进一步地，所述显示面板包括屏下摄像头区以及围绕所述屏下摄像头区设置的显示区，所述像素电路设置于所述屏下摄像头区内。
 有益效果
本发明的技术效果在于，提供一种像素电路及其驱动方法、显示面板，通过在2T1C像素电路上增加一个存储电容，和控制信号电性连接，进而拉低第二薄膜晶体管的栅极电压，使得相同数据信号电压下的像素电路的电流大幅提高，将改像素电路设置在屏下摄像头区域可以很好地降低像素密度，提高屏下摄像头区域的透光率。
 附图说明
下面结合附图，通过对本申请的具体实施方式详细描述，将使本申请的技术方案及其它有益效果显而易见。
图1为现有的一种屏下摄像头显示面板的结构示意图；
图2为一2T1C像素电路的结构示意图；
图3为图2所示2T1C像素电路中的扫描信号Scan的时序图；
图4为图2所示2T1C像素电路的仿真结果图；
图5为一7T1C像素电路的结构示意图；
图6为图5所示7T1C像素电路的时序图；
图7为图5所示7T1C像素电路的仿真结果图；
图8为本发明实施例提供的一2T2C像素电路的结构示意图；
图9为所述显示面板的局部结构示意图；
图10为图8所示2T2C像素电路的时序图；
图11为图8所示2T2C像素电路的仿真结果图。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
在本申请的描述中，需要说明的是，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是电连接或可以相互通讯；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通或两个元件的相互作用关系。对于本领域的普通技术人员而言，可以根据具体情况理解上述术语在本申请中的具体含义。
图2为一2T1C像素电路的结构示意图，所述2T1C像素电路包括第一薄膜晶体管T10、第二薄膜晶体管T20、存储电容Cst以及有机发光元件OLED。
所述第一薄膜晶体管T10的栅极电性连接扫描信号Scan，扫描信号Scan的时序图如图3所示，第一薄膜晶体管T10的源极电性连接数据信号Data，其漏极与第二薄膜晶体管T20的栅极及存储电容Cst的一端电性连接；所述第二薄膜晶体管T20的漏极电性连接电源正电压VDD，源极电性连接有机发光二极管OLED的阳极；有机发光二极管OLED的阴极电性连接电源负电压VSS；存储电容Cst的一端电性连接第一薄膜晶体管T10的漏极，另一端电性连接第二薄膜晶体管T20的源极。
在显示时，扫描信号Scan控制第一薄膜晶体管T10打开，数据信号Data经过第一薄膜晶体管T10进入到第二薄膜晶体管T20的栅极及存储电容Cst，然后第一薄膜晶体管T10闭合，由于存储电容Cst的存储作用，第二薄膜晶体管T20的栅极电压仍可继续保持数据信号电压，使得第二薄膜晶体管T20处于导通状态，驱动电流通过第二薄膜晶体管T20进入有机发光二极管OLED，驱动有机发光二极管OLED发光。
2T1C像素电路没有阈值电压Vth抓取，保持薄膜晶体管和存储电容的尺寸大小与经典7T1C一致，当第一薄膜晶体管T10写入的数据信号Data电压为3.0V时，根据图4的仿真结果可知，第二薄膜晶体管T20的栅极电压Q点会因与第一薄膜晶体管T10的漏极连接作用达到3.4V，故没有7T1C电路的Vth抓取。当写入VDD电压为4.6V，VSS为-4.0V时，对于p型TFT，此时栅极电压Vgs =3.4 - 4.6 = -1.2V，大于第二薄膜晶体管T20的阈值电压Vth（约-2.5V），第二薄膜晶体管T20处于未打开状态，理论上流过有机发光二极管的电流几乎为0，与图4仿真结果IOLED = 3.5 pA 相近。
如图5所示，为一7T1C像素电路的结构示意图，所述7T1C像素电路包括：第一晶体管M1、第二晶体管M2、第三晶体管M3、第四晶体管M4、第五晶体管M5、第六晶体管M6、第七晶体管M7、存储电容Cst以及有机发光元件OLED。
所述第一晶体管M1的栅极与所述存储电容Cst的第一段连接，所述第一晶体管M1的第一电极与所述第二晶体管M2的第一电极连接，所述第一晶体管M1的第二电极与所述第三晶体管M3的第一电极连接。所述第二晶体管M2的栅极与第二扫描信号端Scan(n)连接，所述第二晶体管M2的第二电极与数据信号端Vdata连接。所述第三晶体管M3的栅极与所述第二扫描信号端Scan(n)连接，所述第三晶体管M3的第二电极与所述存储电容Cst的第一端连接。所述存储电容Cst的第二端与第一电压信号端VDD连接。
所述第四晶体管M4的栅极与第一扫描信号端Scan(n-1)连接，所述第四晶体管M4的第一电极与所述存储电容Cst的第一端连接，所述第四晶体管M4的第二电极与初始化信号端Vi连接。所述第五晶体管M5的栅极与控制信号端EM连接，所述第五晶体管M5的第一电极与所述第一电压信号端VDD连接，所述第五晶体管M5的第二电极与所述第一晶体管M1的第一电极连接。所述第六晶体管M6的栅极与所述控制信号端EM连接，所述第六晶体管M6的第一电极与所述第一晶体管M1的第二电极连接，所述第六晶体管M6的第二电极与所述有机发光元件OLED的阳极连接。所述有机发光元件OLED的阴极与第二电压信号端VSS连接。
所述第七晶体管M7的栅极与所述第二扫描信号端Scan(n)连接，所述第七晶体管M7的第一电极与所述初始化信号端Vi连接，所述第七晶体管M7的第二电极与所述有机发光元件OLED的阳极连接。
其中，所述第三晶体管M3包含相串连的两个子晶体管，第一子晶体管M31的栅极与所述第二扫描信号端Scan(n)连接，所述第一子晶体管M31的第一电极与第二子晶体管M32的第二电极连接，第一子晶体管M31的第二电极与所述存储电容Cst的第一端连接；所述第二子晶体管M32的栅极与所述第二扫描信号端Scan(n)连接，所述第二子晶体管M32的第一电极与所述第一晶体管M1的第二电极相连。
其中，所述第四晶体管M4包含相串连的两个子晶体管，第三子晶体管M41的栅极与所述第一扫描信号端Scan(n-1)连接，所述第三子晶体管M41的第一蒂娜及与所述存储电容Cst的第一端连接，所述第三子晶体管M41的第二电极与第四子晶体管M42的第一电极连接；所述第四子晶体管M42的栅极与所述第一扫描信号端Scan(n-1)连接，所述第四子晶体管M42的第二电极与所述初始化信号端Vi连接。
所述存储电容Cst的第一端、所述第一晶体管M1的栅极、所述第三晶体管M3的第二电极以及所述第四晶体管M4的第一电极相互电性连接。
7T1C像素电路的时序图如图6所示，在初始化阶段，所述第一扫描信号端Scan(n-1)提供低电平信号，所述第四晶体管M4导通，所述初始化信号Vi通过所述第四晶体管M4对所述存储电容Cst进行初始化。在数据写入阶段，第二扫描信号端Scan(n)提供低电平信号，所述第二晶体管M2与第三晶体管M3导通，所述数据信号端Data提供的信号对所述存储电容Cst的第一端进行充电，至所述第一晶体管M1截止。在7T1C像素电路中保持常规的薄膜晶体管尺寸和存储电容大小。
仿真结果如图7所示，当写入的Data电压为3.0V时，所述第一晶体管M1的栅极电压因其Vth提取达到1.4V，在7T1C像素电路中写入VDD电压为4.6V，VSS为-4.0V，对于p型TFT，此时栅极电压Vgs =1.4 - 4.6 = -3.2V，小于所述第一晶体管M1的阈值电压Vth（约-2.5V），所述第一晶体管M1处于打开状态，仿真结果可知，通过OLED的电流为18nA。
在相同的Data写入电压下，在2T1C像素电路流过OLED的电流与7T1C像素电路流过OLED的电流相差至少3个数量级，即对于2T1C像素电路，要达到与7T1C像素电路相同电流值，需写入更小的Data电压。一般在7T1C像素电路工作的Data 值范围约为3.0V-6.0V；相对应2T1C像素电路工作的Data 值范围约为0.5V-3.5V，2T1C像素电路工作电压不在驱动电路给定的正常数据电压范围内，故屏下摄像头区域搭载2T1C 像素电路不可取。
针对上述技术问题，申请人经过研究，提供一种像素电路及显示面板，在2T1C 像素电路上引入一个电容，提高透光率。
图8为本实施例提供的2T2C像素电路的结构示意图，所述2T2C像素电路包括第一薄膜晶体管T10、第二薄膜晶体管T20、第一存储电容C10、第二存储电容C20以及有机发光元件OLED。
所述第一薄膜晶体管T10的栅极电性连接扫描信号Scan，第一薄膜晶体管T10的源极电性连接数据信号Data，其漏极与第二薄膜晶体管T20的栅极、第一存储电容C10的第一端、第二存储电容C20的第一端电性连接；所述第二薄膜晶体管T20的源极电性连接电源正电压VDD，漏极电性连接有机发光二极管OLED的阳极；有机发光二极管OLED的阴极电性连接电源负电压VSS；第一存储电容C10的第一端电性连接第一薄膜晶体管T10的漏极，第二端电性连接第二薄膜晶体管T20的源极；第二存储电容C20的第一端电性连接第一薄膜晶体管T10的漏极，第二端电性连接控制信号EM。
图9为所述显示面板的局部结构示意图，包括控制信号EM11、扫描信号Scan12、有源层13、源漏极层14、电容15、第一栅极层16、第二栅极层17。
扫描信号Scan和控制信号EM的时序图如图10所示，在显示时，扫描信号Scan控制第一薄膜晶体管T10打开，数据信号Data经过第一薄膜晶体管T10进入到第二薄膜晶体管T20的栅极、第一存储电容C10和第二存储电容C20，然后第一薄膜晶体管T10闭合，由于第一存储电容C10和第二存储电容C20的存储作用，第二薄膜晶体管T20的栅极电压仍可继续保持数据信号电压，使得第二薄膜晶体管T20处于导通状态，驱动电流通过第二薄膜晶体管T20进入有机发光二极管OLED，驱动有机发光二极管OLED发光。
当第一薄膜晶体管T10写入的数据信号Data电压为3.0V时，在第二薄膜晶体管T20的栅极引入第二存储电容C20，第二存储电容C20为10 fF（约为第一存储电容C10电容值的1/7），根据图11的仿真结果可知，此时第二薄膜晶体管T20的栅极电压Q点会因与第二存储电容C20的第一端连接，EM控制信号拉低Q点电压至1.7V，写入VDD电压为4.6V，VSS为-4.0V时，对于p型TFT，此时第二薄膜晶体管T20的栅极电压Vgs =1.7 - 4.6 = -2.9V，小于第二薄膜晶体管T20的阈值电压Vth（约-2.5V），第二薄膜晶体管T20处于打开状态，由图10仿真结果可知，通过有机发光二极管OLED的电流IOLED = 12.5nA，与7T1C电路流过OLED的电流处同一数量级，即改进后的2T2C 像素电路与7T1C电路达到相同电流范围的电压相差不大。
本实施例还提供一种显示面板，包括本实例涉及的所述2T2C像素电路。
所述显示面板包括屏下摄像头区以及围绕所述屏下摄像头区设置的显示区，所述2T2C像素电路设置于所述屏下摄像头区内。
本发明的技术效果在于，提供一种像素电路及其驱动方法、显示面板，通过在2T1C像素电路上增加一个存储电容，和控制信号电性连接，进而拉低第二薄膜晶体管的栅极电压，使得相同数据信号电压下的像素电路的电流大幅提高，将改像素电路设置在屏下摄像头区域可以很好地降低像素密度，提高屏下摄像头区域的透光率。
在上述实施例中，对各个实施例的描述都各有侧重，某个实施例中没有详述的部分，可以参见其他实施例的相关描述。
以上对本申请实施例所提供的进行了一种像素电路及其驱动方法、显示面板的详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的技术方案及其核心思想；本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例的技术方案的范围。

Claims (18)

  1. 一种像素电路，其中，包括：第一薄膜晶体管、第二薄膜晶体管、第一存储电容、第二存储电容以及有机发光二极管；
    所述第一薄膜晶体管的栅极电性连接扫描信号，第一薄膜晶体管的源极电性连接数据信号，其漏极与第二薄膜晶体管的栅极、第一存储电容的第一端、第二存储电容的第一端电性连接；
    所述第二薄膜晶体管的源极电性连接电源正电压，漏极电性连接有机发光二极管的阳极；
    有机发光二极管的阴极电性连接电源负电压；
    第一存储电容的第一端电性连接第一薄膜晶体管的漏极，第二端电性连接第二薄膜晶体管的源极；
    第二存储电容的第一端电性连接第一薄膜晶体管的漏极，第二端电性连接控制信号。
  2. 如权利要求1所述的像素电路，其中，所述第二存储电容的电容值为所述第一存储电容的电容值的1/7。
  3. 如权利要求1所述的像素电路，其中，所述第一薄膜晶体管、第二薄膜晶体管为低温多晶硅薄膜晶体管、氧化物半导体薄膜晶体管或非晶硅薄膜晶体管中的任一种。
  4. 如权利要求1所述的像素电路，其中，
    所述控制信号由外部时序控制器提供。
  5. 如权利要求1所述的像素电路，其中，
    所述第一薄膜晶体管为所述有机发光二极管提供恒定的驱动电流。
  6. 如权利要求1所述的像素电路的驱动方法，其中，所述驱动方法包括如下步骤：
    扫描信号控制第一薄膜晶体管打开，数据信号经过第一薄膜晶体管进入到第二薄膜晶体管的栅极、第一存储电容和第二存储电容，然后第一薄膜晶体管闭合，由于第一存储电容和第二存储电容的存储作用，第二薄膜晶体管的栅极电压仍可继续保持数据信号电压，使得第二薄膜晶体管处于导通状态，驱动电流通过第二薄膜晶体管进入有机发光二极管，驱动有机发光二极管发光。
  7. 如权利要求6所述的驱动方法，其中，
    第二薄膜晶体管的栅极电压小于所述第二薄膜晶体管的阈值电压。
  8. 如权利要求6所述的驱动方法，其中，
    所述控制信号由外部时序控制器提供。
  9. 如权利要求6所述的驱动方法，其中，所述第二存储电容的电容值为所述第一存储电容的电容值的1/7。
  10. 如权利要求6所述的驱动方法，其中，所述第一薄膜晶体管、第二薄膜晶体管为低温多晶硅薄膜晶体管、氧化物半导体薄膜晶体管或非晶硅薄膜晶体管中的任一种。
  11. 如权利要求6所述的驱动方法，其中，
    所述控制信号由外部时序控制器提供。
  12. 如权利要求6所述的驱动方法，其中，
    所述第一薄膜晶体管为所述有机发光二极管提供恒定的驱动电流。
  13. 一种显示面板，其中，包括权利要求1所述的像素电路。
  14. 根据权利要求13所述的显示面板，其中，所述显示面板包括屏下摄像头区以及围绕所述屏下摄像头区设置的显示区，所述像素电路设置于所述屏下摄像头区内。
  15. 如权利要求14所述的显示面板，其中，所述第二存储电容的电容值为所述第一存储电容的电容值的1/7。
  16. 如权利要求14所述的显示面板，其中，所述第一薄膜晶体管、第二薄膜晶体管为低温多晶硅薄膜晶体管、氧化物半导体薄膜晶体管或非晶硅薄膜晶体管中的任一种。
  17. 如权利要求14所述的显示面板，其中，
    所述控制信号由外部时序控制器提供。
  18. 如权利要求14所述的显示面板，其中，
    所述第一薄膜晶体管为所述有机发光二极管提供恒定的驱动电流。
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