WO2021180102A1 - 评估器件热载流子效应的方法 - Google Patents

评估器件热载流子效应的方法 Download PDF

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WO2021180102A1
WO2021180102A1 PCT/CN2021/079878 CN2021079878W WO2021180102A1 WO 2021180102 A1 WO2021180102 A1 WO 2021180102A1 CN 2021079878 W CN2021079878 W CN 2021079878W WO 2021180102 A1 WO2021180102 A1 WO 2021180102A1
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current
gate
source
ratio
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许杞安
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Changxin Memory Technologies Inc
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2855—Environmental, reliability or burn-in testing
    • G01R31/2856—Internal circuit aspects, e.g. built-in test features; Test chips; Measuring material aspects, e.g. electro migration [EM]
    • G01R31/2858—Measuring of material aspects, e.g. electro-migration [EM], hot carrier injection
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P74/00—Testing or measuring during manufacture or treatment of wafers, substrates or devices
    • H10P74/20—Testing or measuring during manufacture or treatment of wafers, substrates or devices characterised by the properties tested or measured, e.g. structural or electrical properties
    • H10P74/207—Electrical properties, e.g. testing or measuring of resistance, deep levels or capacitance-voltage characteristics
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/26—Testing of individual semiconductor devices
    • G01R31/2607—Circuits therefor
    • G01R31/2637—Circuits therefor for testing other individual devices
    • G01R31/2639—Circuits therefor for testing other individual devices for testing field-effect devices, e.g. of MOS-capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P74/00—Testing or measuring during manufacture or treatment of wafers, substrates or devices

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  • the present invention relates to the field of semiconductors, and in particular to a method for evaluating the hot carrier effect of a device.
  • HCI hot carrier
  • This application provides a method for evaluating the hot carrier effect of a device, including:
  • the influence of the process parameter adjustment or the device parameter adjustment on the hot carrier effect of the device is determined based on the second current ratio and the first current ratio.
  • FIG. 1 is a flowchart of a method for evaluating the hot carrier effect of a device provided by the present invention.
  • Figure 2 is a method for evaluating the hot carrier effect of a device provided by the present invention, taking the drain voltage of the first device and the drain voltage of the second device as 2.6V as an example, and the first current ratio varies with the gate of the first device.
  • the curve of the source voltage change and the curve of the second current ratio changing with the gate-source voltage of the second device; among them, the curve 1 is the curve of the first current ratio changing with the gate-source voltage of the first device, and the curve 2the second The current ratio varies with the gate-source voltage of the second device.
  • the present invention provides a method for evaluating the hot carrier effect of a device, as shown in FIG. 1, which specifically includes the following steps:
  • Step S10 Obtain the ratio of the substrate current to the drain current of the first device under different gate-source voltages, and record it as the first current ratio.
  • Step S20 Obtain the ratio of the substrate current to the drain current of the second device under different gate-source voltages, and record it as the second current ratio, where the second device has undergone process parameter adjustment or device parameter adjustment compared to the first device Adjustment.
  • Step S30 Judging the influence of the process parameter adjustment or the device parameter adjustment on the hot carrier effect of the device based on the second current ratio and the first current ratio.
  • step S10 in an optional embodiment, the following steps are specifically included:
  • Step S101 Obtain the substrate current Isub1 of the first device under different gate-source voltages Vgs1;
  • Step S102 Obtain the drain current Ids1 of the first device under different gate-source voltages Vgs1;
  • Step S103 Divide the substrate current Isub1 and the drain current Ids1 of the first device under each gate-source voltage Vgs1 to obtain the first current ratio Isub1/Ids1.
  • the source-drain voltage Vds1 between the source and the drain of the first device is set to VCC, In addition, the source and the substrate of the first device are both grounded, and the source-drain voltage Vds1 of the first device is not higher than 3V.
  • the gate-source voltage Vgs1 between the gate and the source of the first device is between 0V and VCC.
  • the gate-source voltage Vgs1 of the first device gradually increases from 0V until it reaches the same level as the first device.
  • the source and drain voltages Vds1 are equal, and the step size of the gate-source voltage Vgs1 gradually increases is 0.01V ⁇ 0.1V.
  • the step size of the gate-source voltage Vgs1 gradually increases may be 0.01V, 0.05 V or 0.1V; in this embodiment, the step length of the increase of the gate-source voltage Vgs1 can be 0.05V.
  • the substrate current Isub1 and the drain current Ids1 under each gate-source voltage Vgs1 are collected.
  • step S20 in an optional embodiment, the following steps are specifically included:
  • Step S201 Obtain the substrate current Isub2 of the second device under different gate-source voltages Vgs2.
  • Step S202 Obtain the drain current Ids2 of the second device under different gate-source voltages Vgs2.
  • Step S203 Divide the substrate current Isub2 and the drain current Ids2 of the second device under each gate-source voltage Vgs2 to obtain a second current ratio Isub2/Ids2.
  • the second device is adjusted in process parameters or device parameters relative to the first device.
  • the source-drain voltage Vds2 between the source and drain of the second device is set to VCC, and the second device
  • the source and the substrate of the device are both grounded, and the source-drain voltage Vds2 of the second device is not higher than 3V.
  • the gate-source voltage Vgs2 between the gate and the source of the second device is between 0V and VCC.
  • the gate-source voltage Vgs2 of the second device gradually increases from 0V until it is equal to the source-drain voltage Vds2 of the second device, and the step size of the gate-source voltage Vgs2 gradually increases is 0.01V ⁇ 0.1V.
  • the step length of the stepwise increase of the gate-source voltage Vgs2 may be 0.01V, 0.05V or 0.1V.
  • the value range of the gate-source voltage Vgs2 of the second device is the same as the value range of the gate-source voltage Vgs1 of the first device.
  • the gate-source voltage Vgs1 of the device gradually increases in the same step size.
  • step S30 it specifically includes the following steps:
  • Step S301 Obtain a curve of the first current ratio Isub1/Ids1 varying with the gate-source voltage Vgs1 of the first device.
  • Step S302 Obtain a curve of the second current ratio Isub2/Ids2 varying with the gate-source voltage Vgs2 of the second device.
  • Step S303 Judging the effect of process parameter adjustment or device parameter adjustment on the device hot carrier effect based on the curve of the first current ratio Isub1/Ids1 varying with the gate-source voltage Vgs1 and the curve of the second current ratio Isub2/Ids2 varying with the gate-source voltage Vgs2 Impact.
  • the first current ratio Isub1/Ids1 varies with the gate-source voltage Vgs1 of the first device 1
  • the curve 2 of the second current ratio Isub2/Ids2 varying with the gate-source voltage Vgs2 of the second device is shown in FIG. 2.
  • the first current ratio Isub1/Ids1 and the second current ratio Isub2/Ids2 are both indicated by the current ratio Isub/Ids in FIG. 2, the gate-source voltage Vgs1 of the first device and the gate-source voltage Vgs2 of the second device All are indicated by the gate-source voltage Vgs.
  • step S30 is: under the same gate-source voltage Vgs, if the second current ratio Isub2/Ids2 is higher than the first current ratio Isub1/Ids1, then the process parameters of the second device relative to the first device are determined Adjustment or device parameter adjustment makes the device hot carrier effect enhanced; if the second current ratio Isub2/Ids2 is lower than the first current ratio Isub1/Ids1, then the process parameters of the second device relative to the first device are determined Adjustment or device parameter adjustment makes the device hot carrier effect weakened.
  • the process parameter has an effect on the hot carrier effect of the device. Therefore, it can be judged whether the hot carrier effect is getting better or worse after the process parameter changes are made. Therefore, it can quickly determine the direction of the hot carrier effect adjustment, so there is no need to obtain a device
  • the specific lifetime greatly shortens the evaluation time of the hot carrier effect and accelerates the research and development process.

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Abstract

一种评估器件热载流子效应的方法，包括：获取第一器件于不同栅源电压下的衬底电流与漏极电流之比，记为第一电流比；获取第二器件于不同栅源电压下的衬底电流与漏极电流之比，记为第二电流比，其中，第二器件相较于第一器件进行了工艺参数调整或器件参数调整；基于第二电流比与第一电流比判断工艺参数调整或器件参数调整对器件热载流子效应的影响。

Description

评估器件热载流子效应的方法
本申请要求于2020年3月13日提交的申请号为202010174560.4、名称为“评估器件热载流子效应的方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明涉及半导体领域，特别是涉及评估器件热载流子效应的方法。
背景技术
目前，对于超大规模集成电路制造产业，随着MOSFET装置尺寸的不断减小，现在已经缩小到亚微米和深亚微米，且向超深亚微米发展，现代半导体的制程越来越先进，沟道长度越来越短，结深越来越浅，氧化层越来越薄，尽管工作电压越来越低，但半导体集成电路的可靠性面临的挑战越来越大。可靠性对集成电路产品非常重要，尤其是产品研发过程中，能够快速评估产品的可靠性，对加速研发进程非常重要。故建立一套快速有效的评估机制非常重要。
现有技术中通常通过热载流子(HCI)效应来评估器件。然而，常规的热载流子效应的评估尽管采用了加速测试，但做完一个器件完整的热载流子效应评估仍然需要很长时间，整个评估周期较长，使得研发进程较为缓慢。
发明内容
本申请提供一种评估器件热载流子效应的方法，包括：
获取第一器件于不同栅源电压下的衬底电流与漏极电流之比，记为第一电流比；
获取第二器件于不同栅源电压下的衬底电流与漏极电流之比，记为第二电流比，其中，所述第二器件相较于第一器件进行了工艺参数调整或器件参数调整；
基于所述第二电流比与所述第一电流比判断所述工艺参数调整或所述器件参数调整对器件热载流子效应的影响。
本发明的一个或多个实施例的细节在下面的附图和描述中提出。本发明的其它特征、目的和优点将从说明书、附图以及权利要求书变得明显。
附图说明
为了更好地描述和说明本申请的实施例，可参考一幅或多幅附图，但用于描述附图的附加细节或示例不应当被认为是对本申请的发明创造、目前所描述的实施例或优选方式中任何一者的范围的限制。
图1为本发明提供的评估器件热载流子效应的方法流程图。
图2为本发明提供的评估器件热载流子效应的方法中以第一器件的漏极电压及第二器件的漏极电压均为2.6V为例，第一电流比随第一器件的栅源电压变化的曲线与第二电流比随第二器件的栅源电压变化的曲线的对比图；其中，曲线①为第一电流比随第一器件的栅源电压变化的曲线，曲线②第二电流比随第二器件的栅源电压变化的曲线。
具体实施方式
为了便于理解本发明，下面将参照相关附图对本发明进行更全面的描述。附图中给出了本发明的首选实施例。但是，本发明可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使对本 发明的公开内容更加透彻全面。
除非另有定义，本文所使用的所有的技术和科学术语与属于本发明的技术领域的技术人员通常理解的含义相同。本文中在本发明的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本发明。本文所使用的术语“及/或”包括一个或多个相关的所列项目的任意的和所有的组合。
本发明提供了一种评估器件热载流子效应的方法，如图1所示，具体的包括以下步骤：
步骤S10：获取第一器件于不同栅源电压下的衬底电流与漏极电流之比，记为第一电流比。
步骤S20：获取第二器件于不同栅源电压下的衬底电流与漏极电流之比，记为第二电流比，其中，第二器件相较于第一器件进行了工艺参数调整或器件参数调整。
步骤S30：基于第二电流比与第一电流比判断工艺参数调整或器件参数调整对器件热载流子效应的影响。
对于步骤S10，在一个可选的实施例中具体包括以下步骤：
步骤S101：获取第一器件于不同栅源电压Vgs1下的衬底电流Isub1；
步骤S102：获取第一器件于不同栅源电压Vgs1下的漏极电流Ids1；
步骤S103：将第一器件于各栅源电压Vgs1下的衬底电流Isub1及漏极电流Ids1相除，以得到第一电流比Isub1/Ids1。
具体的，在获取第一器件在不同栅源电压Vgs1下衬底电流Isub1与漏极电流Ids1之比的过程中，对于第一器件源极与漏极之间的源漏电压Vds1设为VCC，且第一器件的源极和衬底均接地，第一器件的源漏电压Vds1不高于3V。第一器件栅极与源极之间栅源电压Vgs1介于0V到VCC之间。在获取第一器件 在不同栅源电压Vgs1下衬底电流Isub1与漏极电流Ids1之比的过程中，第一器件的栅源电压Vgs1从0V开始逐步升高，直至升高到与第一器件的源漏电压Vds1相等，且栅源电压Vgs1逐步升高的步长为0.01V～0.1V，在其他可选的实施例中，栅源电压Vgs1逐步升高的步长可以为0.01V、0.05V或0.1V；在本实施例中，栅源电压Vgs1升高的步长可以为0.05V。在栅源电压Vgs1逐步升高的过程中，收集各栅源电压Vgs1下的衬底电流Isub1与漏极电流Ids1。
对于步骤S20，在一个可选的实施例中具体包括以下步骤：
步骤S201：获取第二器件于不同栅源电压Vgs2下的衬底电流Isub2。
步骤S202：获取第二器件于不同栅源电压Vgs2下的漏极电流Ids2。
步骤S203：将第二器件于各栅源电压Vgs2下的衬底电流Isub2及漏极电流Ids2相除，以得到第二电流比Isub2/Ids2。
具体的，第二器件相对于第一器件，在工艺参数或器件参数上有所调整。在获取第二器件在不同栅源电压Vgs2下的衬底电流Isub2与漏极电流Ids2之比的过程中，第二器件源极与漏极之间的源漏电压Vds2设置为VCC，且第二器件的源极及衬底均接地，第二器件的源漏电压Vds2不高于3V。第二器件栅极与源极之间的栅源电压Vgs2介于0V到VCC之间，在获取第二器件在不同栅源电压Vgs2下衬底电流Isub2与漏极电流Ids2之比的过程中，第二器件的栅源电压Vgs2从0V开始逐步升高，直至升高到与第二器件的源漏电压Vds2相等，且栅源电压Vgs2逐步升高的步长为0.01V～0.1V，在其他可选的实施例中，栅源电压Vgs2逐步升高的步长可以为0.01V、0.05V或0.1V。
需要说明的是，第二器件的栅源电压Vgs2的取值范围与第一器件的栅源电压Vgs1的取值范围相同，且第二器件的栅源电压Vgs2逐步升高的步长与第一器件的栅源电压Vgs1逐步升高的步长相同。
对于步骤S30，具体的包括以下步骤：
步骤S301：获取第一电流比Isub1/Ids1随第一器件的栅源电压Vgs1变化的曲线。
步骤S302：获取第二电流比Isub2/Ids2随第二器件的栅源电压Vgs2变化的曲线。
步骤S303：基于第一电流比Isub1/Ids1随栅源电压Vgs1变化的曲线及第二电流比Isub2/Ids2随栅源电压Vgs2变化的曲线判断工艺参数调整或器件参数调整对器件热载流子效应的影响。
具体的，以第一电流比Isub1/Ids1为y轴，以第一器件的栅源电压Vgs1为x轴，制作出第一电流比Isub1/Ids1随着第一器件的栅源电压Vgs1变化的曲线，继而在同一坐标系中，以第二电流比Isub2/Ids2为y轴，以第二器件的栅源电压Vgs2为x轴，制作出第二电流比Isub2/Ids2随着第二器件的栅源电压Vgs2变化的曲线。
更为具体的，以第一器件的漏极电压Vd1及第二器件的漏极电压Vd2均为2.6V为例，第一电流比Isub1/Ids1随第一器件的栅源电压Vgs1变化的曲线①与第二电流比Isub2/Ids2随第二器件的栅源电压Vgs2变化的曲线②如图2所示。需要说明的是，第一电流比Isub1/Ids1及第二电流比Isub2/Ids2在图2中均以电流比Isub/Ids示意，第一器件的栅源电压Vgs1及第二器件的栅源电压Vgs2均以栅源电压Vgs示意。
步骤S30的方法为：在相同栅源电压Vgs条件下，若第二电流比Isub2/Ids2高于第一电流比Isub1/Ids1，那么，则判定第二器件相对于第一器件做出的工艺参数调整或器件参数调整使得器件热载流子效应增强了；若第二电流比Isub2/Ids2低于第一电流比Isub1/Ids1，那么，则判定第二器件相对于第一器件 做出的工艺参数调整或器件参数调整使得器件热载流子效应减弱了。
以上实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
通过上述评估热载流子效应的方法，在进行器件热载流子效应评估时，通过测量不同工艺参数下器件的衬底电流和漏极电流，推断出该工艺参数对于器件热载流子效应的影响，从而判断出做出工艺参数改变后热载流子效应是呈变好的趋势还是呈变差的趋势，因此能够快速的决定热载流子效应调整的方向，因此并不需要获得器件具体的寿命，大大缩短了热载流子效应的评估时间，加速了研发过程。
以上实施例仅表达了本发明的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干变形和改进，这些都属于本发明的保护范围。因此，本发明专利的保护范围应以所附权利要求为准。

Claims (10)

  1. 一种评估器件热载流子效应的方法，包括：
    获取第一器件于不同栅源电压下的衬底电流与漏极电流之比，记为第一电流比；
    获取第二器件于不同栅源电压下的衬底电流与漏极电流之比，记为第二电流比，其中，所述第二器件相较于第一器件进行了工艺参数调整或器件参数调整；
    基于所述第二电流比与所述第一电流比判断所述工艺参数调整或所述器件参数调整对器件热载流子效应的影响。
  2. 根据权利要求1所述的评估器件热载流子效应的方法，其中，获取所述第一器件于不同栅源电压下的衬底电流与漏极电流之比包括如下步骤：
    获取所述第一器件于不同所述栅源电压下的所述衬底电流；
    获取所述第一器件于不同所述栅源电压下的所述漏极电流；
    将所述第一器件于各所述栅源电压下的所述衬底电流及所述漏极电流相除，以得到所述第一电流比。
  3. 根据权利要求1所述的评估器件热载流子效应的方法，其中，获取第二器件于不同栅源电压下的衬底电流与漏极电流之比包括如下步骤：
    获取所述第二器件于不同所述栅源电压下的所述衬底电流；
    获取所述第二器件于不同所述栅源电压下的所述漏极电流；
    将所述第二器件于各所述栅源电压下的所述衬底电流及所述漏极电流相除，以得到所述第二电流比。
  4. 根据权利要求1所述的评估器件热载流子效应的方法，其中，获取所述第 一器件于不同所述栅源电压下的所述衬底电流与所述漏极电流之比的过程中，所述第一器件的源漏电压设为VCC，所述第一器件的源极及衬底均接地，且所述第一器件的栅源电压介于0～VCC之间；获取所述第二器件于不同所述栅源电压下的所述衬底电流与所述漏极电流之比的过程中，所述第二器件的源漏电压设为VCC，所述第二器件的源极及衬底均接地，且所述第二器件的栅源电压介于0～VCC之间。
  5. 根据权利要求4所述的评估器件热载流子效应的方法，其中，获取所述第一器件于不同所述栅源电压下的所述衬底电流与所述漏极电流之比的过程中，所述第一器件的源漏电压设为VCC，所述第一器件的源极及衬底均接地，且所述第一器件的栅源电压介于0～VCC之间；获取所述第二器件于不同所述栅源电压下的所述衬底电流与所述漏极电流之比的过程中，所述第二器件的源漏电压设为VCC，所述第二器件的源极及衬底均接地，且所述第二器件的栅源电压介于0～VCC之间。
  6. 根据权利要求5所述的评估器件热载流子效应的方法，其中，所述第一器件的源漏电压不高于3V，所述第二器件的源漏电压不高于3V。
  7. 根据权利要求1所述的评估器件热载流子效应的方法，其中，获取所述第一器件于不同所述栅源电压下的所述衬底电流与所述漏极电流之比的过程中，所述栅源电压自0至VCC逐步升高，且所述栅源电压逐步升高的步长为0.01V～0.1V。
  8. 根据权利要求1所述的评估器件热载流子效应的方法，其中，获取所述第二器件于不同所述栅源电压下的所述衬底电流与所述漏极电流之比的过程中，所述栅源电压自0至VCC逐步升高，且所述栅源电压逐步升高的步长为0.01V～0.1V。
  9. 根据权利要求1所述的评估器件热载流子效应的方法，其中，基于所述第二电流比与所述第一电流比判断所述工艺参数调整或所述器件参数调整对器件热载流子效应的影响包括：
    获取所述第一电流比随所述第一器件的栅源电压变化的曲线；
    获取所述第二电流比随所述第二器件的栅源电压变化的曲线；
    基于所述第一电流比随所述栅源电压变化的曲线及所述第二电流比随所述栅源电压变化的曲线判断所述工艺参数调整或所述器件参数调整对器件热载流子效应的影响。
  10. 根据权利要求9所述的评估器件热载流子效应的方法，其中，基于所述第一电流比随所述栅源电压变化的曲线及所述第二电流比随所述栅源电压变化的曲线判断所述工艺参数调整或所述器件参数调整对器件热载流子效应的影响的方法为：于相同所述栅源电压条件下，若所述第二电流比高于所述第一电流比，则判定所述工艺参数调整或所述器件参数调整使得所述器件热载流子效应增强；若所述第二电流比低于所述第一电流比，则判定所述工艺参数调整或所述器件参数调整使得所述器件热载流子效应减弱。
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030195728A1 (en) * 2002-03-26 2003-10-16 Matsushita Electric Industrial Co., Ltd. Method of estimating a lifetime of hot carrier of MOS transistor, and simulation of hot carrier degradation
JP2005259777A (ja) * 2004-03-09 2005-09-22 Matsushita Electric Ind Co Ltd 半導体装置の信頼性シミュレーション方法
US7579859B2 (en) * 2007-06-14 2009-08-25 Taiwan Semiconductor Manufacturing Company, Ltd. Method for determining time dependent dielectric breakdown
CN102495345A (zh) * 2011-12-06 2012-06-13 上海集成电路研发中心有限公司 确定热载流子注入器件寿命的方法

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6825684B1 (en) * 2002-06-10 2004-11-30 Advanced Micro Devices, Inc. Hot carrier oxide qualification method
CN101089642B (zh) 2006-06-13 2012-08-22 中芯国际集成电路制造(上海)有限公司 一种加速热载流子注入测试的方法
CN101740389A (zh) * 2008-11-13 2010-06-16 中芯国际集成电路制造(上海)有限公司 Mos晶体管及其形成方法
CN102253324B (zh) * 2011-06-17 2016-01-27 上海集成电路研发中心有限公司 一种mos器件热载流子效应的测试结构及测试方法
JP2013251465A (ja) * 2012-06-01 2013-12-12 Fuji Electric Co Ltd 半導体装置
CN104977519B (zh) 2014-04-11 2017-11-24 中芯国际集成电路制造(上海)有限公司 一种测试器件热载流子注入效应的方法
CN103955579B (zh) * 2014-04-28 2017-06-23 天津大学仁爱学院 基于spice软件的模拟/射频集成电路设计方法
CN104237764B (zh) 2014-09-15 2017-01-25 工业和信息化部电子第五研究所 Mos器件热载流子注入寿命退化的测试方法和装置
CN105576026B (zh) * 2014-10-16 2018-11-16 中芯国际集成电路制造(上海)有限公司 半导体器件及其制备方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030195728A1 (en) * 2002-03-26 2003-10-16 Matsushita Electric Industrial Co., Ltd. Method of estimating a lifetime of hot carrier of MOS transistor, and simulation of hot carrier degradation
JP2005259777A (ja) * 2004-03-09 2005-09-22 Matsushita Electric Ind Co Ltd 半導体装置の信頼性シミュレーション方法
US7579859B2 (en) * 2007-06-14 2009-08-25 Taiwan Semiconductor Manufacturing Company, Ltd. Method for determining time dependent dielectric breakdown
CN102495345A (zh) * 2011-12-06 2012-06-13 上海集成电路研发中心有限公司 确定热载流子注入器件寿命的方法

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