WO2021179247A1 - 像素电路及其驱动方法和显示装置 - Google Patents

像素电路及其驱动方法和显示装置 Download PDF

Info

Publication number
WO2021179247A1
WO2021179247A1 PCT/CN2020/078982 CN2020078982W WO2021179247A1 WO 2021179247 A1 WO2021179247 A1 WO 2021179247A1 CN 2020078982 W CN2020078982 W CN 2020078982W WO 2021179247 A1 WO2021179247 A1 WO 2021179247A1
Authority
WO
WIPO (PCT)
Prior art keywords
circuit
transistor
node
sub
control
Prior art date
Application number
PCT/CN2020/078982
Other languages
English (en)
French (fr)
Inventor
玄明花
齐琪
刘静
Original Assignee
京东方科技集团股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to CN202080000258.5A priority Critical patent/CN113966528B/zh
Priority to PCT/CN2020/078982 priority patent/WO2021179247A1/zh
Priority to US17/265,246 priority patent/US11455947B2/en
Publication of WO2021179247A1 publication Critical patent/WO2021179247A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2007—Display of intermediate tones
    • G09G3/2011—Display of intermediate tones by amplitude modulation
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2007—Display of intermediate tones
    • G09G3/2014—Display of intermediate tones by modulation of the duration of a single pulse during which the logic level remains constant
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/061—Details of flat display driving waveforms for resetting or blanking
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/06—Adjustment of display parameters
    • G09G2320/066—Adjustment of display parameters for control of contrast

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a pixel circuit, a driving method thereof, and a display device.
  • Micro Light Emitting Diode (Micro-LED) technology is to integrate small-sized LED arrays on a chip with high density to realize the thinning, miniaturization and matrixing of LEDs.
  • the distance between the pixels can reach Micron level, and each pixel can be addressed and emit light individually.
  • Micro-LED display panels have gradually developed into display panels used in consumer terminals due to their low driving voltage, long life, and wide temperature resistance.
  • the embodiments of the present disclosure provide a pixel circuit, a driving method thereof, and a display device, which can prompt the display effect of the display device.
  • embodiments of the present disclosure provide a pixel circuit, which includes: a first reset sub-circuit, a first data writing sub-circuit, a charging and discharging electronic circuit, a first output control sub-circuit, and a switch sub-circuit,
  • the first reset sub-circuit, the charging and discharging electronic circuit, and the first output control sub-circuit are connected to a first node, the first reset sub-circuit, the first data writing sub-circuit, and the first node
  • the charging and discharging electronic circuit is connected to the second node;
  • the first reset sub-circuit is configured to write a reference voltage and an initialization voltage to the first node and the second node in response to the control of the signal of the reset signal line;
  • the first data writing sub-circuit is configured to write the first data voltage to the second node in response to the control of the signal of the gate line;
  • the first output control sub-circuit is configured to respond to the control of the signal of the control signal line, so that a path is formed between the charging and discharging electronic circuit and the charging and discharging terminal, and the voltage at the first node is provided to the Switch sub-circuit;
  • the charging and discharging electronic circuit is configured to perform charging processing or discharging processing on the first node in response to the control of the first data voltage;
  • the switch sub-circuit is connected to the signal supply terminal and the component to be driven, and is configured to control the signal supply terminal and the voltage at the first node in response to the control of the voltage at the first node provided by the first output control sub-circuit. The on-off between the components to be driven.
  • the first reset sub-circuit includes: a first transistor and a second transistor;
  • the control electrode of the first transistor is connected to the reset signal line, the first electrode of the first transistor is connected to a reference voltage terminal, and the second electrode of the first transistor is connected to the first node;
  • the control electrode of the second transistor is connected to the reset signal line, the first electrode of the second transistor is connected to the initialization voltage terminal, and the second electrode of the second transistor is connected to the second node.
  • the first data writing sub-circuit includes: a third transistor
  • the control electrode of the third transistor is connected to the gate line, the first electrode of the third transistor is connected to the first data line, and the second electrode of the third transistor is connected to the second node.
  • the first output control sub-circuit includes: a fourth transistor and a fifth transistor;
  • the control electrode of the fourth transistor is connected to the control signal line, the first electrode of the fourth transistor is connected to the charging and discharging electronic circuit, and the second electrode of the fourth transistor is connected to the charging and discharging end ;
  • the control electrode of the fifth transistor is connected to the control signal line, the first electrode of the fifth transistor is connected to the first node, and the second electrode of the fifth transistor is connected to the switch sub-circuit.
  • the charging and discharging electronic circuit includes: a sixth transistor and a first capacitor;
  • the control electrode of the sixth transistor is connected to the second node, the first electrode of the sixth transistor is connected to the first node, and the second electrode of the sixth transistor is connected to the first output controller. Circuit connection
  • the first terminal of the first capacitor is connected to the first node, and the second terminal of the first capacitor is connected to the first constant voltage terminal.
  • the switch sub-circuit includes: a seventh transistor
  • the control electrode of the seventh transistor is connected to the first output control sub-circuit, the first electrode of the seventh transistor is connected to the signal supply end, and the second electrode of the seventh transistor is connected to the to-be-driven Component connection.
  • the first terminal of the second capacitor is connected to the second node, and the second terminal of the second capacitor is connected to the second constant voltage terminal.
  • the signal supply terminal is connected to a first working voltage terminal, and the first working voltage terminal provides a first working voltage to the switch sub-circuit through the signal supply terminal.
  • the pixel circuit further includes: a driving current supply circuit
  • the driving current supply circuit is connected to the signal supply terminal, and the driving current supply circuit is configured to provide a driving current to the switch sub-circuit through the signal supply terminal.
  • the driving current supply circuit includes: a second reset sub-circuit, a second data writing sub-circuit, a threshold compensation sub-circuit, a second output control sub-circuit, and a driving transistor.
  • the two poles, the threshold compensation sub-circuit and the second output control sub-circuit are connected to a fourth node, and the control pole of the driving transistor, the threshold compensation sub-circuit and the second reset sub-circuit are connected to the first Five nodes, the first pole of the driving transistor, the second data writing sub-circuit and the second output control sub-circuit are connected to the sixth node;
  • the second reset sub-circuit is configured to write a reference voltage to the fifth node in response to the control of the signal of the reset signal line;
  • the second data writing sub-circuit is configured to write a second data voltage to the sixth node in response to the control of the signal of the gate line;
  • the threshold compensation sub-circuit is configured to compensate the threshold voltage of the driving transistor in response to the control of the signal of the gate line;
  • the second output control sub-circuit is configured to write the first operating voltage to the sixth node in response to the control of the signal of the control signal line, and provide the driving current output by the driving transistor to The signal supply terminal;
  • the driving transistor is configured to output a corresponding driving current under the control of the voltage at the fifth node and the voltage at the sixth node.
  • the second reset sub-circuit includes: an eighth transistor;
  • the control electrode of the eighth transistor is connected to the reset signal line, the first electrode of the eighth transistor is connected to the reference voltage terminal, and the second electrode of the eighth transistor is connected to the fifth node .
  • the second data writing sub-circuit includes: a ninth transistor
  • the control electrode of the ninth transistor is connected to the gate line, the first electrode of the ninth transistor is connected to the second data line, and the second electrode of the ninth transistor is connected to the sixth node.
  • the control electrode of the tenth transistor is connected to the gate line, the first electrode of the tenth transistor is connected to the fourth node, and the second electrode of the tenth transistor is connected to the fifth node.
  • the second output control sub-circuit includes: an eleventh transistor and a twelfth transistor;
  • the control electrode of the eleventh transistor is connected to the control signal line, the first electrode of the eleventh transistor is connected to the first operating voltage terminal, and the second electrode of the eleventh transistor is connected to the sixth node connect;
  • the control electrode of the twelfth transistor is connected to the control signal line, the first electrode of the twelfth transistor is connected to the fourth node, and the second electrode of the twelfth transistor is connected to the signal supply end connect.
  • the pixel circuit further includes: a third capacitor
  • the first terminal of the third capacitor is connected to the fifth node, and the second terminal of the third capacitor is connected to the third constant voltage terminal.
  • all transistors in the pixel circuit are N-type transistors
  • all the transistors in the pixel circuit are P-type transistors.
  • an embodiment of the present disclosure further provides a display device, which includes: a display substrate, the display substrate includes a plurality of sub-pixels, at least one of the sub-pixels is provided with the pixel circuit provided in the first aspect And the element to be driven, the pixel circuit is configured to provide a driving signal to the element to be driven.
  • the component to be driven includes: LED or Micro-LED.
  • embodiments of the present disclosure also provide a driving method of a pixel circuit, wherein, for driving the pixel circuit provided in the first aspect, the driving method includes:
  • a reset signal is applied to the reset signal line, a reference voltage is applied to the reference voltage terminal, and an initialization voltage is applied to the initialization voltage terminal, so that the first reset sub-circuit controls the reset signal in response to the reset signal.
  • the reference voltage and the initialization voltage are written to the first node and the second node, respectively;
  • a gate scan signal is applied to the gate line, and a first data voltage is applied to the first data line, so that the first data writing sub-circuit controls the first data in response to the gate scan signal. Voltage is written to the second node;
  • the first output control sub-circuit forms a path between the charging and discharging electronic circuit and the charging and discharging terminal in response to the control of the control signal, and connects the first node
  • the voltage is provided to the switch sub-circuit, the charging and discharging electronic circuit performs charging or discharging processing on the first node in response to the control of the first data voltage, and the switch sub-circuit responds to the first The voltage at the node is controlled to control the on-off between the signal supply terminal and the component to be driven.
  • the pixel circuit includes a driving current supply circuit
  • the driving current supply circuit includes: a second reset sub-circuit, a second data writing sub-circuit, a threshold compensation sub-circuit, and a second output control sub-circuit And drive transistor;
  • the second reset sub-circuit controls the writing of the reference voltage to the reference voltage in response to the reset signal.
  • the method further includes: applying a second data voltage to the second data line, so that the second data writing sub-circuit writes the second data voltage Entering the sixth node, the threshold compensation sub-circuit compensates the threshold voltage of the driving transistor in response to the control of the gate line;
  • While loading the control signal to the control signal line it also includes: loading a first operating voltage to the first operating voltage terminal, so that the second output control sub-circuit responds to the control of the control signal
  • the first operating voltage is written to the sixth node, and the driving current output by the driving transistor is provided to the signal supply terminal.
  • FIG. 1 is a schematic diagram of a circuit structure of a pixel circuit provided by an embodiment of the disclosure
  • FIG. 2 is a schematic diagram of device characteristics of a component to be driven in an embodiment of the disclosure
  • FIG. 3 is a schematic diagram of the circuit structure of another pixel circuit provided by an embodiment of the disclosure.
  • FIG. 5 is a schematic diagram of a circuit structure of another pixel circuit provided by an embodiment of the disclosure.
  • FIG. 6 is a working timing diagram of the pixel circuit shown in FIG. 5;
  • FIG. 7 is a flowchart of a driving method of a pixel circuit according to an embodiment of the disclosure.
  • FIG. 8 is a flowchart of another method for driving a pixel circuit according to an embodiment of the disclosure.
  • FIG. 9 is a schematic diagram of a circuit structure of a display device provided by an embodiment of the disclosure.
  • the element to be driven may be a light-emitting element, and the light-emitting element may be a current/voltage-driven light-emitting device including a light-emitting diode (Light Emitting Diode, LED for short) or a Micro-LED.
  • the component to be driven is a Micro-LED, and the size level of the Micro-LED is a micrometer ( ⁇ m) level.
  • each transistor involved in the embodiments of the present disclosure may be independently selected from one of polysilicon thin film transistors, amorphous silicon thin film transistors, oxide thin film transistors, and organic thin film transistors.
  • the “control electrode” referred to in this disclosure specifically refers to the gate of the transistor, the “first pole” specifically refers to the source of the transistor, and the corresponding “second pole” specifically refers to the drain of the transistor.
  • first pole specifically refers to the source of the transistor
  • second pole specifically refers to the drain of the transistor.
  • transistors can be divided into N-type transistors and P-type transistors. Each transistor in the present disclosure can be independently selected from N-type transistors or P-type transistors. In the following embodiments, all transistors in the pixel unit are N-type transistors. Transistors are taken as an example and described as an example. At this time, the transistors in the pixel circuit can be manufactured at the same time by using the same manufacturing process.
  • the first working voltage is a high-level working voltage Vdd
  • the second working voltage is a low-level working voltage Vss
  • the first constant voltage terminal is grounded to GND
  • the second constant voltage terminal provides a low-level working voltage Vss
  • the third constant voltage terminal provides a high-level working voltage Vdd.
  • FIG. 1 is a schematic diagram of a circuit structure of a pixel circuit provided by an embodiment of the disclosure. As shown in FIG. 1, the pixel circuit includes: a first reset sub-circuit 1, a first data writing sub-circuit 2, a charging and discharging electronic circuit 3.
  • the first output control sub-circuit 4 and the switch sub-circuit 5, the first reset sub-circuit 1, the charging and discharging electronic circuit 3 and the first output control sub-circuit 4 are connected to the first node N1, and the first reset sub-circuit 1 ,
  • the first data writing sub-circuit 2 and the charging and discharging electronic circuit 3 are connected to the second node N2, the anode of the Micro-LED to be driven and the switch sub-circuit 5 are connected to the third node N3, and the cathode of the Micro-LED is connected to the second node N3.
  • the working voltage terminal is connected.
  • the first reset sub-circuit 1 is configured to write the reference voltage and the initialization voltage to the first node N1 and the second node N2 in response to the control of the signal of the reset signal line Reset.
  • the first data writing sub-circuit 2 is configured to write the first data voltage to the second node N2 in response to the control of the signal of the gate line Gate.
  • the first output control sub-circuit 4 is configured to respond to the control of the signal of the control signal line SW, so that a path is formed between the charging and discharging electronic circuit 3 and the charging and discharging terminal Dc, and the voltage at the first node N1 is provided to the switching sub-circuit 5 .
  • the charging and discharging electronic circuit 3 is configured to perform charging processing or discharging processing on the first node N1 in response to the control of the first data voltage.
  • the switch sub-circuit 5 is connected to the signal supply terminal Input and the component to be driven Micro-LED, and is configured to respond to the control of the voltage at the first node N1 provided by the first output control sub-circuit 4 to control the signal supply terminal Input and the to-be-driven component The on-off between the component Micro-LED.
  • the signal supply terminal Input and the Micro-LED of the component to be driven are connected, the signal supplied by the signal supply terminal Input can be written to the Micro-LED of the component to be driven, and the Micro-LED of the component to be driven can be driven thereby Work; when the signal supply terminal Input and the Micro-LED component to be driven are disconnected, the signal supplied by the signal supply terminal Input cannot be written to the Micro-LED component to be driven, and the Micro-LED component to be driven cannot work.
  • the charging/discharging processing speed of the first node N1 of the charging and discharging electronic circuit 3 can be controlled by the first data voltage, that is, the charging/discharging speed of the first node N1 is controlled (the voltage change of the first node N1 Rate), the switch sub-circuit 5 controls the on/off between the signal supply terminal Input and the Micro-LED to be driven based on the magnitude of the voltage at the first node N1.
  • the voltage provided by the charging and discharging terminal Dc (for example, the charging and discharging terminal Dc provides a ground voltage) should be designed to be less than the reference voltage, and the reference voltage is sufficient to make the switch sub-circuit The transistor in 5 is in the conducting state.
  • the charging and discharging electronic circuit 3 will discharge the first node N1, so that the voltage at the first node N1 will drop, and the N-type transistor in the switch sub-circuit 5 will experience Switch from on state to off state.
  • the transistor in the switch sub-circuit 5 is a P-type transistor
  • the voltage provided by the charge and discharge terminal Dc (for example, the charge and discharge terminal Dc provides a high-level operating voltage Vdd) is greater than the reference voltage, and the reference voltage is sufficient to make the switch
  • the transistor in the circuit 5 is in the conducting state.
  • the charging and discharging electronic circuit 3 will charge the voltage at the first node N1, so that the voltage at the first node N1 rises, and the P-type switch in the sub-circuit 5 The transistor undergoes a switch from an on state to an off state.
  • the transistor in the switch sub-circuit 5 is an N-type transistor
  • the switch sub-circuit 5 if the voltage provided by the first output control sub-circuit 4 to the switch sub-circuit 5 is greater than the preset threshold, the switch sub-circuit 5 is in the "closed” state , The signal supply terminal Input and the component to be driven Micro-LED are turned on; if the voltage provided by the first output control sub-circuit 4 to the switch sub-circuit 5 is less than or equal to the preset threshold, the switch sub-circuit 5 is in "off” "In the state, the signal supply terminal Input and the Micro-LED of the component to be driven are disconnected.
  • the transistor in the switch sub-circuit 5 is a P-type transistor
  • the switch sub-circuit 5 if the voltage provided by the first output control sub-circuit 4 to the switch sub-circuit 5 is less than the preset threshold, the switch sub-circuit 5 is "closed” State, the signal supply terminal Input and the component to be driven Micro-LED are conducting; if the voltage provided by the first output control sub-circuit 4 to the switch sub-circuit 5 is greater than or equal to the preset threshold, the switch sub-circuit 5 is in “off” In the "ON” state, the signal supply terminal Input and the Micro-LED of the component to be driven are disconnected.
  • the charging/discharging speed at the first node N1 is controlled by controlling the first data voltage, so as to control the length of time that the voltage at the first node N1 is charged/discharged from the reference voltage to the above-mentioned preset threshold, thereby realizing the switching sub-circuit 5 Control the duration of the "closed" state, that is, control the working duration of the Micro-LED to be driven.
  • the signal supply terminal Input can be used to provide a constant voltage signal or a constant current signal within one frame.
  • the signal supply terminal Input provides a constant voltage signal, taking the constant voltage as the first working voltage Vdd as an example, when the voltage Vdd and the voltage Vss are applied to the two ends of the LED, the current flowing through the current of the Micro-LED to be driven The density is fixed (that is, the current flowing through the Micro-LED of the component to be driven is fixed); when the signal supply terminal Input provides a constant current signal, the current flowing through the Micro-LED of the component to be driven is fixed.
  • the effective light-emitting brightness of the Micro-LED to be driven during the period can be controlled to achieve the purpose of adjusting the display gray scale.
  • FIG. 2 is a schematic diagram of the device characteristics of the device to be driven in the embodiment of the disclosure.
  • the luminous efficiency of the device to be driven Micro-LED will gradually increase with the increase of the current density, and will increase when the current density is between It stabilizes at the maximum value between J1 and J2. Therefore, in consideration of saving display power consumption, it is generally required that the Micro-LED, which is to be driven, work in a state where the current density is between J1 and J2.
  • the range of current density between J1 and J2 is extremely limited for many types of Micro-LEDs to be driven. If only adjusting the current to obtain different gray levels, the resulting display contrast may be very limited. Low.
  • the current density of the Micro-LED to be driven can be set in a stable range (between J1 and J2), and the first data voltage can be used to adjust the current density in each cycle.
  • the length of time that the switch sub-circuit 5 is in the "closed” state is used to control the display gray scale, which can realize the high contrast of the display device.
  • the technical solution of the present disclosure achieves high contrast under the premise that the current density of the element to be driven is in a stable range, which can avoid problems such as color shift and efficiency drop caused by the current density of the element to be driven outside the stable range, and can also help realize display products
  • the required high contrast ratio therefore, the embodiments of the present disclosure can alleviate the display defects caused by the electrical characteristics of the components to be driven easily drifting with the current density, and improve the display performance of related display products.
  • FIG. 3 is a schematic diagram of the circuit structure of another pixel circuit provided by an embodiment of the disclosure.
  • the pixel circuit is a specific implementation based on the pixel circuit shown in FIG.
  • the terminal Input is connected to the first working voltage terminal, and the first working voltage terminal provides the first working voltage Vdd to the switch sub-circuit 5 through the signal supply terminal Input.
  • the first data writing sub-circuit 2 includes: a third transistor M3; the control electrode of the third transistor M3 is connected to the gate line Gate, and the first electrode of the third transistor M3 is connected to the first data line Data_T, The second electrode of the third transistor M3 is connected to the second node N2.
  • the first output control sub-circuit 4 includes: a fourth transistor M4 and a fifth transistor M5; the control electrode of the fourth transistor M4 is connected to the control signal line SW, and the first electrode of the fourth transistor M4 is connected to the charging and discharging The electronic circuit 3 is connected, the second electrode of the fourth transistor M4 is connected to the charge and discharge terminal Dc; the control electrode of the fifth transistor M5 is connected to the control signal line SW, the first electrode of the fifth transistor M5 is connected to the first node N1, and the first electrode of the fifth transistor M5 is connected to the first node N1.
  • the second pole of the five transistor M5 is connected to the switch sub-circuit 5.
  • the charging and discharging electronic circuit 3 includes: a sixth transistor M6 and a first capacitor C1; the control electrode of the sixth transistor M6 is connected to the second node N2, and the first electrode of the sixth transistor M6 is connected to the first node N1. Connected, the second pole of the sixth transistor M6 is connected to the first output control sub-circuit 4; the first terminal of the first capacitor C1 is connected to the first node N1, and the second terminal of the first capacitor C1 is connected to the first constant voltage terminal .
  • the first transistor M1 to the seventh transistor M7 are all N-type transistors.
  • the charging and discharging electronic circuit 3 is used for discharging the first node N1, and the ground voltage V GND provided by the charging and discharging terminal Dc.
  • FIG. 4 is a working timing diagram of the pixel circuit shown in FIG. 3. As shown in FIG. 4, the working process of the pixel circuit can be divided into three stages.
  • the reset signal provided by the reset signal line Reset is in a high-level state
  • the gate scan signal provided by the gate line Gate is in a low-level state
  • the control signal provided by the control signal line SW is in a low-level state.
  • the first transistor M1 and the second transistor M2 are in an on state
  • the third transistor M3 to the seventh transistor M7 are in an off state.
  • the reference voltage Vref provided by the reference voltage terminal is written to the first node N1 through the first transistor M1
  • the initialization voltage Vinit provided by the initialization voltage terminal is written to the second node N2 through the second transistor M2. Since the seventh transistor M7 is in an off state, there is a disconnection between the first operating voltage terminal and the third node N3.
  • the reset signal provided by the reset signal line Reset is in a low level state
  • the gate scan signal provided by the gate line Gate is in a high level state
  • the control signal provided by the control signal line SW is in a low level state.
  • the third transistor M3 is in the on state
  • the first transistor M1, the second transistor M2, and the fourth transistor M4 to the seventh transistor M7 are in the off state.
  • the first data voltage provided by the first data line Data_T is written to the second node N2 through the third transistor M3. Since the seventh transistor M7 is in an off state, there is a disconnection between the first operating voltage terminal and the third node N3.
  • I_ M6 K_ M6 *(Vgs_ M6 -Vth_ M6 ) 2
  • I_ M6 of the sixth transistor M6 output current at saturation
  • Vgs_ M6 gate-source voltage of the sixth transistor M6 is the threshold voltage of the sixth transistor M6
  • Vdata_ T is the first data voltage
  • V GND a ground voltage (approximately 0V)
  • K_ M6 is a constant and is determined by the electrical characteristics of the sixth transistor M6.
  • Vref is a reference voltage; in certain circumstances Vref, K_ M6, V GND and Vth_ M6, R_ equivalent resistance of the sixth transistor M6 M6 is determined by the size of only the first data voltage Vdata_ T.
  • the reference voltage Vref becomes the reference ground voltage V GND process
  • the total discharge duration t R_ M6 ⁇ C1 ', where C1' represents the magnitude of the capacitance of the first capacitor C1.
  • the size of the discharge time also reflects the average discharge speed of the first node N1, where the shorter the discharge time, the faster the average discharge speed.
  • a length t equivalent resistance R_ sixth transistor M6 M6 determines the size of the total discharge, and because the equivalent resistance of the sixth transistor M6 M6 R_ size only by the first data voltage determined Vdata_ T, the first data voltage Vdata_ T determines the total duration of the discharge and an average discharge velocity.
  • the seventh transistor M7 is always in the ON state, the voltage of the third node N3 is at the high level voltage; wherein, V_ led to be in operation when the drive element voltage difference between the anode and the cathode, Vth_ M7 is the threshold voltage of the seventh transistor M7.
  • V_ led to be in operation when the drive element voltage difference between the anode and the cathode Vth_ M7 is the threshold voltage of the seventh transistor M7.
  • the seventh transistor M7 is switched from ON state to the OFF state (at this time is a preset threshold value Vss + V_ led + Vth_ M7) .
  • the seventh transistor M7 is always in an off state, the voltage at the third node N3 to low level voltage.
  • the voltage at the first node N1 is discharged by Vref to Vss + V_ led + long Vth_ M7 experienced t_ EM with negative correlation average discharge velocity; i.e. average discharge faster, at the first node N1 by the voltage Vref discharged to Vss + V_ led + long Vth_ M7 experienced shorter t_ EM. Therefore, by adjusting the first data voltage Vdata_ T, may be a voltage at the first node N1 is discharged by the length Vref to Vss + V_ led + Vth_ M7 experienced t_ EM adjusted.
  • the length of time that the seventh transistor M7 is in the on state can be adjusted by adjusting the magnitude of the first data voltage, so that the display gray scale can be adjusted.
  • the charging and discharging electronic circuit 3 is used for charging the first node N1, and the high-level operating voltage provided by the charging and discharging terminal Dc In this case, the corresponding drawings are not given.
  • the working process in which all the transistors in the pixel circuit are P-type transistors is the same as the working process in which all the transistors are N-type transistors, and will not be repeated here.
  • FIG. 5 is a schematic diagram of the circuit structure of another pixel circuit provided by an embodiment of the disclosure.
  • the pixel circuit shown in FIG. 5 The current supply circuit 10, wherein the driving current supply circuit 10 is connected to the signal supply terminal Input, and the driving current supply circuit 10 is configured to provide a driving current to the switch sub-circuit 5 through the signal supply terminal Input.
  • the driving current supply circuit 10 can provide the signal supply terminal Input with driving currents of different magnitudes in different periods (for example, one frame). At this time, the display comparison can be obtained. Effective promotion.
  • the driving current supply circuit 10 includes: a second reset sub-circuit 6, a second data writing sub-circuit 7, a threshold compensation sub-circuit 8, a second output control sub-circuit 9 and a driving transistor DTFT.
  • the second pole of the DTFT, the threshold compensation sub-circuit 8 and the second output control sub-circuit 9 are connected to the fourth node N4, and the control pole of the driving transistor DTFT, the threshold compensation sub-circuit 8 and the second reset sub-circuit 6 are connected to the fifth node.
  • the node N5, the first pole of the driving transistor DTFT, the second data writing sub-circuit 7 and the second output control sub-circuit 9 are connected to the sixth node N6.
  • the second reset sub-circuit 6 is configured to write the reference voltage to the fifth node N5 in response to the control of the signal of the reset signal line Reset.
  • the second data writing sub-circuit 7 is configured to write the second data voltage to the sixth node N6 in response to the control of the signal of the gate line Gate.
  • the second output control sub-circuit 9 is configured to write the first operating voltage to the sixth node N6 in response to the control of the signal of the control signal line SW, and provide the driving current output by the driving transistor DTFT to the signal supply terminal Input.
  • the driving transistor DTFT is configured to output a corresponding driving current under the control of the voltage at the fifth node N5 and the voltage at the sixth node N6.
  • the second reset sub-circuit 6 includes: an eighth transistor M8; the control electrode of the eighth transistor M8 is connected to the reset signal line Reset, the first electrode of the eighth transistor M8 is connected to the reference voltage terminal, and the first electrode of the eighth transistor M8 is connected to the reference voltage terminal.
  • the second pole of the eight transistor M8 is connected to the fifth node N5.
  • the second data writing sub-circuit 7 includes: a ninth transistor M9; the control electrode of the ninth transistor M9 is connected to the gate line Gate, and the first electrode of the ninth transistor M9 is connected to the second data line Data_I, The second electrode of the ninth transistor M9 is connected to the sixth node N6.
  • the threshold compensation sub-circuit 8 includes: a tenth transistor M10; the control electrode of the tenth transistor M10 is connected to the gate line Gate, the first electrode of the tenth transistor M10 is connected to the fourth node N4, and the tenth transistor M10 The second pole of is connected to the fifth node N5.
  • the pixel circuit further includes: a third capacitor C3; the first terminal of the third capacitor C3 is connected to the fifth node N5, and the second terminal of the third capacitor C3 is connected to the third constant voltage terminal.
  • the third capacitor C3 is used to maintain the stability of the voltage of the fifth node N5, which is not a necessary result in the pixel circuit.
  • the reset signal provided by the reset signal line Reset is in a high-level state
  • the gate scan signal provided by the gate line Gate is in a low-level state
  • the control signal provided by the control signal line SW is in a low-level state.
  • the first transistor M1, the second transistor M2, and the eighth transistor M8 are in an on state
  • the third transistor M3 to the seventh transistor M7, and the ninth transistor M9 to the twelfth transistor M12 are in an off state.
  • the reference voltage Vref provided by the reference voltage terminal is written to the first node N1 through the first transistor M1, is written to the fifth node N5 through the eighth transistor M8, and the initialization voltage Vinit provided by the initialization voltage terminal is written to the first node N5 through the second transistor M2.
  • the reset signal provided by the reset signal line Reset is in a low level state
  • the gate scan signal provided by the gate line Gate is in a high level state
  • the control signal provided by the control signal line SW is in a low level state.
  • the third transistor M3, the ninth transistor M9, and the tenth transistor M10 are in the on state
  • the first transistor M1, the second transistor M2, the fourth transistor M4 to the seventh transistor M7, the eighth transistor M8, and the eleventh transistor M10 are in a conducting state.
  • the transistor M11 and the twelfth transistor M12 are in an off state.
  • the first data voltage provided by the first data line Data_T is written to the second node N2 through the third transistor M3, and the second data voltage provided by the second data line Data_I is written to the sixth node N6 through the ninth transistor M9.
  • Vdata_ I wherein the second data voltage, Vth_ DTFT a threshold voltage of the driving transistor DTFT. Since the eleventh transistor M11 and the twelfth transistor M12 are in an off state, the drive current supply circuit 10 has no drive current output. At the same time, since the seventh transistor M7 is in the off state, the first operating voltage terminal is disconnected from the third node N3.
  • the reset signal provided by the reset signal line Reset is in a low level state
  • the gate scan signal provided by the gate line Gate is in a low level state
  • the control signal provided by the control signal line SW is in a high level state.
  • the fourth transistor M4 to the sixth transistor M6, the eleventh transistor M11, and the twelfth transistor M12 are in an on state
  • the first transistor M1 to the third transistor M3, and the eighth transistor M8 to the tenth transistor M10 are in an off state.
  • the seventh transistor M7 and the driving transistor DTFT are both in the on state and then switched to the off state.
  • the third capacitor C3 maintains the voltage at the fifth node N5 is the third stage in stable t3 Vdata_ I + Vth_ DTFT.
  • I_ DTFT K_ DTFT *(Vgs_ DTFT -Vth_ DTFT ) 2
  • I_ DTFT DTFT output transistor drive current at saturation Vgs_ DTFT gate-source voltage of the driving transistor DTFT, K_ M6 is a constant and is determined by the electrical characteristics of the sixth transistor M6.
  • the driving current I of the drive transistor DTFT output associated with the second data voltage only Vdata_, regardless of the threshold voltage of the driving transistor of the DTFT Vth_ DTFT, thereby avoiding the driving transistor DTFT
  • the output driving current is affected by the unevenness and drift of the threshold voltage, thereby effectively improving the uniformity of the driving current output by the driving transistor DTFT.
  • the driving current can be supplied to the element to be driven through the signal supply terminal Input and the seventh transistor M7 to drive the element to be driven to work. Since the seventh transistor M7 is switched from the on state to the off state in the third stage t3 (for details, please refer to the description in the previous embodiment), when the seventh transistor M7 is switched to the off state, the driving transistor DTFT and the first There is a circuit break between the two working power terminals, and the driving transistor DTFT is also switched to an off state.
  • the driving current supply circuit in this embodiment can also adopt other circuit structures, which will not be described here as examples.
  • FIG. 7 is a flowchart of a driving method of a pixel circuit provided by an embodiment of the disclosure. As shown in FIG. 7, the pixel circuit adopts the pixel circuit provided in any of the above embodiments, and the driving method includes:
  • Step S101 Load the reset signal to the reset signal line, load the reference voltage to the reference voltage terminal, and load the initialization voltage to the initialization voltage terminal, so that the first reset sub-circuit controls the reference voltage and the reference voltage in response to the reset signal.
  • the initialization voltage is written to the first node and the second node respectively.
  • Step S102 Load the gate scan signal to the gate line, and load the first data voltage to the first data line, so that the first data writing sub-circuit controls the writing of the first data voltage to the second node in response to the gate scan signal .
  • Step S103 Load the control signal to the control signal line, so that the first output control sub-circuit forms a path between the charging and discharging electronic circuit and the charging and discharging terminal in response to the control of the control signal, and provides the voltage at the first node to the switch
  • the sub-circuit, the charging and discharging electronic circuit responds to the control of the first data voltage to charge or discharge the first node
  • the switch sub-circuit responds to the control of the voltage at the first node to control the signal supply terminal and the component to be driven. On and off.
  • FIG. 8 is a flowchart of another driving method of a pixel circuit provided by an embodiment of the disclosure.
  • the pixel circuit not only includes a first reset sub-circuit, a first data writing sub-circuit, and a charge and discharge electronic The circuit, the first output control sub-circuit, and the switch sub-circuit, and further include a drive current supply circuit; wherein, the drive current supply circuit includes: a second reset sub-circuit, a second data writing sub-circuit, a threshold compensation sub-circuit, and a second Output control sub-circuit and drive transistor.
  • the driving method of the pixel circuit includes:
  • Step S201 Load the reset signal to the reset signal line, load the reference voltage to the reference voltage terminal, and load the initialization voltage to the initialization voltage terminal, so that the first reset sub-circuit controls the reference voltage and the reference voltage in response to the reset signal.
  • the initialization voltage is written to the first node and the second node respectively, and the second reset sub-circuit controls the writing of the reference voltage to the fifth node in response to the reset signal.
  • Step S203 Load the control signal to the control signal line, and load the first operating voltage to the first operating voltage terminal, so that the second output control sub-circuit writes the first operating voltage to the sixth node in response to the control of the control signal , And provide the drive current output by the drive transistor to the signal supply terminal, the first output control sub-circuit responds to the control signal to form a path between the charge and discharge electronic circuit and the charge and discharge terminal and provide the voltage at the first node to the
  • the charging and discharging electronic circuit responds to the control of the first data voltage to charge or discharge the first node
  • the switch sub-circuit responds to the control of the voltage at the first node to control the signal supply terminal and the component to be driven The on-off.
  • FIG. 9 is a schematic diagram of the circuit structure of a display device provided by an embodiment of the disclosure. As shown in FIG. The pixel circuit and Micro-LED of the component to be driven are provided in the example. The pixel circuit is used to provide driving signals to the component to be driven.
  • the component to be driven includes: LED or Micro-LED.
  • the number of sub-pixels is greater than or equal to 2; it should be noted that 2 ⁇ 2 sub-pixels are exemplarily drawn in FIG. 9, and the pixel circuit in the sub-pixels is shown in FIG. 5 ( That is, it includes the first transistor M1 to the twelfth transistor M12, the driving transistor DTFT, and the first capacitor C1 to the third capacitor C3). This situation is only exemplary and does not limit the technical solution of the present disclosure.
  • sub-pixels located in the same row correspond to the same gate line Gate(1)/Gate(2)
  • sub-pixels located in the same column correspond to the same first gate line.
  • the data line Data_T(1)/Data_T(2) and the same second data line Data_I(1)/Data_I(2), all sub-pixels correspond to the same control signal line SW. It should be noted that the above situation only plays an exemplary role and does not limit the technical solution of the present disclosure.
  • the display device provided by the embodiment of the present disclosure may be any product or component with display function such as electronic paper, LED panel, mobile phone, tablet computer, television, monitor, notebook computer, digital photo frame, navigator, etc.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Control Of El Displays (AREA)

Abstract

一种像素电路及其驱动方法和显示装置，像素电路包括：第一重置子电路（1），配置为响应于重置信号线（Reset）的信号的控制，将参考电压（Vref）和初始化电压（Vinit）分别写入至第一节点（N1）和第二节点（N2）；第一数据写入子电路（2），配置为响应于栅线（Gate）的信号的控制，将第一数据电压写入至第二节点（N2）；第一输出控制子电路（4），配置为响应于控制信号线（SW）的信号的控制，将第一节点（N1）处电压提供给开关子电路（5）；充放电子电路（3），配置为响应于第一数据电压的控制，对第一节点（N1）进行充电处理或放电处理；开关子电路（5），与信号供给端（Input）和待驱动元件（Micro-LED）连接，配置为响应于第一输出控制子电路（4）所提供的第一节点（N1）处电压的控制，来控制信号供给端（Input）与待驱动元件（Micro-LED）之间的通断。

Description

像素电路及其驱动方法和显示装置 技术领域
本公开涉及显示技术领域，特别涉及一种像素电路及其驱动方法和显示装置。
背景技术
微型发光二极管(Micro Light Emitting Diode，Micro-LED)技术是通过在一个芯片上高密度地集成微小尺寸的LED阵列，以实现LED的薄膜化、微小化和矩阵化，其像素间的距离能够达到微米级别，而且每一个像素都能定址、单独发光。Micro-LED显示面板因其低驱动电压、长寿命、耐宽温等特点，逐渐向消费者终端机所用的显示面板发展。
发明内容
本公开实施例提供了一种像素电路及其驱动方法和显示装置，能够提示显示装置的显示效果。
第一方面，本公开实施例提供了一种像素电路，其中，包括：第一重置子电路、第一数据写入子电路、充放电子电路、第一输出控制子电路和开关子电路，所述第一重置子电路、所述充放电子电路和所述第一输出控制子电路连接于第一节点，所述第一重置子电路、所述第一数据写入子电路和所述充放电子电路连接于第二节点；
所述第一重置子电路，配置为响应于重置信号线的信号的控制，将参考电压和初始化电压分别写入至所述第一节点和所述第二节点；
所述第一数据写入子电路，配置为响应于栅线的信号的控制，将第一数据电压写入至所述第二节点；
所述第一输出控制子电路，配置为响应于控制信号线的信号的控制， 使得所述充放电子电路与充放电端之间形成通路，以及将所述第一节点处电压提供给所述开关子电路；
所述充放电子电路，配置为响应于所述第一数据电压的控制，对所述第一节点进行充电处理或放电处理；
所述开关子电路，与信号供给端和待驱动元件连接，配置为响应于所述第一输出控制子电路所提供的所述第一节点处电压的控制，来控制所述信号供给端与所述待驱动元件之间的通断。
在一些实施例中，所述第一重置子电路包括：第一晶体管和第二晶体管；
所述第一晶体管的控制极与所述重置信号线连接，所述第一晶体管的第一极与参考电压端连接，所述第一晶体管的第二极与所述第一节点连接；
所述第二晶体管的控制极与所述重置信号线连接，所述第二晶体管的第一极与初始化电压端连接，所述第二晶体管的第二极与所述第二节点连接。
在一些实施例中，所述第一数据写入子电路包括：第三晶体管；
所述第三晶体管的控制极与所述栅线连接，所述第三晶体管的第一极与第一数据线连接，所述第三晶体管的第二极与所述第二节点连接。
在一些实施例中，所述第一输出控制子电路包括：第四晶体管和第五晶体管；
所述第四晶体管的控制极与所述控制信号线连接，所述第四晶体管的第一极与所述充放电子电路连接，所述第四晶体管的第二极与所述充放电端连接；
所述第五晶体管的控制极与所述控制信号线连接，所述第五晶体管的第一极与所述第一节点连接，所述第五晶体管的第二极与所述开关子电路连接。
在一些实施例中，所述充放电子电路包括：第六晶体管和第一电容；
所述第六晶体管的控制极与所述第二节点连接，所述第六晶体管的第一极与所述第一节点连接，所述第六晶体管的第二极与所述第一输出控制子电路连接；
所述第一电容的第一端与所述第一节点连接，所述第一电容的第二端与第一恒压端连接。
在一些实施例中，所述开关子电路包括：第七晶体管；
所述第七晶体管的控制极与所述第一输出控制子电路连接，所述第七晶体管的第一极与所述信号供给端连接，所述第七晶体管的第二极与所述待驱动元件连接。
在一些实施例中，所述像素电路还包括：第二电容；
所述第二电容的第一端与所述第二节点连接，所述第二电容的第二端与所述第二恒压端连接。
在一些实施例中，所述信号供给端与第一工作电压端连接，所述第一工作电压端通过所述信号供给端向所述开关子电路提供第一工作电压。
在一些实施例中，所述像素电路还包括：驱动电流供给电路；
所述驱动电流供给电路与所述信号供给端连接，所述驱动电流供给电路配置为通过所述信号供给端向所述开关子电路提供驱动电流。
在一些实施例中，所述驱动电流供给电路包括：第二重置子电路、第二数据写入子电路、阈值补偿子电路、第二输出控制子电路和驱动晶体管，所述驱动晶体管的第二极、所述阈值补偿子电路和所述第二输出控制子电路连接于第四节点，所述驱动晶体管的控制极、所述阈值补偿子电路和所述第二重置子电路连接于第五节点，所述驱动晶体管的第一极、所述第二数据写入子电路和所述第二输出控制子电路连接于第六节点；
所述第二重置子电路，配置为响应于所述重置信号线的信号的控制，将参考电压写入至所述第五节点；
所述第二数据写入子电路，配置为响应于所述栅线的信号的控制，将第二数据电压写入至所述第六节点；
所述阈值补偿子电路，配置为响应于所述栅线的信号的控制，对所述驱动晶体管的阈值电压进行补偿；
所述第二输出控制子电路，配置为响应于所述控制信号线的信号的控制，将第一工作电压写入至所述第六节点，以及将所述驱动晶体管所输出的驱动电流提供给所述信号供给端；
所述驱动晶体管，配置为在所述第五节点处电压和所述第六节点处电压的控制下输出相应的驱动电流。
在一些实施例中，所述第二重置子电路包括：第八晶体管；
所述第八晶体管的控制极与所述重置信号线连接，所述第八晶体管的第一极与所述参考电压端连接，所述第八晶体管的第二极与所述第五节点连接。
在一些实施例中，所述第二数据写入子电路包括：第九晶体管；
所述第九晶体管的控制极与所述栅线连接，所述第九晶体管的第一极与第二数据线连接，所述第九晶体管的第二极与所述第六节点连接。
在一些实施例中，所述阈值补偿子电路包括：第十晶体管；
所述第十晶体管的控制极与所述栅线连接，所述第十晶体管的第一极与所述第四节点连接，所述第十晶体管的第二极与所述第五节点连接。
在一些实施例中，所述第二输出控制子电路包括：第十一晶体管和第十二晶体管；
所述第十一晶体管控制极与所述控制信号线连接，所述第十一晶体管的第一极与第一工作电压端连接，所述第十一晶体管的第二极与所述第六节点连接；
所述第十二晶体管控制极与所述控制信号线连接，所述第十二晶体管的第一极与所述第四节点连接，所述第十二晶体管的第二极与所述信号供给端连接。
在一些实施例中，所述像素电路还包括：第三电容；
所述第三电容的第一端与所述第五节点连接，所述第三电容的第二端与所述第三恒压端连接。
在一些实施例中，所述像素电路中的全部晶体管均为N型晶体管；
或者，所述像素电路中的全部晶体管均为P型晶体管。
第二方面，本公开实施例还提供了一种显示装置，其中，包括：包括显示基板，所述显示基板包括多个亚像素，至少一个所述亚像素内设置有如第一方面提供的像素电路和待驱动元件，所述像素电路配置为向所述待驱动元件提供驱动信号。
在一些实施例中，所述待驱动元件包括：LED或Micro-LED。
第三方面，本公开实施例还提供了一种像素电路的驱动方法，其中，用于驱动第一方面所提供的像素电路，所述驱动方法包括：
将重置信号加载至所述重置信号线，将参考电压加载至参考电压端，将初始化电压加载至初始化电压端，以使得所述第一重置子电路响应于所述重置信号控制将所述参考电压和所述初始化电压分别写入至所述第一节点和所述第二节点；
将栅扫描信号加载至所述栅线，将第一数据电压加载至所述第一数据线，以使得所述第一数据写入子电路响应于所述栅扫描信号控制将所述第一数据电压写入至所述第二节点；
将控制信号加载至所述控制信号线，以使得第一输出控制子电路响应于所述控制信号的控制将所述充放电子电路与充放电端之间形成通路，且将所述第一节点处电压提供给所述开关子电路，所述充放电子电路响应于所述第一数据电压的控制对所述第一节点进行充电处理或放电 处理，所述开关子电路响应于所述第一节点处电压的控制来控制所述信号供给端与所述待驱动元件之间的通断。
在一些实施例中，所述像素电路包括驱动电流供给电路，所述驱动电流供给电路包括：第二重置子电路、第二数据写入子电路、阈值补偿子电路、第二输出控制子电路和驱动晶体管；
在将重置信号加载至所述重置信号线，将参考电压加载至参考电压端时，所述第二重置子电路响应于所述重置信号控制将所述参考电压写入至所述第五节点；
在将栅扫描信号加载至所述栅线的同时，还包括：将第二数据电压加载至所述第二数据线，以使得所述第二数据写入子电路将所述第二数据电压写入至所述第六节点，所述阈值补偿子电路响应于所述栅线的控制对所述驱动晶体管的阈值电压进行补偿；
在将控制信号加载至所述控制信号线的同时，还包括：将第一工作电压加载至所述第一工作电压端，以使得所述第二输出控制子电路响应于所述控制信号的控制将所述第一工作电压写入至所述第六节点，且将所述驱动晶体管所输出的驱动电流提供给所述信号供给端。
附图说明
图1为本公开实施例提供的一种像素电路的电路结构示意图；
图2为本公开实施例中待驱动元件的器件特性示意图；
图3为本公开实施例提供的另一种像素电路的电路结构示意图；
图4为图3所示像素电路的一种工作时序图；
图5为本公开实施例提供的又一种像素电路的电路结构示意图；
图6为图5所示像素电路的一种工作时序图；
图7为本公开实施例提供的一种像素电路的驱动方法流程图；
图8为本公开实施例提供的另一种像素电路的驱动方法流程图；
图9为本公开实施例提供的一种显示装置的电路结构示意图。
具体实施方式
为使本领域的技术人员更好地理解本发明的技术方案，下面结合附图对本发明提供的一种像素电路及其驱动方法和显示装置进行详细描述。
在本公开实施例中，待驱动元件可以为发光元件，发光元件可以为包括发光二极管(Light Emitting Diode，简称LED)或Micro-LED在内电流/电压驱动的发光器件，在下述实施例中以待驱动元件为Micro-LED为例进行描述，Micro-LED的尺寸级别为微米(μm)级别。
此外，在本公开实施例中所涉及的各个晶体管可分别独立选自多晶硅薄膜晶体管、非晶硅薄膜晶体管、氧化物薄膜晶体管以及有机薄膜晶体管中的一种。在本公开中涉及到的“控制极”具体是指晶体管的栅极，“第一极”具体是指晶体管的源极，相应的“第二极”具体是指晶体管的漏极。当然，本领域的技术人员应该知晓的是，该“第一极”与“第二极”可进行互换。
另外，晶体管可以划分为N型晶体管和P型晶体管，本公开中的各晶体管可分别独立选自N型晶体管或P型晶体管；在下述实施例中将以像素单元中的全部晶体管均为N型晶体管为例进行示例性描述，此时像素电路中的晶体管可采用相同的制备工艺得以同时制备。相应地，第一工作电压为高电平工作电压Vdd，第二工作电压为低电平工作电压Vss；另外，假定第一恒压端接地GND，第二恒压端提供低电平工作电压Vss，第三恒压端提供高电平工作电压Vdd。上述对晶体管类型、工作电压、恒压端的设定仅起到示例性作用，其不会对本公开的技术方案产生限制。
图1为本公开实施例提供的一种像素电路的电路结构示意图，如图1所示，该像素电路包括：第一重置子电路1、第一数据写入子电路2、 充放电子电路3、第一输出控制子电路4和开关子电路5，第一重置子电路1、充放电子电路3和第一输出控制子电路4连接于第一节点N1，第一重置子电路1、第一数据写入子电路2和充放电子电路3连接于第二节点N2，待驱动元件Micro-LED的阳极与开关子电路5连接于第三节点N3，Micro-LED的阴极与第二工作电压端连接。
其中，第一重置子电路1配置为响应于重置信号线Reset的信号的控制，将参考电压和初始化电压分别写入至第一节点N1和第二节点N2。
第一数据写入子电路2配置为响应于栅线Gate的信号的控制，将第一数据电压写入至第二节点N2。
第一输出控制子电路4配置为响应于控制信号线SW的信号的控制，使得充放电子电路3与充放电端Dc之间形成通路，以及将第一节点N1处电压提供给开关子电路5。
充放电子电路3配置为响应于第一数据电压的控制，对第一节点N1进行充电处理或放电处理。
开关子电路5与信号供给端Input和待驱动元件Micro-LED连接，配置为响应于第一输出控制子电路4所提供的第一节点N1处电压的控制，来控制信号供给端Input与待驱动元件Micro-LED之间的通断。其中，当信号供给端Input与待驱动元件Micro-LED之间导通时，信号供给端Input所供给的信号可被写入至待驱动元件Micro-LED，待驱动元件Micro-LED可被驱动从而进行工作；当信号供给端Input与待驱动元件Micro-LED之间断路时，信号供给端Input所供给的信号无法写入至待驱动元件Micro-LED，待驱动元件Micro-LED无法工作。
在本公开实施例中，通过第一数据电压可以控制充放电子电路3对第一节点N1的充电/放电处理速度，即控制第一节点N1的充电/放电速度(第一节点N1的电压变化速率)，开关子电路5基于第一节点N1处电压的大小来控制信号供给端Input与待驱动元件Micro-LED之间的通 断。
具体地，当开关子电路5中的晶体管为N型晶体管时，需设计充放电端Dc所提供的电压(例如，充放电端Dc提供接地电压)小于参考电压，且参考电压足以使得开关子电路5中的晶体管处于导通状态，此时充放电子电路3会对第一节点N1处进行放电处理，以使得第一节点N1处的电压下降，且开关子电路5中的N型晶体管会经历由导通状态切换至截止状态。当开关子电路5中的晶体管为P型晶体管时，需设计充放电端Dc所提供的电压(例如，充放电端Dc提供高电平工作电压Vdd)大于参考电压，且参考电压足以使得开关子电路5中的晶体管处于导通状态，此时充放电子电路3会对第一节点N1处的电压进行充电处理，以使得第一节点N1处的电压上升，且开关子电路5中的P型晶体管会经历由导通状态切换至截止状态。
作为一种示例，当开关子电路5中的晶体管为N型晶体管时，若第一输出控制子电路4提供给开关子电路5的电压大于预设阈值，则开关子电路5处于“闭合”状态，信号供给端Input与待驱动元件Micro-LED之间导通；若第一输出控制子电路4提供给开关子电路5的电压小于或等于预设阈值时，则开关子电路5处于“断开”状态，信号供给端Input与待驱动元件Micro-LED之间断路。
作为另一种示例，当开关子电路5中的晶体管为P型晶体管时，若第一输出控制子电路4提供给开关子电路5的电压小于预设阈值，则开关子电路5处于“闭合”状态，信号供给端Input与待驱动元件Micro-LED之间导通；若第一输出控制子电路4提供给开关子电路5的电压大于或等于预设阈值时，则开关子电路5处于“断开”状态，信号供给端Input与待驱动元件Micro-LED之间断路。
通过控制第一数据电压来控制第一节点N1处的充电/放电速度，从而可对第一节点N1处电压由参考电压充电/放电至上述预设阈值的时长 进行控制，进而实现对开关子电路5处于“闭合”状态的时长进行控制，即实现对待驱动元件Micro-LED的工作时长进行控制。
在本公开实施例中，信号供给端Input可用于在一帧内提供恒定电压信号或恒定电流信号。当信号供给端Input提供恒定电压信号时，以该恒定电压为第一工作电压Vdd为例，在LED两端分别加载有电压Vdd和电压Vss时，流过待驱动元件Micro-LED的电流的电流密度固定(即流过待驱动元件Micro-LED的电流大小固定)；当信号供给端Input提供恒定电流信号时，流过待驱动元件Micro-LED的电流大小固定。由于流过待驱动元件Micro-LED的电流大小和待驱动元件Micro-LED在一个周期(例如，一帧)内的工作时长影响待驱动元件Micro-LED的在该周期内的有效发光亮度，因此通过控制信号供给端Input提供的电压/电流信号以及第一数据线Data_T提供的第一数据电压，可以控制待驱动元件Micro-LED在该周期内的有效发光亮度，达到调节显示灰阶的目的。
图2为本公开实施例中待驱动元件的器件特性示意图，如图2所示，待驱动元件Micro-LED的发光效率会随着电流密度的增大而逐渐上升，并会在电流密度介于J1与J2之间时稳定在最大值。由此，出于节省显示功耗的考虑，一般要求待驱动元件Micro-LED工作在电流密度介于J1与J2之间的状态。然而，电流密度介于J1与J2之间的范围对于很多类型的待驱动元件Micro-LED是极其有限的，而如果只通过调节电流大小来得到不同灰阶，则所得到的显示对比度可能会非常低。为此，在本公开实施例中，可将待驱动元件Micro-LED工作时的电流密度设定在稳定范围(介于J1与J2之间)内，通过第一数据电压来调节每个周期内开关子电路5处于“闭合”状态的时长，来对显示灰阶的进行控制，可实现显示装置的高对比度。
本公开的技术方案在待驱动元件的电流密度处于稳定范围的前提下实现高对比度，既可以避免待驱动元件的电流密度处于稳定范围以外引 起色偏、效率下降等问题，又可以帮助实现显示产品所需要的高对比度，因此本公开实施例可以减轻待驱动元件的电学特性容易随电流密度漂移所引发的显示缺陷，提升相关显示产品的显示性能。
图3为本公开实施例提供的另一种像素电路的电路结构示意图，如图3所示，该，该像素电路为基于图1所示像素电路的一种具体化实施方案，其中，信号供给端Input与第一工作电压端连接，第一工作电压端通过信号供给端Input向开关子电路5提供第一工作电压Vdd。
在一些实施例中，第一重置子电路1包括：第一晶体管M1和第二晶体管M2；第一晶体管M1的控制极与重置信号线Reset连接，第一晶体管M1的第一极与参考电压端连接，第一晶体管M1的第二极与第一节点N1连接；第二晶体管M2的控制极与重置信号线Reset连接，第二晶体管M2的第一极与初始化电压端连接，第二晶体管M2的第二极与第二节点N2连接。
在一些实施例中，第一数据写入子电路2包括：第三晶体管M3；第三晶体管M3的控制极与栅线Gate连接，第三晶体管M3的第一极与第一数据线Data_T连接，第三晶体管M3的第二极与第二节点N2连接。
在一些实施例中，第一输出控制子电路4包括：第四晶体管M4和第五晶体管M5；第四晶体管M4的控制极与控制信号线SW连接，第四晶体管M4的第一极与充放电子电路3连接，第四晶体管M4的第二极与充放电端Dc连接；第五晶体管M5的控制极与控制信号线SW连接，第五晶体管M5的第一极与第一节点N1连接，第五晶体管M5的第二极与开关子电路5连接。
在一些实施例中，充放电子电路3包括：第六晶体管M6和第一电容C1；第六晶体管M6的控制极与第二节点N2连接，第六晶体管M6的第一极与第一节点N1连接，第六晶体管M6的第二极与第一输出控制子电路4连接；第一电容C1的第一端与第一节点N1连接，第一电容C1的第二 端与第一恒压端连接。
在一些实施例中，开关子电路5包括：第七晶体管M7；第七晶体管M7的控制极与第一输出控制子电路4连接，第七晶体管M7的第一极与信号供给端Input连接，第七晶体管M7的第二极与待驱动元件Micro-LED连接。
在一些实施例中，像素电路还包括：第二电容C2；第二电容C2的第一端与第二节点N2连接，第二电容C2的第二端与第二恒压端连接。其中，第二电容C2用于维持第二节点N2电压的稳定，其并非为像素电路中的必要结果。
其中，假定第一晶体管M1～第七晶体管M7均为N型晶体管，此时充放电子电路3用于对第一节点N1处进行放电处理，充放电端Dc提供的接地电压V GND。
下面将结合附图来对图3所示像素电路的工作过程进行详细描述。图4为图3所示像素电路的一种工作时序图，如图4所示，该像素电路的工作过程可划分为三个阶段。
第一阶段t1，重置信号线Reset提供的重置信号处于高电平状态，栅线Gate提供的栅扫描信号处于低电平状态，控制信号线SW提供的控制信号处于低电平状态。此时，第一晶体管M1和第二晶体管M2处于导通状态，第三晶体管M3～第七晶体管M7处于截止状态。参考电压端提供的参考电压Vref通过第一晶体管M1写入至第一节点N1，初始化电压端提供的初始化电压Vinit通过第二晶体管M2写入至第二节点N2。由于第七晶体管M7处于截止状态，因此第一工作电压端与第三节点N3之间断路。
第二阶段t2，重置信号线Reset提供的重置信号处于低电平状态，栅线Gate提供的栅扫描信号处于高电平状态，控制信号线SW提供的控制信号处于低电平状态。此时，第三晶体管M3处于导通状态，第一晶体 管M1、第二晶体管M2、第四晶体管M4～第七晶体管M7处于截止状态。第一数据线Data_T提供的第一数据电压通过第三晶体管M3写入至第二节点N2。由于第七晶体管M7处于截止状态，因此第一工作电压端与第三节点N3之间断路。
第三阶段t3，重置信号线Reset提供的重置信号处于低电平状态，栅线Gate提供的栅扫描信号处于低电平状态，控制信号线SW提供的控制信号处于高电平状态。此时，第四晶体管M4～第六晶体管M6处于导通状态，第一晶体管M1～第三晶体管M3处于截止状态，第七晶体管M7先处于导通状态后又切换至截止状态。
其中，第二电容C2可维持第二节点N2的电压在第三阶段t3中稳定于第一数据电压。
当第四晶体管M4处于导通状态时，第六晶体管M6的第二极与充放电端Dc连接，第六晶体管M6受控于第二节点N2处电压的控制而工作于饱和状态，根据饱和电流公式可得：
I_ M6＝K_ M6*(Vgs_ M6-Vth_ M6) 2
＝K_ M6*(Vdata_ T-V GND-Vth_ M6) 2
其中，I_ M6为第六晶体管M6在饱和状态下输出的电流，Vgs_ M6为第六晶体管M6的栅源电压，Vth_ M6为第六晶体管M6的阈值电压，Vdata_ T为第一数据电压，V GND为接地电压(近似为0V),K_ M6为一个常量且由第六晶体管M6的电学特性决定。
此时，第六晶体管M6的等效电阻R_ M6：
Figure PCTCN2020078982-appb-000001
其中，Vref为参考电压；在Vref、K_ M6、V GND和Vth_ M6一定的情况下，第六晶体管M6的等效电阻R_ M6的大小由仅第一数据电压Vdata_ T决定。
第一节点N1处放电使得电压由参考电参考Vref变为接地电压V GND的 过程中，放电总时长t＝R_ M6×C1'，其中C1'表示第一电容C1的电容大小。放电时间的大小也反应了第一节点N1的平均放电速度，其中放电时长越小，则表示平均放电速度越快。在第一电容C1的电容大小C1'固定的情况下，放电总时长t由第六晶体管M6的等效电阻R_ M6的大小决定，又因为第六晶体管M6的等效电阻R_ M6的大小由仅第一数据电压Vdata_ T决定，因此第一数据电压Vdata_ T决定了放电总时长和平均放电速度。
在放电过程中，在第一节点N1处的电压由Vref放电至Vss+V_ led+Vth_ M7过程中，第七晶体管M7始终处于导通状态，第三节点N3处的电压为高电平电压；其中，V_ led为待驱动元件处于工作状态时阳极与阴极的电压差，Vth_ M7为第七晶体管M7的阈值电压。当第一节点N1处的电压到达Vss+V_ led+Vth_ M7时，第七晶体管M7由导通状态切换至截止状态(此时的预设阈值为Vss+V_ led+Vth_ M7)。当第一节点N1处的电压小于Vss+V_ led+Vth_ M7时，第七晶体管M7始终处于截止状态，第三节点N3处的电压为低电平电压。
其中，第一节点N1处的电压由Vref放电至Vss+V_ led+Vth_ M7所经历的时长t_ EM与平均放电速度负相关；即平均放电速度越快，则第一节点N1处的电压由Vref放电至Vss+V_ led+Vth_ M7所经历的时长t_ EM越短。因此通过调节第一数据电压Vdata_ T，可对第一节点N1处的电压由Vref放电至Vss+V_ led+Vth_ M7所经历的时长t_ EM进行调节。
由此可见，在本公开实施例中，可通过调节第一数据电压的大小来实现对第七晶体管M7处于导通状态的时长进行调节，从而能够实现对显示灰阶的调节。
需要说明的是，若第一晶体管M1～第七晶体管M7均为P型晶体管，则充放电子电路3用于对第一节点N1处进行充电处理，充放电端Dc提供的高电平工作电压，此种情况未给出相应附图。像素电路中全部晶体 管均为P型晶体管的工作过程与全部晶体管均为N型晶体管的工作过程相同，此处不再赘述。
图5为本公开实施例提供的又一种像素电路的电路结构示意图，如图5所示，与前述实施例所提供的像素电路不同的是，在图5所示像素电路中还包括：驱动电流供给电路10，其中驱动电流供给电路10与信号供给端Input连接，驱动电流供给电路10配置为通过信号供给端Input向开关子电路5提供驱动电流。与前述实施例相比，在本公开实施例中，通过驱动电流供给电路10可在不同周期(例如，一帧)中向信号供给端Input提供不同大小的驱动电流，此时显示对比对可得到有效提升。
对于图5所示像素电路内第一重置子电路1、第一数据写入子电路2、充放电子电路3、第一输出控制子电路4和开关子电路5的具体描述，可参见前面实施例中相应内容，此处不再赘述。下面仅对本实施例中的驱动电流供给电路进行详细描述。
在一些实施例中，驱动电流供给电路10包括：第二重置子电路6、第二数据写入子电路7、阈值补偿子电路8、第二输出控制子电路9和驱动晶体管DTFT，驱动晶体管DTFT的第二极、阈值补偿子电路8和第二输出控制子电路9连接于第四节点N4，驱动晶体管DTFT的控制极、阈值补偿子电路8和第二重置子电路6连接于第五节点N5，驱动晶体管DTFT的第一极、第二数据写入子电路7和第二输出控制子电路9连接于第六节点N6。
其中，第二重置子电路6配置为响应于重置信号线Reset的信号的控制，将参考电压写入至第五节点N5。
第二数据写入子电路7配置为响应于栅线Gate的信号的控制，将第二数据电压写入至第六节点N6。
阈值补偿子电路8配置为响应于栅线Gate的信号的控制，对驱动晶 体管的阈值电压进行补偿。
第二输出控制子电路9配置为响应于控制信号线SW的信号的控制，将第一工作电压写入至第六节点N6，以及将驱动晶体管DTFT所输出的驱动电流提供给信号供给端Input。
驱动晶体管DTFT配置为在第五节点N5处电压和第六节点N6处电压的控制下输出相应的驱动电流。
在一些实施例中，第二重置子电路6包括：第八晶体管M8；第八晶体管M8的控制极与重置信号线Reset连接，第八晶体管M8的第一极与参考电压端连接，第八晶体管M8的第二极与第五节点N5连接。
在一些实施例中，第二数据写入子电路7包括：第九晶体管M9；第九晶体管M9的控制极与栅线Gate连接，第九晶体管M9的第一极与第二数据线Data_I连接，第九晶体管M9的第二极与第六节点N6连接。
在一些实施例中，阈值补偿子电路8包括：第十晶体管M10；第十晶体管M10的控制极与栅线Gate连接，第十晶体管M10的第一极与第四节点N4连接，第十晶体管M10的第二极与第五节点N5连接。
在一些实施例中，第二输出控制子电路9包括：第十一晶体管M11和第十二晶体管M12；第十一晶体管M11控制极与控制信号线SW连接，第十一晶体管M11的第一极与第一工作电压端连接，第十一晶体管M11的第二极与第六节点N6连接；第十二晶体管M12控制极与控制信号线SW连接，第十二晶体管M12的第一极与第四节点N4连接，第十二晶体管M12的第二极与信号供给端Input连接。
在一些实施例中，像素电路还包括：第三电容C3；第三电容C3的第一端与第五节点N5连接，第三电容C3的第二端与第三恒压端连接。其中，第三电容C3用于维持第五节点N5电压的稳定，其并非为像素电路中的必要结果。
其中，假定第八晶体管M8～第十二晶体管M12均为N型晶体管，且 参考电压足以使得驱动晶体管DTFT导通。
下面将结合附图来对图5所示像素电路的工作过程进行详细描述。图6为图5所示像素电路的一种工作时序图，如图6所示，该像素电路的工作过程可划分为三个阶段。
第一阶段t1，重置信号线Reset提供的重置信号处于高电平状态，栅线Gate提供的栅扫描信号处于低电平状态，控制信号线SW提供的控制信号处于低电平状态。此时，第一晶体管M1、第二晶体管M2和第八晶体管M8处于导通状态，第三晶体管M3～第七晶体管M7、第九晶体管M9～第十二晶体管M12均处于截止状态。参考电压端提供的参考电压Vref通过第一晶体管M1写入至第一节点N1、通过第八晶体管M8写入至第五节点N5，初始化电压端提供的初始化电压Vinit通过第二晶体管M2写入至第二节点N2。由于第十一晶体管M11和第十二晶体管M12处于截止状态，因此驱动电流供给电路10无驱动电流输出。与此同时，由于第七晶体管M7处于截止状态，因此第一工作电压端与第三节点N3之间断路。
第二阶段t2，重置信号线Reset提供的重置信号处于低电平状态，栅线Gate提供的栅扫描信号处于高电平状态，控制信号线SW提供的控制信号处于低电平状态。此时，第三晶体管M3、第九晶体管M9和第十晶体管M10处于导通状态，第一晶体管M1、第二晶体管M2、第四晶体管M4～第七晶体管M7、第八晶体管M8、第十一晶体管M11和第十二晶体管M12处于截止状态。第一数据线Data_T提供的第一数据电压通过第三晶体管M3写入至第二节点N2，第二数据线Data_I提供的第二数据电压通过第九晶体管M9写入至第六节点N6，此时第五节点N5处通过第十晶体管M10和驱动晶体管DTFT进行放电，当第五节点N5处的电压下降至Vdata_ I+Vth_ DTFT时驱动晶体管DTFT截止，放电结束；其中Vdata_ I为第二 数据电压，Vth_ DTFT为驱动晶体管DTFT的阈值电压。由于第十一晶体管M11和第十二晶体管M12处于截止状态，因此驱动电流供给电路10无驱动电流输出。与此同时，由于第七晶体管M7处于截止状态，因此第一工作电压端与第三节点N3之间断路。
第三阶段t3，重置信号线Reset提供的重置信号处于低电平状态，栅线Gate提供的栅扫描信号处于低电平状态，控制信号线SW提供的控制信号处于高电平状态。此时，第四晶体管M4～第六晶体管M6、第十一晶体管M11、第十二晶体管M12处于导通状态，第一晶体管M1～第三晶体管M3、第八晶体管M8～第十晶体管M10处于截止状态，第七晶体管M7和驱动晶体管DTFT均是先处于导通状态后又切换至截止状态。
其中，第三电容C3可维持第五节点N5的电压在第三阶段t3中稳定于Vdata_ I+Vth_ DTFT。
对于驱动晶体管DTFT而言，七工作于饱和状态，根据饱和电流公式可得：
I_ DTFT＝K_ DTFT*(Vgs_ DTFT-Vth_ DTFT) 2
＝K_ DTFT*(Vdata_ I+Vth_ DTFT-Vdd-Vth_ DTFT) 2
＝K_ DTFT*(Vdata_ I-Vdd) 2
其中，I_ DTFT为驱动晶体管DTFT在饱和状态下输出的电流，Vgs_ DTFT为驱动晶体管DTFT的栅源电压，K_ M6为一个常量且由第六晶体管M6的电学特性决定。由此可见，在第一工作电压Vdd一定的情况下，驱动晶体管DTFT输出的驱动电流仅与第二数据电压Vdata_ I相关，而与驱动晶体管DTFT的阈值电压Vth_ DTFT无关，从而可避免驱动晶体管DTFT所输出驱动电流受到阈值电压不均匀和漂移的影响，进而有效的提高了驱动晶体管DTFT所输出驱动电流的均匀性。
由于第十二晶体管M12导通，因此该驱动电流可通过信号供给端Input、第七晶体管M7供给给待驱动元件，以驱动待驱动元件进行工作。 由于第七晶体管M7在第三阶段t3中会由导通状态切换至截止状态(具体内容可参见前面实施例中的描述)，因此当第七晶体管M7切换为截止状态时，驱动晶体管DTFT与第二工作电源端之间断路，驱动晶体管DTFT也切换至截止状态。
需要说明的是，当本实施例提供的像素电路中全部晶体管均为P型晶体管的工作过程与全部晶体管均为N型晶体管的工作过程相同，此处不再赘述。
本领域技术人员应该知晓的是，本实施例中的驱动电流供给电路还可以采用其他电路结构，此处不再一一举例描述。
图7为本公开实施例提供的一种像素电路的驱动方法流程图，如图7所示，该像素电路采用上面任一实施例提供的像素电路，该驱动方法包括：
步骤S101、将重置信号加载至重置信号线，将参考电压加载至参考电压端，将初始化电压加载至初始化电压端，以使得第一重置子电路响应于重置信号控制将参考电压和初始化电压分别写入至第一节点和第二节点。
步骤S102、将栅扫描信号加载至栅线，将第一数据电压加载至第一数据线，以使得第一数据写入子电路响应于栅扫描信号控制将第一数据电压写入至第二节点。
步骤S103、将控制信号加载至控制信号线，以使得第一输出控制子电路响应于控制信号的控制将充放电子电路与充放电端之间形成通路，且将第一节点处电压提供给开关子电路，充放电子电路响应于第一数据电压的控制对第一节点进行充电处理或放电处理，开关子电路响应于第一节点处电压的控制来控制信号供给端与待驱动元件之间的通断。
对于上述步骤S101～步骤S103的具体描述，可参见描述实施例中相应内容，此处不再赘述。
图8为本公开实施例提供的另一种像素电路的驱动方法流程图，如图8所示，该像素电路中不但包括第一重置子电路、第一数据写入子电路、充放电子电路、第一输出控制子电路和开关子电路，还包括驱动电流供给电路；其中，驱动电流供给电路包括：第二重置子电路、第二数据写入子电路、阈值补偿子电路、第二输出控制子电路和驱动晶体管。该像素电路的驱动方法包括：
步骤S201、将重置信号加载至重置信号线，将参考电压加载至参考电压端，将初始化电压加载至初始化电压端，以使得第一重置子电路响应于重置信号控制将参考电压和初始化电压分别写入至第一节点和第二节点，第二重置子电路响应于重置信号控制将参考电压写入至第五节点。
步骤S202、将栅扫描信号加载至栅线，将第一数据电压加载至第一数据线，将第二数据电压加载至第二数据线，以使得第一数据写入子电路响应于栅扫描信号控制将第一数据电压写入至第二节点，第二数据写入子电路将第二数据电压写入至第六节点，阈值补偿子电路响应于栅线的控制对驱动晶体管的阈值电压进行补偿。
步骤S203、将控制信号加载至控制信号线，将第一工作电压加载至第一工作电压端，以使得第二输出控制子电路响应于控制信号的控制将第一工作电压写入至第六节点，且将驱动晶体管所输出的驱动电流提供给信号供给端，第一输出控制子电路响应于控制信号的控制将充放电子电路与充放电端之间形成通路且将第一节点处电压提供给开关子电路，充放电子电路响应于第一数据电压的控制对第一节点进行充电处理或放电处理，开关子电路响应于第一节点处电压的控制来控制信号供给端与待驱动元件之间的通断。
对于上述步骤S201～步骤S203的具体描述，可参见描述实施例中相应内容，此处不再赘述。
图9为本公开实施例提供的一种显示装置的电路结构示意图，如图 9所示，该显示装置包括：包括显示基板，显示基板包括多个亚像素，至少一个亚像素内设置有如前面实施例所提供的像素电路和待驱动元件Micro-LED，像素电路用于向待驱动元件提供驱动信号。
在一些实施例中，待驱动元件包括：LED或Micro-LED。
在一些实施例中，亚像素的数量大于或等于2个；需要说明的是，图9中示例性画出了2×2个亚像素，且亚像素中的像素电路采用图5中所示(即包括第一晶体管M1～第十二晶体管M12、驱动晶体管DTFT、第一电容C1～第三电容C3)，该情况仅起到示例性作用，不会对本公开的技术方案产生限制。
在一些实施例中，在多个亚像素所构成的像素阵列中，位于同一行的亚像素对应同一条栅线Gate(1)/Gate(2)，位于同一列的亚像素对应同一条第一数据线Data_T(1)/Data_T(2)和同一条第二数据线Data_I(1)/Data_I(2)，全部亚像素对应同一条控制信号线SW。需要说明的是，上述情况仅起到示例性作用，不会对本公开的技术方案产生限制。
本公开实施例提供的显示装置可以为电子纸、LED面板、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
可以理解的是，以上实施方式仅仅是为了说明本发明的原理而采用的示例性实施方式，然而本发明并不局限于此。对于本领域内的普通技术人员而言，在不脱离本发明的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本发明的保护范围。

Claims (20)

  1. 一种像素电路，包括：第一重置子电路、第一数据写入子电路、充放电子电路、第一输出控制子电路和开关子电路，其中，所述第一重置子电路、所述充放电子电路和所述第一输出控制子电路连接于第一节点，所述第一重置子电路、所述第一数据写入子电路和所述充放电子电路连接于第二节点；
    所述第一重置子电路，配置为响应于重置信号线的信号的控制，将参考电压和初始化电压分别写入至所述第一节点和所述第二节点；
    所述第一数据写入子电路，配置为响应于栅线的信号的控制，将第一数据电压写入至所述第二节点；
    所述第一输出控制子电路，配置为响应于控制信号线的信号的控制，使得所述充放电子电路与充放电端之间形成通路，以及将所述第一节点处电压提供给所述开关子电路；
    所述充放电子电路，配置为响应于所述第一数据电压的控制，对所述第一节点进行充电处理或放电处理；
    所述开关子电路，与信号供给端和待驱动元件连接，配置为响应于所述第一输出控制子电路所提供的所述第一节点处电压的控制，来控制所述信号供给端与所述待驱动元件之间的通断。
  2. 根据权利要求1所述的像素电路，其中，所述第一重置子电路包括：第一晶体管和第二晶体管；
    所述第一晶体管的控制极与所述重置信号线连接，所述第一晶体管的第一极与参考电压端连接，所述第一晶体管的第二极与所述第一节点连接；
    所述第二晶体管的控制极与所述重置信号线连接，所述第二晶体管 的第一极与初始化电压端连接，所述第二晶体管的第二极与所述第二节点连接。
  3. 根据权利要求1所述的像素电路，其中，所述第一数据写入子电路包括：第三晶体管；
    所述第三晶体管的控制极与所述栅线连接，所述第三晶体管的第一极与第一数据线连接，所述第三晶体管的第二极与所述第二节点连接。
  4. 根据权利要求1所述的像素电路，其中，所述第一输出控制子电路包括：第四晶体管和第五晶体管；
    所述第四晶体管的控制极与所述控制信号线连接，所述第四晶体管的第一极与所述充放电子电路连接，所述第四晶体管的第二极与所述充放电端连接；
    所述第五晶体管的控制极与所述控制信号线连接，所述第五晶体管的第一极与所述第一节点连接，所述第五晶体管的第二极与所述开关子电路连接。
  5. 根据权利要求1所述的像素电路，其中，所述充放电子电路包括：第六晶体管和第一电容；
    所述第六晶体管的控制极与所述第二节点连接，所述第六晶体管的第一极与所述第一节点连接，所述第六晶体管的第二极与所述第一输出控制子电路连接；
    所述第一电容的第一端与所述第一节点连接，所述第一电容的第二端与第一恒压端连接。
  6. 根据权利要求1所述的像素电路，其中，所述开关子电路包括： 第七晶体管；
    所述第七晶体管的控制极与所述第一输出控制子电路连接，所述第七晶体管的第一极与所述信号供给端连接，所述第七晶体管的第二极与所述待驱动元件连接。
  7. 根据权利要求1所述的像素电路，其中，还包括：第二电容；
    所述第二电容的第一端与所述第二节点连接，所述第二电容的第二端与所述第二恒压端连接。
  8. 根据权利要求1-7中任一所述的像素电路，其中，所述信号供给端与第一工作电压端连接，所述第一工作电压端通过所述信号供给端向所述开关子电路提供第一工作电压。
  9. 根据权利要求1-7中任一所述的像素电路，其中，还包括：驱动电流供给电路；
    所述驱动电流供给电路与所述信号供给端连接，所述驱动电流供给电路配置为通过所述信号供给端向所述开关子电路提供驱动电流。
  10. 根据权利要求9所述的像素电路，其中，所述驱动电流供给电路包括：第二重置子电路、第二数据写入子电路、阈值补偿子电路、第二输出控制子电路和驱动晶体管，所述驱动晶体管的第二极、所述阈值补偿子电路和所述第二输出控制子电路连接于第四节点，所述驱动晶体管的控制极、所述阈值补偿子电路和所述第二重置子电路连接于第五节点，所述驱动晶体管的第一极、所述第二数据写入子电路和所述第二输出控制子电路连接于第六节点；
    所述第二重置子电路，配置为响应于所述重置信号线的信号的控制， 将参考电压写入至所述第五节点；
    所述第二数据写入子电路，配置为响应于所述栅线的信号的控制，将第二数据电压写入至所述第六节点；
    所述阈值补偿子电路，配置为响应于所述栅线的信号的控制，对所述驱动晶体管的阈值电压进行补偿；
    所述第二输出控制子电路，配置为响应于所述控制信号线的信号的控制，将第一工作电压写入至所述第六节点，以及将所述驱动晶体管所输出的驱动电流提供给所述信号供给端；
    所述驱动晶体管，配置为在所述第五节点处电压和所述第六节点处电压的控制下输出相应的驱动电流。
  11. 根据权利要求10所述的像素电路，其中，所述第二重置子电路包括：第八晶体管；
    所述第八晶体管的控制极与所述重置信号线连接，所述第八晶体管的第一极与所述参考电压端连接，所述第八晶体管的第二极与所述第五节点连接。
  12. 根据权利要求10所述的像素电路，其中，所述第二数据写入子电路包括：第九晶体管；
    所述第九晶体管的控制极与所述栅线连接，所述第九晶体管的第一极与第二数据线连接，所述第九晶体管的第二极与所述第六节点连接。
  13. 根据权利要求10所述的像素电路，其中，所述阈值补偿子电路包括：第十晶体管；
    所述第十晶体管的控制极与所述栅线连接，所述第十晶体管的第一极与所述第四节点连接，所述第十晶体管的第二极与所述第五节点连接。
  14. 根据权利要求10所述的像素电路，其中，所述第二输出控制子电路包括：第十一晶体管和第十二晶体管；
    所述第十一晶体管控制极与所述控制信号线连接，所述第十一晶体管的第一极与第一工作电压端连接，所述第十一晶体管的第二极与所述第六节点连接；
    所述第十二晶体管控制极与所述控制信号线连接，所述第十二晶体管的第一极与所述第四节点连接，所述第十二晶体管的第二极与所述信号供给端连接。
  15. 根据权利要求10所述的像素电路，其中，还包括：第三电容；
    所述第三电容的第一端与所述第五节点连接，所述第三电容的第二端与所述第三恒压端连接。
  16. 根据权利要求1-15中任一所述的像素电路，所述像素电路中的全部晶体管均为N型晶体管；
    或者，所述像素电路中的全部晶体管均为P型晶体管。
  17. 一种显示装置，其中，包括：包括显示基板，所述显示基板包括多个亚像素，至少一个所述亚像素内设置有如权利要求1-16中任一所述的像素电路和待驱动元件，所述像素电路配置为向所述待驱动元件提供驱动信号。
  18. 根据权利要求17所述的显示装置，其中，所述待驱动元件包括：LED或Micro-LED。
  19. 一种像素电路的驱动方法，其中，用于驱动如权利要求1-16中任一所述的像素电路，所述驱动方法包括：
    将重置信号加载至所述重置信号线，将参考电压加载至参考电压端，将初始化电压加载至初始化电压端，以使得所述第一重置子电路响应于所述重置信号控制将所述参考电压和所述初始化电压分别写入至所述第一节点和所述第二节点；
    将栅扫描信号加载至所述栅线，将第一数据电压加载至第一数据线，以使得所述第一数据写入子电路响应于所述栅扫描信号控制将所述第一数据电压写入至所述第二节点；
    将控制信号加载至控制信号线，以使得第一输出控制子电路响应于所述控制信号的控制将所述充放电子电路与充放电端之间形成通路，且将所述第一节点处电压提供给所述开关子电路，所述充放电子电路响应于所述第一数据电压的控制对所述第一节点进行充电处理或放电处理，所述开关子电路响应于所述第一节点处电压的控制来控制所述信号供给端与所述待驱动元件之间的通断。
  20. 根据权利要求19所述的驱动方法，其中，所述像素电路包括驱动电流供给电路，所述驱动电流供给电路包括：第二重置子电路、第二数据写入子电路、阈值补偿子电路、第二输出控制子电路和驱动晶体管；
    在将重置信号加载至所述重置信号线，将参考电压加载至参考电压端时，所述第二重置子电路响应于所述重置信号控制将所述参考电压写入至所述第五节点；
    在将栅扫描信号加载至所述栅线的同时，还包括：将第二数据电压加载至第二数据线，以使得所述第二数据写入子电路将所述第二数据电压写入至所述第六节点，所述阈值补偿子电路响应于所述栅线的控制对所述驱动晶体管的阈值电压进行补偿；
    在将控制信号加载至所述控制信号线的同时，还包括：将第一工作电压加载至所述第一工作电压端，以使得所述第二输出控制子电路响应于所述控制信号的控制将所述第一工作电压写入至所述第六节点，且将所述驱动晶体管所输出的驱动电流提供给所述信号供给端。
PCT/CN2020/078982 2020-03-12 2020-03-12 像素电路及其驱动方法和显示装置 WO2021179247A1 (zh)

Priority Applications (3)

Application Number Priority Date Filing Date Title
CN202080000258.5A CN113966528B (zh) 2020-03-12 2020-03-12 像素电路及其驱动方法和显示装置
PCT/CN2020/078982 WO2021179247A1 (zh) 2020-03-12 2020-03-12 像素电路及其驱动方法和显示装置
US17/265,246 US11455947B2 (en) 2020-03-12 2020-03-12 Pixel circuit, driving method thereof and display device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2020/078982 WO2021179247A1 (zh) 2020-03-12 2020-03-12 像素电路及其驱动方法和显示装置

Publications (1)

Publication Number Publication Date
WO2021179247A1 true WO2021179247A1 (zh) 2021-09-16

Family

ID=77671140

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2020/078982 WO2021179247A1 (zh) 2020-03-12 2020-03-12 像素电路及其驱动方法和显示装置

Country Status (3)

Country Link
US (1) US11455947B2 (zh)
CN (1) CN113966528B (zh)
WO (1) WO2021179247A1 (zh)

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110164016A1 (en) * 2010-01-05 2011-07-07 Chul-Kyu Kang Pixel circuit, organic light emitting display, and driving method thereof
US20120139901A1 (en) * 2010-12-06 2012-06-07 Young-In Hwang Pixel, stereopsis display device, and driving method thereof
CN103871356A (zh) * 2012-12-13 2014-06-18 三星显示有限公司 像素和使用该像素的有机发光显示器
CN103985350A (zh) * 2014-04-29 2014-08-13 上海天马有机发光显示技术有限公司 一种像素电路、显示面板、显示装置和驱动方法
CN104318898A (zh) * 2014-11-11 2015-01-28 京东方科技集团股份有限公司 像素电路、驱动方法和显示装置
CN104715718A (zh) * 2013-12-11 2015-06-17 乐金显示有限公司 显示装置的像素电路、有机发光显示装置及其驱动方法
CN105448234A (zh) * 2014-09-01 2016-03-30 昆山工研院新型平板显示技术中心有限公司 像素电路及其驱动方法和有源矩阵有机发光显示器

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102072795B1 (ko) * 2013-08-12 2020-02-04 삼성디스플레이 주식회사 유기 전계 발광 표시 장치 및 이의 구동 방법
CN105609049B (zh) * 2015-12-31 2017-07-21 京东方科技集团股份有限公司 显示驱动电路、阵列基板、电路驱动方法和显示装置
CN106910468B (zh) * 2017-04-28 2019-05-10 上海天马有机发光显示技术有限公司 显示面板、显示装置及像素电路的驱动方法
KR102538488B1 (ko) * 2018-10-04 2023-06-01 삼성전자주식회사 디스플레이 패널 및 디스플레이 패널의 구동 방법
CN109256088B (zh) * 2018-10-31 2021-10-01 京东方科技集团股份有限公司 像素电路、显示面板、显示装置和像素驱动方法
KR102564366B1 (ko) * 2018-12-31 2023-08-04 엘지디스플레이 주식회사 표시 장치

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110164016A1 (en) * 2010-01-05 2011-07-07 Chul-Kyu Kang Pixel circuit, organic light emitting display, and driving method thereof
US20120139901A1 (en) * 2010-12-06 2012-06-07 Young-In Hwang Pixel, stereopsis display device, and driving method thereof
CN103871356A (zh) * 2012-12-13 2014-06-18 三星显示有限公司 像素和使用该像素的有机发光显示器
CN104715718A (zh) * 2013-12-11 2015-06-17 乐金显示有限公司 显示装置的像素电路、有机发光显示装置及其驱动方法
CN103985350A (zh) * 2014-04-29 2014-08-13 上海天马有机发光显示技术有限公司 一种像素电路、显示面板、显示装置和驱动方法
CN105448234A (zh) * 2014-09-01 2016-03-30 昆山工研院新型平板显示技术中心有限公司 像素电路及其驱动方法和有源矩阵有机发光显示器
CN104318898A (zh) * 2014-11-11 2015-01-28 京东方科技集团股份有限公司 像素电路、驱动方法和显示装置

Also Published As

Publication number Publication date
US20220114948A1 (en) 2022-04-14
CN113966528A (zh) 2022-01-21
US11455947B2 (en) 2022-09-27
CN113966528B (zh) 2024-03-19

Similar Documents

Publication Publication Date Title
WO2021043102A1 (zh) 驱动电路及其驱动方法、显示装置
US10978002B2 (en) Pixel circuit and driving method thereof, and display panel
WO2020186933A1 (zh) 像素电路、其驱动方法、电致发光显示面板及显示装置
US9269304B2 (en) Pixel circuit for organic light emitting display and driving method thereof, organic light emitting display
WO2020052287A1 (zh) 像素电路及其驱动方法、显示装置
WO2020001027A1 (zh) 像素驱动电路及方法、显示装置
CN113192460A (zh) 一种显示面板和显示装置
WO2019029278A1 (zh) 像素单元电路、像素电路、驱动方法和显示装置
WO2021184192A1 (zh) 像素电路及其驱动方法和显示装置
CN111223443B (zh) 像素电路及其驱动方法、显示基板、显示装置
WO2019109673A1 (zh) 像素电路及其驱动方法、显示面板和显示设备
CN105161051A (zh) 像素电路及其驱动方法、阵列基板、显示面板及显示装置
CN106960656B (zh) 一种有机发光显示面板及其显示方法
CN111354308A (zh) 一种像素驱动电路、有机发光显示面板及显示装置
CN106297663B (zh) 一种像素电路、其驱动方法及相关装置
WO2022022146A1 (zh) 像素电路及其驱动方法、显示基板和显示装置
CN106782321A (zh) 一种像素电路、其驱动方法、显示面板及显示装置
US9646536B2 (en) Pixel circuit for organic light emitting display and driving method thereof, organic light emitting display
CN110164375A (zh) 像素补偿电路、驱动方法、电致发光显示面板及显示装置
US11501713B2 (en) Pixel circuit, driving method thereof and display device
CN113284462A (zh) 像素补偿电路、方法及显示面板
WO2019019622A1 (zh) 像素电路及其驱动方法、显示面板和显示装置
CN107103882A (zh) 一种像素电路、其驱动方法及显示面板
US11302245B2 (en) Pixel circuit, driving method thereof, and display device
WO2021179247A1 (zh) 像素电路及其驱动方法和显示装置

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 20923771

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 20923771

Country of ref document: EP

Kind code of ref document: A1

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205A DATED 08.05.2023)

122 Ep: pct application non-entry in european phase

Ref document number: 20923771

Country of ref document: EP

Kind code of ref document: A1