WO2021175294A1 - 超级结的制造方法及其超级结肖特基二极管 - Google Patents

超级结的制造方法及其超级结肖特基二极管 Download PDF

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WO2021175294A1
WO2021175294A1 PCT/CN2021/079118 CN2021079118W WO2021175294A1 WO 2021175294 A1 WO2021175294 A1 WO 2021175294A1 CN 2021079118 W CN2021079118 W CN 2021079118W WO 2021175294 A1 WO2021175294 A1 WO 2021175294A1
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concentration
energy
ions
conductivity type
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PCT/CN2021/079118
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French (fr)
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陈伟
仲雪倩
黄海涛
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上海瞻芯电子科技有限公司
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Priority to US17/909,657 priority Critical patent/US20230123112A1/en
Priority to EP21764865.8A priority patent/EP4095927A4/en
Priority to JP2022551785A priority patent/JP2023516011A/ja
Publication of WO2021175294A1 publication Critical patent/WO2021175294A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/1608—Silicon carbide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/0445—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide
    • H01L21/0455—Making n or p doped regions or layers, e.g. using diffusion
    • H01L21/046—Making n or p doped regions or layers, e.g. using diffusion using ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/0445—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide
    • H01L21/0455—Making n or p doped regions or layers, e.g. using diffusion
    • H01L21/046—Making n or p doped regions or layers, e.g. using diffusion using ion implantation
    • H01L21/047—Making n or p doped regions or layers, e.g. using diffusion using ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/167—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table further characterised by the doping material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
    • H01L29/6606—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/872—Schottky diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/04—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
    • H01L29/045—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes by their particular orientation of crystalline planes

Definitions

  • This application relates to the field of semiconductors, and in particular to a method for manufacturing a super junction and a super junction Schottky diode.
  • Wide bandgap power semiconductor devices are increasingly widely used in various power systems because of their superior performance such as larger bandgap width, higher critical breakdown field strength, and stronger thermal conductivity.
  • silicon carbide power devices especially silicon carbide diodes
  • high cost has become an obstacle to its further expansion of application scale.
  • One of the key ways to reduce the cost is to continuously reduce the characteristic on-resistance, thereby improving the current capacity per unit area, and ultimately reducing the chip area.
  • the super junction technology is the most effective means to achieve the above path.
  • manufacturing super junction structures in silicon carbide materials has considerable technical difficulties.
  • the multiple epitaxial technology, trench etching and epitaxial backfilling technology which are widely used in silicon-based superjunction devices, are difficult to directly apply to the preparation of silicon carbide superjunction devices due to high process costs and difficult process control.
  • the present invention proposes a method for manufacturing a super junction and a super junction Schottky diode.
  • the manufacturing method can greatly reduce the difficulty of preparing the wide-bandgap semiconductor super junction power semiconductor device, and the process consistency is excellent, and the manufacturing cost is reduced.
  • an embodiment of the present application provides a method for manufacturing a super junction, and the method includes:
  • An epitaxial layer is formed on the surface of the wide bandgap semiconductor substrate through an epitaxial growth process
  • the second doping ions are implanted into at least a part of the first conductivity type region along the predetermined crystal orientation of the wide-gap semiconductor to form a second conductivity type region, wherein the second doping ions and The conductivity types of the first doped ions are different;
  • the predetermined crystal orientation is a crystal orientation that enables channel effect to occur when dopant ions are implanted along the predetermined crystal orientation.
  • the wide-gap semiconductor is silicon carbide
  • the predetermined crystal orientation of the wide-gap semiconductor is the C-axis direction of the silicon carbide
  • the silicon carbide includes 4H-SiC or 6H-SiC.
  • the injecting first dopant ions into at least a part of the epitaxial layer along the crystal direction of the wide band gap semiconductor includes:
  • the first dopant ions are injected into at least a part of the epitaxial layer along the crystal direction of the wide band gap semiconductor at a first concentration, a first energy, a second concentration, and a second energy, respectively.
  • the first concentration is 1E13 to 3E14 atoms per square centimeter
  • the first energy is 500 kev to 2000 kev
  • the second concentration is 1E12 to 5E13 atoms per square centimeter
  • the second energy is 50kev to 300kev.
  • injecting second dopant ions into at least a part of the region of the first conductivity type region along the crystal direction of the wide band gap semiconductor includes:
  • the second doping ions are injected into at least a part of the epitaxial layer along the crystal direction of the wide band gap semiconductor at a third concentration, a third energy, a fourth concentration, and a fourth energy, respectively.
  • the third concentration is 5E13 to 3E14 atoms per square centimeter, the third energy is 500 kev to 2000 kev; the fourth concentration is 5E12 to 5E13 atoms per square centimeter, The fourth energy is 50kev to 300kev.
  • the first doping ions include nitrogen ions or phosphorus ions.
  • the second doping ions include aluminum ions or boron ions.
  • an embodiment of the present application provides a super junction Schottky diode, including:
  • the first conductivity type region is formed by injecting first dopant ions into at least a part of the epitaxial layer along the predetermined crystal direction of the wide band gap semiconductor;
  • the second conductivity type region is formed by implanting at least a part of the first conductivity type region with second dopant ions along the predetermined crystal direction of the wide band gap semiconductor;
  • a metal layer disposed on at least a part of the surface of the first conductivity type region away from the substrate, so that the metal layer and the first conductivity type region form a Schottky junction;
  • the predetermined crystal orientation is a crystal orientation that enables channel effect to occur when dopant ions are implanted along the predetermined crystal orientation.
  • it further includes a second conductivity type implantation region, formed by implanting a part of the second conductivity type region along the normal direction of the wide band gap semiconductor by second doping ions.
  • the wide band gap semiconductor is silicon carbide.
  • the silicon carbide includes 4H-SiC or 6H-SiC.
  • the first ions include nitrogen ions or phosphorus ions, and the nitrogen ions or phosphorus ions have a first concentration, a first energy and a second concentration, and a second energy along the
  • the silicon carbide semiconductor is implanted into at least a part of the epitaxial layer in the C-axis direction.
  • the second doping ions include aluminum ions or boron ions, and the aluminum ions have a third concentration, a third energy, a fourth concentration, and a fourth energy along the
  • the silicon carbide semiconductor is implanted in at least a part of the first conductivity type region in the C axis direction.
  • the second doping ions include aluminum ions or boron ions, and the aluminum ions are along the fifth concentration, fifth energy, sixth concentration, and sixth energy, respectively.
  • the normal direction of the silicon carbide semiconductor is implanted into a partial area of the second conductivity type region.
  • Fig. 1 shows a flow chart of a method for manufacturing a super junction according to some embodiments of the present application
  • Figures 2a-2g show schematic diagrams of a super junction Schottky diode corresponding to one or more steps shown in Figure 1 according to some embodiments of the present application;
  • Fig. 3 shows a schematic diagram of the crystal orientation of a silicon carbide semiconductor according to some embodiments of the present application.
  • Illustrative embodiments of the present application include, but are not limited to, a method of manufacturing a super junction and a super junction Schottky diode.
  • FIG. 1 schematically shows a schematic flow chart of a method for manufacturing a super junction. Specifically, as shown in FIG. 1, the method includes:
  • An epitaxial layer (101) is formed on the surface of a wide-gap semiconductor substrate through an epitaxial growth process; the wide-gap semiconductor includes but is not limited to silicon carbide, gallium nitride, aluminum nitride, or diamond, etc. Do restrictions.
  • the epitaxial growth process refers to the growth of a single crystal layer with the same crystal orientation as the wide bandgap semiconductor substrate through methods such as vapor phase epitaxy, liquid phase epitaxy, or molecular beam epitaxy along the original crystal orientation of the wide bandgap semiconductor substrate.
  • the conductivity type of the epitaxial layer may be the same as or different from the conductivity type of the wide-gap semiconductor substrate, which is not limited here.
  • the first doped ions are injected into at least a part of the epitaxial layer along the predetermined crystal orientation of the wide-gap semiconductor to form the first conductivity type region (102); wherein the predetermined crystal orientation is such that the first doped ions
  • the channel effect is implanted along the preset crystal direction.
  • the channel effect refers to the ion implantation into the solid, which collides with the atoms of the solid. If the solid is amorphous, then the atoms that make up the solid are in space. It is randomly distributed, so the collision between the ion and the target atom is random, and the size of the collision parameter P is a random parameter. If the solid is a crystal, the atoms are regularly arranged in space.
  • the ions When the ions are injected along the main crystal axis of the crystal, they may collide similarly with the lattice atoms (collision parameter P is approximately equal), and the collisions are related to each other. In the second collision, the ion movement deflection is very small, and the ion can penetrate a deeper distance into the solid after passing near the same row of atoms in the lattice.
  • the first dopant ions can have a channel effect and penetrate a deeper distance along the predetermined crystal direction.
  • the wide bandgap semiconductor can be silicon carbide, and the crystal orientation of the wide bandgap semiconductor can be selected as the C-axis direction of the silicon carbide. As shown in FIG. 3, the normal line of the 4H-SiC wafer is perpendicular to the 4H -The main plane of the SiC wafer, and the angle between the C axis and the normal of the 4H-SiC wafer is 4 degrees.
  • the conductivity type of the second doping ion is different from that of the first doping ion.
  • the first doping ion is an N-type ion (nitrogen ion or phosphorus ion)
  • the second doping ion is a P-type ion (aluminum ion). Or boron ion), there is no restriction here.
  • the super junction formed by the first conductivity type region and the second conductivity type region can be applied to various power semiconductor devices, so that the characteristic on-resistance of the device is reduced, thereby reducing the chip area and reducing the wide bandgap power semiconductor device Cost, while optimizing device performance.
  • FIGS. 2a-2g A schematic diagram of a super-junction Schottky diode corresponding to one or more steps in the flow chart of the super-junction manufacturing method shown in FIG. 1 will be introduced below in conjunction with FIGS. 2a-2g.
  • the wide band gap semiconductor substrate is a silicon carbide material
  • the first conductivity type is N-type
  • the second conductivity type is P-type
  • the first conductivity type region is an N-type implanted region
  • the second conductivity type region is Taking the P-type pillar, the first doping ion being nitrogen ion or phosphorous ion, and the second doping ion being aluminum ion or boron ion as examples, the manufacturing process of the super junction Schottky diode of the present application will be described in detail.
  • the manufacturing process of the super junction Schottky diode of the present application will be described in detail.
  • an epitaxial layer 202 is grown.
  • a lightly doped N-type epitaxial layer 202 is grown on a heavily doped N-type silicon carbide substrate 201 through an epitaxial growth process. It can be understood that the difference between heavily doped and lightly doped is that the dopant ion concentration of heavily doped is higher than that of lightly doped.
  • the N-type doping concentration of the epitaxial layer 202 is between 1E14 and 5E16 atoms per square centimeter, and the thickness of the epitaxial layer 202 is between 1 um and 200 um. It can be understood that the thickness and doping concentration of the N-type epitaxial layer can be determined according to the withstand voltage rating of the device.
  • the N-type doping ions include but are not limited to nitrogen ions or phosphorus ions, which are not limited here.
  • an inorganic thin film material formed on the surface of the N-type epitaxial layer 202 by CVD can be used as the hard mask layer 203.
  • the composition of the inorganic thin film material includes, but is not limited to, silicon dioxide, silicon nitride, or nickel.
  • photoresist can be coated on the surface of the N-type epitaxial layer 202 as a mask. ⁇ 203 ⁇ Film 203. Then, a pattern is formed through a photolithography mask and an etching process to determine the region where the N-type implantation region is to be formed. It can be understood that the formation of the mask layer 203 is determined by an inorganic thin film material generated by CVD or a photoresist coating, which is determined by the energy value of ion implantation, which is not limited here.
  • Ion implantation forms the N-type implanted region 204.
  • nitrogen ions or phosphorous ions are used with a first energy of 500kev to 2000kev and a first concentration of 1E13 to 3E14 atoms per square centimeter.
  • the second energy is 50kev to 300kev, the second concentration is 1E12 to 5E13 atoms per square centimeter, along the C-axis direction of silicon carbide (as shown in Figure 3, for 4H-SiC, the C-axis direction and 4H-SiC crystal The angle between the normal direction of the circle is 4 degrees.)
  • Part of the N-type epitaxial layer 202 is implanted to form an N-type implanted region 204.
  • nitrogen ions or phosphorous ions can be implanted to a sufficiently deep depth to obtain a sufficiently deep N-type implantation region 204, which greatly reduces the number of ion implantation and implantation energy, and reduces the manufacturing cost.
  • the depth of the N-type implanted region 204 in FIG. 2c is less than the depth of the N-type epitaxial layer 202, but in other embodiments of the present application, the depth of the N-type implanted region 204 may be equal to that of the N-type epitaxial layer 202.
  • the depth that is, the entire N-type outer layer 202 is completely implanted with dopant ions to form an N-type implanted region, which is not limited here.
  • an inorganic thin film material formed on the surface of the N-type implanted region 204 by CVD can be used as the hard mask layer 205.
  • the composition of the inorganic thin film material includes, but is not limited to, silicon dioxide, silicon nitride, or nickel.
  • photoresist can be coated on the surface of the N-type implanted region 204 as a mask. ⁇ 205 ⁇ Film 205. Then, a pattern is formed through a photolithography mask and an etching process to determine the region where the P-type pillar is to be formed. It can be understood that the formation of the mask layer 205 is determined by the inorganic thin film material generated by CVD or the photoresist coating, which is determined by the energy value of the ion implantation, which is not limited here.
  • Ion implantation forms the P-type pillar 206.
  • aluminum ions such as Al-27
  • a third energy of 500kev to 2000kev
  • the fourth energy is 50kev to 300kev
  • the fourth concentration is 5E12 to 5E13 atoms per square centimeter
  • a part of the N-type implantation region 204 is injected along the C-axis direction of the silicon carbide to form a P-type pillar 206
  • P-type The pillar 206 and the area of the N-type implanted region 204 that are not doped with aluminum ions form a super junction.
  • aluminum ions for example, Al-27
  • Al-27 can be implanted to a sufficiently deep depth to obtain a sufficiently deep P-type pillar 206, which greatly reduces the number of ion implantation and implantation energy, and reduces the manufacturing cost.
  • Ion implantation forms the P + implantation region 207.
  • aluminum ions such as Al-27 are used at a fifth energy of 80kev to 200kev, and a fifth concentration of 5E13 to 3E14.
  • the sixth concentration is 5E13 to 5E14 atoms per square centimeter, along the normal direction of the silicon carbide wafer (as shown in Figure 3, the normal direction is perpendicular to the silicon carbide crystal
  • the main plane of the circle is injected into the P-type pillar 206 to form a P + injection region 207, where the P + injection region 207 can shield the surface electric field of the power semiconductor device, that is, reduce the surface electric field strength, reduce the reverse leakage current, and then increase the reflection
  • the reverse breakdown voltage of the super-junction Schottky diode is larger, which can be used in the high-voltage field.
  • High temperature annealing Expose the power semiconductor device of FIG. 2f to a high temperature for a period of time, and then slowly cool it down. All the above implanted N-type and P-type dopant ions can be activated by high-temperature annealing.
  • the electrode 208 and the surface passivation layer 209 are formed.
  • the power semiconductor device can be subjected to the conventional ohmic contact process, Schottky contact process, and metallization process to form the electrode 208, where the electrode 208 and N
  • the type implantation region 204 forms a Schottky junction.
  • the Schottky junction is a simple metal-semiconductor contact interface, which is similar to a PN junction and has nonlinear impedance characteristics.
  • passivation treatment is performed on the surface of the electrode 208 to form a passivation layer 209 to improve the stability and reliability of the electrical performance of the super junction Schottky diode.
  • the implantation depth can be selected according to the required implantation depth. Times, corresponding energy and concentration.
  • ion implantation involved in the above-mentioned implantation from the C-axis direction of the 4H-SiC wafer is exemplary and not restrictive. In other embodiments of the present application, ion implantation can be along other tolerances.
  • the crystal phase with semiconductor is implanted into the epitaxial layer to utilize the channel effect and reduce the implantation energy to achieve a deeper implantation depth.
  • the power semiconductor device super junction manufacturing method described above in conjunction with the embodiments of the present application can be applied to other power semiconductor device structures other than Schottky diodes, such as JFET (Junction Field-Effect Transistor, junction type). Field-effect transistors), MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors, metal oxide semiconductor field-effect transistors) are not limited here.
  • each unit/device mentioned in each device embodiment of this application is a logical unit/device.
  • a logical unit/device can be a physical unit/device or a physical unit/device.
  • a part of the device can also be realized by a combination of multiple physical units/devices.
  • the physical realization of these logical units/devices is not the most important.
  • the combination of the functions implemented by these logical units/devices is the solution to this application.
  • the above-mentioned equipment embodiments of this application do not introduce units/devices that are not closely related to solving the technical problems proposed by this application. This does not mean that the above-mentioned equipment embodiments do not exist. Other units/devices.

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Abstract

本申请涉及半导体领域，公开了一种超级结的制造方法及其超级结肖特基二极管。本申请中超级结的制造方法包括：通过外延生长工艺在宽禁带半导体衬底表面上形成外延层；将第一掺杂离子沿宽禁带半导体的预设晶向注入外延层的至少一部分区域，形成第一导电类型区；将第二掺杂离子沿宽禁带半导体的预设晶向注入第一导电类型区的至少一部分区域，形成第二导电类型区，其中，第二掺杂离子与第一掺杂离子的导电类型不同；预设晶向为使得掺杂离子沿预设晶向注入会发生沟道效应的晶向。

Description

超级结的制造方法及其超级结肖特基二极管
本申请要求于2020年03月06日提交中国专利局、申请号为202010150476.9、申请名称为“超级结的制造方法及其超级结肖特基二极管”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及半导体领域，特别涉及一种超级结的制造方法及其超级结肖特基二极管。
背景技术
宽禁带功率半导体器件因为其更大的禁带宽度、更高的临界击穿场强、更强的热导率等优异性能，被日益广泛应用到各类电源系统内。但是随着常规碳化硅功率器件(尤其是碳化硅二极管)技术上的逐步成熟，高成本已经成为其进一步扩大应用规模的障碍。降低成本的关键路径之一在于不断降低特征导通电阻，从而提升单位面积通流能力，最终减小芯片面积。而超级结技术是实现上述路径的最有效手段。但是众所周知，在碳化硅材料中制造超级结结构具有相当大的技术难度。广泛应用于硅基超结器件的多次外延技术、沟槽刻蚀加外延回填技术等，都因为制程成本高、工艺控制困难等原因，难以直接应用于碳化硅超级结器件的制备。
发明内容
为了解决现有技术中的上述问题，本发明提出了一种超级结的制造方法及其超级结肖特基二极管。该制造方法能够大幅度降低宽禁带半导体超级结功率半导体器件的制备难度，并且工艺一致性优，制造成本降低。
第一方面，本申请实施例提供了一种超级结的制造方法，所述方法包括；
通过外延生长工艺在宽禁带半导体衬底表面上形成外延层；
将第一掺杂离子沿所述宽禁带半导体的预设晶向注入所述外延层的至少一部分区域， 形成第一导电类型区；
将第二掺杂离子沿所述宽禁带半导体的所述预设晶向注入所述第一导电类型区的至少一部分区域，形成第二导电类型区，其中，所述第二掺杂离子与所述第一掺杂离子的导电类型不同；
所述预设晶向为使得掺杂离子沿所述预设晶向注入会发生沟道效应的晶向。
在上述第一方面的一种可能实现中，所述宽禁带半导体为碳化硅，所述宽禁带半导体的预设晶向为所述碳化硅的C轴方向。
在上述第一方面的一种可能实现中，所述碳化硅包括4H-SiC或6H-SiC。
在上述第一方面的一种可能实现中，所述将第一掺杂离子沿所述宽禁带半导体的晶向注入所述外延层的至少一部分区域，包括：
将所述第一掺杂离子分别以第一浓度、第一能量及第二浓度、第二能量沿所述宽禁带半导体的晶向注入所述外延层的至少一部分区域。
在上述第一方面的一种可能实现中，所述第一浓度为1E13至3E14原子数每平方厘米，所述第一能量为500kev至2000kev；第二浓度为1E12至5E13原子数每平方厘米，所述第二能量为50kev至300kev。
在上述第一方面的一种可能实现中，将第二掺杂离子沿所述宽禁带半导体的晶向注入所述第一导电类型区的至少一部分区域，包括：
将所述第二掺杂离子分别以第三浓度、第三能量及第四浓度、第四能量沿所述宽禁带半导体的晶向注入所述外延层的至少一部分区域。
在上述第一方面的一种可能实现中，所述第三浓度为5E13至3E14原子数每平方厘米，所述第三能量为500kev至2000kev；第四浓度为5E12至5E13原子数每平方厘米，所述第四能量为50kev至300kev。
在上述第一方面的一种可能实现中，所述第一掺杂离子包括氮离子或磷离子。
在上述第一方面的一种可能实现中，所述第二掺杂离子包括铝离子或硼离子。
第二方面，本申请实施例提供了一种超级结肖特基二极管，包括：
通过外延生长工艺在宽禁带半导体衬底表面上形成的外延层；
第一导电类型区，通过第一掺杂离子沿所述宽禁带半导体的预设晶向注入所述外延层的至少一部分区域形成；
第二导电类型区，通过第二掺杂离子沿所述宽禁带半导体的所述预设晶向注入所述第 一导电类型区的至少一部分区域形成；
金属层，设置在所述第一导电类型区远离所述衬底的至少部分表面上，以使得所述金属层与所述第一导电类型区形成肖特基结；
所述预设晶向为使得掺杂离子沿所述预设晶向注入会发生沟道效应的晶向。
在上述第二方面的一种可能实现中，还包括第二导电类型注入区，通过第二掺杂离子沿所述宽禁带半导体的法线方向注入所述第二导电类型区部分区域形成。
在上述第二方面的一种可能实现中，所述宽禁带半导体为碳化硅。
在上述第二方面的一种可能实现中，所述碳化硅包括4H-SiC或6H-SiC。
在上述第二方面的一种可能实现中，所述第一离子包括氮离子或磷离子，所述氮离子或磷离子分别以第一浓度、第一能量及第二浓度、第二能量沿所述碳化硅半导体的C轴方向注入所述外延层的至少一部分区域。
在上述第二方面的一种可能实现中，所述第二掺杂离子包括铝离子或硼离子，所述铝离子分别以第三浓度、第三能量及第四浓度、第四能量沿所述碳化硅半导体的C轴方向注入所述第一导电类型区的至少一部分区域。
在上述第二方面的一种可能实现中，所述第二掺杂离子包括铝离子或硼离子，所述铝离子分别以第五浓度、第五能量及第六浓度、第六能量沿所述碳化硅半导体的法线方向注入所述第二导电类型区的部分区域。
附图说明
图1根据本申请的一些实施例，示出了一种超级结的制造方法流程图；
图2a-2g根据本申请的一些实施例，示出了一种与图1所示的一个或多个步骤相应的超级结肖特基二极管的结构示意图；
图3根据本申请的一些实施例，示出了一种碳化硅半导体的晶向示意图。
具体实施例
本申请的说明性实施例包括但不限于超级结的制造方法及其超级结肖特基二极管。
下面将结合附图对本申请的实施例作进一步地详细描述。
根据本申请的一些实施例，图1示意性示出了一种超级结的制造方法的流程示意图，具体地，如图1所示，方法包括：
(1)通过外延生长工艺在宽禁带半导体衬底表面上形成外延层(101)；其中，宽禁带半导体包括但不限于碳化硅、氮化镓、氮化铝或金刚石等，在此不做限制。外延生长工艺是指沿着宽禁带半导体衬底原来的晶向，通过气相外延、液相外延或者分子束外延等方法，生长一层与宽禁带半导体衬底晶向相同的单晶层。在本申请的实施例中，外延层的导电类型可以与宽禁带半导体衬底的导电类型相同，也可以不同，在此不做限制。
(2)将第一掺杂离子沿宽禁带半导体的预设晶向注入外延层的至少一部分区域，形成第一导电类型区(102)；其中，预设晶向为使得第一掺杂离子沿所述预设晶向注入会发生沟道效应的晶向，沟道效应是指离子注入固体中，它与固体的原子发生碰撞，如果固体是无定形的，那么，组成固体的原子在空间是无规则分布的，因而离子与靶原子的碰撞是随机的，碰撞参数P的大小是个随机参数。如果固体是晶体，则原子在空间规则地排列着，离子沿晶体的主晶轴方向注入时，它们可能与晶格原子发生相类似的碰撞(碰撞参数P近似相等)，各个碰撞互相有关，每次碰撞时，离子运动偏转很小，离子经过晶格同一排原子附近，可以穿透入固体中较深的距离。在本申请的实施例中，由于宽禁带半导体衬底为单晶，内部原子规则排列，因此，第一掺杂离子沿预设晶向可以发生沟道效应穿透较深的距离。
第一掺杂离子沿着宽禁带半导体的晶向注入时，由于沟道效应，第一掺杂离子在外延层的射程比随机方向或沿晶圆的法线方向注入时更远，具有更强的穿透力，从而降低离子注入的能量和制造成本。在一些实施例中，宽禁带半导体可以为碳化硅，则宽禁带半导体晶向的可以选取为碳化硅的C轴方向，如图3所示，4H-SiC晶圆的法线垂直于4H-SiC晶圆的主平面，而C轴与4H-SiC晶圆的法线夹角为4度。
(3)将第二掺杂离子沿宽禁带半导体的预设晶向注入第一导电类型区的至少一部分区域，形成第二导电类型区(103)；其中，预设晶向为使得第一掺杂离子沿所述预设晶向注入会发生沟道效应的晶向，第二掺杂离子的注入方向与第一掺杂离子的注入方向相同，使得第二掺杂离子注入到第一导电类型区时充分利用沟道效应，形成更深的第二导电类型区，但所需注入的能量更少。可以理解，第二掺杂离子与第一掺杂离子的导电类型不同， 例如，第一掺杂离子为N型离子(氮离子或磷离子)，第二掺杂离子为P型离子(铝离子或硼离子)，在此不做限制。
通过以上方法，第一导电类型区与第二导电类型区形成的超级结可以应用于各类功率半导体器件，使得器件的特征导通电阻降低，从而减小芯片面积，降低宽禁带功率半导体器件的成本，同时优化器件性能。
下面结合图2a-2g介绍一种与图1所示的超级结制造方法的流程图中一个或多个步骤相对应的超级结肖特基二极管的示意图。图2a-2g中，以宽禁带半导体衬底为碳化硅材料、第一导电类型为N型、第二导电类型为P型、第一导电类型区为N型注入区、第二导电类型区为P型柱、第一掺杂离子为氮离子或磷离子、第二掺杂离子为铝离子或硼离子为例，对本申请的具有超级结肖特基二极管的制造过程进行具体说明。包括：
(1)首先，生长外延层202，参考图2a，在重掺杂的N型碳化硅衬底201上通过外延生长工艺生长轻掺杂的N型外延层202。可以理解，重掺杂与轻掺杂的区别在于重掺杂的掺杂离子浓度比轻掺杂的掺杂离子浓度高。在一些实施例中，外延层202的N型掺杂浓度在1E14至5E16原子数每平方厘米之间，外延层202的厚度在1um至200um之间。可以理解的是N型外延层的厚度和掺杂浓度可以根据器件的耐压额定值确定，N型掺杂离子包括但不限于氮离子或磷离子等，在此不做限制。
(2)形成掩膜层203，参考图2b，在一个实施例中，可以通过CVD(Chemical Vapor Deposition,化学气相沉积)在N型外延层202表面生成的无机薄膜材料作为硬掩膜层203，无机薄膜材料的成分包括但不限于二氧化硅、氮化硅或镍等，在另一个实施例中，离子注入能量在600kev以下时，可以在N型外延层202表面涂覆光刻胶作为掩膜层203。然后通过光刻掩膜和刻蚀工艺形成图案，以确定待形成N型注入区的区域。可以理解的是，掩膜层203的形成通过CVD生成的无机薄膜材料还是涂覆光刻胶由离子注入的能量值确定，在此不做限制。
(3)离子注入形成N型注入区204，参考图2c，在一些实施例中，将氮离子或磷离子以第一能量为500kev至2000kev、第一浓度为1E13至3E14原子数每平方厘米，及第二能量为50kev至300kev、第二浓度为1E12至5E13原子数每平方厘米，沿着碳化硅的C轴方向(如图3所示，对于4H-SiC，C轴方向和4H-SiC晶圆的法线方向的夹角为4度) 注入N型外延层202的部分区域，形成N型注入区204。由于沟道效应，氮离子或磷离子能够注入足够深的深度，获得足够深的N型注入区204，大大降低了离子注入的次数和注入能量，降低了制造成本。
需要说明的是，图2c中N型注入区204的深度小于N型外延层202的深度，但在本申请的其他实施例中，N型注入区204的深度可以等于N型外延层的202的深度，即整个N型外层202被完全注入掺杂离子，形成N型注入区，在此不做限制。
(4)形成掩膜层205，参考图2d，在一个实施例中，可以通过CVD(Chemical Vapor Deposition,化学气相沉积)在N型注入区204表面生成的无机薄膜材料作为硬掩膜层205，无机薄膜材料的成分包括但不限于二氧化硅、氮化硅或镍等，在另一个实施例中，离子注入能量在600kev以下时，可以在N型注入区204表面涂覆光刻胶作为掩膜层205。然后通过光刻掩膜和刻蚀工艺形成图案，以确定待形成P型柱的区域。可以理解的是，掩膜层205的形成通过CVD生成的无机薄膜材料还是涂覆光刻胶由离子注入的能量值确定，在此不做限制。
(5)离子注入形成P型柱206，参考图2e，在一些实施例中，将铝离子(例如Al-27)以第三能量为500kev至2000kev、第三浓度为5E13至3E14原子数每平方厘米，及第四能量为50kev至300kev、第四浓度为5E12至5E13原子数每平方厘米，沿着碳化硅的C轴方向注入N型注入区204的部分区域，形成P型柱206，P型柱206与N型注入区204中未被掺杂铝离子的区域形成超级结。由于沟道效应，铝离子(例如Al-27)能够注入足够深的深度，获得足够深的P型柱206，大大降低了离子注入的次数和注入能量，降低了制造成本。
(6)离子注入形成P +注入区207，参考图2f，在一些实施例中，将铝离子(例如Al-27)以第五能量为80kev至200kev、第五浓度为5E13至3E14原子数每平方厘米，及第六能量为20kev至70kev、第六浓度为5E13至5E14原子数每平方厘米，沿着碳化硅晶圆的法线方向(如图3所示，法线方向垂直于碳化硅晶圆的主平面)注入P型柱206，形成P +注入区207，其中，P +注入区207可以屏蔽功率半导体器件的表面电场，即降低表面电场强度，减小反向漏电流，进而提高反向击穿电压，从而使得超级结肖特基二极管的反向击穿电压较大，能够应用于高压领域。
(7)高温退火，将图2f的功率半导体器件暴露于高温中一段时间，再慢慢冷却，通过高温退火可以激活以上所有注入的N型和P型的掺杂离子。
(8)形成电极208和表面钝化层209，参考图2g，可以对功率半导体器件进行常规的欧姆接触工艺、肖特基接触工艺以及金属化工艺等，形成电极208，其中，电极208与N型注入区204形成肖特基结，可以理解，肖特基结是一种简单的金属与半导体接触的界面，与PN结类似，具有非线性阻抗特性。再在电极208的表面进行钝化处理，形成钝化层209，以提高超级结肖特基二极管的电学性能的稳定性和可靠性。
需要说明的是，以上所有涉及到的离子注入的次数、对应的能量和浓度的数值是示例性的，并非限制性的，在本申请的其他实施例中，可以根据需要注入的深度选择注入的次数、对应的能量和浓度。
需要说明的是，以上所有涉及到的离子注入从4H-SiC晶圆的C轴方向注入是示例性的，并非限制性的，在本申请的其他实施例中，离子注入可以沿着其他宽禁带半导体的晶相注入外延层，以利用沟道效应，降低注入能量实现较深的注入深度。
需要说明的是，上面结合本申请的实施例介绍的功率半导体器件超级结的制造方法可以应用于除肖特基二极管之外的其他功率半导体器件结构，例如JFET(Junction Field-Effect Transistor，结型场效应晶体管)、MOSFET(Metal-Oxide-Semiconductor Field-Effect Transistor，金属氧化物半导体场效应晶体管)，在此不作限制。
在附图中，可以以特定布置和/或顺序示出一些结构或方法特征。然而，应该理解，可能不需要这样的特定布置和/或排序。而是，在一些实施例中，这些特征可以以不同于说明性附图中所示的方式和/或顺序来布置。另外，在特定图中包括结构或方法特征并不意味着暗示在所有实施例中都需要这样的特征，并且在一些实施例中，可以不包括这些特征或者可以与其他特征组合。
需要说明的是，本申请各设备实施例中提到的各单元/装置都是逻辑单元/装置，在物理上，一个逻辑单元/装置可以是一个物理单元/装置，也可以是一个物理单元/装置的一部分，还可以以多个物理单元/装置的组合实现，这些逻辑单元/装置本身的物理实现方式并不是最重要的，这些逻辑单元/装置所实现的功能的组合才是解决本申请所提出的技术问题的关键。此外，为了突出本申请的创新部分，本申请上述各设备实施例并没有将与解决本 申请所提出的技术问题关系不太密切的单元/装置引入，这并不表明上述设备实施例并不存在其它的单元/装置。
需要说明的是，在本专利的示例和说明书中，诸如第一和第二等之类的关系术语仅仅用来将一个实体或者操作与另一个实体或操作区分开来，而不一定要求或者暗示这些实体或操作之间存在任何这种实际的关系或者顺序。而且，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者设备不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者设备所固有的要素。在没有更多限制的情况下，由语句“包括一个”限定的要素，并不排除在包括所述要素的过程、方法、物品或者设备中还存在另外的相同要素。
虽然通过参照本申请的某些优选实施例，已经对本申请进行了图示和描述，但本领域的普通技术人员应该明白，可以在形式上和细节上对其作各种改变，而不偏离本申请的精神和范围。

Claims (16)

  1. 一种超级结的制造方法，其特征在于，包括：
    通过外延生长工艺在宽禁带半导体衬底表面上形成外延层；
    将第一掺杂离子沿所述宽禁带半导体的预设晶向注入所述外延层的至少一部分区域，形成第一导电类型区；
    将第二掺杂离子沿所述宽禁带半导体的所述预设晶向注入所述第一导电类型区的至少一部分区域，形成第二导电类型区，其中，所述第二掺杂离子与所述第一掺杂离子的导电类型不同；
    所述预设晶向为使得掺杂离子沿所述预设晶向注入会发生沟道效应的晶向。
  2. 根据权利要求1所述的方法，其特征在于，所述宽禁带半导体为碳化硅，所述宽禁带半导体的预设晶向为所述碳化硅的C轴方向。
  3. 根据权利要求2所述的方法，其特征在于，所述碳化硅包括4H-SiC或6H-SiC。
  4. 根据权利要求1或2所述的方法，其特征在于，所述将第一掺杂离子沿所述宽禁带半导体的晶向注入所述外延层包括至少一部分区域，包括：
    将所述第一掺杂离子分别以第一浓度、第一能量及第二浓度、第二能量沿所述宽禁带半导体的晶向注入所述外延层至少一部分区域。
  5. 根据权利要求4所述的方法，其特征在于，所述第一浓度为1E13至3E14原子数每平方厘米，所述第一能量为500kev至2000kev；第二浓度为1E12至5E13原子数每平方厘米，所述第二能量为50kev至300kev。
  6. 根据权利要求1或2所述的方法，其特征在于，将第二掺杂离子沿所述宽禁带半导体的晶向注入所述第一导电类型区至少一部分区域，包括：
    将所述第二掺杂离子分别以第三浓度、第三能量及第四浓度、第四能量沿所述宽禁带半导体的晶向注入所述外延层。
  7. 根据权利要求6所述的方法，其特征在于，所述第三浓度为5E13至3E14原子数每平方厘米，所述第三能量为500kev至2000kev；第四浓度为5E12至5E13原子数每平方厘米，所述第四能量为50kev至300kev。
  8. 根据权利要求1所述的方法，其特征在于，所述第一掺杂离子包括氮离子或磷离 子。
  9. 根据权利要求1所述的方法，其特征在于，所述第二掺杂离子包括铝离子或硼离子。
  10. 一种超级结肖特基二极管，其特征在于，包括：
    通过外延生长工艺在宽禁带半导体衬底表面上形成的外延层；
    第一导电类型区，通过第一掺杂离子沿所述宽禁带半导体的预设晶向注入所述外延层的至少一部分区域形成；
    第二导电类型区，通过第二掺杂离子沿所述宽禁带半导体的所述预设晶向注入所述第一导电类型区的至少一部分区域形成；
    金属层，设置在所述第一导电类型区远离所述衬底的至少部分表面上，以使得所述金属层与所述第一导电类型区形成肖特基结；
    所述预设晶向为使得掺杂离子沿所述预设晶向注入会发生沟道效应的晶向。
  11. 根据权利要求10所述的超级结肖特基二极管，其特征在于，还包括第二导电类型注入区，通过第二掺杂离子沿所述宽禁带半导体的法线方向注入所述第二导电类型区部分区域形成。
  12. 根据权利要求10所述的超级结肖特基二极管，其特征在于，所述宽禁带半导体为碳化硅。
  13. 根据权利要求12所述的超级结肖特基二极管，其特征在于，所述碳化硅包括4H-SiC或6H-SiC。
  14. 根据权利要求10或12所述的超级结肖特基二极管，其特征在于，所述第一离子包括氮离子或磷离子，所述氮离子或磷离子分别以第一浓度、第一能量及第二浓度、第二能量沿所述碳化硅半导体的C轴方向注入所述外延层的至少一部分区域。
  15. 根据权利要求10或12所述的超级结肖特基二极管，其特征在于，所述第二掺杂离子包括铝离子或硼离子，所述铝离子或硼离子分别以第三浓度、第三能量及第四浓度、第四能量沿所述碳化硅半导体的C轴方向注入所述第一导电类型区的至少一部分区域。
  16. 根据权利要求11或12所述的超级结肖特基二极管，其特征在于，所述第二掺杂离子包括铝离子，所述铝离子分别以第五浓度、第五能量及第六浓度、第六能量沿所述碳化硅半导体的法线方向注入所述第二导电类型区的部分区域。
PCT/CN2021/079118 2020-03-06 2021-03-04 超级结的制造方法及其超级结肖特基二极管 WO2021175294A1 (zh)

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