WO2021174473A1 - 发光基板及其驱动方法、发光模组、显示装置 - Google Patents

发光基板及其驱动方法、发光模组、显示装置 Download PDF

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Publication number
WO2021174473A1
WO2021174473A1 PCT/CN2020/077881 CN2020077881W WO2021174473A1 WO 2021174473 A1 WO2021174473 A1 WO 2021174473A1 CN 2020077881 W CN2020077881 W CN 2020077881W WO 2021174473 A1 WO2021174473 A1 WO 2021174473A1
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WIPO (PCT)
Prior art keywords
light
emitting
signal
power supply
supply voltage
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PCT/CN2020/077881
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English (en)
French (fr)
Other versions
WO2021174473A9 (zh
Inventor
郝卫
王飞飞
苏文刚
石蕊
时凌云
孙海威
陈明
董学
Original Assignee
京东方科技集团股份有限公司
北京京东方显示技术有限公司
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Application filed by 京东方科技集团股份有限公司, 北京京东方显示技术有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US17/255,060 priority Critical patent/US11357083B2/en
Priority to KR1020227017340A priority patent/KR20220150271A/ko
Priority to PCT/CN2020/077881 priority patent/WO2021174473A1/zh
Priority to JP2022547796A priority patent/JP7497445B2/ja
Priority to CN202080000224.6A priority patent/CN113614625B/zh
Priority to EP20922728.9A priority patent/EP4099088A4/en
Publication of WO2021174473A1 publication Critical patent/WO2021174473A1/zh
Publication of WO2021174473A9 publication Critical patent/WO2021174473A9/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/3406—Control of illumination source
    • G09G3/342—Control of illumination source using several illumination sources separately controlled corresponding to different display panel areas, e.g. along one dimension such as lines
    • G09G3/3426—Control of illumination source using several illumination sources separately controlled corresponding to different display panel areas, e.g. along one dimension such as lines the different display panel areas being distributed in two dimensions, e.g. matrix
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B45/00—Circuit arrangements for operating light-emitting diodes [LED]
    • H05B45/10—Controlling the intensity of the light
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/075—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00
    • H01L25/0753—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H01L25/167—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits comprising optoelectronic devices, e.g. LED, photodiodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B33/00—Electroluminescent light sources
    • H05B33/12—Light sources with substantially two-dimensional radiating surfaces
    • H05B33/26—Light sources with substantially two-dimensional radiating surfaces characterised by the composition or arrangement of the conductive material used as an electrode
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B47/00—Circuit arrangements for operating light sources in general, i.e. where the type of light source is not relevant
    • H05B47/10—Controlling the light source
    • H05B47/16—Controlling the light source by timing means
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
    • G02F1/1336—Illuminating devices
    • G02F1/133602—Direct backlight
    • G02F1/133603—Direct backlight with LEDs
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
    • G02F1/1336—Illuminating devices
    • G02F1/133602—Direct backlight
    • G02F1/133612—Electrical details
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/02—Composition of display devices
    • G09G2300/026—Video wall, i.e. juxtaposition of a plurality of screens to create a display screen of bigger dimensions
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/06—Adjustment of display parameters
    • G09G2320/0626—Adjustment of display parameters for control of overall brightness
    • G09G2320/0633—Adjustment of display parameters for control of overall brightness by amplitude modulation of the brightness of the illumination source
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/06—Adjustment of display parameters
    • G09G2320/0626—Adjustment of display parameters for control of overall brightness
    • G09G2320/064—Adjustment of display parameters for control of overall brightness by time modulation of the brightness of the illumination source
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2370/00—Aspects of data communication
    • G09G2370/08—Details of image data interface between the display device controller and the data line driver circuit
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B20/00—Energy efficient lighting technologies, e.g. halogen lamps or gas discharge lamps
    • Y02B20/40—Control techniques providing energy savings, e.g. smart controller or presence detection

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a light-emitting substrate and a driving method thereof, a light-emitting module, and a display device.
  • HDR High-Dynamic Range
  • the mini LED mini Light Emitting Diode
  • the mini LED has a small size and high brightness, and can be used in a large number of backlight modules of display devices, and the backlight can be finely adjusted to achieve high dynamic range image display.
  • a light-emitting substrate includes a substrate, a plurality of light-emitting components, a plurality of first power supply voltage signal lines, and a plurality of first control circuits.
  • the plurality of light-emitting components are arranged on the substrate, and one light-emitting component is located in a light-emitting zone; the plurality of first power supply voltage signal lines are arranged on the substrate and are arranged at intervals;
  • a control circuit is disposed on the substrate, each first control circuit is coupled to a first pole of a light-emitting component, and each first power supply voltage signal line is coupled to at least two first control circuits; the The first control circuit is configured to transmit the first power supply voltage signal from the first power supply voltage signal line to the first pole of the light-emitting component coupled to the first control circuit to control the flow of the light-emitting component Current amplitude.
  • the plurality of light-emitting partitions are arranged in an array, and the plurality of first control circuits are arranged in an array;
  • the power voltage signal line is coupled, or, the light-emitting components in the same column of light-emitting partitions are coupled to one of the first power voltage signal lines through a column of first control circuits.
  • the first control circuit is configured to receive a first light-emitting signal and a first enable signal, and according to the first light-emitting signal and the first enable signal, the first power supply The voltage signal is transmitted to the first pole of the light-emitting component coupled to the first control circuit to control the amplitude of the current flowing through the light-emitting component.
  • the first control circuit includes: a processor, an analog-digital converter, and a first output sub-circuit; the processor is configured to receive the first light-emitting signal and perform format conversion on the first light-emitting signal, Generate a second light-emitting signal; the analog-digital converter is configured to receive the first enable signal to generate a reference signal; the first output sub-circuit and the processor, the analog-digital converter, the The first power supply voltage signal line is coupled to the first pole of the light-emitting component; the first output sub-circuit is configured to, according to the second light-emitting signal from the processor and from the analog-to-digital conversion
  • the reference signal of the device transmits the first power supply voltage signal from the first power supply voltage signal line to the first pole of the light-emitting component.
  • the first output sub-circuit includes: a first transistor, a first resistor, a comparator, and a second transistor; the control electrode of the first transistor is coupled to the processor, and the first transistor The second pole of the transistor is coupled to the first pole of the light-emitting component; the first end of the first resistor is coupled to the first power supply voltage signal line; the non-inverting input terminal of the comparator is coupled to the The output terminal of the analog-to-digital converter is coupled, the negative input terminal of the comparator is coupled to the second terminal of the first resistor; the control electrode of the second transistor is coupled to the output terminal of the comparator , The first electrode of the second transistor is coupled to the second end of the first resistor, and the second electrode of the second transistor is coupled to the first electrode of the first transistor.
  • the light-emitting substrate includes: a first control chip, and the first control chip includes the first control circuit.
  • the first control chip further includes: a first interface, a second interface, a third interface, and a fourth interface; the first interface is coupled to the processor in the first control circuit, and the first interface is It is configured to receive the first light-emitting signal and transmit the first light-emitting signal to the processor; the second interface is coupled to the analog-digital converter in the first control circuit, and the first The second interface is configured to receive the first enable signal and transmit the first enable signal to the analog-to-digital converter; the third interface is connected to the first power supply voltage signal line and the The first output sub-circuit in the first control circuit is coupled, and the third interface is configured to receive a first power supply voltage signal from the first power supply voltage signal line, and transmit the first power supply voltage signal To the first output sub-circuit; the fourth interface is coupled to the first output sub-circuit in the first control circuit and the first pole of the light-emitting component,
  • the light-emitting substrate further includes: a second control circuit disposed on the substrate, the second control circuit is coupled to the plurality of first control circuits; the second control circuit It is configured to receive a drive signal, and transmit a first light-emitting signal and a first enable signal to each of the first control circuits according to the drive signal.
  • the second control circuit includes: a timing control sub-circuit, a data processing sub-circuit, a memory, and an amplifying sub-circuit; the timing control sub-circuit is configured to generate a clock signal; the data processing sub-circuit Coupled with the timing control sub-circuit and the plurality of first control circuits, the data processing sub-circuit is configured to receive the drive signal, and according to the drive signal and all from the timing control sub-circuit The clock signal, the second enable signal is output, and the first light-emitting signal is transmitted to the plurality of first control circuits; the memory is configured to store the timing data of the preset light-emitting mode and the light-emitting current data; the The amplifying sub-circuit is coupled to the data processing sub-circuit, the memory and the plurality of first control circuits; the amplifying sub-circuit is configured to, according to the timing data and the light-emitting current data of the preset light-emitting mode, The second enable signal from the data processing
  • the light-emitting substrate includes a second control chip, and the second control chip includes the second control circuit.
  • the second control chip further includes: a plurality of enable signal interfaces, a plurality of light-emitting signal interfaces, and a driving signal interface; the plurality of enable signal interfaces are coupled to the amplifying sub-circuit in the second control circuit, and Each enable signal interface is coupled to at least one of the first control circuits, and the enable signal interface is configured to receive a first enable signal from the amplifying sub-circuit, and configure the first enable signal The signal is transmitted to the first control circuit to which it is coupled; the plurality of light-emitting signal interfaces are coupled to the data processing sub-circuit in the second control circuit, and each light-emitting signal interface is connected to one of the first control circuits Coupled, the light-emitting signal interface is configured to receive the first light-emitting signal from the data processing sub-circuit, and transmit the first light-emitting signal to the first control circuit to which it is coupled
  • each of the enable signal interfaces is coupled to a row or column of the first control circuits.
  • the light-emitting substrate further includes a plurality of second power supply voltage signal lines arranged on the substrate and spaced apart; the second poles of the light-emitting components in the at least two light-emitting regions and one second The power voltage signal line is coupled.
  • the light-emitting components in the same row or the same column of the light-emitting regions are coupled to one of the second power voltage signal lines.
  • the first power supply voltage signal line and the second power supply voltage signal line both extend in a column direction, or both extend in a row direction.
  • the second power supply voltage signal line and the first power supply voltage signal line are made of the same material and arranged in the same layer.
  • the light-emitting substrate further includes an insulating layer; along a direction perpendicular to the substrate, the first power supply voltage signal line and the second power supply voltage signal line are located on the insulating layer close to the On one side of the substrate, the light-emitting component and the first control circuit are located on the side of the insulating layer away from the substrate; the insulating layer is provided with a first via hole and a second via hole, the The first control circuit is coupled to the first power supply voltage signal line through a first via hole; the second pole of the light-emitting component is coupled to the second power supply voltage signal line via the second via hole.
  • the light-emitting substrate further includes a second control circuit
  • the light-emitting substrate further includes: a plurality of connecting leads arranged on a side of the insulating layer away from the substrate; A connecting lead is configured to couple each of the first control circuit and the second control circuit.
  • the light-emitting assembly includes: a plurality of light-emitting devices and a plurality of conductive patterns; the plurality of light-emitting devices are arranged in an array; the plurality of conductive patterns connect the plurality of light-emitting devices in series; Wherein, in the circuit formed by serially connecting the plurality of light-emitting devices, the cathode of one of the two light-emitting devices at both ends of the circuit is the first electrode of the light-emitting assembly, and the anode of the other light-emitting device is the first electrode of the light-emitting assembly.
  • the second pole of the light-emitting component is used to generate a plurality of light-emitting components.
  • the light-emitting module includes: the light-emitting substrate, the flexible circuit board and the power chip as described in any of the above embodiments.
  • the light-emitting substrate includes a first power supply voltage signal line and a second power supply voltage signal line; the power supply chip is bound to the light-emitting substrate through the flexible circuit board, and the power supply chip is configured to connect to the first
  • the power supply voltage signal line transmits a first power supply voltage signal, and transmits a second power supply voltage signal to the second power supply voltage signal line.
  • a display device in another aspect, includes the light-emitting module and the driving chip in the above embodiment.
  • the light-emitting substrate in the light-emitting module includes a plurality of first control circuits and a second control circuit; the driving chip is coupled to the second control circuit, and the driving chip is configured to control the second control circuit The circuit transmits the driving signal.
  • the light-emitting substrate includes a plurality of first control circuits and second control circuits.
  • the driving method of the light-emitting substrate includes: the second control circuit receives a driving signal, and according to the driving signal, transmits a first light-emitting signal and a first enable signal to each of the first control circuits;
  • the control circuit transmits the first power supply voltage signal from the first power supply voltage signal line to the first pole of the light emitting component coupled to the first control circuit according to the first light emitting signal and the first enable signal, To control the amplitude of the current flowing through the light-emitting component.
  • the second control circuit transmits a first enable signal to each of the first control circuits, including : In one driving cycle, the second control circuit transmits the first enable signal to the first control circuit of each row row by row to control the first control circuit of each row to turn on sequentially, and the first control circuit of the previous row is in the next row The first control circuit is closed before being opened.
  • the second control circuit transmits a first enable signal to each of the first control circuits, including : In one driving cycle, the second control circuit transmits the first enable signal to the first control circuit of each row at the same time to control the first control circuit of each row to be turned on at the same time, and the first control circuit of each row in the current driving cycle In the next driving cycle, the first control circuit of each row is turned off before it is turned on.
  • the second control circuit transmits a first enable signal to each of the first control circuits, including : In a driving cycle, the second control circuit sequentially transmits the first enable signal to the first control circuit of each row to control the first control circuit of each row to turn on sequentially, and the first control circuit of each row of the current driving cycle In the next driving cycle, the first control circuit of each row is turned off before it is turned on.
  • the first control circuit when the first control circuit includes a processor, an analog-digital converter, and a first output sub-circuit, the first control circuit is based on the first light-emitting signal and the first output sub-circuit.
  • the second control circuit in the case that the second control circuit includes a timing control sub-circuit, a data processing sub-circuit, a memory, and an amplifying sub-circuit, the second control circuit receives a driving signal, and according to the driving signal,
  • Each of the first control circuits transmitting the first light-emitting signal and the first enable signal includes: the timing control sub-circuit generates a clock signal; the data processing sub-circuit receives a driving signal, according to the driving signal and the signal from the The clock signal of the timing control sub-circuit outputs a second enable signal, and transmits the first lighting signal to the plurality of first control circuits; the memory stores the timing data of the preset lighting mode and the lighting Current data; the amplifying sub-circuit power amplifies the second enable signal from the data processing sub-circuit according to the timing data of the preset light emitting mode and the light emitting current data from the memory to generate the first An enable signal, and transmit the first enable signal to the plurality of first control circuits.
  • FIG. 1 is a structural diagram of a light-emitting substrate according to some embodiments of the related art
  • FIG. 2 is a structural diagram of a light-emitting substrate according to some embodiments.
  • Fig. 3 is another structural diagram of a light-emitting substrate according to some embodiments.
  • Fig. 4 is a structural diagram of a first control circuit according to some embodiments.
  • FIG. 5 is another structural diagram of a light-emitting substrate according to some embodiments.
  • Fig. 6 is another structural diagram of a light emitting substrate according to some embodiments.
  • FIG. 7 is another structural diagram of a light-emitting substrate according to some embodiments.
  • FIG. 8 is another structural diagram of a light-emitting substrate according to some embodiments.
  • FIG. 9 is another structural diagram of a light-emitting substrate according to some embodiments.
  • FIG. 10 is a structural diagram of a second control chip according to some embodiments.
  • FIG. 11 is a structural diagram of the Q area of the light-emitting substrate in FIG. 2;
  • Fig. 12 is a cross-sectional view of the light-emitting substrate in Fig. 11 along B-B';
  • FIG. 13 is another structural diagram of the Q area of the light-emitting substrate in FIG. 2;
  • Fig. 14 is a structural diagram of a light emitting module according to some embodiments.
  • FIG. 15 is a structural diagram of a display device according to some embodiments.
  • FIG. 16 is another structural diagram of a display device according to some embodiments.
  • FIG. 17 is another structural diagram of a light-emitting substrate according to some embodiments.
  • FIG. 18 is another structural diagram of a light-emitting substrate according to some embodiments.
  • FIG. 19 is a driving timing diagram of the light-emitting substrate according to some embodiments.
  • FIG. 20 is another driving timing diagram of the light-emitting substrate according to some embodiments.
  • FIG. 21 is another driving timing diagram of the light-emitting substrate according to some embodiments.
  • first and second are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Thus, the features defined with “first” and “second” may explicitly or implicitly include one or more of these features. In the description of the embodiments of the present disclosure, unless otherwise specified, “plurality” means two or more.
  • the expressions “coupled” and “connected” and their extensions may be used.
  • the term “connected” may be used when describing some embodiments to indicate that two or more components are in direct physical or electrical contact with each other.
  • the term “coupled” may be used when describing some embodiments to indicate that two or more components have direct physical or electrical contact.
  • the term “coupled” or “communicatively coupled” may also mean that two or more components are not in direct contact with each other, but still cooperate or interact with each other.
  • the embodiments disclosed herein are not necessarily limited to the content of this document.
  • At least one of A, B, and C has the same meaning as “at least one of A, B, or C", and both include the following combinations of A, B, and C: only A, only B, only C, A and B The combination of A and C, the combination of B and C, and the combination of A, B and C.
  • a and/or B includes the following three combinations: A only, B only, and the combination of A and B.
  • the light-emitting substrate 100' includes a plurality of light-emitting components 20', and each light-emitting component 20' is coupled to a first power supply voltage signal line LV1' and a second power supply voltage signal line LV2'. Then, the first power supply voltage signal line LV1' and the second power supply voltage signal line LV2' respectively transmit the first power supply voltage signal and the second power supply voltage signal to the light-emitting assembly 20' to control the amplitude of the current flowing through the light-emitting assembly 20' .
  • the first power supply voltage signal line LV1' and the second power supply voltage signal line LV2' need to be led out to the surface of the peripheral area of the light-emitting substrate 100' through a via hole, and then bound to an external driving circuit through a flexible circuit board.
  • a rigid material such as glass
  • the limit spacing of the gold fingers on the circuit board and the size of the flexible circuit board one light-emitting substrate 100' needs to be connected with multiple flexible circuit boards to meet the requirements, resulting in higher production costs.
  • the light-emitting substrate 100 has a plurality of light-emitting regions S. It includes: a substrate 10, a plurality of light-emitting components 20, a plurality of first power supply voltage signal lines LV1, and a plurality of first control circuits 30.
  • a plurality of light-emitting components 20 are disposed on the substrate 10, and one light-emitting component 20 is located in a light-emitting zone S.
  • a plurality of first power supply voltage signal lines LV1 are disposed on the substrate 10 and arranged at intervals.
  • a plurality of first control circuits 30 are disposed on the substrate 10, each first control circuit 30 is coupled to a first pole of a light emitting component 20, and each first power supply voltage signal line LV1 is connected to at least two first control circuits.
  • the circuit 30 is coupled.
  • the first control circuit 30 is configured to transmit the first power supply voltage signal from the first power supply voltage signal line LV1 to the first pole of the light emitting component 20 coupled to the first control circuit 30 to control the flow of the light.
  • the current amplitude of the component 20 is configured to transmit the first power supply voltage signal from the first power supply voltage signal line LV1 to the first pole of the light emitting component 20 coupled to the first control circuit 30 to control the flow of the light. The current amplitude of the component 20.
  • the first power supply voltage signal is a direct current low voltage signal.
  • each first control circuit 30 in the light-emitting substrate 100 is coupled to a first pole of a light-emitting component 20, and each first power supply voltage signal line LV1 is coupled to at least two first control circuits 30 Therefore, the number of signal lines (such as the first power supply voltage signal line LV1) on the light-emitting substrate 100 is reduced, the voltage drop of the signal lines is reduced, and the signal stability is improved.
  • the first control circuit 30 transmits the first power supply voltage signal to the first pole of the light-emitting component 20 coupled to the first control circuit 30, and the first power voltage signal determines the amplitude of the current transmitted to the light-emitting component 20;
  • the first control circuit 30 can control the length of time during which the first power supply voltage signal is transmitted to the light-emitting component 20; the current amplitude and the time length jointly determine the light-emitting brightness of the light-emitting component 20.
  • each first control circuit 30 is coupled to a first pole of a light-emitting component 20, and each first power supply voltage signal line LV1 is connected to at least two first control circuits. 30, the first control circuit 30 transmits the first power supply voltage signal from the first power supply voltage signal line LV1 to the first pole of the light emitting component 20 coupled to the first control circuit 30 to control the flow of light The current amplitude and duration of the component 20.
  • the first control circuit 30 controls the duration of the first power supply voltage signal transmitted to the light-emitting component 20, and the first power voltage signal determines the current amplitude transmitted to the light-emitting component 20, through which the current amplitude and duration are common
  • the light-emitting brightness of the light-emitting component 20 is controlled.
  • the number of signal lines (for example, the first power supply voltage signal line LV1) of the light-emitting substrate 100 is reduced, and the wiring of the light-emitting substrate 100 is simplified. design. As the number of signal lines is reduced, the interval between the signal lines is relatively increased.
  • the width of the signal line can be appropriately increased, and the thickness of the signal line can be reduced, thereby reducing the impedance of the signal line and reducing the signal line.
  • the pressure drop improves the stability of the signal.
  • the plurality of light-emitting regions S are arranged in an array, and the plurality of first control circuits 30 are arranged in an array.
  • the light-emitting partitions S arranged in a row along the horizontal direction X are called a row of light-emitting partitions
  • the light-emitting partitions S arranged in a row along the vertical direction Y are called a column of light-emitting partitions.
  • the first control circuits 30 arranged in a row along the horizontal direction X are referred to as a row of first control circuits
  • the first control circuits 30 arranged in a row along the vertical direction Y are referred to as a column of first control circuits.
  • the light-emitting components 20 in the same row of light-emitting partitions S are coupled to a first power supply voltage signal line LV1 through a row of first control circuits 30, or, as shown in FIG. 2, the light-emitting components 20 in the same row of light-emitting partitions S
  • the light-emitting component 20 is coupled to a first power voltage signal line LV1 through a column of first control circuits 30.
  • the light-emitting substrate 100 includes n rows and m columns of light-emitting partitions S and n rows and m columns of first control circuits 30, where n and m are both positive integers, and one light-emitting partition S corresponds to one first control circuit 30.
  • the first power supply voltage signal line LV1 is along the row direction (ie, the horizontal direction X in FIG.
  • the number of the first power supply voltage signal line LV1 is n; the light-emitting components 20 in the same column of the light-emitting subarea S are coupled to a first power supply voltage signal line LV1 through a column of first control circuits 30 In this case, the first power supply voltage signal line LV1 extends along the column direction (ie, the vertical direction Y in FIG. 2). At this time, the number of the first power supply voltage signal line LV1 is m.
  • a first power supply voltage signal line LV1' is coupled to a light-emitting component 20' in a light-emitting subarea S', the first power supply voltage signal
  • the number of lines LV1' is (n ⁇ m), and the number of first power supply voltage signal lines LV1 in the light-emitting substrate 100 in the embodiment of the present disclosure is reduced. For example, when the first power supply voltage signal line LV1 runs along the row direction When extending, the number of the first power supply voltage signal line LV1 is n.
  • the number of the first power supply voltage signal line LV1 is m, which reduces the light emitting substrate 100
  • the number of signal lines simplifies the wiring design of the light-emitting substrate 100. Because the number of signal lines is reduced, the design interval between the signal lines can be relatively increased. Therefore, the width of the signal line can be appropriately increased, thereby reducing the impedance of the signal line, reducing the voltage drop on the signal line, and increasing the signal The stability.
  • the first control circuit 30 is configured to receive the first light-emitting signal EM1 and the first enable signal PW1, and according to the first light-emitting signal EM1 and the first enable signal PW1, the first control circuit 30
  • the power voltage signal V1 is transmitted to the first pole of the light-emitting element 20 coupled to the first control circuit 30 to control the amplitude of the current flowing through the light-emitting element 20.
  • V1 represents the first power supply voltage signal from the first power supply voltage signal line LV1.
  • the first light-emitting signal EM1 received by the first control circuit 30 is the light-emitting data of the light-emitting component 20 coupled to the first control circuit 30.
  • the first light-emitting signal EM1 includes pulse width modulation (Pulse Width Modulation). , PWM) signal.
  • PWM pulse width modulation
  • the first enable signal PW1 received by the first control circuit 30 is a signal for driving the first control circuit 30 to turn on.
  • the first enable signal PW1 includes a power (Power) signal.
  • the first control circuit 30 includes: a processor 31, an analog-to-digital converter ADC and a first output sub-circuit 32.
  • the processor 31 is configured to receive the first luminescence signal EM1 and perform format conversion on the first luminescence signal EM1 to generate a second luminescence signal EM2.
  • the processor 31 converts the first luminescence signal EM1 to generate the second luminescence signal EM2 to match the format of the signal required for the operation of the first control circuit 30.
  • the specific conversion method is not limited here. The personnel can set according to the needs of the actual product.
  • the first light-emitting signal EM1 and the second light-emitting signal EM2 may both be PWM signals, but the formats of the two are different.
  • the analog-to-digital converter ADC is configured to receive the first enable signal PW1 and generate a reference signal REF.
  • the first enable signal PW1 is an analog signal
  • the reference signal REF is a digital signal.
  • the analog-to-digital converter ADC generates a reference signal REF of different potentials according to the received first enable signal PW1 of different potentials.
  • the first output sub-circuit 32 is configured to transmit the first power supply voltage signal V1 from the first power supply voltage signal line LV1 according to the second light emission signal EM2 from the processor 31 and the reference signal REF from the analog-to-digital converter ADC To the first pole of the light-emitting assembly 20.
  • the potential of the second light-emitting signal EM2 generated by each first control circuit 30 and the potential of the reference signal REF are not completely the same.
  • the first output sub-circuit 32 is turned on under the control of the second light-emitting signal EM2 and the reference signal REF, and transmits the first power supply voltage signal to the first pole of the light-emitting component 20, and adjusts the second light-emitting signal EM2.
  • the first control circuit 30 is not completely the same in the open time, so as to adjust the transmission time of the first power voltage signal V1 to the first pole of the light-emitting component 20, control the working time of the light-emitting component 20, and adjust the reference signal REF.
  • the potential of controls the amplitude of the current flowing through the light-emitting component 20.
  • the potential of the first enable signal PW1 received by each first control circuit 30 may be the same or may be different.
  • the reference signal REF generated by each first control circuit 30 is the same, and the first light-emitting signal EM1 can be adjusted according to the different received first light-emitting signals EM1.
  • the reference signal REF generated by each first control circuit 30 is different, and the amplitude of the current flowing through the light-emitting component 20 is adjusted. Therefore, according to the received first enable signal PW1 and the first light emitting signal EM1, the amplitude and duration of the current flowing through the light emitting component 20 are controlled to adjust the brightness of the light emitting component 20 in the light emitting zone S.
  • the first output sub-circuit 32 includes: a first transistor M1, a first resistor R1, a comparator A, and a second transistor M2.
  • the control electrode of the first transistor M1 is coupled to the processor 31, and the second electrode of the first transistor M1 is coupled to the first electrode of the light-emitting component 20.
  • the first end of the first resistor R1 is coupled to the first power voltage signal line LV1.
  • the positive input terminal of the comparator A is coupled to the output terminal of the analog-to-digital converter ADC, and the negative input terminal of the comparator A is coupled to the second terminal of the first resistor R1.
  • the control electrode of the second transistor M2 is coupled to the output terminal of the comparator A, the first electrode of the second transistor M2 is coupled to the second end of the first resistor R1, and the second electrode of the second transistor M2 is coupled to the first transistor M1.
  • the first pole is coupled.
  • the comparator A compares the first power supply voltage signal V1 transmitted through the first resistor R1 with the reference signal REF from the analog-to-digital converter ADC, transmits the compared signal to the second transistor M2, and controls the second transistor M2.
  • the second transistor M2 is turned on.
  • the potentials of the first enable signal PW1 received by the first control circuit 30 coupled to different light-emitting components 20 are not completely the same, and the potentials of the reference signal REF generated according to the first enable signal PW1 are not completely the same, therefore, By adjusting the potential of the first enable signal PW1, a reference signal REF with different potentials is generated, and the amplitude of the current flowing through the second transistor M2 is controlled, thereby controlling the amplitude of the current flowing through the light-emitting component 20.
  • the processor 31 converts the format of the first light-emitting signal EM1 to generate a second light-emitting signal EM2, and the first transistor M1 is turned on under the control of the second light-emitting signal EM2. Since the potentials of the first light-emitting signal EM1 corresponding to different light-emitting components 20 are not completely the same, and the potentials of the second light-emitting signal EM2 are not completely the same, therefore, the potentials of the first light-emitting signal EM1 can be adjusted to generate different potentials.
  • the second light-emitting signal EM2 controls the conduction time of the first transistor M1 in each first control circuit 30, thereby controlling the length of time during which the first power supply voltage signal V1 is transmitted to the first pole of the light-emitting component 20 through the first output sub-circuit 32 .
  • the above-mentioned transistors may be thin film transistors, field effect transistors, or other switching devices with the same characteristics, which are not limited in the embodiments of the present disclosure.
  • the control pole of the above-mentioned transistor is the gate of the transistor, the first pole is one of the source and drain of the transistor, and the second pole is the other of the source and drain of the transistor. Since the source and drain of the transistor can be symmetrical in structure, the source and drain of the transistor can be structurally indistinguishable. That is to say, the first and second electrodes of the transistor in the embodiment of the present disclosure The two poles can be indistinguishable in structure.
  • the first electrode of the transistor is a source and the second electrode is a drain; for example, when the transistor is an N-type transistor, the first electrode of the transistor is a drain, The second pole is the source.
  • the light-emitting substrate 100 includes a first control chip 101.
  • the first control chip 101 includes a first control circuit 30.
  • the first control chip 101 further includes: a first interface P1, a second interface P2, a third interface P3, and a fourth interface P4.
  • the first interface P1 is coupled to the processor 31 in the first control circuit 30.
  • the second interface P2 is coupled to the analog-to-digital converter ADC in the first control circuit 30.
  • the third interface P3 is coupled to the first power supply voltage signal line LV1 and the first output sub-circuit 32 in the first control circuit 30.
  • the fourth interface P4 is coupled to the first output sub-circuit 32 in the first control circuit 30 and the first pole of the light-emitting assembly 20.
  • the first interface P1 is configured to receive the first light-emitting signal EM1 and transmit the first light-emitting signal EM1 to the processor 31.
  • the second interface P2 is configured to receive the first enable signal PW1 and transmit the first enable signal PW1 to the analog-to-digital converter ADC.
  • the third interface P3 is configured to receive the first power supply voltage signal V1 from the first power supply voltage signal line LV1 and transmit the first power supply voltage signal to the first output sub-circuit 32.
  • the fourth interface P4 is configured to transmit the first power supply voltage signal transmitted through the first output sub-circuit 32 to the first pole of the light-emitting component 20.
  • the first control chip 101 controls the duration of the transmission of the first power supply voltage signal V1 to the light-emitting component 20 coupled thereto according to the received first light-emitting signal EM1 and the first enable signal PW1, thereby controlling the flow and
  • the first control chip 101 is coupled to the current amplitude and duration of the light-emitting component 20.
  • the number of interfaces of the first control chip 101 is small, and the size of the first control chip 101 is on the order of micrometers, so that the first control chip 101 has a small influence on the area of the effective light emitting area in the light emitting substrate 100.
  • the light-emitting substrate 100 further includes a second control circuit 40 disposed on the substrate 10.
  • the second control circuit 40 is coupled to the plurality of first control circuits 30.
  • the second control circuit 40 is configured to receive a driving signal, and according to the driving signal, transmit the first light emitting signal EM1 and the first enable signal PW1 to each first control circuit 30.
  • the second control circuit 40 includes: a timing control sub-circuit 41, a data processing sub-circuit 42, a memory 43, and an amplifying sub-circuit 44.
  • the data processing sub-circuit 42 is coupled to the timing control sub-circuit 41 and the plurality of first control circuits 30.
  • the amplifying sub-circuit 44 is coupled to the data processing sub-circuit 42, the memory 43 and the plurality of first control circuits 30.
  • the timing control sub-circuit 41 is configured to generate a clock signal.
  • the data processing sub-circuit 42 is configured to receive the drive signal DRV, output the second enable signal PW2 according to the drive signal DRV and the clock signal from the timing control sub-circuit 41, and transmit the first light emission to the plurality of first control circuits 30 Signal EM1.
  • the memory 43 is configured to store time series data and light emission current data of the preset light emission mode.
  • the light-emitting substrate 100 when the light-emitting substrate 100 is applied to a display device, those skilled in the art can set the light-emitting mode of the light-emitting substrate 100 according to the display mode of the display device, and set the timing data and light-emitting current data of the preset light-emitting mode. Store it.
  • the amplifying sub-circuit 44 is configured to amplify the power of the second enable signal PW2 from the data processing sub-circuit 42 according to the timing data of the preset light-emitting mode and the light-emitting current data, to generate the first enable signal PW1, and to multiply it.
  • the first control circuit 30 transmits the first enable signal PW1.
  • the timing control sub-circuit 41 when the second control circuit 40 starts to work, the timing control sub-circuit 41 generates a clock signal, and the data processing sub-circuit 42 transmits the first control circuit 30 to the plurality of first control circuits 30 according to the clock signal and the received drive signal DRV.
  • a light-emitting signal EM1 transmits the second enable signal PW2 to the amplifying sub-circuit 44.
  • the amplifying sub-circuit 44 power-amplifies the second enable signal PW2 according to the timing data of the preset lighting mode and the lighting current data stored in the memory 43 to generate the first enable signal PW1, and the first enable signal PW1 It is transmitted to a plurality of first control circuits 30 to control the current of the first control circuit 30 to drive the plurality of first control circuits 30 to work, so as to realize the control of the working state of the light-emitting assembly 20 coupled to the first control circuit 30 .
  • the amplifying sub-circuit 44 amplifies the power of the second enable signal PW2, which can improve the carrying capacity of the second control chip 102.
  • the light-emitting substrate 100 includes a second control chip 102. As shown in FIG. 9, the second control chip 102 includes a second control circuit 40.
  • the second control chip 102 further includes: multiple enable signal interfaces E, multiple light-emitting signal interfaces L, and drive signal interfaces D.
  • the multiple enable signal interfaces E are coupled to the amplifying sub-circuit 44 in the second control circuit 40, and each enable signal interface E is coupled to at least one first control circuit 30.
  • the multiple light-emitting signal interfaces L are coupled to the data processing sub-circuit 42 in the second control circuit 40, and each light-emitting signal interface L is coupled to a first control circuit 30.
  • the light-emitting substrate 100 includes the first control circuit 30 in n rows and m columns, as shown in FIG.
  • the first control circuit 30 in the second row and the first column is coupled to the light-emitting signal interface L(1_2)
  • the first control circuit 30 in the nth row and the first column is coupled to the light-emitting signal interface L(1_n)
  • the mth row in the first row
  • the first control circuit 30 in the column is coupled to the light-emitting signal interface L(m_1)
  • the first control circuit 30 in the second row and the mth column is coupled to the light-emitting signal interface L(m_2)
  • the first control circuit 30 in the nth row and mth column is coupled to the
  • the control circuit 30 is coupled to the light-emitting signal interface L(m_n).
  • the driving signal interface D is coupled to the data processing sub-circuit 42.
  • the enable signal interface E is configured to receive the first enable signal PW1 from the amplifying sub-circuit 44 and transmit the first enable signal PW1 to the first control circuit 30 to which it is coupled.
  • the light-emitting signal interface L is configured to receive the first light-emitting signal EM1 from the data processing sub-circuit 42 and transmit the first light-emitting signal EM1 to the first control circuit 30 to which it is coupled.
  • the driving signal interface D is configured to receive the driving signal DRV and transmit the driving signal DRV to the data processing sub-circuit 42.
  • the drive signal interface D may adopt SPI (Serial Peripheral Interface).
  • the drive signal interface D includes an SCLK (Serial Clock) interface for receiving a serial clock signal generated by the master device, and a MOSI (Master Output/Slave Input) for receiving a data signal transmitted by the master device.
  • SCLK Serial Clock
  • MOSI Master Output/Slave Input
  • Host output/slave input data) interface, and vertical frame synchronization signal interface Vsync for receiving the vertical frame synchronization signal transmitted by the master device, that is, the drive signal DRV received by the drive signal interface D includes SCLK signal, MOSI signal and vertical frame Synchronization signal Vsync.
  • the master device is the display device
  • the slave device is the second control chip 102
  • the driving signal received by the driving signal interface D may come from the SOC (System on Chip, System chip) or T-con (Timing Controller, timing controller).
  • the second control chip 102 further includes a control signal interface EN, a MISO (Master Input/Slave Output, host input/slave output data) interface, and a CS (Chip Select) interface.
  • the control signal interface EN is used to receive a control signal from the main device to control the second control chip 102 to start working. For example, when the signal received by the control signal interface EN is at a high level, the second control chip 102 starts working. When the signal received by the interface EN is low, the second control chip 102 stops working.
  • the MISO interface is used to transmit data from the second control chip 102 to the master device.
  • the signal received by the CS interface is used to drive the second control chip 102 to start transmitting data. For example, when the signal received by the CS interface is active at low level, the second control chip 102 performs data transmission.
  • each enable signal interface E is coupled to a row or column of first control circuits 30.
  • each enable signal interface E when each enable signal interface E is coupled to a row of first control circuits 30, each enable signal receives the signal output by E to control the operation of a row of first control circuits 30; when each enable signal interface E is coupled to a column of first control circuits 30, and each enable signal receives the signal output by E to control the operation of a column of first control circuits 30.
  • an enable signal interface E may be coupled to one row of first control circuits 30, as shown in FIG. 9, the first control circuit in row 1 It is coupled to the enable signal interface E(1), the first control circuit in the second row is coupled to the enable signal interface E(2), and the first control circuit in the nth row is coupled to the enable signal interface E(n).
  • the light-emitting substrate 100 further includes a plurality of second power supply voltage signal lines LV2.
  • a plurality of second power supply voltage signal lines LV2 are disposed on the substrate 10 and arranged at intervals.
  • the second poles of the light-emitting components 20 in the at least two light-emitting regions S are coupled to a second power voltage signal line LV2.
  • the second power supply voltage signal line LV2 is configured to transmit the second power supply voltage signal to the second pole of the light emitting component 20 coupled thereto.
  • V2 represents the second power supply voltage signal from the second power supply voltage signal line LV2.
  • the second power supply voltage signal V2 is a direct current high voltage signal.
  • the A control circuit 30 transmits the duration of the first power supply voltage signal V1 to the light-emitting component 20 to control the working duration of the light-emitting component 20.
  • the second poles of the light-emitting components 20 in at least two light-emitting regions S in the light-emitting substrate 100 are coupled to a second power voltage signal line LV2, and the number of the second power voltage signal lines LV2 is reduced, which simplifies the light-emitting substrate 100 The routing design.
  • the spacing between the signal lines is relatively increased. Therefore, the width of the signal line can be increased appropriately, thereby reducing the impedance of the signal line, reducing the voltage drop on the signal line, and improving the stability of the signal sex.
  • a flexible circuit board is used to bind the light-emitting substrate 100 with an external driving circuit, since the number of wires is reduced, the number of flexible circuit boards is also reduced accordingly, thereby reducing the production cost.
  • the light-emitting components 20 in the same row or column of the light-emitting regions are coupled to a second power voltage signal line LV2.
  • the light-emitting substrate 100 includes n rows and m columns of light-emitting regions S and n rows and m columns of a first control circuit 30.
  • the second power supply voltage signal line LV2 extends along the row direction (horizontal direction X in FIG. 3).
  • the number of the second power supply voltage signal line LV2 is n; as shown in FIG.
  • the second power supply voltage signal line LV2 extends along the column direction (the vertical direction Y in FIG. 2), At this time, the number of second power supply voltage signal lines LV2 is m.
  • the second The number of power supply voltage signal lines LV2' is (n ⁇ m), and the number of second power supply voltage signal lines LV2 in the light-emitting substrate 100 in the embodiment of the present disclosure is reduced, for example, when the second power supply voltage signal line LV2 Extending in the row direction, the number of second power voltage signal lines LV2 is n.
  • the number of second power voltage signal lines LV2 is m, which decreases The number of signal lines of the light-emitting substrate 100 is shown. As the number of signal lines is reduced, the spacing between the signal lines is relatively increased. Therefore, the width of the signal line can be appropriately increased, thereby reducing the impedance of the signal line, reducing the voltage drop on the signal line, and improving the stability of the signal sex. In addition, when the light-emitting substrate 100 is bound to an external driving circuit through a flexible circuit board, since the number of wires is reduced, the number of flexible circuit boards is also reduced accordingly, thereby reducing production costs.
  • the first power supply voltage signal line LV1 and the second power supply voltage signal line LV2 both extend in the column direction, or both extend in the row direction.
  • the light-emitting substrate 100 includes n rows and m columns of light-emitting partitions S and n rows and m columns of the first control circuit 30.
  • the first power supply voltage signal line LV1 and the second power supply voltage signal line LV2 extend in the row direction.
  • the total number of a power supply voltage signal line LV1 and a second power supply voltage signal line LV2 is (2 ⁇ n); the case where the light-emitting components 20 in the same column of the light-emitting subarea S are coupled to a second power supply voltage signal line LV2
  • the first power supply voltage signal line LV1 and the second power supply voltage signal line LV2 extend along the column direction.
  • the total number of the first power supply voltage signal line LV1 and the second power supply voltage signal line LV2 is (2 ⁇ m) strip.
  • the first power supply voltage signal line LV1 compared to the case where one second power supply voltage signal line LV2 and one first power supply voltage signal line LV1 are coupled to the light-emitting components 20 in one light-emitting section S in the light-emitting substrate 100, the first power supply voltage signal line LV1 And the total number of the second power supply voltage signal line LV2 is 2 ⁇ (n ⁇ m), the first power supply voltage signal line LV1 and the second power supply voltage signal line LV2 in the light-emitting substrate 100 in the embodiment of the present disclosure The numbers are reduced.
  • the total number of the first power supply voltage signal line LV1 and the second power supply voltage signal line LV2 is (2 ⁇ n)
  • the total number of the first power supply voltage signal line LV1 and the second power supply voltage signal line LV2 is (2 ⁇ m)
  • the width of the line thereby reducing the impedance of the signal line, reducing the voltage drop on the signal line, and improving the stability of the signal.
  • a flexible circuit board is used to bind the external driving circuit and the light-emitting substrate 100, since the number of wires is reduced, the number of flexible circuit boards is also reduced accordingly, thereby reducing production costs.
  • the second power supply voltage signal line LV2 and the first power supply voltage signal line LV1 have the same material and are arranged in the same layer.
  • the second power supply voltage signal line LV2 and the first power supply voltage signal line LV1 can be formed synchronously, thereby simplifying the production process.
  • the light-emitting substrate 100 further includes an insulating layer 50.
  • the first power supply voltage signal line LV1 and the second power supply voltage signal line LV2 are located on the side of the insulating layer 50 close to the substrate 10, and the light emitting component 20 and the first control circuit 30 are located far away from the insulating layer 50.
  • the insulating layer 50 is provided with a first via 51 and a second via 52.
  • the first control circuit 30 is coupled to the first power voltage signal line LV1 through the first via hole 51, and the second pole of the light-emitting component 20 is coupled to the second power voltage signal line LV2 through the second via hole 52.
  • the light-emitting substrate 100 further includes a connection pattern 103 disposed on the side of the insulating layer 50 away from the substrate 10, the connection pattern 103 covers the first via 51 and the second via 52, and the first control circuit 30 passes through the connection pattern 103 and the second via.
  • a via 51 is coupled to the first power supply voltage signal line LV1
  • the first control circuit 30 is also coupled to the first pole of the light-emitting component 20 through the connection pattern 103
  • the second pole of the light-emitting component 20 is coupled through the connection pattern 103 and the second pole.
  • the via 52 is coupled to the second power voltage signal line LV2.
  • the material of the insulating layer 50 may be an inorganic material including silicon nitride (Si x N y ) or silicon oxide (SiO x ).
  • the light-emitting substrate 100 when the light-emitting substrate 100 further includes the second control circuit 40, the light-emitting substrate 100 further includes: a plurality of connecting leads 60 disposed on the side of the insulating layer 50 away from the substrate 10 .
  • the plurality of connecting leads 60 are configured to couple each of the first control circuit 30 and the second control circuit 40.
  • the light-emitting substrate 100 when the light-emitting substrate 100 includes the first control chip 101 and the second control chip 102, a part of the plurality of connecting leads 60 is used to couple the enable signal interface E in the second control chip 102. With the second interface P2 in the first control chip 101 in each row, the other part of the multiple connecting leads 60 is used to couple the light-emitting signal interface L in the second control chip 102 with the first control chip 101 in each row. Interface P1.
  • the second interface P2 in the first control chip 101 in the first row is connected to the second control chip 102 through the connecting lead 60
  • the enable signal interface E(1) in the nth row is coupled to the second interface P2 in the first control chip 101 in the nth row, and the enable signal interface E(n) in the second control chip 102 is coupled through the connecting lead 60 Connect;
  • the first interface P1 in the first control chip 101 in the first row and the first column is coupled to the light-emitting signal interface L(1_1) in the second control chip 102 through the connecting lead 60, the nth row and the mth column
  • the first interface P1 in the first control chip 101 is coupled to the light-emitting signal interface L(m_n) in the second control chip 102 through the connecting lead 60.
  • connection lead 60 may be a metal material including copper (Cu) or aluminum (Al).
  • the light-emitting assembly 20 includes a plurality of light-emitting devices 21 and a plurality of conductive patterns 22.
  • the multiple light emitting devices 21 are arranged in an array.
  • the plurality of conductive patterns 22 sequentially connect the plurality of light emitting devices 21 in series.
  • the cathode of one light-emitting device 21 of the two light-emitting devices 31 located at both ends of the circuit is the first pole of the light-emitting assembly 20, and the anode of the other light-emitting device 31 is the light-emitting assembly 20 second pole.
  • the light-emitting device 31 may be an inorganic light-emitting device including a micro LED (micro LED) or a mini LED (mini LED).
  • a micro LED micro LED
  • mini LED mini LED
  • the multiple light-emitting devices 21 are connected in series in sequence, that is, the multiple light-emitting devices 21 are connected in series with each other.
  • a plurality of light-emitting devices 21 may also be connected in parallel with each other, or a part of the light-emitting devices 21 of the plurality of light-emitting devices 21 may be connected in series and another part of the light-emitting devices 21 may be connected in parallel.
  • Those skilled in the art can select the connection mode of the light-emitting devices 21 in the light-emitting subarea S according to actual conditions, which is not limited in the present disclosure.
  • the shape of the conductive patterns 22 of the light-emitting devices 21 in the same row in series is in a zigzag shape, and the conductive patterns 22 of the light-emitting devices 21 in the same column are connected in series.
  • the shape is a strip; or, the shape of the conductive pattern 22 connected in series with the light-emitting devices 21 in the same row is a broken line, and the shape of the conductive pattern 22 connected in series with the light-emitting devices 21 in the same row is a strip.
  • the plurality of conductive patterns 22 are located on the side of the first power voltage signal line LV1 and the second power voltage signal line LV2 away from the substrate 10 along the direction perpendicular to the substrate 10, the plurality of conductive patterns 22 and the first power voltage signal line The line LV1 and the second power supply voltage signal line LV2 are in different layers. Therefore, the conductive pattern 22 has a small influence on the wiring space of the first power supply voltage signal line LV1 and the second power supply voltage signal line LV2, and avoids the first power supply voltage signal line.
  • the wiring gap between the line LV1 and the second power supply voltage signal line LV2 is reduced, so that the widths of the first power supply voltage signal line LV1 and the second power supply voltage signal line LV2 are reduced, resulting in the first power supply voltage signal line LV1 and the second power supply
  • the impedance of the voltage signal line LV2 increases, which affects the signal transmission effect.
  • the conductive pattern 22 and the connection pattern 103 are made of the same material and provided in the same layer. In terms of process, the conductive pattern 22 and the connection pattern 103 are formed in the same film forming process. It should be noted that in some embodiments of the present disclosure, the first control circuit 30 may be disposed outside the light-emitting zone S and adjacent to the light-emitting component 20, as shown in FIG.
  • the first control circuit 30 A control circuit 30 can be directly arranged in the light-emitting zone S, for example, the orthographic projection of the first control circuit 30 on the substrate and the conductive pattern 22, the connection pattern 103, the light-emitting device 31, the first power supply voltage signal line LV1 and the second
  • the orthographic projection of any one of the power supply voltage signal lines LV2 on the substrate may not overlap; of course, the orthographic projection of the first control circuit 30 on the substrate may also be the same as that of any of the above-mentioned structures on the substrate. There is partial overlap in the orthographic projection.
  • Some embodiments of the present disclosure provide a light-emitting module 200, as shown in FIG. 14, including: the light-emitting substrate 100, the flexible circuit board 201, and the power chip 202 in any of the above-mentioned embodiments.
  • the light-emitting substrate 100 includes a first power supply voltage signal line LV1 and a second power supply voltage signal line LV2.
  • the power chip 202 is bound to the light-emitting substrate 100 through the flexible circuit board 201.
  • the power supply chip 202 is configured to transmit a first power supply voltage signal to the first power supply voltage signal line LV1 and to transmit a second power supply voltage signal to the second power supply voltage signal line LV2.
  • the power chip 202 is configured to transmit the third power supply voltage signal and the fourth power supply voltage signal to the second control circuit 40.
  • the second control chip 102 further includes a third power supply voltage signal interface VDD and a fourth power supply voltage signal interface GND.
  • the third power supply voltage signal interface VDD is configured to receive the third power supply voltage signal from the power chip 202
  • the fourth power supply voltage signal interface GND is configured to receive the fourth power supply voltage signal from the power chip 202.
  • the third power supply voltage signal is a DC high voltage signal, for example, a signal from the positive pole of the power supply
  • the fourth power supply voltage signal is a DC low voltage signal, for example, a signal from the negative pole of the power supply.
  • the potential of the third power supply voltage signal is higher than the potential of the second power supply voltage signal.
  • the potential of the fourth power supply voltage signal is equal to the potential of the first power supply voltage signal.
  • the embodiment of the present disclosure further provides a display device 300, as shown in FIG. 15, including: the light-emitting module 200 and the driving chip 301 as in the above-mentioned embodiment.
  • the light-emitting substrate 100 in the light-emitting module 200 includes a plurality of first control circuits 30 and second control circuits 40.
  • the driving chip 301 is coupled to the second control circuit 40.
  • the driving chip 301 is configured to transmit a driving signal to the second control circuit 40.
  • the driving chip 301 may be a SOC (System on Chip) or a T-con (Timing Controller, timing controller).
  • SOC System on Chip
  • T-con Timing Controller, timing controller
  • the driving chip 301 transmits the driving signal to the second control circuit 40, and the second control circuit 40 receives the driving signal, and according to the driving signal, transmits the first light-emitting signal and the first light-emitting signal to each first control circuit 30.
  • the first control circuit 30 receives the first light-emitting signal and the first enable signal, and according to the first light-emitting signal and the first enable signal, transmits the first power voltage signal to the light-emitting component 20 coupled to the first control circuit 30 To control the amplitude of the current flowing through the light-emitting component 20, so as to control the light-emitting brightness of the light-emitting component 20.
  • the display device 300 when the display device 300 is a liquid crystal display device, the light-emitting module 200 is a backlight module. As shown in FIG. 16, the display device 300 further includes an array substrate 400, a counter substrate 500 and a liquid crystal layer 600.
  • the counter substrate 500 is disposed opposite to the array substrate 400, and the light emitting module 200 is disposed on the side of the array substrate 400 away from the counter substrate 500.
  • the liquid crystal layer 600 is located between the counter substrate 500 and the array substrate 400.
  • the liquid crystal molecules in the liquid crystal layer 600 are deflected under the action of the electric field formed between the pixel electrode 401 and the common electrode 402 in the array substrate 400, and the light emitting module 200 emits The light passing through the liquid crystal layer 600 is emitted from the side of the opposing substrate 500 away from the light emitting module 200.
  • the above-mentioned display device 300 may be any device that displays images whether in motion (for example, video) or fixed (for example, still images), and regardless of text or images. More specifically, it is expected that the described embodiments can be implemented in or associated with a variety of electronic devices, such as (but not limited to) mobile phones, wireless devices, personal data assistants (PDAs) , Handheld or portable computers, GPS receivers/navigators, cameras, MP4 video players, camcorders, game consoles, watches, clocks, calculators, TV monitors, flat panel displays, computer monitors, car monitors (e.g., Odometer display, etc.), navigator, cockpit controller and/or display, camera view display (for example, the display of a rear-view camera in a vehicle), electronic photos, electronic billboards or signs, projectors, building structures, packaging And aesthetic structure (for example, a display of the image of a piece of jewelry), etc.
  • PDAs personal data assistants
  • Handheld or portable computers GPS receivers/navigators,
  • the embodiments of the present disclosure further provide a method for driving a light-emitting substrate, and the light-emitting substrate is the light-emitting substrate 100 in any of the above-mentioned embodiments.
  • the light emitting substrate 100 includes a first control circuit 30 and a second control circuit 40.
  • the driving method of the light-emitting substrate 100 includes:
  • the second control circuit 40 receives the driving signal DRV, and transmits the first light emitting signal EM1 and the first enable signal PW1 to each first control circuit 30 according to the driving signal DRV.
  • the first control circuit 30 transmits the first power voltage signal V1 from the first power voltage signal line LV1 to the light emitting component 20 coupled to the first control circuit 30 according to the first light emitting signal EM1 and the first enable signal PW1 To control the amplitude of the current flowing through the light-emitting component 20.
  • the second control circuit 40 transmits the first light emitting signal EM1 and the first enable signal PW1 to the first control circuit 30 coupled to the light emitting component 20 in the light emitting zone S according to the driving signal DRV.
  • the potentials of the first light-emitting signal EM1 received by the first control circuit 30 coupled to the 20 are not completely the same, and the potentials of the first enable signal PW1 received are not completely the same.
  • the first control circuit 30 transmits the first power supply voltage signal V1 to the first pole of the light-emitting component 20 coupled to the first control circuit 30 according to the first enable signal PW1 and the first light-emitting signal EM1, and adjusts the first
  • the potential of the light-emitting signal EM1 controls the working time of the light-emitting component 20, and the amplitude of the current flowing through the light-emitting component 20 is controlled by adjusting the potential of the first enable signal PW1, so as to realize the control of the light-emitting component 20 in each light-emitting zone S. Control of the luminous brightness.
  • the second control circuit 40 transmits the first enable signal PW1 to each first control circuit 30, including:
  • the second control circuit 40 transmits the first enable signal PW1 to the first control circuit of each row row by row to control the first control circuit 30 of each row to turn on sequentially, and the first control circuit of the previous row is the first control circuit of the next row.
  • the control circuit is closed before it is opened.
  • a plurality of light-emitting partitions (S(1_1)...S(m_n)) are arranged in n rows and m columns.
  • the light-emitting partition S(1_1) is the light-emitting partition in the first row and m-th column.
  • the light-emitting partition S(m_n) is the light-emitting partition of the nth row and mth column, and the plurality of first control circuits 30 are arranged in n rows and m columns.
  • the second control circuit 40 transmits the first enable signal (PW1(1)...PW1) to the first control circuit 30 from the first row to the nth row row by row.
  • the first control circuit 30 of each row is controlled to turn on sequentially, and the second control circuit 40 transmits the first light-emitting signal EM1 to each first control circuit 30, for example, the first control circuit 30 in the first row receives the first control circuit 30
  • the second control circuit 40 transmits the first light-emitting signal EM1 to the first control circuit 30 in the first row, the first column to the m-th column.
  • the first control circuit 30 is turned on under the control of the first enable signal PW1 and the first light-emitting signal EM1, and transmits the first power supply voltage signal V1 from the first power supply voltage signal line LV1 to the first power supply voltage signal line LV1.
  • the first pole of the light-emitting component 20 in the light-emitting zone S coupled to the control circuit 30 to make the light-emitting component 20 work.
  • the enable signal interface E in the second control chip 102 is connected to the second control chip 101 in the first control chip 101.
  • the interface P2 is coupled, and each enable signal interface E is coupled to a row of the first control circuit 30, for example, the enable signal interface E(1) is coupled to the first control circuit 30 in the first row, and the enable signal interface E (2) It is coupled to the first control circuit 30 in the second row, and the enable signal interface E(n) is coupled to the first control circuit 30 in the nth row.
  • the multiple enable signal interfaces (E(1), E(2)...E(n-1), E(n)) of the second control chip 102 proceed to the first row to the nth row in sequence
  • the first control circuit 30 transmits a first enable signal (PW1(1)...PW1(n)) to control the first control circuit 30 from the first row to the nth row to turn on sequentially.
  • the light-emitting signal interface L in the second control chip 102 is coupled to the first interface P1 in the first control chip 101, and each light-emitting signal interface L is coupled to a first control circuit 30 and is connected to the first control circuit 30 coupled to it.
  • the control circuit 30 transmits the first light-emitting signal EM1.
  • the light-emitting signal interface L(m_n) is coupled to the first control circuit 30 in the nth row and mth column, and the light-emitting signal interface L(m_n) is connected to the nth row and mth column.
  • the first control circuit 30 transmits the first light-emitting signal corresponding to the light-emitting subarea S(m_n) in the nth row and mth column.
  • the first control circuit 30 is turned on under the control of the first light-emitting signal EM1 and the first enable signal PW1, and transmits the first power supply voltage signal V1 to the first pole of the light-emitting component 20 to which it is coupled. In order to make the light-emitting assembly 20 work.
  • the first control circuit in the previous row is turned off before the first control circuit in the next row is turned on.
  • the first control circuit 30 in the first row is turned off, the first control circuit 30 in the second row is turned on, and the first control circuit in the second row is turned on.
  • the first control circuit 30 in the third row is turned on, and so on, until the first control circuit 30 in the (n-1)th row is turned off, and the first control circuit 30 in the nth row is turned on.
  • the light-emitting components 20 in the first row to the n-th row in the light-emitting substrate 100 work row by row, which shortens the operating time of the light-emitting components 20 in each row, so that the power consumption of the light-emitting substrate 100 can be reduced.
  • the second control circuit 40 transmits the first enable signal PW1 to each first control circuit 30, including:
  • the second control circuit 40 transmits the first enable signal PW1 to the first control circuit of each row at the same time to control the first control circuit of each row to be turned on at the same time, and the first control circuit of each row in the current driving cycle drives the first control circuit in the next row.
  • the first control circuit in each line of the cycle is turned off before it is turned on.
  • a plurality of first control circuits 30 are arranged in n rows and m columns.
  • the second control circuit 40 simultaneously moves from the first row to the nth row
  • the first control circuit 30 of the row transmits the first enable signal PW1 to control the first control circuit 30 of each row to be turned on at the same time, and the second control circuit 40 transmits the first light-emitting signal EM1 to each first control circuit 30, in this case
  • the first control circuit 30 is turned on under the control of the first enable signal PW1 and the first light-emitting signal EM1, and transmits the first power supply voltage signal V1 from the first power supply voltage signal line LV1 to the first control circuit 30
  • the first pole of the light-emitting component 20 in the coupled light-emitting subarea S to make the light-emitting component 20 work.
  • each enable signal interface E is coupled to a row of the first control circuit 30, and the second control chip 102
  • the multiple enable signal interfaces (E(1), E(2)...E(n-1), E(n)) simultaneously transmit the first enable signal to the first control circuit 30 from the first row to the nth row Enable signals (PW1(1)...PW1(n)) to control the first control circuit 30 from the first row to the nth row to be turned on at the same time.
  • Each light-emitting signal interface L in the second control chip 102 is coupled to a first control circuit 30, and transmits the first light-emitting signal EM1 to the first control circuit 30 coupled to it, and the first control circuit 30 emits light in the first
  • the signal PW1 and the first enable signal EM1 are turned on under the control of the first enable signal EM1, and the first power supply voltage signal V1 is transmitted to the first pole of the light-emitting component 20 to which it is coupled to make the light-emitting component 20 work.
  • the second control circuit 40 transmits the first enable signal PW1 to each first control circuit 30, including:
  • the second control circuit 40 sequentially transmits the first enable signal PW1 to the first control circuit of each row to control the first control circuit of each row to turn on in turn, and the first control circuit of each row in the current driving cycle drives the first control circuit in the next row.
  • the first control circuit in each line of the cycle is turned off before it is turned on.
  • the plurality of first control circuits 30 are arranged in n rows and m columns.
  • the second control circuit 40 performs The first control circuit 30 transmits the first enable signal (PW1(1)...PW1(n)) row by row, controls the first control circuit 30 of each row to turn on in turn, and the second control circuit 40 sends each first
  • the control circuit 30 transmits the first light-emitting signal EM1, and the first control circuit 30 is turned on under the control of the first enable signal PW1 and the first light-emitting signal EM1, and transmits the first power voltage signal V1 from the first power voltage signal line LV1 To the first pole of the light-emitting component 20 in the light-emitting zone S coupled to the first control circuit 30 to make the light-emitting component 20 work.
  • each enable signal interface E is coupled to a row of the first control circuit 30, and the multiple enable signals of the second control chip 102
  • the interfaces (E(1), E(2)...E(n-1), E(n)) sequentially transmit the first enable signal (PW1(1) to the first control circuit 30 in the first row to the nth row )...PW1(n)) to control the first control circuit 30 in the first row to the n-th row to turn on sequentially.
  • Each light-emitting signal interface L in the second control chip 102 is coupled to a first control circuit 30, and transmits the first light-emitting signal EM1 to the first control circuit 30 coupled to it, and the first control circuit 30 emits light in the first
  • the signal EM1 and the first enable signal PW1 are turned on under the control of the first enable signal PW1, and the first power supply voltage signal V1 is transmitted to the first pole of the light-emitting component 20 to which it is coupled to make the light-emitting component 20 work.
  • the first control circuit of each row in the current driving cycle is turned off before the first control circuit in each row of the next driving cycle is turned on.
  • the first control circuits 30 from the 1st row to the nth row are sequentially turned on, and the first control circuits 30 from the 1st row to the nth row have the same operating time.
  • the first control circuit 30 of each row will be turned on with a delay, for example, As shown in FIGS. 19, 20 and 21, when the vertical frame synchronization signal Vsync of a driving cycle is valid, the enable signal interface E(1) transmits the first control circuit 30 of the first row to which it is coupled. An enable signal causes the first control circuit 30 in the first row to be turned on for a first delay time t1. Similarly, after the end of a driving period, the next driving period starts, and there is a certain delay in turning off the first control circuit 30 in each row. For example, as shown in FIG.
  • the vertical frame synchronization signal in the next driving period When Vsync is active, the enable signal interface E(1) transmits the first enable signal to the first control circuit 30 of the first row to which it is coupled, so that the first control circuit 30 of the first row is turned off with a second delay Time t2.
  • the liquid crystal molecules can be adjusted in the first delay time t1 and the second delay time t2, so that the liquid crystal molecules are in a stable state when the light-emitting assembly 20 is working, and avoiding the unstable state of the liquid crystal molecules when the light-emitting assembly 20 is working.
  • the light-emitting duration of the light-emitting assembly 20 can be ensured, and the loss of electro-optical conversion efficiency can be reduced.
  • the first enable signal transmitted by the enable signal interface E(1) to the first control circuit 30 in the first row to which it is coupled adopts PW1( 1) indicates that the first enable signal transmitted by the enable signal interface E(2) to the first control circuit 30 in the second row to which it is coupled is represented by PW1(2), and the enable signal interface E(n)
  • the first enable signal transmitted by the first control circuit 30 in the nth row to which it is coupled is represented by PW1(n).
  • the vertical frame synchronization signal received by the vertical frame synchronization signal interface Vsync is represented by Vsync, but it does not mean that the two are the same component.
  • the first control circuit 30 includes a processor 31, an analog-to-digital converter ADC, and a first output sub-circuit 32.
  • the first control circuit 30 transmits the first power supply voltage signal V1 from the first power supply voltage signal line LV1 to the first control circuit 30 according to the first light-emitting signal EM1 and the first enable signal PW1.
  • the first pole of the connected light-emitting assembly 20 includes:
  • the processor 31 receives the first luminescence signal EM1, and performs format conversion on the first luminescence signal EM1 to generate a second luminescence signal EM2.
  • the analog-to-digital converter ADC receives the first enable signal PW1 and generates a reference signal REF.
  • the first output sub-circuit 32 transmits the first power supply voltage signal V1 from the first power supply voltage signal line LV1 to the first pole of the light emitting component 20 according to the second light emitting signal EM2 and the reference signal REF.
  • the first output sub-circuit 32 is turned on under the control of the second light-emitting signal EM2 and the reference signal REF, and transmits the first power supply voltage signal V1 to the first pole of the light-emitting assembly 20, because each first control circuit 30
  • the potential of the second light-emitting signal EM2 generated is not exactly the same as the potential of the reference signal REF.
  • the potential of the second light-emitting signal EM2 can be adjusted to control the first control circuit 30 to transmit the first power voltage signal V1 to the first light-emitting component 20.
  • the duration of one pole is used to control the working time of the light-emitting component 20, and by adjusting the potential of the reference signal REF, the amplitude of the current flowing through the light-emitting component 20 is controlled.
  • the second control circuit 40 includes a timing control sub-circuit 41, a data processing sub-circuit 42, a memory 43 and an amplifying sub-circuit 44.
  • the second control circuit 40 receives the driving signal DRV, and transmits the first light emitting signal EM1 and the first enable signal PW1 to each first control circuit 30 according to the driving signal DRV, including:
  • the timing control sub-circuit 41 generates a clock signal.
  • the data processing sub-circuit 42 receives the driving signal DRV, outputs the second enable signal PW2 according to the driving signal DRV and the clock signal from the timing control sub-circuit 41, and transmits the first light emitting signal EM1 to the plurality of first control circuits 30.
  • the memory 43 stores time series data of the preset light emitting mode and light emitting current data.
  • the amplifying sub-circuit 44 amplifies the power of the second enable signal PW2 from the data processing sub-circuit 42 according to the timing data of the preset light emitting mode and the light emitting current data from the memory 43 to generate the first enable signal PW1, and multiply it.
  • the first control circuit 30 transmits the first enable signal PW1.
  • the timing control sub-circuit 41 when the second control circuit 40 starts to work, the timing control sub-circuit 41 generates a clock signal, and the data processing sub-circuit 42 transmits the first control circuit 30 to the plurality of first control circuits 30 according to the clock signal and the received drive signal DRV.
  • a light-emitting signal EM1 transmits the second enable signal PW2 to the amplifying sub-circuit 44.
  • the amplifying sub-circuit 44 power-amplifies the second enable signal PW2 according to the timing data of the preset lighting mode and the lighting current data stored in the memory 43 to generate the first enable signal PW1, and the first enable signal PW1 It is transmitted to a plurality of first control circuits 30 to control the current of the first control circuit 30 to drive the plurality of first control circuits 30 to work, so as to realize the control of the working state of the light-emitting assembly 20 coupled to the first control circuit 30 .

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Abstract

一种发光基板及其驱动方法、发光模组、显示装置，发光基板，具有多个发光分区；所述发光基板包括：衬底、多个发光组件、多条第一电源电压信号线和多个第一控制电路；多个发光组件设置于所述衬底上；多条第一电源电压信号线设置于所述衬底上且间隔排布；多个第一控制电路设置于所述衬底上；一个发光组件位于一个发光分区内；每个第一控制电路与一个发光组件的第一极耦接，且每条第一电源电压信号线与至少两个第一控制电路耦接；所述第一控制电路被配置为，将来自所述第一电源电压信号线的第一电源电压信号传输至与该第一控制电路耦接的发光组件的第一极，以控制流过该发光组件的电流幅值。

Description

发光基板及其驱动方法、发光模组、显示装置 技术领域
本公开涉及显示技术领域，尤其涉及一种发光基板及其驱动方法、发光模组、显示装置。
背景技术
在显示技术领域，显示装置中应用HDR(高动态范围图像，High-Dynamic Range)技术能够实现显示画面的画质提升，同时也对显示装置的色域和亮度提出更高的要求。迷你发光二极管(mini LED，mini Light Emitting Diode)的尺寸小，亮度高，可以大量的应用于显示装置的背光模组中，并对背光进行精细调节，从而实现高动态范围图像的显示。
发明内容
一方面，提供一种发光基板。所述发光基板包括衬底、多个发光组件、多条第一电源电压信号线和多个第一控制电路。所述多个发光组件设置于所述衬底上，一个发光组件位于一个发光分区内；所述多条第一电源电压信号线设置于所述衬底上且间隔排布；所述多个第一控制电路设置于所述衬底上，每个第一控制电路与一个发光组件的第一极耦接，且每条第一电源电压信号线与至少两个第一控制电路耦接；所述第一控制电路被配置为，将来自所述第一电源电压信号线的第一电源电压信号传输至与该第一控制电路耦接的发光组件的第一极，以控制流过该发光组件的电流幅值。
在一些实施例中，所述多个发光分区呈阵列排布，所述多个第一控制电路呈阵列排布；同一行发光分区中的发光组件通过一行第一控制电路与一条所述第一电源电压信号线耦接，或者，同一列发光分区中的发光组件通过一列第一控制电路与一条所述第一电源电压信号线耦接。
在一些实施例中，所述第一控制电路被配置为，接收第一发光信号和第一使能信号，根据所述第一发光信号和所述第一使能信号，将所述第一电源电压信号传输至与该第一控制电路耦接的发光组件的第一极，以控制流过该发光组件的电流幅值。所述第一控制电路包括：处理器、模拟数字转换器和第一输出子电路；所述处理器被配置为，接收所述第一发光信号，并对所述第一发光信号进行格式转换，生成第二发光信号；所述模拟数字转换器被配置为，接收所述第一使能信号，生成参考信号；所述第一输出子电路与所述处理器、所述模拟数字转换器、所述第一电源电压信号线和所述发光组件的第一极耦接；所述第一输出子电路被配置为，根据来自所述处理器的所述第 二发光信号和来自所述模拟数字转换器的所述参考信号，将来自所述第一电源电压信号线的第一电源电压信号传输至所述发光组件的第一极。
在一些实施例中，所述第一输出子电路包括：第一晶体管、第一电阻、比较器和第二晶体管；所述第一晶体管的控制极与所述处理器耦接，所述第一晶体管的第二极与所述发光组件的第一极耦接；所述第一电阻的第一端与所述第一电源电压信号线耦接；所述比较器的正相输入端与所述模拟数字转换器的输出端耦接，所述比较器的负相输入端与所述第一电阻的第二端耦接；所述第二晶体管的控制极与所述比较器的输出端耦接，所述第二晶体管的第一极与所述第一电阻的第二端耦接，所述第二晶体管的第二极与所述第一晶体管的第一极耦接。
在一些实施例中，所述发光基板包括：第一控制芯片，所述第一控制芯片包括所述第一控制电路。所述第一控制芯片还包括：第一接口、第二接口、第三接口和第四接口；所述第一接口与所述第一控制电路中的处理器耦接，所述第一接口被配置为，接收所述第一发光信号，并将所述第一发光信号传输至所述处理器；所述第二接口与所述第一控制电路中的模拟数字转换器耦接，所述第二接口被配置为，接收所述第一使能信号，并将所述第一使能信号传输至所述模拟数字转换器；所述第三接口与所述第一电源电压信号线和所述第一控制电路中的第一输出子电路耦接，所述第三接口被配置为，接收来自所述第一电源电压信号线的第一电源电压信号，并将所述第一电源电压信号传输至所述第一输出子电路；所述第四接口与所述第一控制电路中的第一输出子电路和所述发光组件的第一极耦接，所述第四接口被配置为，将经过所述第一输出子电路传输的第一电源电压信号传输至所述发光组件的第一极。
在一些实施例中，所述发光基板还包括：设置于所述衬底上的第二控制电路，所述第二控制电路与所述多个第一控制电路耦接；所述第二控制电路被配置为，接收驱动信号，根据所述驱动信号，向每个所述第一控制电路传输第一发光信号和第一使能信号。
在一些实施例中，所述第二控制电路包括：时序控制子电路、数据处理子电路、存储器和放大子电路；所述时序控制子电路被配置为，生成时钟信号；所述数据处理子电路与所述时序控制子电路和所述多个第一控制电路耦接，所述数据处理子电路被配置为，接收所述驱动信号，根据所述驱动信号和来自所述时序控制子电路的所述时钟信号，输出第二使能信号，及向所述多个第一控制电路传输所述第一发光信号；所述存储器被配置为存储预设发 光模式的时序数据和发光电流数据；所述放大子电路与所述数据处理子电路、所述存储器和所述多个第一控制电路耦接；所述放大子电路被配置为，根据所述预设发光模式的时序数据和发光电流数据，将来自所述数据处理子电路的所述第二使能信号进行功率放大，生成所述第一使能信号，并向所述多个第一控制电路传输所述第一使能信号。
在一些实施例中，所述发光基板包括：第二控制芯片，所述第二控制芯片包括所述第二控制电路。所述第二控制芯片还包括：多个使能信号接口、多个发光信号接口和驱动信号接口；所述多个使能信号接口与所述第二控制电路中的放大子电路耦接，且每个使能信号接口与至少一个所述第一控制电路耦接，所述使能信号接口被配置为，接收来自所述放大子电路的第一使能信号，并将所述第一使能信号传输至其所耦接的第一控制电路；所述多个发光信号接口与所述第二控制电路中的数据处理子电路耦接，且每个发光信号接口与一个所述第一控制电路耦接，所述发光信号接口被配置为，接收来自所述数据处理子电路的所述第一发光信号，并将所述第一发光信号传输至其所耦接的第一控制电路；所述驱动信号接口与所述数据处理子电路耦接，所述驱动信号接口被配置为，接收所述驱动信号，并将所述驱动信号传输至所述数据处理子电路。
在一些实施例中，在所述多个第一控制电路呈阵列排布的情况下，每个所述使能信号接口与一行或一列所述第一控制电路耦接。
在一些实施例中，所述发光基板还包括设置于所述衬底上且间隔排布的多条第二电源电压信号线；至少两个发光分区中的发光组件的第二极与一条第二电源电压信号线耦接。
在一些实施例中，在所述多个发光分区呈阵列排布的情况下，同一行或同一列发光分区中的发光组件与一条所述第二电源电压信号线耦接。
在一些实施例中，所述第一电源电压信号线和所述第二电源电压信号线均沿列方向延伸，或者均沿行方向延伸。
在一些实施例中，所述第二电源电压信号线和所述第一电源电压信号线的材料相同且同层设置。
在一些实施例中，所述发光基板还包括绝缘层；沿垂直于所述衬底的方向，所述第一电源电压信号线和所述第二电源电压信号线位于所述绝缘层靠近所述衬底的一侧，所述发光组件和所述第一控制电路位于所述绝缘层远离所述衬底的一侧；所述绝缘层中设置有第一过孔和第二过孔，所述第一控制电路通过第一过孔与所述第一电源电压信号线耦接；所述发光组件的第二极 通过所述第二过孔与所述第二电源电压信号线耦接。
在一些实施例中，在所述发光基板还包括第二控制电路的情况下，所述发光基板还包括：设置于所述绝缘层远离所述衬底一侧的多条连接引线，所述多条连接引线被配置为将各所述第一控制电路和所述第二控制电路进行耦接。
在一些实施例中，所述发光组件包括：多个发光器件和多个导电图案；所述多个发光器件呈阵列排布；所述多个导电图案将所述多个发光器件依次串接；其中，所述多个发光器件依次串接所形成的线路中，处于线路两端的两个发光器件中的一个发光器件的阴极为所述发光组件的第一极，另一个发光器件的阳极为所述发光组件的第二极。
另一方面，提供一种发光模组。所述发光模组包括：如上述任一实施例所述的发光基板、柔性线路板和电源芯片。所述发光基板包括第一电源电压信号线和第二电源电压信号线；所述电源芯片通过所述柔性线路板与所述发光基板绑定，所述电源芯片被配置为，向所述第一电源电压信号线传输第一电源电压信号，并向所述第二电源电压信号线传输第二电源电压信号。
又一方面，提供一种显示装置。所述显示装置包括上述实施例中的发光模组和驱动芯片。所述发光模组中的发光基板包括多个第一控制电路和第二控制电路；所述驱动芯片与所述第二控制电路耦接，所述驱动芯片被配置为，向所述第二控制电路传输驱动信号。
再一方面，提供一种如上述任一实施例所述的发光基板的驱动方法，所述发光基板包括多个第一控制电路和第二控制电路。所述发光基板的驱动方法包括：所述第二控制电路接收驱动信号，根据所述驱动信号，向每个所述第一控制电路传输第一发光信号和第一使能信号；所述第一控制电路根据所述第一发光信号和所述第一使能信号，将来自第一电源电压信号线的第一电源电压信号传输至与该第一控制电路耦接的发光组件的第一极，以控制流过该发光组件的电流幅值。
在一些实施例中，在所述发光基板中的多个第一控制电路呈阵列排布的情况下，所述第二控制电路向每个所述第一控制电路传输第一使能信号，包括：在一个驱动周期内，所述第二控制电路逐行向每行第一控制电路传输所述第一使能信号，以控制各行第一控制电路依次打开，且上一行第一控制电路在下一行第一控制电路打开前关闭。
在一些实施例中，在所述发光基板中的多个第一控制电路呈阵列排布的情况下，所述第二控制电路向每个所述第一控制电路传输第一使能信号，包 括：在一个驱动周期内，所述第二控制电路同时向每行第一控制电路传输所述第一使能信号，以控制各行第一控制电路同时打开，且当前驱动周期每行第一控制电路在下个驱动周期每行第一控制电路打开前关闭。
在一些实施例中，在所述发光基板中的多个第一控制电路呈阵列排布的情况下，所述第二控制电路向每个所述第一控制电路传输第一使能信号，包括：在一个驱动周期内，所述第二控制电路依次向每行第一控制电路传输所述第一使能信号，以控制各行第一控制电路依次打开，且当前驱动周期每行第一控制电路在下个驱动周期每行第一控制电路打开前关闭。
在一些实施例中，在所述第一控制电路包括处理器、模拟数字转换器和第一输出子电路的情况下，所述第一控制电路根据所述第一发光信号和所述第一使能信号，将来自第一电源电压信号线的第一电源电压信号传输至与该第一控制电路耦接的发光组件的第一极，包括：所述处理器接收所述第一发光信号，并对所述第一发光信号进行格式转换，生成第二发光信号；所述模拟数字转换器接收所述第一使能信号，生成参考信号；所述第一输出子电路根据所述第二发光信号和所述参考信号，将来自所述第一电源电压信号线的第一电源电压信号传输至所述发光组件的第一极。
在一些实施例中，在所述第二控制电路包括时序控制子电路、数据处理子电路、存储器和放大子电路的情况下，所述第二控制电路接收驱动信号，根据所述驱动信号，向每个所述第一控制电路传输第一发光信号和第一使能信号包括：所述时序控制子电路生成时钟信号；所述数据处理子电路接收驱动信号，根据所述驱动信号和来自所述时序控制子电路的所述时钟信号，输出第二使能信号，并向所述多个第一控制电路传输所述第一发光信号；所述存储器中存储有预设发光模式的时序数据和发光电流数据；所述放大子电路根据来自所述存储器的预设发光模式的时序数据和发光电流数据，将来自所述数据处理子电路的所述第二使能信号进行功率放大，生成所述第一使能信号，并向所述多个第一控制电路传输所述第一使能信号。
附图说明
为了更清楚地说明本公开中的技术方案，下面将对本公开一些实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例的附图，对于本领域普通技术人员来讲，还可以根据这些附图获得其他的附图。此外，以下描述中的附图可以视作示意图，并非对本公开实施例所涉及的产品的实际尺寸、方法的实际流程、信号的实际时序等的限制。
图1为根据相关技术一些实施例的发光基板的结构图；
图2为根据一些实施例的发光基板的结构图；
图3为根据一些实施例的发光基板的另一种结构图；
图4为根据一些实施例的第一控制电路的一种结构图；
图5为根据一些实施例的发光基板的又一种结构图；
图6为根据一些实施例的发光基板的又一种结构图；
图7为根据一些实施例的发光基板的又一种结构图；
图8为根据一些实施例的发光基板的又一种结构图；
图9为根据一些实施例的发光基板的又一种结构图；
图10为根据一些实施例的第二控制芯片的一种结构图；
图11为图2中的发光基板Q区域的一种结构图；
图12为图11中的发光基板沿B-B’的剖视图；
图13为图2中的发光基板Q区域的另一种结构图；
图14为根据一些实施例的发光模组的一种结构图；
图15为根据一些实施例的显示装置的一种结构图；
图16为根据一些实施例的显示装置的另一种结构图；
图17为根据一些实施例的发光基板的又一种结构图；
图18为根据一些实施例的发光基板的又一种结构图；
图19为根据一些实施例的发光基板的一种驱动时序图；
图20为根据一些实施例的发光基板的另一种驱动时序图；
图21为根据一些实施例的发光基板的又一种驱动时序图。
具体实施方式
下面将结合附图，对本公开一些实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开所提供的实施例，本领域普通技术人员所获得的所有其他实施例，都属于本公开保护的范围。
除非上下文另有要求，否则，在整个说明书和权利要求书中，术语“包括(comprise)”及其其他形式例如第三人称单数形式“包括(comprises)”和现在分词形式“包括(comprising)”被解释为开放、包含的意思，即为“包含，但不限于”。在说明书的描述中，术语“一个实施例(one embodiment)”、“一些实施例(some embodiments)”、“示例性实施例(exemplary embodiments)”、“示例(example)”、“特定示例(specific example)”或“一些示例(some examples)”等旨在表明与该实施例或示例相关的特定 特征、结构、材料或特性包括在本公开的至少一个实施例或示例中。上述术语的示意性表示不一定是指同一实施例或示例。此外，所述的特定特征、结构、材料或特点可以以任何适当方式包括在任何一个或多个实施例或示例中。
以下，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本公开实施例的描述中，除非另有说明，“多个”的含义是两个或两个以上。
在描述一些实施例时，可能使用了“耦接”和“连接”及其衍伸的表达。例如，描述一些实施例时可能使用了术语“连接”以表明两个或两个以上部件彼此间有直接物理接触或电接触。又如，描述一些实施例时可能使用了术语“耦接”以表明两个或两个以上部件有直接物理接触或电接触。然而，术语“耦接”或“通信耦合(communicatively coupled)”也可能指两个或两个以上部件彼此间并无直接接触，但仍彼此协作或相互作用。这里所公开的实施例并不必然限制于本文内容。
“A、B和C中的至少一个”与“A、B或C中的至少一个”具有相同含义，均包括以下A、B和C的组合：仅A，仅B，仅C，A和B的组合，A和C的组合，B和C的组合，及A、B和C的组合。
“A和/或B”，包括以下三种组合：仅A，仅B，及A和B的组合。
在相关技术中，如图1所示，发光基板100’包括多个发光组件20’，每个发光组件20’与一条第一电源电压信号线LV1’和一条第二电源电压信号线LV2’耦接，第一电源电压信号线LV1’和第二电源电压信号线LV2’分别向发光组件20’传输第一电源电压信号和第二电源电压信号，以控制流过发光组件20’的电流幅值。由于第一电源电压信号线LV1’和第二电源电压信号线LV2’需要通过过孔引出至发光基板100’周边区域的表面，再通过柔性线路板与外部驱动电路绑定。在发光基板100’的材料的硬性材料(例如玻璃)的情况下，形成过孔难度较大，需要很高的生产工艺精度；而发光基板100’上的走线数量较多，受限于柔性线路板上金手指的极限间距和柔性线路板的尺寸，一个发光基板100’需要与多块柔性线路板连接才能满足要求，导致生产成本较高。
本公开的一些实施例提供一种发光基板100，如图2所示，该发光基板100具有多个发光分区S。包括：衬底10、多个发光组件20、多条第一电源电压信号线LV1和多个第一控制电路30。
多个发光组件20设置于衬底10上，一个发光组件20位于一个发光分区S内。
多条第一电源电压信号线LV1设置于衬底10上且间隔排布。
多个第一控制电路30设置于衬底10上，每个第一控制电路30与一个发光组件20的第一极耦接，且每条第一电源电压信号线LV1与至少两个第一控制电路30耦接。
第一控制电路30被配置为，将来自第一电源电压信号线LV1的第一电源电压信号传输至与该第一控制电路30耦接的发光组件20的第一极，以控制流过该发光组件20的电流幅值。
示例性地，第一电源电压信号为直流低电压信号。
在此基础上，发光基板100中的每个第一控制电路30与一个发光组件20的第一极耦接，且每条第一电源电压信号线LV1与至少两个第一控制电路30耦接，减少了发光基板100上的信号线(例如第一电源电压信号线LV1)数量，减小了信号线的压降，提高了信号的稳定性。并且，第一控制电路30将第一电源电压信号传输至与该第一控制电路30耦接的发光组件20的第一极，第一电源电压信号决定了传输至发光组件20的电流幅值；而第一控制电路30可以控制第一电源电压信号传输至发光组件20的时长；电流幅值和时长共同决定了发光组件20的发光亮度。
因此，本公开的实施例提供的发光基板100，每个第一控制电路30与一个发光组件20的第一极耦接，且每条第一电源电压信号线LV1与至少两个第一控制电路30耦接，第一控制电路30将来自第一电源电压信号线LV1的第一电源电压信号传输至与该第一控制电路30耦接的发光组件20的第一极，以控制流过该发光组件20的电流幅值和时长。
这样一来，通过第一控制电路30控制第一电源电压信号传输至发光组件20的时长，且第一电源电压信号决定了传输至发光组件20的电流幅值，通过该电流幅值和时长共同控制发光组件20的发光亮度。并且，相比于一条第一电源电压信号线LV1与一个发光组件20耦接，减少了发光基板100的信号线(例如第一电源电压信号线LV1)的数量，简化了发光基板100的走线设计。由于信号线数量减少，使得各信号线之间的间隔相对增大，因此，可以适当地增大信号线的宽度，减小信号线的厚度，从而减小信号线的阻抗，减小了信号线的压降，提高了信号的稳定性。在采用例如柔性线路板将外部驱动电路与发光基板100进行绑定时，由于走线数量减少，故柔性线路板的数量也可以相应减少，从而降低生产成本。
在一些实施例中，如图2所示，多个发光分区S呈阵列排布，多个第一控制电路30呈阵列排布。
示例性地，如图2所示，沿水平方向X排列成一排的发光分区S称为一行发光分区，沿竖直方向Y排列成一排的发光分区S称为一列发光分区。沿水平方向X排列成一排的第一控制电路30称为一行第一控制电路，沿竖直方向Y排列成一排的第一控制电路30称为一列第一控制电路。
如图3所示，同一行发光分区S中的发光组件20通过一行第一控制电路30与一条第一电源电压信号线LV1耦接，或者，如图2所示，同一列发光分区S中的发光组件20通过一列第一控制电路30与一条第一电源电压信号线LV1耦接。
示例性地，发光基板100包括n行m列发光分区S和n行m列第一控制电路30，其中，n和m均为正整数，一个发光分区S对应一个第一控制电路30，在同一行发光分区S中的发光组件20通过一行第一控制电路30与一条第一电源电压信号线LV1耦接的情况下，第一电源电压信号线LV1沿行方向(即图3中的水平方向X)延伸，此时，第一电源电压信号线LV1的条数为n条；在同一列发光分区S中的发光组件20通过一列第一控制电路30与一条第一电源电压信号线LV1耦接的情况下，第一电源电压信号线LV1沿列方向(即图2中的竖直方向Y)延伸，此时，第一电源电压信号线LV1的条数为m条。
因此，相比于在如图1所示的发光基板100’中，一条第一电源电压信号线LV1’与一个发光分区S’中的发光组件20’耦接的情况下，第一电源电压信号线LV1’的条数为(n×m)条，本公开的实施例中的发光基板100中的第一电源电压信号线LV1的数量减少，例如，当第一电源电压信号线LV1沿行方向延伸时，第一电源电压信号线LV1的条数为n条，当第一电源电压信号线LV1沿列方向延伸时，第一电源电压信号线LV1的条数为m条，降低了发光基板100的信号线的数量，简化了发光基板100的走线设计。由于信号线数量减少，使得各信号线之间的设计间隔可以相对增大，因此，可以适当地增大信号线的宽度，从而减小信号线的阻抗，降低信号线上的压降，提高信号的稳定性。
在一些实施例中，参考图4，第一控制电路30被配置为，接收第一发光信号EM1和第一使能信号PW1，根据第一发光信号EM1和第一使能信号PW1，将第一电源电压信号V1传输至与该第一控制电路30耦接的发光组件20的第一极，以控制流过该发光组件20的电流幅值。
需要说明的是，参考图4，V1表示来自第一电源电压信号线LV1的第一电源电压信号。
其中，第一控制电路30接收的第一发光信号EM1为该第一控制电路30 所耦接的发光组件20的发光数据，示例性地，该第一发光信号EM1包括脉冲宽度调制(Pulse Width Modulation，PWM)信号。第一控制电路30接收的第一使能信号PW1为驱动该第一控制电路30打开的信号，示例性地，该第一使能信号PW1包括功率(Power)信号。
如图4所示，第一控制电路30包括：处理器31、模拟数字转换器ADC和第一输出子电路32。
处理器31被配置为，接收第一发光信号EM1，并对第一发光信号EM1进行格式转换，生成第二发光信号EM2。
需要说明的是，处理器31将第一发光信号EM1进行转换生成第二发光信号EM2，以匹配第一控制电路30的运行所需信号的格式，具体转换方式在此不做限定，本领域技术人员可以根据实际产品的需要进行设定。示例性地，第一发光信号EM1和第二发光信号EM2可以均为PWM信号，但两者格式不同。
模拟数字转换器ADC被配置为，接收第一使能信号PW1，生成参考信号REF。
可以理解的是，第一使能信号PW1为模拟信号，参考信号REF为数字信号。模拟数字转换器ADC根据接收的不同电位的第一使能信号PW1，相应的生成不同电位的参考信号REF。
第一输出子电路32被配置为，根据来自处理器31的第二发光信号EM2和来自模拟数字转换器ADC的参考信号REF，将来自第一电源电压信号线LV1的第一电源电压信号V1传输至发光组件20的第一极。
其中，各第一控制电路30生成的第二发光信号EM2的电位和参考信号REF的电位不完全相同。在此情况下，第一输出子电路32在第二发光信号EM2和参考信号REF的控制下打开，将第一电源电压信号传输至发光组件20的第一极，通过调整第二发光信号EM2的电位，使得第一控制电路30的打开的时间不完全相同，以调整第一电源电压信号V1传输至发光组件20的第一极的时长，控制发光组件20的工作时间，并通过调整参考信号REF的电位，控制流过该发光组件20的电流幅值。
需要说明的是，在发光基板100应用于显示装置时，各第一控制电路30接收的第一使能信号PW1的电位可以相同，或者可以不同。在各第一控制电路30接收的第一使能信号PW1的电位相同的情况下，各第一控制电路30生成的参考信号REF相同，可以根据接收的不同的第一发光信号EM1，调整第一电源电压信号V1传输至发光组件20的第一极的时长。在各第一控制电路 30接收的第一使能信号PW1的电位不同的情况下，各第一控制电路30生成的参考信号REF不同，调整流过发光组件20的电流幅值。因此，根据接收的第一使能信号PW1和第一发光信号EM1，控制流过该发光组件20的电流幅值和时长，以调整发光分区S中的发光组件20的亮度。
示例性地，如图5所示，第一输出子电路32包括：第一晶体管M1、第一电阻R1、比较器A和第二晶体管M2。
第一晶体管M1的控制极与处理器31耦接，第一晶体管M1的第二极与发光组件20的第一极耦接。
第一电阻R1的第一端与第一电源电压信号线LV1耦接。
比较器A的正相输入端与模拟数字转换器ADC的输出端耦接，比较器A的负相输入端与第一电阻R1的第二端耦接。
第二晶体管M2的控制极与比较器A的输出端耦接，第二晶体管M2的第一极与第一电阻R1的第二端耦接，第二晶体管M2的第二极与第一晶体管M1的第一极耦接。
在此情况下，比较器A根据经过第一电阻R1传输的第一电源电压信号V1和来自模拟数字转换器ADC的参考信号REF进行比较，将比较后的信号传输至第二晶体管M2，控制第二晶体管M2开启。由于不同发光组件20所耦接的第一控制电路30接收的第一使能信号PW1的电位不完全相同，根据第一使能信号PW1生成的参考信号REF的电位也不完全相同，因此，可以通过调整第一使能信号PW1的电位，生成电位不完全相同的参考信号REF，控制流过第二晶体管M2的电流幅值，从而控制流过发光组件20的电流幅值。
并且，处理器31将第一发光信号EM1进行格式转换，生成第二发光信号EM2，第一晶体管M1在第二发光信号EM2的控制下开启。由于不同发光组件20对应的第一发光信号EM1的电位不完全相同，第二发光信号EM2的电位也不完全相同，因此，可以通过调整的第一发光信号EM1的电位，生成电位不完全相同的第二发光信号EM2，控制各第一控制电路30中的第一晶体管M1的导通时间，从而控制第一电源电压信号V1经过第一输出子电路32传输至发光组件20的第一极的时长。
需要说明的是，上述的晶体管可以为薄膜晶体管、场效应晶体管或其他特性相同的开关器件，本公开的实施例对此并不设限。上述的晶体管的控制极为晶体管的栅极，第一极为晶体管的源极和漏极中一者，第二极为晶体管的源极和漏极中另一者。由于晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在结构上可以是没有区别的，也就是说，本公开的实施例 中的晶体管的第一极和第二极在结构上可以是没有区别的。示例性的，在晶体管为P型晶体管的情况下，晶体管的第一极为源极，第二极为漏极；示例性的，在晶体管为N型晶体管的情况下，晶体管的第一极为漏极，第二极为源极。
在一些实施例中，如图6所示，发光基板100包括第一控制芯片101。第一控制芯片101包括第一控制电路30。
第一控制芯片101还包括：第一接口P1、第二接口P2、第三接口P3和第四接口P4。
第一接口P1与第一控制电路30中的处理器31耦接。
第二接口P2与第一控制电路30中的模拟数字转换器ADC耦接。
第三接口P3与第一电源电压信号线LV1和第一控制电路30中的第一输出子电路32耦接。
第四接口P4与第一控制电路30中的第一输出子电路32和发光组件20的第一极耦接。
其中，第一接口P1被配置为，接收第一发光信号EM1，并将第一发光信号EM1传输至处理器31。
第二接口P2被配置为，接收第一使能信号PW1，并将第一使能信号PW1传输至模拟数字转换器ADC。
第三接口P3被配置为，接收来自第一电源电压信号线LV1的第一电源电压信号V1，并将第一电源电压信号传输至第一输出子电路32。
第四接口P4被配置为，将经过第一输出子电路32传输的第一电源电压信号，传输至发光组件20的第一极。
在此情况下，第一控制芯片101根据接收的第一发光信号EM1和第一使能信号PW1，控制第一电源电压信号V1传输至与其耦接的发光组件20的时长，从而控制流过与该第一控制芯片101耦接的发光组件20的电流的幅值和时长。并且，第一控制芯片101的接口数量较少，第一控制芯片101的尺寸在微米尺寸量级，使得第一控制芯片101对发光基板100中的有效出光区域的面积的影响较小。
在一些实施例中，如图7所示，发光基板100还包括设置于衬底10上的第二控制电路40。第二控制电路40与多个第一控制电路30耦接。
其中，第二控制电路40被配置为，接收驱动信号，根据该驱动信号，向每个第一控制电路30传输第一发光信号EM1和第一使能信号PW1。
在一些实施例中，如图8所示，第二控制电路40包括：时序控制子电路 41、数据处理子电路42、存储器43和放大子电路44。
数据处理子电路42与时序控制子电路41和多个第一控制电路30耦接。
放大子电路44与数据处理子电路42、存储器43和多个第一控制电路30耦接。
时序控制子电路41被配置为生成时钟信号。
数据处理子电路42被配置为，接收驱动信号DRV，根据驱动信号DRV和来自时序控制子电路41的时钟信号，输出第二使能信号PW2，及向多个第一控制电路30传输第一发光信号EM1。
存储器43被配置为存储预设发光模式的时序数据和发光电流数据。
需要说明的是，在发光基板100应用于显示装置的情况下，本领域技术人员可以根据显示装置的显示模式设定发光基板100的发光模式，并将预设发光模式的时序数据和发光电流数据进行存储。
放大子电路44被配置为，根据预设发光模式的时序数据和发光电流数据，将来自数据处理子电路42的第二使能信号PW2进行功率放大，生成第一使能信号PW1，并向多个第一控制电路30传输第一使能信号PW1。
在此情况下，在第二控制电路40开始工作时，时序控制子电路41生成时钟信号，数据处理子电路42根据该时钟信号和接收的驱动信号DRV，向多个第一控制电路30传输第一发光信号EM1，向放大子电路44传输第二使能信号PW2。放大子电路44根据存储器43中存储的预设发光模式的时序数据和发光电流数据，将第二使能信号PW2进行功率放大，生成第一使能信号PW1，并将该第一使能信号PW1传输至多个第一控制电路30，控制第一控制电路30的电流大小，以驱动多个第一控制电路30工作，从而实现对与第一控制电路30耦接的发光组件20的工作状态的控制。此外，放大子电路44将第二使能信号PW2进行功率放大，可以提高第二控制芯片102的带载能力。
在一些实施例中，发光基板100包括第二控制芯片102。如图9所示，第二控制芯片102包括第二控制电路40。
第二控制芯片102还包括：多个使能信号接口E、多个发光信号接口L和驱动信号接口D。
多个使能信号接口E与第二控制电路40中的放大子电路44耦接，且每个使能信号接口E与至少一个第一控制电路30耦接。
多个发光信号接口L与第二控制电路40中的数据处理子电路42耦接，且每个发光信号接口L与一个第一控制电路30耦接。
例如，在发光基板100包括n行m列第一控制电路30的情况下，如图9 所示，第1行第1列的第一控制电路30与发光信号接口L(1_1)耦接，第2行第1列的第一控制电路30与发光信号接口L(1_2)耦接，第n行第1列的第一控制电路30与发光信号接口L(1_n)耦接，第1行第m列的第一控制电路30与发光信号接口L(m_1)耦接，第2行第m列的第一控制电路30与发光信号接口L(m_2)耦接，第n行第m列的第一控制电路30与发光信号接口L(m_n)耦接。
驱动信号接口D与数据处理子电路42耦接。
使能信号接口E被配置为，接收来自放大子电路44的第一使能信号PW1，并将第一使能信号PW1传输至其所耦接的第一控制电路30。
发光信号接口L被配置为，接收来自数据处理子电路42的第一发光信号EM1，并将第一发光信号EM1传输至其所耦接的第一控制电路30。
驱动信号接口D被配置为，接收驱动信号DRV，并将驱动信号DRV传输至数据处理子电路42。
其中，驱动信号接口D可以采用SPI(串行外设接口，Serial Peripheral Interface)。如图10所示，驱动信号接口D包括用于接收由主设备产生的串行时钟信号的SCLK(Serial Clock)接口，用于接收由主设备传输的数据信号的MOSI(Master Output/Slave Input，主机输出/从机输入数据)接口，以及用于接收主设备传输的垂直帧同步信号的垂直帧同步信号接口Vsync，即，驱动信号接口D接收的驱动信号DRV包括SCLK信号、MOSI信号和垂直帧同步信号Vsync。示例性地，在发光基板100用于显示装置时，主设备为显示装置，从设备为第二控制芯片102，驱动信号接口D接收的驱动信号可以来自于显示装置中的SOC(System on Chip，系统芯片)或者T-con(Timing Controller，时序控制器)。
此外，如图10所示，第二控制芯片102还包括控制信号接口EN、MISO(Master Input/Slave Output，主机输入/从机输出数据)接口和CS(Chip Select)接口。控制信号接口EN用于接收来自主设备的控制信号，以控制第二控制芯片102开始工作，例如，当控制信号接口EN接收的信号为高电平时，第二控制芯片102开始工作，当控制信号接口EN接收的信号为低电平时，第二控制芯片102停止工作。MISO接口用于向主设备传输来自第二控制芯片102的数据。CS接口接收的信号用于驱动第二控制芯片102开始传输数据，例如，当CS接口接收的信号低电平有效时，第二控制芯片102进行数据传输。
在一些实施例中，在多个第一控制电路30呈阵列排布的情况下，每个使能信号接口E与一行或一列第一控制电路30耦接。
可以理解的是，当每个使能信号接口E与一行第一控制电路30耦接，每个使能信号接收E输出的信号可以控制一行第一控制电路30工作；当每个使能信号接口E与一列第一控制电路30耦接，每个使能信号接收E输出的信号可以控制一列第一控制电路30工作。
例如，在发光基板100包括n行m列第一控制电路30的情况下，一个使能信号接口E可以与一行第一控制电路30耦接，如图9所示，第1行第一控制电路与使能信号接口E(1)耦接，第2行第一控制电路与使能信号接口E(2)耦接，第n行第一控制电路与使能信号接口E(n)耦接。
在一些实施例中，如图2所示，发光基板100还包括多条第二电源电压信号线LV2。多条第二电源电压信号线LV2设置于衬底10上且间隔排布。
至少两个发光分区S中的发光组件20的第二极与一条第二电源电压信号线LV2耦接。
其中，第二电源电压信号线LV2被配置为向与其耦接的发光组件20的第二极传输第二电源电压信号。
需要说明的是，参考图4，V2表示来自第二电源电压信号线LV2的第二电源电压信号。
示例性地，该第二电源电压信号V2为直流高电压信号。
在此情况下，由于第二电源电压信号V2传输至发光组件20的第二极，第一电源电压信号V1通过第一控制电路30传输至发光组件20的第一极，因此，可以通过控制第一控制电路30将第一电源电压信号V1传输至发光组件20的时长，控制发光组件20的工作时长。并且，发光基板100中的至少两个发光分区S中的发光组件20的第二极与一条第二电源电压信号线LV2耦接，第二电源电压信号线LV2的数量减少，简化了发光基板100的走线设计。由于信号线数量减少，使得各信号线之间的间隔相对增大，因此，可以适当地增大信号线的宽度，从而减小信号线的阻抗，降低信号线上的压降，提高信号的稳定性。在采用柔性线路板将发光基板100与外部驱动电路进行绑定时，由于走线数量减少，故柔性线路板的数量也相应减少，从而降低生产成本。
在一些实施例中，在多个发光分区S呈阵列排布的情况下，同一行或同一列发光分区中的发光组件20与一条第二电源电压信号线LV2耦接。
示例性地，发光基板100包括n行m列发光分区S和n行m列第一控制电路30，如图3所示，在同一行发光分区S中的发光组件20与一条第二电源电压信号线LV2耦接的情况下，第二电源电压信号线LV2沿行方向(图3中的水平方向X)延伸，此时，第二电源电压信号线LV2的条数为n条；如图 2所示，在同一列发光分区S中的发光组件20与一条第二电源电压信号线LV2耦接的情况下，第二电源电压信号线LV2沿列方向(图2中的竖直方向Y)延伸，此时，第二电源电压信号线LV2的条数为m条。
在此情况下，相比于在如图1所示的发光基板100’中，一条第二电源电压信号线LV2’与一个发光分区S’中的发光组件20’耦接的情况下，第二电源电压信号线LV2’的条数为(n×m)条，本公开的实施例中的发光基板100中的第二电源电压信号线LV2的数量减少，例如，当第二电源电压信号线LV2沿行方向延伸，第二电源电压信号线LV2的条数为n条，当第二电源电压信号线LV2沿列方向延伸，此时，第二电源电压信号线LV2的条数为m条，降低了发光基板100的信号线的数量。由于信号线数量减少，使得各信号线之间的间隔相对增大，因此，可以适当地增加信号线的宽度，从而减小信号线的阻抗，降低信号线上的压降，提高了信号的稳定性。并且，在通过柔性线路板将发光基板100与外部驱动电路进行绑定时，由于走线数量减少，故柔性线路板的数量也相应减少，从而降低生产成本。
在一些实施例中，第一电源电压信号线LV1和第二电源电压信号线LV2均沿列方向延伸，或者均沿行方向延伸。
示例性地，发光基板100包括n行m列发光分区S和n行m列第一控制电路30，第一电源电压信号线LV1和第二电源电压信号线LV2沿行方向延伸，此时，第一电源电压信号线LV1和第二电源电压信号线LV2的总条数为(2×n)条；在同一列发光分区S中的发光组件20与一条第二电源电压信号线LV2耦接的情况下，第一电源电压信号线LV1和第二电源电压信号线LV2沿列方向延伸，此时，第一电源电压信号线LV1和第二电源电压信号线LV2的总条数为(2×m)条。
因此，相比于发光基板100中，一条第二电源电压信号线LV2和一条第一电源电压信号线LV1与一个发光分区S中的发光组件20耦接的情况下，第一电源电压信号线LV1和第二电源电压信号线LV2的总条数为2×(n×m)条，本公开的实施例中的发光基板100中的第一电源电压信号线LV1和第二电源电压信号线LV2的数量均减少，例如，当第一电源电压信号线LV1和第二电源电压信号线LV2沿行方向延伸时，第一电源电压信号线LV1和第二电源电压信号线LV2的总条数为(2×n)条，当第一电源电压信号线LV1和第二电源电压信号线LV2沿列方向延伸时，第一电源电压信号线LV1和第二电源电压信号线LV2的总条数为(2×m)条，降低了发光基板100的信号线的数量，简化了发光基板100的走线设计，由于信号线数量减少，使得各信号线之间的 间隔相对增大，因此，可以适当地增加信号线的宽度，从而减小信号线的阻抗，降低信号线上的压降，提高信号的稳定性。并且，在采用柔性线路板将外部驱动电路与发光基板100进行绑定工艺时，由于走线数量减少，故柔性线路板的数量也相应减少，从而降低生产成本。
在一些实施例中，第二电源电压信号线LV2和第一电源电压信号线LV1材料相同，且同层设置。
在工艺上，第二电源电压信号线LV2和第一电源电压信号线LV1可以同步形成，从而简化生产工序。
在一些实施例中，如图11和图12所示，发光基板100还包括绝缘层50。
沿垂直于衬底10的方向，第一电源电压信号线LV1和第二电源电压信号线LV2位于绝缘层50靠近衬底10的一侧，发光组件20和第一控制电路30位于绝缘层50远离衬底10的一侧。
绝缘层50中设置有第一过孔51和第二过孔52。第一控制电路30通过第一过孔51与第一电源电压信号线LV1耦接，发光组件20的第二极通过第二过孔52与第二电源电压信号线LV2耦接。
其中，发光基板100还包括设置于绝缘层50远离衬底10一侧的连接图案103，连接图案103覆盖第一过孔51和第二过孔52，第一控制电路30通过连接图案103和第一过孔51与第一电源电压信号线LV1耦接，第一控制电路30还通过连接图案103与发光组件20的第一极耦接，发光组件20的第二极通过连接图案103和第二过孔52与第二电源电压信号线LV2耦接。
示例性地，绝缘层50的材料可以采用包括氮化硅(Si xN y)或氧化硅(SiO x)等无机材料。
在一些实施例中，如图7所示，在发光基板100还包括第二控制电路40的情况下，发光基板100还包括：设置于绝缘层50远离衬底10一侧的多条连接引线60。
多条连接引线60被配置为将各第一控制电路30和第二控制电路40进行耦接。
在一些实施例中，在发光基板100包括第一控制芯片101和第二控制芯片102的情况下，多条连接引线60中的一部分用于耦接第二控制芯片102中的使能信号接口E与每行第一控制芯片101中的第二接口P2，多条连接引线60中的另一部分用于耦接第二控制芯片102中的发光信号接口L与各第一控制芯片101中的第一接口P1。例如，在发光基板100包括呈n行m列排布的第一控制芯片101的情况下，第1行的第一控制芯片101中的第二接口P2， 通过连接引线60与第二控制芯片102中的使能信号接口E(1)耦接，第n行的第一控制芯片101中的第二接口P2，通过连接引线60与第二控制芯片102中的使能信号接口E(n)耦接；第1行第1列的第一控制芯片101中的第一接口P1，通过连接引线60与第二控制芯片102中的发光信号接口L(1_1)耦接，第n行第m列的第一控制芯片101中的第一接口P1，通过连接引线60与第二控制芯片102中的发光信号接口L(m_n)耦接。
示例性地，连接引线60的材料可以采用包括铜(Cu)或铝(Al)等金属材料。
在一些实施例中，如图13所示，发光组件20包括：多个发光器件21和多个导电图案22。多个发光器件21呈阵列排布。多个导电图案22将多个发光器件21依次串接。
多个发光器件31依次串接所形成的线路中，位于线路两端的两个发光器件31中的一个发光器件21的阴极为发光组件20的第一极，另一个发光器件31的阳极为发光组件20的第二极。
示例性地，发光器件31可以采用包括微型发光二极管(micro LED)或迷你发光二极管(mini LED)等无机发光器件。
需要说明的是，多个发光器件21依次串接即为多个发光器件21相互串联。此外，多个发光器件21还可以相互并联，或者多个发光器件21中的一部分发光器件21串联且与另一部分发光器件21并联。本领域技术人员可以根据实际情况选择发光分区S中的发光器件21的连接方式，本公开在此不做限定。
示例性地，在多个发光器件21相互串联的情况下，在一发光分区S中，串联同一行发光器件21的导电图案22的形状呈折线状，串联同一列发光器件21的导电图案22的形状呈条状；或者，串联同一列发光器件21的导电图案22的形状呈折线状，串联同一行发光器件21的导电图案22的形状呈条状。
由于沿垂直于衬底10的方向，多个导电图案22位于第一电源电压信号线LV1和第二电源电压信号线LV2远离衬底10的一侧，多个导电图案22与第一电源电压信号线LV1和第二电源电压信号线LV2不同层，因此，导电图案22对第一电源电压信号线LV1和第二电源电压信号线LV2的走线空间的影响较小，避免因第一电源电压信号线LV1和第二电源电压信号线LV2的走线空隙减小，使得第一电源电压信号线LV1和第二电源电压信号线LV2的宽度减小而导致第一电源电压信号线LV1和第二电源电压信号线LV2的阻抗增大，影响信号传输效果。
在发光基板100包括连接图案103的情况下，导电图案22与连接图案103 的材料相同且同层设置。在工艺上，导电图案22与连接图案103在同一次成膜工艺中形成。需要说明的是，在本公开的一些实施例中，第一控制电路30可以设置于发光分区S外且与发光组件20毗邻，如图13所示；在本公开的另一些实施例中，第一控制电路30可以直接设置于发光分区S内，例如，第一控制电路30在衬底上的正投影与导电图案22、连接图案103、发光器件31、第一电源电压信号线LV1和第二电源电压信号线LV2中的任一者在衬底上的正投影可以均不重合；当然第一控制电路30在衬底上的正投影也可以与上述结构中的任一者在衬底上的正投影存在部分交叠。
本公开的一些实施例提供一种发光模组200，如图14所示，包括：如上述任一实施例中的发光基板100、柔性线路板201和电源芯片202。
其中，发光基板100包括第一电源电压信号线LV1和第二电源电压信号线LV2。
电源芯片202通过柔性线路板201与发光基板100绑定。电源芯片202被配置为向第一电源电压信号线LV1传输第一电源电压信号，并向第二电源电压信号线LV2传输第二电源电压信号。
在一些实施例中，参考图7，发光基板100包括第二控制电路40的情况下，电源芯片202被配置为向第二控制电路40传输第三电源电压信号和第四电源电压信号。
示例的，在发光基板100包括第二控制芯片102的情况下，如图10所示，第二控制芯片102还包括第三电源电压信号接口VDD和第四电源电压信号接口GND。第三电源电压信号接口VDD被配置为接收来自电源芯片202的第三电源电压信号，第四电源电压信号接口GND被配置为接收来自电源芯片202的第四电源电压信号。
其中，第三电源电压信号为直流高电压信号，例如可以为来自电源的正极的信号，第四电源电压信号为直流低电压信号，例如可以为来自电源的负极的信号。第三电源电压信号的电位高于第二电源电压信号的电位。第四电源电压信号的电位等于第一电源电压信号的电位。
本公开的实施例还提供一种显示装置300，如图15所示，包括：如上述实施例中的发光模组200和驱动芯片301。
发光模组200中的发光基板100包括多个第一控制电路30和第二控制电路40。驱动芯片301与第二控制电路40耦接。驱动芯片301被配置为，向第二控制电路40传输驱动信号。
示例性地，该驱动芯片301可以为SOC(System on Chip，系统芯片)或 者T-con(Timing Controller，时序控制器)。
在此情况下，驱动芯片301向第二控制电路40传输至驱动信号，第二控制电路40接收驱动信号，根据该驱动信号，向每个第一控制电路30传输第一发光信号和第一使能信号。第一控制电路30接收第一发光信号和第一使能信号，根据第一发光信号和第一使能信号，将第一电源电压信号传输至与该第一控制电路30耦接的发光组件20的第一极，以控制流过该发光组件20的电流幅值，从而控制发光组件20的发光亮度。
在一些实施例中，在显示装置300为液晶显示装置的情况下，该发光模组200为背光模组。如图16所示，显示装置300还包括阵列基板400、对置基板500和液晶层600。对置基板500与阵列基板400相对设置，发光模组200设置于阵列基板400远离对置基板500的一侧。液晶层600位于对置基板500和阵列基板400之间。
示例性地，在显示装置300进行显示的过程中，液晶层600中的液晶分子在阵列基板400中的像素电极401和公共电极402之间形成的电场的作用下发生偏转，发光模组200发出的光，经过液晶层600，从对置基板500远离发光模组200的一侧出射。
上述显示装置300可以是显示不论运动(例如，视频)还是固定(例如，静止图像)的且不论文字还是的图像的任何装置。更明确地说，预期所述实施例可实施在多种电子装置中或与多种电子装置关联，所述多种电子装置例如(但不限于)移动电话、无线装置、个人数据助理(PDA)、手持式或便携式计算机、GPS接收器/导航器、相机、MP4视频播放器、摄像机、游戏控制台、手表、时钟、计算器、电视监视器、平板显示器、计算机监视器、汽车显示器(例如，里程表显示器等)、导航仪、座舱控制器和/或显示器、相机视图的显示器(例如，车辆中后视相机的显示器)、电子相片、电子广告牌或指示牌、投影仪、建筑结构、包装和美学结构(例如，对于一件珠宝的图像的显示器)等。
本公开的实施例又提供一种发光基板的驱动方法，该发光基板为上述任一实施例中的发光基板100。参考图8，发光基板100包括第一控制电路30和第二控制电路40。
发光基板100的驱动方法包括：
第二控制电路40接收驱动信号DRV，根据驱动信号DRV，向每个第一控制电路30传输第一发光信号EM1和第一使能信号PW1。
第一控制电路30根据第一发光信号EM1和第一使能信号PW1，将来自第一电源电压信号线LV1的第一电源电压信号V1传输至与该第一控制电路 30耦接的发光组件20的第一极，以控制流过该发光组件20的电流幅值。
在此情况下，第二控制电路40根据驱动信号DRV，向发光分区S中的发光组件20所耦接的第一控制电路30传输第一发光信号EM1和第一使能信号PW1，不同发光组件20所耦接的第一控制电路30接收的第一发光信号EM1的电位不完全相同，接收的第一使能信号PW1的电位不完全相同。第一控制电路30根据第一使能信号PW1和第一发光信号EM1，将第一电源电压信号V1传输至与该第一控制电路30耦接的发光组件20的第一极，通过调整第一发光信号EM1的电位，控制发光组件20的工作时长，并通过调整第一使能信号PW1的电位，控制流过该发光组件20的电流幅值，从而实现对各发光分区S中的发光组件20的发光亮度的控制。
在一些实施例中，在发光基板100中的多个第一控制电路30呈阵列排布的情况下，第二控制电路40向每个第一控制电路30传输第一使能信号PW1，包括：
在一个驱动周期内，第二控制电路40逐行向每行第一控制电路传输第一使能信号PW1，以控制各行第一控制电路30依次打开，且上一行第一控制电路在下一行第一控制电路打开前关闭。
示例性地，参考图17，多个发光分区(S(1_1)……S(m_n))呈n行m列排布，例如，发光分区S(1_1)为第1行第m列发光分区，发光分区S(m_n)为第n行第m列发光分区，多个第一控制电路30呈n行m列排布。在一个驱动周期F(如图19所示)内，第二控制电路40对第1行至第n行的第一控制电路30进行逐行传输第一使能信号(PW1(1)……PW1(n))，控制各行第一控制电路30依次打开，并且，第二控制电路40向每个第一控制电路30传输第一发光信号EM1，例如，在第1行第一控制电路30接收第一使能信号PW1(1)时，第二控制电路40向第1行第1列至第m列的第一控制电路30传输第一发光信号EM1。
在此情况下，第一控制电路30在第一使能信号PW1和第一发光信号EM1的控制下打开，将来自第一电源电压信号线LV1的第一电源电压信号V1传输至与该第一控制电路30耦接的发光分区S中的发光组件20的第一极，以使发光组件20工作。
示例性地，参考图18，在发光基板100包括第一控制芯片101和第二控制芯片102的情况下，第二控制芯片102中的使能信号接口E与第一控制芯片101中的第二接口P2耦接，每个使能信号接口E与一行第一控制电路30耦接，例如，使能信号接口E(1)与第1行的第一控制电路30耦接，使能信 号接口E(2)与第2行的第一控制电路30耦接，使能信号接口E(n)与第n行的第一控制电路30耦接。在此情况下，第二控制芯片102的多个使能信号接口(E(1)、E(2)……E(n-1)、E(n))依次向第1行至第n行的第一控制电路30传输第一使能信号(PW1(1)……PW1(n))，以控制第1行至第n行的第一控制电路30依次打开。第二控制芯片102中的发光信号接口L与第一控制芯片101中的第一接口P1耦接，每个发光信号接口L与一个第一控制电路30耦接，并向与其耦接的第一控制电路30传输第一发光信号EM1，例如，发光信号接口L(m_n)与第n行第m列的第一控制电路30耦接，发光信号接口L(m_n)向第n行第m列的第一控制电路30传输第n行第m列的发光分区S(m_n)对应的第一发光信号。
在此基础上，第一控制电路30在第一发光信号EM1和第一使能信号PW1的控制下打开，将第一电源电压信号V1传输至其所耦接的发光组件20的第一极，以使该发光组件20工作。
并且，上一行第一控制电路在下一行第一控制电路打开前关闭，例如，第1行的第一控制电路30关闭后，第2行的第一控制电路30开启，第2行的第一控制电路30关闭后，第3行的第一控制电路30开启，依次类推，直至第(n-1)行的第一控制电路30关闭，第n行的第一控制电路30开启。在此情况下，发光基板100中的第1行至第n行的发光组件20逐行工作，缩短每一行的发光组件20的工作时长，从而可以降低发光基板100的功耗。
在一些实施例中，在发光基板100中的多个第一控制电路30呈阵列排布的情况下，第二控制电路40向每个第一控制电路30传输第一使能信号PW1，包括：
在一个驱动周期内，第二控制电路40同时向每行第一控制电路传输第一使能信号PW1，以控制各行第一控制电路同时打开，且当前驱动周期每行第一控制电路在下个驱动周期每行第一控制电路打开前关闭。
示例性地，参考图17，多个第一控制电路30呈n行m列排布，在一个驱动周期F(如图20所示)内，第二控制电路40同时向第1行至第n行的第一控制电路30传输第一使能信号PW1，控制各行第一控制电路30同时打开，并且，第二控制电路40向每个第一控制电路30传输第一发光信号EM1，在此情况下，第一控制电路30在第一使能信号PW1和第一发光信号EM1的控制下打开，将来自第一电源电压信号线LV1的第一电源电压信号V1传输至与该第一控制电路30耦接的发光分区S中的发光组件20的第一极，以使发光组件20工作。
示例性地，参考图18，在发光基板100包括第一控制芯片101和第二控制芯片102的情况下，每个使能信号接口E与一行第一控制电路30耦接，第二控制芯片102的多个使能信号接口(E(1)、E(2)……E(n-1)、E(n))同时向第1行至第n行的第一控制电路30传输第一使能信号(PW1(1)……PW1(n))，以控制第1行至第n行的第一控制电路30同时打开。第二控制芯片102中的每个发光信号接口L与一个第一控制电路30耦接，并向与其耦接的第一控制电路30传输第一发光信号EM1，第一控制电路30在第一发光信号PW1和第一使能信号EM1的控制下打开，将第一电源电压信号V1传输至其所耦接的发光组件20的第一极，以使该发光组件20工作。
在一些实施例中，在发光基板100中的多个第一控制电路30呈阵列排布的情况下，第二控制电路40向每个第一控制电路30传输第一使能信号PW1，包括：
在一个驱动周期内，第二控制电路40依次向每行第一控制电路传输第一使能信号PW1，以控制各行第一控制电路依次打开，且当前驱动周期每行第一控制电路在下个驱动周期每行第一控制电路打开前关闭。
示例性地，参考图17，多个第一控制电路30呈n行m列排布，在一个驱动周期F(如图21所示)内，第二控制电路40对第1行至第n行的第一控制电路30进行逐行传输第一使能信号(PW1(1)……PW1(n))，控制各行第一控制电路30依次打开，并且，第二控制电路40向每个第一控制电路30传输第一发光信号EM1，第一控制电路30在第一使能信号PW1和第一发光信号EM1的控制下打开，将来自第一电源电压信号线LV1的第一电源电压信号V1传输至与该第一控制电路30耦接的发光分区S中的发光组件20的第一极，以使发光组件20工作。
示例性地，参考图18，在发光基板100包括第二控制芯片102的情况下，每个使能信号接口E与一行第一控制电路30耦接，第二控制芯片102的多个使能信号接口(E(1)、E(2)……E(n-1)、E(n))依次向第1行至第n行的第一控制电路30传输第一使能信号(PW1(1)……PW1(n))，以控制第1行至第n行的第一控制电路30依次打开。第二控制芯片102中的每个发光信号接口L与一个第一控制电路30耦接，并向与其耦接的第一控制电路30传输第一发光信号EM1，第一控制电路30在第一发光信号EM1和第一使能信号PW1的控制下打开，将第一电源电压信号V1传输至其所耦接的发光组件20的第一极，以使该发光组件20工作。
并且，当前驱动周期每行第一控制电路在下个驱动周期每行第一控制电 路打开前关闭。第1行至第n行的第一控制电路30依次打开，第1行至第n行的第一控制电路30的工作时长相同。
在此基础上，在发光基板100应用于液晶显示装置的情况下，考虑到液晶分子的响应需要一定的时间，在一驱动周期开始时，每行第一控制电路30会延迟打开，例如，如图19、图20和图21所示，在一驱动周期的垂直帧同步信号Vsync有效时，使能信号接口E(1)向其所耦接的第1行的第一控制电路30传输的第一使能信号，使得第1行的第一控制电路30打开存在第一延迟时间t1。同样的，在一驱动周期结束后，下一驱动周期开始，每行第一控制电路30的关闭存在一定的延迟，例如，如图20和图21所示，在下一驱动周期的垂直帧同步信号Vsync有效时，使能信号接口E(1)向其所耦接的第1行的第一控制电路30传输的第一使能信号，使得第1行的第一控制电路30关闭存在第二延迟时间t2。
在此情况下，液晶分子可以在第一延迟时间t1和第二延迟时间t2内进行状态调整，使得在发光组件20工作时液晶分子处于稳定状态，避免因发光组件20工作时液晶分子不稳定而导致显示画面出现拖影问题，从而提高显示效果。并且，可以保证发光组件20的发光时长，降低电光转换效率的损失。
需要说明的是，如图19、图20和图21所示，使能信号接口E(1)向其所耦接的第1行的第一控制电路30传输的第一使能信号采用PW1(1)表示，使能信号接口E(2)向其所耦接的第2行的第一控制电路30传输的第一使能信号采用PW1(2)表示，使能信号接口E(n)向其所耦接的第n行的第一控制电路30传输的第一使能信号采用PW1(n)表示。此外，为了描述方便，垂直帧同步信号接口Vsync接收的垂直帧同步信号采用Vsync表示，但不代表两者为同一部件。
在一些实施例中，参考图4，第一控制电路30包括处理器31、模拟数字转换器ADC和第一输出子电路32。在此情况下，第一控制电路30根据第一发光信号EM1和第一使能信号PW1，将来自第一电源电压信号线LV1的第一电源电压信号V1传输至与该第一控制电路30耦接的发光组件20的第一极，包括：
处理器31接收第一发光信号EM1，并对第一发光信号EM1进行格式转换，生成第二发光信号EM2。
模拟数字转换器ADC接收第一使能信号PW1，生成参考信号REF。
第一输出子电路32根据第二发光信号EM2和参考信号REF，将来自第一电源电压信号线LV1的第一电源电压信号V1传输至发光组件20的第一极。
在此情况下，第一输出子电路32在第二发光信号EM2和参考信号REF的控制下打开，将第一电源电压信号V1传输至发光组件20的第一极，由于各第一控制电路30生成的第二发光信号EM2的电位和参考信号REF的电位不完全相同，可以通过调整第二发光信号EM2的电位，控制第一控制电路30将第一电源电压信号V1传输至发光组件20的第一极的时长，控制发光组件20的工作时间，并通过调整参考信号REF的电位，控制流过该发光组件20的电流幅值。
在一些实施例中，参考图8，第二控制电路40包括时序控制子电路41、数据处理子电路42、存储器43和放大子电路44。在此情况下，第二控制电路40接收驱动信号DRV，根据驱动信号DRV，向每个第一控制电路30传输第一发光信号EM1和第一使能信号PW1包括：
时序控制子电路41生成时钟信号。
数据处理子电路42接收驱动信号DRV，根据驱动信号DRV和来自时序控制子电路41的时钟信号，输出第二使能信号PW2，及向多个第一控制电路30传输第一发光信号EM1。
存储器43中存储有预设发光模式的时序数据和发光电流数据。
放大子电路44根据来自存储器43的预设发光模式的时序数据和发光电流数据，将来自数据处理子电路42的第二使能信号PW2进行功率放大，生成第一使能信号PW1，并向多个第一控制电路30传输第一使能信号PW1。
在此情况下，在第二控制电路40开始工作时，时序控制子电路41生成时钟信号，数据处理子电路42根据该时钟信号和接收的驱动信号DRV，向多个第一控制电路30传输第一发光信号EM1，向放大子电路44传输第二使能信号PW2。放大子电路44根据存储器43中存储的预设发光模式的时序数据和发光电流数据，将第二使能信号PW2进行功率放大，生成第一使能信号PW1，并将该第一使能信号PW1传输至多个第一控制电路30，控制第一控制电路30的电流大小，以驱动多个第一控制电路30工作，从而实现对与第一控制电路30耦接的发光组件20的工作状态的控制。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (19)

  1. 一种发光基板，具有多个发光分区；所述发光基板包括：
    衬底；
    设置于所述衬底上的多个发光组件，一个发光组件位于一个发光分区内；
    设置于所述衬底上且间隔排布的多条第一电源电压信号线；
    设置于所述衬底上的多个第一控制电路，每个第一控制电路与一个发光组件的第一极耦接，且每条第一电源电压信号线与至少两个第一控制电路耦接；所述第一控制电路被配置为，将来自所述第一电源电压信号线的第一电源电压信号传输至与该第一控制电路耦接的发光组件的第一极，以控制流过该发光组件的电流幅值。
  2. 根据权利要求1所述的发光基板，其中，所述多个发光分区呈阵列排布，所述多个第一控制电路呈阵列排布；
    同一行发光分区中的发光组件通过一行第一控制电路与一条所述第一电源电压信号线耦接，或者，同一列发光分区中的发光组件通过一列第一控制电路与一条所述第一电源电压信号线耦接。
  3. 根据权利要求1或2所述的发光基板，其中，所述第一控制电路被配置为，接收第一发光信号和第一使能信号，根据所述第一发光信号和所述第一使能信号，将所述第一电源电压信号传输至与该第一控制电路耦接的发光组件的第一极，以控制流过该发光组件的电流幅值；
    所述第一控制电路包括：
    处理器，所述处理器被配置为，接收所述第一发光信号，并对所述第一发光信号进行格式转换，生成第二发光信号；
    模拟数字转换器，所述模拟数字转换器被配置为，接收所述第一使能信号，生成参考信号；
    第一输出子电路，所述第一输出子电路与所述处理器、所述模拟数字转换器、所述第一电源电压信号线和所述发光组件的第一极耦接；所述第一输出子电路被配置为，根据来自所述处理器的所述第二发光信号和来自所述模拟数字转换器的所述参考信号，将来自所述第一电源电压信号线的第一电源电压信号传输至所述发光组件的第一极。
  4. 根据权利要求3所述的发光基板，其中，所述第一输出子电路包括：
    第一晶体管，所述第一晶体管的控制极与所述处理器耦接，所述第一晶体管的第二极与所述发光组件的第一极耦接；
    第一电阻，所述第一电阻的第一端与所述第一电源电压信号线耦接；
    比较器，所述比较器的正相输入端与所述模拟数字转换器的输出端耦接， 所述比较器的负相输入端与所述第一电阻的第二端耦接；
    第二晶体管，所述第二晶体管的控制极与所述比较器的输出端耦接，所述第二晶体管的第一极与所述第一电阻的第二端耦接，所述第二晶体管的第二极与所述第一晶体管的第一极耦接。
  5. 根据权利要求3或4所述的发光基板，所述发光基板包括：第一控制芯片，所述第一控制芯片包括所述第一控制电路；
    所述第一控制芯片还包括：
    第一接口，所述第一接口与所述第一控制电路中的处理器耦接；所述第一接口被配置为，接收所述第一发光信号，并将所述第一发光信号传输至所述处理器；
    第二接口，所述第二接口与所述第一控制电路中的模拟数字转换器耦接；所述第二接口被配置为，接收所述第一使能信号，并将所述第一使能信号传输至所述模拟数字转换器；
    第三接口，所述第三接口与所述第一电源电压信号线和所述第一控制电路中的第一输出子电路耦接；所述第三接口被配置为，接收来自所述第一电源电压信号线的第一电源电压信号，并将所述第一电源电压信号传输至所述第一输出子电路；
    第四接口，所述第四接口与所述第一控制电路中的第一输出子电路和所述发光组件的第一极耦接；所述第四接口被配置为，将经过所述第一输出子电路传输的第一电源电压信号传输至所述发光组件的第一极。
  6. 根据权利要求1～5中任一项所述的发光基板，还包括：
    设置于所述衬底上的第二控制电路，所述第二控制电路与所述多个第一控制电路耦接；
    所述第二控制电路被配置为，接收驱动信号，根据所述驱动信号，向每个所述第一控制电路传输第一发光信号和第一使能信号。
  7. 根据权利要求6所述的发光基板，其中，所述第二控制电路包括：
    时序控制子电路，被配置为生成时钟信号；
    数据处理子电路，与所述时序控制子电路和所述多个第一控制电路耦接；所述数据处理子电路被配置为，接收所述驱动信号，根据所述驱动信号和来自所述时序控制子电路的所述时钟信号，输出第二使能信号，及向所述多个第一控制电路传输所述第一发光信号；
    存储器，被配置为存储预设发光模式的时序数据和发光电流数据；
    放大子电路，与所述数据处理子电路、所述存储器和所述多个第一控制 电路耦接；所述放大子电路被配置为，根据所述预设发光模式的时序数据和发光电流数据，将来自所述数据处理子电路的所述第二使能信号进行功率放大，生成所述第一使能信号，并向所述多个第一控制电路传输所述第一使能信号。
  8. 根据权利要求7所述的发光基板，所述发光基板包括：第二控制芯片，所述第二控制芯片包括所述第二控制电路；
    所述第二控制芯片还包括：
    多个使能信号接口，所述多个使能信号接口与所述第二控制电路中的放大子电路耦接，且每个使能信号接口与至少一个所述第一控制电路耦接；所述使能信号接口被配置为，接收来自所述放大子电路的第一使能信号，并将所述第一使能信号传输至其所耦接的第一控制电路；
    多个发光信号接口，所述多个发光信号接口与所述第二控制电路中的数据处理子电路耦接，且每个发光信号接口与一个所述第一控制电路耦接；所述发光信号接口被配置为，接收来自所述数据处理子电路的所述第一发光信号，并将所述第一发光信号传输至其所耦接的第一控制电路；
    驱动信号接口，所述驱动信号接口与所述数据处理子电路耦接；所述驱动信号接口被配置为，接收所述驱动信号，并将所述驱动信号传输至所述数据处理子电路。
  9. 根据权利要求8所述的发光基板，其中，在所述多个第一控制电路呈阵列排布的情况下，每个所述使能信号接口与一行或一列所述第一控制电路耦接。
  10. 根据权利要求1～9中任一项所述的发光基板，还包括：
    设置于所述衬底上且间隔排布的多条第二电源电压信号线；至少两个发光分区中的发光组件的第二极与一条第二电源电压信号线耦接。
  11. 根据权利要求10所述的发光基板，其中，在所述多个发光分区呈阵列排布的情况下，同一行或同一列发光分区中的发光组件与一条所述第二电源电压信号线耦接。
  12. 根据权利要求10或11所述的发光基板，其中，所述第一电源电压信号线和所述第二电源电压信号线均沿列方向延伸，或者均沿行方向延伸。
  13. 根据权利要求12所述的发光基板，其中，所述第二电源电压信号线和所述第一电源电压信号线的材料相同且同层设置。
  14. 根据权利要求10～12中任一项所述的发光基板，还包括：
    绝缘层；沿垂直于所述衬底的方向，所述第一电源电压信号线和所述第 二电源电压信号线位于所述绝缘层靠近所述衬底的一侧，所述发光组件和所述第一控制电路位于所述绝缘层远离所述衬底的一侧；
    所述绝缘层中设置有第一过孔和第二过孔，所述第一控制电路通过第一过孔与所述第一电源电压信号线耦接；所述发光组件的第二极通过所述第二过孔与所述第二电源电压信号线耦接。
  15. 根据权利要求14所述的发光基板，其中，在所述发光基板还包括第二控制电路的情况下，所述发光基板还包括：
    设置于所述绝缘层远离所述衬底一侧的多条连接引线，所述多条连接引线被配置为将各所述第一控制电路和所述第二控制电路进行耦接。
  16. 根据权利要求1～15中任一项所述的发光基板，其中，所述发光组件包括：
    呈阵列排布的多个发光器件；
    多个导电图案，所述多个导电图案将所述多个发光器件依次串接；
    其中，所述多个发光器件依次串接所形成的线路中，处于线路两端的两个发光器件中的一个发光器件的阴极为所述发光组件的第一极，另一个发光器件的阳极为所述发光组件的第二极。
  17. 一种发光模组，包括：
    如权利要求1～16中任一项所述的发光基板；所述发光基板包括第一电源电压信号线和第二电源电压信号线；
    柔性线路板；和
    电源芯片，所述电源芯片通过所述柔性线路板与所述发光基板绑定；所述电源芯片被配置为，向所述第一电源电压信号线传输第一电源电压信号，并向所述第二电源电压信号线传输第二电源电压信号。
  18. 一种显示装置，包括：
    如权利要求17所述的发光模组，所述发光模组中的发光基板包括多个第一控制电路和第二控制电路；和
    驱动芯片，所述驱动芯片与所述第二控制电路耦接；所述驱动芯片被配置为，向所述第二控制电路传输驱动信号。
  19. 一种如1～17中任一项所述的发光基板的驱动方法，所述发光基板包括多个第一控制电路和第二控制电路；
    所述发光基板的驱动方法包括：
    所述第二控制电路接收驱动信号，根据所述驱动信号，向每个所述第一控制电路传输第一发光信号和第一使能信号；
    所述第一控制电路根据所述第一发光信号和所述第一使能信号，将来自第一电源电压信号线的第一电源电压信号传输至与该第一控制电路耦接的发光组件的第一极，以控制流过该发光组件的电流幅值。
PCT/CN2020/077881 2020-03-05 2020-03-05 发光基板及其驱动方法、发光模组、显示装置 WO2021174473A1 (zh)

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