WO2021169796A1 - 导线层的制作方法 - Google Patents

导线层的制作方法 Download PDF

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Publication number
WO2021169796A1
WO2021169796A1 PCT/CN2021/076097 CN2021076097W WO2021169796A1 WO 2021169796 A1 WO2021169796 A1 WO 2021169796A1 CN 2021076097 W CN2021076097 W CN 2021076097W WO 2021169796 A1 WO2021169796 A1 WO 2021169796A1
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temperature
wafer
conductive
conductive film
reaction chamber
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PCT/CN2021/076097
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English (en)
French (fr)
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李凯旋
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长鑫存储技术有限公司
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Priority to US17/400,549 priority Critical patent/US11978667B2/en
Publication of WO2021169796A1 publication Critical patent/WO2021169796A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76882—Reflowing or applying of pressure to better fill the contact hole
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76883—Post-treatment or after-treatment of the conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53214—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being aluminium

Definitions

  • the embodiments of the present application relate to the field of semiconductors, and in particular to a method for manufacturing a wire layer.
  • Aluminum metal has the advantages of low resistance, easy availability, low price, and easy dry etching. It is widely used in metal wires in the semiconductor industry.
  • the melting point of aluminum metal is greater than 660°C, but aluminum begins to show a molten state when its temperature reaches 330°C (half the melting point, also known as the semi-melting point). Because aluminum has the characteristics of reflow at high temperatures, it is often used as a hole-filling for metal wires.
  • Process methods commonly used for aluminum include heating evaporation, reflow, and sputtering.
  • Some embodiments of the present application provide a method for fabricating a wire layer, which is beneficial to reduce the occurrence of defects such as edge protrusions.
  • some embodiments of the present application provide a method for fabricating a wire layer, including: providing a wafer with an opening; depositing conductive dies on the wafer and the bottom and sidewalls of the opening to form a conductive Film; wherein, during the deposition of the conductive die, the temperature of the wafer surface is less than the flow temperature of the conductive film, and when the temperature of the wafer surface is greater than or equal to the flow temperature, the conductive film starts Flow; After the conductive film is formed, the temperature of the wafer surface is increased to perform a reflow process, so that the conductive film is converted into a conductive layer that fills the opening.
  • the depositing conductive crystal grains on the wafer specifically includes: passing a sputtering gas into the reaction chamber and turning on a DC power supply, so that the sputtering gas forms a plasma, and the plasma hits the conductive target The conductive crystal grains are sputtered out of the material, and the conductive crystal grains are deposited on the wafer.
  • the increasing the temperature of the wafer surface to perform the reflow process specifically includes: increasing the temperature of the reaction chamber, and injecting gas into the reaction chamber, so that the temperature of the wafer is greater than or equal to the temperature of the reaction chamber. Flow temperature; wherein the flow rate of the gas is 2 sccm to 10 sccm.
  • the flow temperature is 330°C to 350°C
  • the process temperature of the reflow process is 400°C to 450°C.
  • the thickness of the conductive film on the wafer is 500 nm to 750 nm; and the gas passing time is 60 s to 120 s.
  • the material of the conductive crystal grains includes aluminum.
  • the raising the temperature of the reaction chamber specifically includes: first raising the temperature of the reaction chamber to a first preset temperature, and then lowering the temperature of the reaction chamber to a second preset temperature, and The first preset temperature is greater than the second preset temperature, and the first preset temperature and the second preset temperature are greater than the flow temperature.
  • the providing a wafer with an opening specifically includes: providing a wafer with an opening, the surface of the wafer for depositing the conductive die is covered with an isolation layer; and depositing the conductive die to the The surface of the isolation layer to form the conductive film; wherein the material of the isolation layer includes titanium, titanium nitride, tantalum, or tantalum nitride.
  • the thickness of the isolation layer is 5 nm to 50 nm.
  • an anti-reflection layer is formed, and the anti-reflection layer covers the surface of the conductive layer away from the wafer.
  • the material of the anti-reflection layer includes titanium nitride, and the thickness of the anti-reflection layer is 10 nm-50 nm.
  • the reflow process is performed after the conductive film is formed, so that the temperature of the wafer is lower during the deposition of the conductive crystal grains, and there is no plasma impact during the reflow of the conductive film, so that the deposited conductive crystal grains
  • the size is small, thereby reducing defects such as edge protrusions caused by mutual extrusion of conductive crystal grains.
  • 400°C-450°C is used as the process temperature of the reflow process, so that aluminum can better reflow and fill holes.
  • the surface of the wafer is covered with an isolation layer, which can block aluminum ions and prevent aluminum ions from penetrating into the wafer, thereby ensuring the performance of the wafer.
  • 1 to 3 are schematic diagrams of the cross-sectional structure corresponding to each step of a method for manufacturing a wire layer
  • FIG. 4 is a diagram of wafer temperature change corresponding to a method of manufacturing a wire layer
  • FIG. 5 is a flowchart of a method for manufacturing a wire layer provided by an embodiment of the application.
  • 6 to 9 are schematic diagrams of the cross-sectional structure corresponding to each step of the manufacturing method of the wire layer according to an embodiment of the application;
  • FIG. 10 is a graph of wafer temperature changes corresponding to a method for fabricating a wire layer according to an embodiment of the application.
  • FIGS. 1 to 3 are schematic diagrams of the cross-sectional structure corresponding to each step of a method for manufacturing a wire layer.
  • the manufacturing method of aluminum wire includes the following steps:
  • a layer of cold aluminum 12 is deposited on the wafer 11 first. Since the temperature of the wafer 11 is relatively low during the deposition process of the cold aluminum 12, the crystal grains of the deposited cold aluminum 12 are smaller, which can play a role in improving the reflow efficiency.
  • the wafer 11 is heated so that the temperature of the surface of the wafer 11 is greater than the melting point of aluminum, that is, the temperature of the surface of the wafer 11 reaches 350°C to 400°C.
  • the cold aluminum 12 is reflowed. In an ideal state, the reflowed cold aluminum 12 still covers the wafer 11 and the bottom and side walls of the opening.
  • FIG. 4 is a graph of wafer temperature change corresponding to a method of manufacturing a wire layer.
  • the wafer temperature change diagram includes a cold aluminum deposition stage 101, a wafer heating stage 102, and a hot aluminum deposition stage 103.
  • the cold aluminum deposition stage 101 the aluminum grains generated after plasma impact are compared Since the aluminum target has a higher temperature, the aluminum crystal grains with increased temperature are deposited on the wafer 11 that is still at room temperature, which will slightly increase the temperature of the wafer 11; in the wafer heating stage 102, the surface of the wafer 11 Heating is performed so that the temperature of the surface of the wafer 11 reaches the temperature at which the aluminum crystal grains are melted; in the hot aluminum deposition stage 103, the plasma strikes the surface of the wafer 11, so that the temperature of the surface of the wafer 11 is further increased, due to the impact of the plasma. The uncertainty may cause the temperature of the wafer 11 to exceed the tolerable range of the wafer 11, thereby causing damage to the performance of the wafer 11.
  • the present application provides a method for fabricating a wire layer, including: providing a wafer with an opening; depositing conductive dies on the wafer and the bottom and sidewalls of the opening to form a conductive film;
  • the temperature of the wafer surface is less than the flow temperature of the conductive film.
  • the conductive film starts to flow; after the conductive film is formed, the temperature of the wafer surface is increased to facilitate the reflow process.
  • the conductive film is converted into a conductive layer that fills the openings.
  • FIG. 5 is a flowchart of a method for manufacturing a wire layer according to an embodiment of the application
  • FIGS. 6 to 9 are schematic diagrams of cross-sectional structures corresponding to each step of the method for manufacturing a wire layer according to an embodiment of the application.
  • the method of making the wire layer is as follows:
  • step S101 a wafer 21 with openings is provided.
  • the wafer 21 includes a copper layer 211, a titanium nitride layer 212, and a silicon dioxide layer 213 that are sequentially stacked.
  • the titanium nitride layer 212 functions to isolate the copper layer 211 and the silicon dioxide layer 213 to avoid copper
  • the ions penetrate into the silicon dioxide layer 213 to ensure that the silicon dioxide layer 213 has a preset performance.
  • the surface of the wafer 21 used to deposit conductive dies that is, the upper surface of the wafer 21, the bottom surface of the opening and the sidewall surfaces are covered with an isolation layer 214, and subsequently deposited conductive dies will fall on the isolation layer.
  • 214 surface to form a conductive film wherein, the material of the isolation layer 214 includes titanium, titanium nitride, tantalum or tantalum nitride, which serves to isolate the subsequently deposited metal material and the silicon dioxide layer 213 and prevent metal ions from penetrating into The silicon dioxide layer 213 affects the performance of the wafer 21.
  • the thickness of the isolation layer 214 is 5 nm-50 nm, for example, 10 nm, 20 nm, and 40 nm. In this way, it not only helps to ensure the isolation between the subsequently deposited metal material and the silicon dioxide layer 213, but also ensures that the structural size of the wire layer meets the preset requirements.
  • step S102 conductive dies are deposited on the wafer 21 and on the bottom and sidewalls of the opening to form a conductive film 22.
  • the temperature of the surface of the wafer 21 is less than the flow temperature of the conductive film 22.
  • the conductive film 22 starts flow. In this way, since cold aluminum deposition is eliminated, only one reaction chamber is needed to fabricate the wire layer, which is beneficial to improve production efficiency and save costs.
  • depositing conductive crystal grains on the wafer 21 specifically includes: placing the wafer 21 and a conductive target in the reaction chamber; passing sputtering gas into the reaction chamber and turning on the DC power supply so that the sputtering gas is ionized
  • the plasma hits the conductive target to sputter out conductive crystal grains; the conductive crystal grains are deposited on the surface of the wafer 21.
  • the wafer 21 since the wafer 21 is in an unheated normal temperature state, the size of the conductive crystal grains deposited on the surface of the wafer 21 is small. In this way, the mutual squeezing between the conductive crystal grains can be effectively reduced, and the occurrence of crystal grain defects can be reduced. ; In addition, it also helps to improve the efficiency of the subsequent reflow process.
  • the sputtering gas may be an inert gas, such as argon.
  • the wafer temperature change diagram includes a die deposition stage 201 and a die reflow stage 202. In the die deposition stage 201, the temperature of the wafer 21 is increased.
  • the flow temperature of the conductive film 22 is related to the material of the conductive film 22. Taking the material of the conductive film 22 as an example, the flow temperature of the conductive film 22 is 330°C to 350°C, for example, 335°C, 340°C. In addition, since the surface of the wafer 21 is covered with the isolation layer 214, the temperature of the surface of the isolation layer 214 is lower than the flow temperature of the conductive film 22 during the process of depositing conductive crystal grains to form the conductive film 22.
  • step S103 the temperature of the surface of the wafer 21 is increased to perform a reflow process.
  • the temperature of the reaction chamber is increased, and gas is introduced into the reaction chamber.
  • the flowing gas transfers the temperature of the reaction chamber to the surface of the wafer 21, so that the temperature of the wafer 21 is greater than or It is equal to the flow temperature, that is, the conductive film 22 enters a molten state and starts to flow toward the position of the opening, and then the conductive film is converted into a conductive layer 23 that fills the opening.
  • the conductive film 22 enters a molten state and starts to flow toward the position of the opening, and then the conductive film is converted into a conductive layer 23 that fills the opening.
  • the reflow temperature will affect the size of the conductive crystal grains. Without plasma impact, the increase in the size of the conductive crystal grains caused by the rise in the temperature of the wafer 21 is small, which can reduce the size of the conductive crystal grains. The occurrence of wafer defects.
  • the flow rate of the gas introduced into the reaction chamber is 2 sccm-10 sccm, for example, 4 sccm, 6 sccm, and 8 sccm. In this way, the temperature of the surface of the wafer 21 can be quickly and uniformly increased to the temperature of the reaction chamber.
  • the material of the conductive crystal grains is aluminum.
  • the temperature of the reaction chamber (that is, the process temperature of the reflow process) is 400° C. to 450° C., for example, 410° C., 430° C., or 440° C.
  • the thickness d of the conductive film 22 on the wafer 21 is 500 nm to 750 nm, for example, 550 nm, 600 nm, 650 nm, 700 nm; correspondingly, the gas passing time is 60 s to 120 s , For example, 80s, 90s, 100s. In this way, it is beneficial to ensure that the conductive film 22 can be fully reflowed, and to avoid crystal grain defects such as edge protrusions caused by insufficient reflow.
  • the temperature of the reaction chamber is first increased to a first preset temperature, and then the temperature of the reaction chamber is decreased to a second preset temperature, and the first preset temperature is greater than the first preset temperature.
  • Two preset temperatures, and the first preset temperature and the second preset temperature are greater than the flow temperature.
  • the second preset temperature is the process temperature of the reflow process, which is beneficial to shorten the time consumption of the reflow process.
  • the die reflow stage 202 includes a first reflow stage 211 and a second reflow stage 212.
  • the temperature of the reaction chamber is at a first preset temperature
  • the temperature of the reaction chamber is at the second preset temperature.
  • an anti-reflection layer 24 is formed, and the anti-reflection layer 24 covers the surface of the conductive layer 23 away from the wafer 21; wherein the material of the anti-reflection layer 24 includes titanium nitride. Since titanium nitride has a low reflectivity, it is beneficial to improve the resolution of the lithography technology during the metal patterning process.
  • the thickness of the anti-reflection layer 24 is 10 nm to 50 nm, for example, 20 nm, 30 nm, and 40 nm.
  • the reflow process is performed after the conductive film 22 is formed, so that the temperature of the wafer 21 is lower during the deposition of the conductive crystal grains, and there is no plasma impact during the reflow of the conductive film 22, so that the deposited
  • the size of the conductive crystal grains is small, thereby reducing defects such as edge protrusion caused by the mutual extrusion of the conductive crystal grains.

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Abstract

本申请部分实施例提供一种导线层的制作方法，导线层的制作方法包括：提供具有开口的晶圆(21)；在晶圆(21)上以及开口底部和侧壁沉积导电晶粒，以形成导电膜(22)；其中，在沉积导电晶粒期间，晶圆(21)表面的温度小于导电膜(22)的流动温度，晶圆(21)的温度大于或等于流动温度时，导电膜(22)开始流动；在形成导电膜(22)后，增加晶圆(21)表面的温度以进行回流工艺，使导电膜(22)转换为填充满开口的导电层(23)。

Description

导线层的制作方法
交叉引用
本申请要求于2020年2月27日递交的名称为“导线层的制作方法”、申请号为202010123283.4的中国专利申请的优先权，其通过引用被全部并入本申请。
技术领域
本申请实施例涉及半导体领域，特别涉及一种导线层的制作方法。
背景技术
铝金属具有电阻值较低、容易获得、价格便宜且容易被干刻蚀等优点，在半导体行业被广泛应用于金属导线。铝金属的熔点大于为660℃，但是铝在自身温度达到330℃(即熔点的一半，又称为半熔点)时便开始呈现熔融状态。因为铝在高温下具有回流的特性，因此常被用作金属导线的填洞。
铝常使用的工艺方法包括加热蒸发法、回流法和溅射法等。
申请内容
本申请部分实施例提供了一种导线层的制作方法，有利于减少边缘突出等缺陷的产生。
为解决上述问题，本申请部分实施例提供一种导线层的制作方法，包括：提供具有开口的晶圆；在所述晶圆上以及所述开口底部和侧壁沉积导电晶粒，以形成导电膜；其中，在沉积所述导电晶粒期间，所述晶圆表面的温度小于所述导电膜的流动温度，所述晶圆表面的温度大于或等于所述流动温度时，所述导电膜开始流动；在形成所述导电膜后，增加所述晶圆表面的温度以进行回流工艺，使所述导电膜转换为填充满所述开口的导电层。
另外，所述在所述晶圆上沉积导电晶粒，具体包括：向反应腔室内通入 溅射气体并开启直流电源，以使所述溅射气体形成等离子体，所述等离子体撞击导电靶材以溅射出所述导电晶粒，所述导电晶粒沉积在所述晶圆上。
另外，所述增加所述晶圆表面的温度以进行回流工艺，具体包括：提高反应腔室的温度，并向所述反应腔室内通入气体，使得所述晶圆的温度大于或等于所述流动温度；其中，所述气体的流量为2sccm～10sccm。
另外，所述流动温度为330℃～350℃，所述回流工艺的工艺温度为400℃～450℃。
另外，在进行所述回流工艺之前，位于所述晶圆上的所述导电膜的厚度为500nm～750nm；所述气体的通入时间为60s～120s。
另外，所述导电晶粒的材料包括铝。
另外，所述提高反应腔室的温度，具体包括：先将所述反应腔室的温度提升至第一预设温度，再将所述反应腔室的温度下降至第二预设温度，所述第一预设温度大于所述第二预设温度，且所述第一预设温度和所述第二预设温度大于所述流动温度。
另外，所述提供具有开口的晶圆，具体包括：提供具有开口的晶圆，所述晶圆的用于沉积所述导电晶粒的表面覆盖有隔离层；沉积所述导电晶粒至所述隔离层表面，以形成所述导电膜；其中，所述隔离层的材料包括钛、氮化钛、钽或氮化钽。
另外，所述隔离层的厚度为5nm～50nm。
另外，在进行所述回流工艺之后，形成抗反射层，所述抗反射层覆盖所述导电层远离所述晶圆的表面。
另外，所述抗反射层的材料包括氮化钛，所述抗反射层的厚度为10nm～50nm。
与现有技术相比，本申请部分实施例提供的技术方案具有以下优点：
本实施例中，在形成导电膜之后进行回流工艺，使得在导电晶粒的沉积过程中晶圆的温度较低，且在导电膜回流过程中没有等离子体撞击，从而使得沉积得到的导电晶粒尺寸较小，进而减少导电晶粒之间相互挤压而造成的边缘突出等缺陷。
另外，采用400℃～450℃作为回流工艺的工艺温度，使得铝能够更好地回流填洞。
另外，晶圆表面覆盖有隔离层，隔离层能够对铝离子进行阻拦，避免铝离子渗透至晶圆内，从而保证晶圆的性能。
附图说明
一个或多个实施例通过与之对应的附图中的图片进行示例性说明，这些示例性说明并不构成对实施例的限定，附图中具有相同参考数字标号的元件表示为类似的元件，除非有特别申明，附图中的图不构成比例限制。
图1至图3为一种导线层的制作方法各步骤所对应的剖面结构示意图；
图4为一种导线层的制作方法所对应的晶圆温度变化图；
图5为本申请一实施例提供的导线层的制作方法流程图；
图6至图9为本申请一实施例提供的导线层的制作方法各步骤所对应的剖面结构示意图；
图10为本申请一实施例提供的导线层的制作方法所对应的晶圆温度变化图。
具体实施方式
图1至图3为一种导线层的制作方法各步骤所对应的剖面结构示意图。参考图1至图3，铝导线的制作方法包括以下步骤：
如图1所示，在进行物理气相沉积工艺之前，先在晶圆11上沉积一层冷铝12。由于在进行冷铝12的沉积工艺时，晶圆11的温度较低，因此沉积得到的冷铝12的晶粒较小，可起到提高回流效率的作用。
如图2所示，对晶圆11进行加热，以使晶圆11表面的温度大于铝的熔融点，即使得晶圆11表面的温度达到350℃～400℃，进而使得位于晶圆11表面的冷铝12发生回流，理想状态下，回流后的冷铝12依然覆盖晶圆11上以及开口底部和侧壁。
需要说明的是，冷铝12的沉积和对晶圆11进行加热需要在两个不同的腔室内进行。
如图3所示，在晶圆11表面的温度达到预设温度的情况下，采用等离子体轰击铝靶材的方式生成铝晶粒，铝晶粒沉积在晶圆11表面而形成铝膜13，这一步骤通常称为热铝沉积。由于在形成铝膜13的过程中，晶圆11表面的温度较高且等离子体还会撞击已沉积的铝晶粒，这导致沉积得到的铝膜13中的铝晶粒尺寸较大，而尺寸较大的铝晶粒之间会相互挤压，进而形成边缘突出和须晶等缺陷。
图4为一种导线层的制作方法所对应的晶圆温度变化图。
参考图1和图4，晶圆温度变化图包括冷铝沉积阶段101、晶圆加热阶段102及热铝沉积阶段103，在冷铝沉积阶段101，经等离子体撞击后生成的铝晶粒相较于铝靶材具有较高的温度，温度提高的铝晶粒沉积在依旧处于常温状态的晶圆11上，会使得晶圆11的温度略微提高；在晶圆加热阶段102，对晶圆11表面进行加热，以使晶圆11表面的温度达到使铝晶粒熔融的温度；在热铝沉积阶段103，等离子体撞击晶圆11表面，使得晶圆11表面的温度进一步提高，由于等离子体的撞击具有不确定性，可能导致晶圆11的温度超出晶圆11的可承受范围，从而对晶圆11的性能造成损伤。
为解决上问题，本申请实施提供一种导线层的制作方法，包括：提供具有开口的晶圆；在晶圆上以及开口底部和侧壁沉积导电晶粒，以形成导电膜；其中，在沉积导电晶粒器件，晶圆表面的温度小于导电膜的流动温度，晶圆的温度大于或等于流动温度时，导电膜开始流动；在形成导电膜后，增加晶圆表面的温度易进行回流工艺，使导电膜转换为填充满开口的导电层。
为使本申请实施例的目的、技术方案和优点更加清楚，下面将结合附图对本申请的各实施例进行详细的阐述。然而，本领域的普通技术人员可以理解，在本申请各实施例中，为了使读者更好地理解本申请而提出了许多技术细节。但是，即使没有这些技术细节和基于以下各实施例的种种变化和修改，也可以实现本申请所要求保护的技术方案。
参考图5，图5为本申请一实施例提供的导线层的制作方法流程图；图6至图9为本申请一实施例提供的导线层的制作方法各步骤所对应的剖面结构示意图。参考图5至图9，导线层的制作方法具体如下：
步骤S101，提供具有开口的晶圆21。
参考图6，晶圆21包括位于依次层叠的铜层211、氮化钛层212以及二氧化硅层213，氮化钛层212起到隔离铜层211和二氧化硅层213的作用，避免铜离子渗透至二氧化硅层213内，从而保证二氧化硅层213具有预设的性能。
此外，本实施例中，晶圆21用于沉积导电晶粒的表面，即晶圆21上表面以及开口底部表面和侧壁表面覆盖有隔离层214，后续沉积的导电晶粒会落在隔离层214表面，以形成导电膜；其中，隔离层214的材料包括钛、氮化钛、钽或氮化钽，起到隔离后续沉积的金属材料和二氧化硅层213的作用，避免金属离子渗透进入二氧化硅层213，对晶圆21的性能造成影响。
本实施例中，隔离层214的厚度为5nm～50nm，例如为10nm、20nm、40nm。如此，既有利于保证后续沉积的金属材料与二氧化硅层213之间的隔离，又能够保证导线层的结构尺寸满足预设要求。
步骤S102，在晶圆21上以及开口底部和侧壁沉积导电晶粒，以形成导电膜22。
参考图7，在沉积导电晶粒以形成导电膜22的过程中，晶圆21表面的温度小于导电膜22的流动温度，当晶圆21表面的温度大于或等于流动温度时，导电膜22开始流动。如此，由于取消了冷铝沉积，使得仅需要一个反应腔室即可制作导线层，有利于提高生产效率和节约成本。
其中，在晶圆21上沉积导电晶粒，具体包括：将晶圆21和导电靶材置于反应腔室内；向反应腔室内通入溅射气体并开启直流电源，以使溅射气体被电离为等离子体，等离子体撞击导电靶材以溅射出导电晶粒；导电晶粒沉积在晶圆21表面。其中，由于晶圆21处于未加热的常温状态，因此沉积在晶圆21表面的导电晶粒的尺寸较小，如此，能够有效减少导电晶粒之间的相互挤压，减少晶粒缺陷的产生；此外，还有利于提高后续回流工艺的效率。
其中，溅射气体可以为惰性气体，例如为氩气。
在导电晶粒沉积在晶圆21表面时，等离子体会撞击晶圆21时，会造成晶圆21的温度升高。参考图10，晶圆温度变化图包括晶粒沉积阶段201和晶粒回流阶段202，在晶粒沉积阶段201阶段，晶圆21的温度有所提高。
需要说明的是，导电膜22的流动温度与导电膜22的材料有关，以导电 膜22的材料为铝作为示例，导电膜22的流动温度为330℃～350℃，例如为335℃、340℃、345℃；此外，由于晶圆21表面覆盖有隔离层214，在沉积导电晶粒以形成导电膜22的过程中，隔离层214表面的温度小于导电膜22的流动温度。
步骤S103，增加晶圆21表面的温度以进行回流工艺。
参考图8，在形成导电膜之后，提升反应腔室的温度，并向反应腔室通入气体，流动的气体将反应腔室的温度传递至晶圆21表面，使得晶圆21的温度大于或等于流动温度，即使得导电膜22进入熔融状态，开始向开口所在位置流动，进而使导电膜转换为填充满开口的导电层23。如此，在回流过程中，只有回流温度会对导电晶粒的大小造成影响，在没有等离子体撞击的情况下，晶圆21温度上升导致的导电晶粒粒径增长的幅度较小，从而能够减少晶圆缺陷的产生。
本实施例中，向反应腔室通入的气体的流量为2sccm～10sccm，例如为4sccm、6sccm、8sccm。如此，使得晶圆21表面的温度能够快速均匀地提高至反应腔室的温度。
本实施例中，导电晶粒的材料为铝，在进行回流工艺时，反应腔室的温度(即回流工艺的工艺温度)为400℃～450℃，例如为410℃、430℃、440℃。
本实施例中，在进行回流工艺之前，位于晶圆21上的导电膜22的厚度d为500nm～750nm，例如为550nm、600nm、650nm、700nm；相应地，气体的通入时间为60s～120s，例如为80s、90s、100s。如此，既有利于保证导电膜22能够被充分回流，避免因回流不充分而导致的晶粒缺陷，例如边缘突出等。
本实施例中，在持续通气气体的情况下，先将反应腔室的温度提升至第一预设温度，再将反应腔室的温度下降至第二预设温度，第一预设温度大于第二预设温度，且第一预设温度和第二预设温度大于流动温度。其中，第二预设温度为回流工艺的工艺温度，如此，有利于缩短回流工艺的耗时。
参考图10，晶粒回流阶段202包括第一回流阶段211和第二回流阶段212，在第一回流阶段211中，反应腔室的温度处于第一预设温度；在第二回流阶段212中，反应腔室的温度处于第二预设温度。
参考图9，在回流工艺结束后，形成抗反射层24，抗反射层24覆盖导电层23远离晶圆21的表面；其中，抗反射层24的材料包括氮化钛。由于氮化钛具有较低的反射率，如此，有利于改进金属图案化工艺过程中的微影技术解析度。
本实施例中，抗反射层24的厚度为10nm～50nm，例如为20nm、30nm、40nm。
本实施例中，在形成导电膜22之后进行回流工艺，使得在导电晶粒的沉积过程中晶圆21的温度较低，且在导电膜22回流过程中没有等离子体撞击，从而使得沉积得到的导电晶粒尺寸较小，进而减少导电晶粒之间相互挤压而造成的边缘突出等缺陷。
本领域的普通技术人员可以理解，上述各实施方式是实现本申请的具体实施例，而在实际应用中，可以在形式上和细节上对其作各种改变，而不偏离本申请的精神和范围。任何本领域技术人员，在不脱离本申请的精神和范围内，均可作各自更动与修改，因此本申请的保护范围应当以权利要求限定的范围为准。

Claims (11)

  1. 一种导线层的制作方法，包括：
    提供具有开口的晶圆；
    在所述晶圆上以及所述开口底部和侧壁沉积导电晶粒，以形成导电膜；其中，在沉积所述导电晶粒期间，所述晶圆表面的温度小于所述导电膜的流动温度，所述晶圆表面的温度大于或等于所述流动温度时，所述导电膜开始流动；
    在形成所述导电膜后，增加所述晶圆表面的温度以进行回流工艺，使所述导电膜转换为填充满所述开口的导电层。
  2. 根据权利要求1所述的方法，其中，所述在所述晶圆上沉积导电晶粒，具体包括：向反应腔室内通入溅射气体并开启直流电源，以使所述溅射气体形成等离子体，所述等离子体撞击导电靶材以溅射出所述导电晶粒，所述导电晶粒沉积在所述晶圆上。
  3. 根据权利要求1或2所述的方法，其中，所述增加所述晶圆表面的温度以进行回流工艺，具体包括：提高反应腔室的温度，并向所述反应腔室内通入气体，使得所述晶圆的温度大于或等于所述流动温度；其中，所述气体的流量为2sccm～10sccm。
  4. 根据权利要求3所述的方法，其中，所述流动温度为330℃～350℃，所述回流工艺的工艺温度为400℃～450℃。
  5. 根据权利要求4所述的方法，其中，在进行所述回流工艺之前，位于所述晶圆上的所述导电膜的厚度为500nm～750nm；所述气体的通入时间为60s～120s。
  6. 根据权利要求4所述的方法，其中，所述导电晶粒的材料包括铝。
  7. 根据权利要求3所述的方法，其中，所述提高反应腔室的温度，具体包括：先将所述反应腔室的温度提升至第一预设温度，再将所述反应腔室的温度下降至第二预设温度，所述第一预设温度大于所述第二预设温度，且所述第一预设温度和所述第二预设温度大于所述流动温度。
  8. 根据权利要求1所述的方法，其中，所述提供具有开口的晶圆，具体包括：提供具有开口的晶圆，所述晶圆的用于沉积所述导电晶粒的表面覆盖有隔离 层；沉积所述导电晶粒至所述隔离层表面，以形成所述导电膜；其中，所述隔离层的材料包括钛、氮化钛、钽或氮化钽。
  9. 根据权利要求8所述的方法，其中，所述隔离层的厚度为5nm～50nm。
  10. 根据权利要求1所述的方法，其中，在进行所述回流工艺之后，形成抗反射层，所述抗反射层覆盖所述导电层远离所述晶圆的表面。
  11. 根据权利要求10所述的方法，其中，所述抗反射层的材料包括氮化钛，所述抗反射层的厚度为10nm～50nm。
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