WO2021166963A1 - 個片化方法 - Google Patents

個片化方法 Download PDF

Info

Publication number
WO2021166963A1
WO2021166963A1 PCT/JP2021/005957 JP2021005957W WO2021166963A1 WO 2021166963 A1 WO2021166963 A1 WO 2021166963A1 JP 2021005957 W JP2021005957 W JP 2021005957W WO 2021166963 A1 WO2021166963 A1 WO 2021166963A1
Authority
WO
WIPO (PCT)
Prior art keywords
wafer
irradiation
laser beam
metal layer
street
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2021/005957
Other languages
English (en)
French (fr)
Japanese (ja)
Inventor
剛史 原田
博昭 太田
芳宏 松島
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nuvoton Technology Corp Japan
Original Assignee
Nuvoton Technology Corp Japan
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nuvoton Technology Corp Japan filed Critical Nuvoton Technology Corp Japan
Priority to JP2022501939A priority Critical patent/JP7062147B2/ja
Priority to CN202210985262.2A priority patent/CN115332064B/zh
Priority to CN202180005345.4A priority patent/CN114424323B/zh
Publication of WO2021166963A1 publication Critical patent/WO2021166963A1/ja
Priority to JP2022032197A priority patent/JP2022067118A/ja
Priority to US17/722,993 priority patent/US11488867B2/en
Anticipated expiration legal-status Critical
Priority to US17/951,021 priority patent/US11646230B2/en
Ceased legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P52/00—Grinding, lapping or polishing of wafers, substrates or parts of devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P54/00—Cutting or separating of wafers, substrates or parts of devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P34/00—Irradiation with electromagnetic or particle radiation of wafers, substrates or parts of devices
    • H10P34/40—Irradiation with electromagnetic or particle radiation of wafers, substrates or parts of devices with high-energy radiation
    • H10P34/42—Irradiation with electromagnetic or particle radiation of wafers, substrates or parts of devices with high-energy radiation with electromagnetic radiation, e.g. laser annealing
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/7402—Wafer tapes, e.g. grinding or dicing support tapes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N30/00—Piezoelectric or electrostrictive devices
    • H10N30/01—Manufacture or treatment
    • H10N30/08—Shaping or machining of piezoelectric or electrostrictive bodies
    • H10N30/085—Shaping or machining of piezoelectric or electrostrictive bodies by machining
    • H10N30/088—Shaping or machining of piezoelectric or electrostrictive bodies by machining by cutting or dicing
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P70/00—Cleaning of wafers, substrates or parts of devices
    • H10P70/30—Cleaning after the substrates have been singulated
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/7416—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/7422—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support used to protect an active side of a device or wafer
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W46/00—Marks applied to devices, e.g. for alignment or identification
    • H10W46/501—Marks applied to devices, e.g. for alignment or identification for use before dicing
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W46/00—Marks applied to devices, e.g. for alignment or identification
    • H10W46/601—Marks applied to devices, e.g. for alignment or identification for use after dicing

Definitions

  • Patent Document 1 a semiconductor device including a semiconductor layer and a metal layer formed on the lower surface thereof is known (see, for example, Patent Document 1).
  • a semiconductor device including a semiconductor layer and a metal layer formed on the lower surface thereof can be obtained by separating a wafer having a metal layer formed on the lower surface into pieces.
  • the thickness of the wafer in order to reduce the resistance value in the thickness direction of the semiconductor layer, there is a desire to make the thickness of the wafer relatively thin, more specifically, to be as thin as 30 ⁇ m or less.
  • an object of the present disclosure is to provide a method for individualizing a wafer without using a blade.
  • the individualization method is an individualization method for individualizing a wafer having a plurality of semiconductor element structures formed on its upper surface, and a surface retaining film is formed on the upper surface of the wafer.
  • the ninth step of removing the water-soluble protective layer is included in order, and the thickness of the first metal layer is 30 ⁇ m or more and 60 ⁇ m or less, and the thickness of the second metal layer is 10 ⁇ m or more and 40 ⁇ m or less.
  • the young ratio of the first metal layer is 80 GPa or more and 130 GPa or less, and the young ratio of the second metal layer is 190 GPa or more and 220 GPa or less.
  • the individualization method is an individualization method for individualizing a wafer in which a plurality of semiconductor element structures are formed on the upper surface, and the lower surface of the wafer is thinned.
  • a second laser is provided in a region adjacent to the cut within a predetermined range on both sides of the center line of the cut region cut by the third step.
  • a fourth step of irradiating the in-cut region included in the cutting region with a third laser beam is sequentially included.
  • the wafer can be individualized without using a blade.
  • FIG. 1 is a cross-sectional view showing an example of the structure of the semiconductor device according to the first embodiment.
  • FIG. 2 is a plan view showing an example of the structure of the semiconductor device according to the first embodiment.
  • FIG. 3A is a schematic enlarged cross-sectional view of the wafer according to the first embodiment.
  • FIG. 3B is a schematic enlarged cross-sectional view of the wafer according to the first embodiment.
  • FIG. 3C is a schematic enlarged cross-sectional view of the wafer according to the first embodiment.
  • FIG. 3D is a schematic enlarged cross-sectional view of the wafer according to the first embodiment.
  • FIG. 3E is a schematic enlarged cross-sectional view of the wafer according to the first embodiment.
  • FIG. 3F is a schematic enlarged cross-sectional view of the wafer according to the first embodiment.
  • FIG. 3G is a schematic enlarged cross-sectional view of the wafer according to the first embodiment.
  • FIG. 3H is a schematic enlarged cross-sectional view of the wafer according to the first embodiment.
  • FIG. 3I is a schematic enlarged cross-sectional view of the wafer according to the first embodiment.
  • FIG. 3J is a schematic enlarged cross-sectional view of the wafer according to the first embodiment.
  • FIG. 4 is a schematic plan view of the wafer according to the first embodiment.
  • FIG. 5A is a schematic plan view showing an example of irradiating the upper surface of the wafer with laser light in the eighth step according to the first embodiment.
  • FIG. 5A is a schematic plan view showing an example of irradiating the upper surface of the wafer with laser light in the eighth step according to the first embodiment.
  • FIG. 5B is a schematic plan view showing an example of irradiating the upper surface of the wafer with laser light in the eighth step according to the first embodiment.
  • FIG. 6 is a schematic enlarged cross-sectional view of the semiconductor device according to the first embodiment.
  • FIG. 7 is a schematic enlarged cross-sectional view of the semiconductor device according to the first embodiment.
  • FIG. 8A is a schematic enlarged cross-sectional view of the wafer according to the second embodiment.
  • FIG. 8B is a schematic enlarged cross-sectional view of the wafer according to the second embodiment.
  • FIG. 8C is a schematic enlarged cross-sectional view of the wafer according to the second embodiment.
  • FIG. 9A is a schematic enlarged cross-sectional view of the wafer according to the third embodiment.
  • FIG. 9B is a schematic enlarged cross-sectional view of the wafer according to the third embodiment.
  • FIG. 9C is a schematic enlarged cross-sectional view of the wafer according to the third embodiment.
  • FIG. 9D is a schematic enlarged cross-sectional view of the wafer according to the third embodiment.
  • FIG. 10 is a schematic enlarged plan view showing an example of irradiating the upper surface of the wafer with the second laser beam and the third laser beam in the 49th step according to the third embodiment.
  • FIG. 11A is a schematic enlarged plan view showing an example of irradiating the upper surface of the wafer with the second laser beam in the 49th step according to the third embodiment.
  • FIG. 11B is a schematic enlarged plan view showing an example of irradiating the upper surface of the wafer with the second laser beam in the 49th step according to the third embodiment.
  • FIG. 11C is a schematic enlarged plan view showing an example of irradiating the upper surface of the wafer with the second laser beam in the 49th step according to the third embodiment.
  • FIG. 11D is a schematic enlarged plan view showing an example of irradiating the upper surface of the wafer with the second laser beam in the 49th step according to the third embodiment.
  • FIG. 12A is a schematic enlarged plan view showing an example of irradiating the upper surface of the wafer with the second laser beam and the third laser beam in the 49th step according to the third embodiment.
  • FIG. 12B is a schematic enlarged plan view showing an example of irradiating the upper surface of the wafer with the second laser beam and the third laser beam in the 49th step according to the third embodiment.
  • FIG. 12C is a schematic enlarged plan view showing an example of irradiating the upper surface of the wafer with the second laser beam and the third laser beam in the 49th step according to the third embodiment.
  • the inventors have diligently, experimented, and studied a method for individualizing a wafer having a metal layer formed on its lower surface without using a blade. Then, the inventors have obtained the finding that the wafer can be cut together with the metal layer by irradiating the upper surface of the wafer having the metal layer formed on the lower surface with a laser beam.
  • the inventors further diligently, experimented, and studied. More specifically, the inventors have described a metal having a thickness of 30 ⁇ m or less, a thickness of 30 ⁇ m or more and 60 ⁇ m or less, and a Young's modulus of 80 GPa or more and 130 GPa or less (for example, silver, copper, etc.) on the lower surface thereof. ) And a second metal layer made of a metal having a thickness of 10 ⁇ m or more and 40 ⁇ m or less and a Young's modulus of 100 GPa or more and 220 GPa or less (for example, nickel). , Diligently, experimented, and examined.
  • a metal layer When cutting a metal layer using a laser, it is formed by forming a metal that is scattered by irradiation with laser light, or by cooling and solidifying the metal that was once liquefied or vaporized by the heat generated by irradiation with laser light. It is known that the formed product adheres to the semiconductor device. Therefore, when the metal layer is cut using a laser, the surface of the wafer is covered with a water-soluble protective layer before irradiation with the laser beam, and a metal-containing formation forming the metal layer is formed on the surface of the wafer. It is desirable not to adhere to. In this case, if the entire surface of the wafer cannot be covered with the water-soluble protective layer, the metal-containing formation forming the metal layer adheres to the surface portion of the wafer that is not covered with the water-soluble protective layer. Sometimes.
  • a process of grinding the lower surface of the wafer to thin the wafer is performed before the process of forming a metal layer on the lower surface of a wafer. Then, in order to protect the upper surface of the wafer in the thinning process, a step of forming a surface retaining film on the upper surface of the wafer is performed before the thinning process. This surface retaining film is removed from the wafer after the thinning process.
  • the inventors have found that the cause of the metal-containing formations constituting the metal layer adhering to the semiconductor layer is locally on the surface of the wafer when the surface retaining film is removed from the upper surface of the wafer.
  • the surface-retaining film partially remains, and the residual surface-retaining film reduces the hydrophilicity of the wafer surface, making it impossible to cover the entire surface of the wafer with the water-soluble protective layer.
  • the inventors will construct a metal layer if the surface of the wafer can be made highly hydrophilic at the start of the process of covering the entire surface of the wafer with the water-soluble protective layer.
  • it is possible to individualize a semiconductor device that suppresses the adhesion of metal-containing formations further experiments and studies were conducted. As a result, the inventors came up with the following individualization method.
  • the individualization method is an individualization method for individualizing a wafer having a plurality of semiconductor element structures formed on its upper surface, and a surface retaining film is formed on the upper surface of the wafer.
  • the ninth step of removing the water-soluble protective layer is included in order, and the thickness of the first metal layer is 30 ⁇ m or more and 60 ⁇ m or less, and the thickness of the second metal layer is 10 ⁇ m or more and 40 ⁇ m or less.
  • the young ratio of the first metal layer is 80 GPa or more and 130 GPa or less, and the young ratio of the second metal layer is 190 GPa or more and 220 GPa or less.
  • the wafer can be individualized without using a blade.
  • the surface of the wafer can be made highly hydrophilic by the sixth step before forming the water-soluble protective layer on the surface of the wafer in the seventh step. can.
  • the entire surface of the wafer can be covered with the water-soluble protective layer. Therefore, the metal-containing formation forming the metal layer, which is formed by the irradiation of the laser beam in the eighth step, is suppressed from adhering to the surface of the wafer. Therefore, the adhesion of the metal-containing formation forming the metal layer is suppressed to the semiconductor device that has been individualized by the above-mentioned individualization method.
  • a semiconductor device that suppresses adhesion of a formation containing a metal constituting a metal layer is provided.
  • the predetermined region comprises a plurality of grid-like streets that individually divide the plurality of semiconductor element structures in the plan view of the wafer
  • the eighth step is the first step in the plan view of the wafer.
  • the tenth step of irradiating each of the plurality of first streets extending in the direction with the laser beam from one end to the other end or from the other end to the one end of the first street is performed a plurality of times. From one end to the other end of the second street in each of the eleventh step and the plurality of second streets extending in the second direction orthogonal to the first direction in the plan view of the wafer.
  • a thirteenth step of performing the twelfth step of irradiating the laser beam from the other end to the one end a plurality of times and the eleventh step is among the plurality of first streets.
  • the thirteenth step is a step of not irradiating the laser beam, and the thirteenth step starts the twelfth step of the plurality of times with respect to one second street of the plurality of second streets.
  • the step may be a step in which the laser beam is not applied to the other second street of the plurality of second streets.
  • the first metal layer and the second metal layer have a bimetal structure composed of two types of metals having different Young's moduli. Therefore, cutting of the wafer, the first metal layer, and the second metal layer in the next one street in a state where the wafer in one street, the first metal layer, and the second metal layer cannot be completely cut.
  • the release of the warp stress inherent in the wafer occurs in a non-uniform state in the wafer, so that the misalignment of the street may occur.
  • the eleventh step after performing the tenth step a plurality of times for one first street, the tenth step for the next one first street starts. Will be done. Therefore, after the wafer in the first street of 1 and the first metal layer and the second metal layer are surely cut, the wafer in the next 1st street, the first metal layer, and the first metal layer are cut. Cutting with the metal layer of 2 can be started.
  • the twelfth step for the next one second street is started. Therefore, after the wafer in the first second street, the first metal layer, and the second metal layer are surely cut, the wafer in the next first second street, the first metal layer, and the first metal layer are cut. Cutting with the metal layer of 2 can be started.
  • the wafer and the first metal layer in the next one street are in a state where the wafer in one street, the first metal layer, and the second metal layer are not completely cut. It is possible to prevent the start of cutting between the and the second metal layer.
  • the eleventh step the tenth step, which is performed a plurality of times for each of the plurality of first streets, is performed from the first street at one end to the other end in the second direction.
  • the twelfth step which is performed in the order of arranging toward the first street and is performed for each of the plurality of second streets in the thirteenth step, is performed at one end in the first direction. It may be performed in the order of arranging from the second street of the above to the second street at the other end.
  • the wafer and the first metal layer and the second metal layer can be efficiently cut in the plurality of first streets, and the wafer and the first metal layer in the plurality of second streets can be efficiently cut. Cutting between the metal layer and the second metal layer can be efficiently performed.
  • the plurality of times the tenth step performed on each of the plurality of first streets emits the laser beam from one end to the other end of the first street.
  • the thirteenth step comprises one first outbound irradiation step of irradiating and one first inbound irradiation step of irradiating the laser beam from the other end to the one end of the first street.
  • one second step of irradiating the laser beam from one end to the other end of the second street may be composed of the outbound irradiation step of the above and one second return irradiation step of irradiating the laser beam from the other end to the one end of the second street.
  • the first metal layer is cut, and the second outbound irradiation step and the second outbound irradiation step are performed.
  • the first metal layer may be cut in the first step of the return irradiation step of the above.
  • the plurality of times the tenth step performed on each of the plurality of first streets emits the laser beam from one end to the other end of the first street.
  • the irradiation condition of the laser beam in the outbound irradiation step is equal to the irradiation condition of the laser beam in the first return irradiation step, and in the thirteenth step, for each of the plurality of second streets.
  • the plurality of times of the twelfth step is one or more second outbound irradiation steps of irradiating the laser beam from one end to the other end of the second street, and the second street. It comprises one or more second return irradiation steps of irradiating the laser beam from the other end to the one end, and the irradiation conditions of the laser beam in the second outbound irradiation step and the second return path irradiation step. It may be the same as the irradiation condition of the laser beam.
  • a groove is formed in the inter-element structure region between the plurality of semiconductor element structures on the upper surface of the wafer.
  • the predetermined region may be included in the inter-element structure region.
  • HAZ Heat Affected Zone
  • the region where HAZ that can be formed by the irradiation of the laser beam in the eighth step is generated can be removed in advance by the fourteenth step.
  • the individualization method is an individualization method for individualizing a wafer having a plurality of semiconductor element structures formed on its upper surface, and is a first method of thinning the lower surface of the wafer.
  • the third step of cutting the layer and in the plan view of the wafer the second laser beam is applied to the cutting adjacent region within a predetermined range on both sides of the center line of the cutting region cut by the third step.
  • a fourth step of irradiating the in-cut region included in the cutting region with a third laser beam in the plan view of the wafer is included in order.
  • the wafer can be individualized without using a blade.
  • HAZ that can be formed by the first laser beam irradiated in the third step can be removed by the irradiation of the second laser beam in the fourth step.
  • the metal-containing formation forming the metal layer adheres as burrs to the inside of the cut region in the plan view of the wafer. There is.
  • the burr can be removed by irradiating the third laser beam in the fourth step.
  • the first laser beam, the second laser beam, and the third laser beam may use one laser beam output device as a light source.
  • the above-mentioned individualization method can be realized by one laser beam output device.
  • the cutting adjacent region comprises a first cutting adjacent region on one side of the center line and a second cutting adjacent region on the other side of the center line.
  • the irradiation of the second laser beam to the cutting adjacent region is obtained by splitting a part of the laser beam output from the first laser beam output device into a plurality of second laser beams.
  • the plurality of second irradiation spots obtained by irradiating the first irradiation spot to the first cutting adjacent region and branching a part of the laser light output from the first laser light output device into a plurality of laser light output spots are described above.
  • the irradiation of the third laser beam to the cutting inner region branches a plurality of a part of the laser light output from the laser light output device of the first.
  • This is carried out by irradiating the cut inner region with the plurality of third irradiation spots obtained by the above, and in the plan view of the wafer, the plurality of first irradiation spots and the plurality of second irradiation spots.
  • the plurality of first irradiation spots and the plurality of second irradiation spots so that the plurality of third irradiation spots proceed relative to the wafer along the cutting direction of the cutting region.
  • the plurality of third irradiation spots, or the plurality of first irradiation spots and the plurality of second irradiation spots in a plan view of the wafer by advancing the wafer.
  • the plurality of first irradiation spots are the plurality of first irradiation spots and the plurality of second irradiation spots.
  • the irradiation spot and the plurality of third irradiation spots are located so as to monotonically increase the shortest distance from the center line from the front to the rear in the traveling direction in which the laser travels relative to the wafer.
  • the plurality of third irradiation spots may be arranged on one or more straight lines.
  • the shallow part from the wafer surface which is the irradiated surface of the laser beam, is removed from the cutting area to the far part, and the deep part from the wafer surface is only near the cutting area. Will be removed. Further, if the positions of the irradiation spots are slightly shifted, the probability that any of the irradiation spots will be irradiated near both ends of the cutting region can be increased, so that the desired processing can be realized.
  • At least one of the plurality of first irradiation spots may be located in the cutting region.
  • the HAZ formed in the cutting region can be removed by irradiating the second laser beam in the fourth step.
  • the plurality of first irradiation spots may be arranged on one straight line.
  • the plurality of first irradiation spots may be arranged on two or more sides.
  • At least one of the plurality of third irradiation spots may be located in front of the plurality of first irradiation spots in the traveling direction.
  • the irradiation of the third laser beam, which precedes the second laser beam can raise the temperature of the planned processing region of the second laser beam in advance, so that the metal layer can be efficiently vaporized. Therefore, the adhesion of the burr can be suppressed.
  • At least one of the plurality of first irradiation spots may be located in front of the plurality of third irradiation spots in the traveling direction.
  • the metal-containing formation that constitutes the metal layer which is newly generated by the irradiation of the second laser beam, grows into burrs in a state where it can be easily removed, and then is removed by the third laser beam. can. Therefore, the adhesion of the burr can be suppressed.
  • At least one of the plurality of third irradiation spots may be located behind the plurality of first irradiation spots in the traveling direction.
  • the formation containing the metal constituting the metal layer newly generated by the irradiation of the second laser beam can be more effectively removed by the third laser beam. Therefore, the adhesion of the burr can be suppressed.
  • the plurality of third irradiation spots may be arranged on a straight line of 2.
  • the semiconductor device according to the first embodiment is a chip size package (CSP) type semiconductor device capable of face-down mounting in which two vertical MOS (Metal Oxide Semiconductor) transistors are formed.
  • the above two vertical MOS transistors are power transistors, and are so-called trench MOS type FETs (Field Effect Transistors).
  • FIG. 1 is a cross-sectional view showing an example of the structure of the semiconductor device 1 according to the first embodiment.
  • FIG. 2 is a plan view showing an example of the configuration of the semiconductor device 1.
  • FIG. 1 shows the cut surface in I-I of FIG.
  • the semiconductor device 1 includes a semiconductor layer 40, a metal layer 30, and a first vertical MOS transistor 10 (hereinafter, hereinafter, formed in a first region A1 in the semiconductor layer 40). It also has a “transistor 10") and a second vertical MOS transistor 20 (hereinafter, also referred to as "transistor 20") formed in the second region A2 in the semiconductor layer 40.
  • the first region A1 and the second region A2 are adjacent to each other in the plan view of the semiconductor layer 40, and the semiconductor device 1 is bisected by the area and the other. ..
  • the semiconductor layer 40 is formed by laminating a semiconductor substrate 32, a low-concentration impurity layer 33, and an oxide film 34.
  • the wafer refers to the semiconductor layer 40.
  • the semiconductor substrate 32 is arranged on the lower surface side of the semiconductor layer 40 and is made of silicon containing first conductive type impurities.
  • the low-concentration impurity layer 33 is arranged on the upper surface side of the semiconductor layer 40, is formed in contact with the semiconductor substrate 32, and has a concentration of first conductive type impurities lower than the concentration of the first conductive type impurities of the semiconductor substrate 32. include.
  • the low-concentration impurity layer 33 may be formed on the semiconductor substrate 32 by, for example, epitaxial growth.
  • the oxide film 34 is arranged on the uppermost surface of the semiconductor layer 40 and is formed in contact with the low-concentration impurity layer 33.
  • the protective layer 35 is formed in contact with the upper surface of the semiconductor layer 40 and covers at least a part of the upper surface of the semiconductor layer 40.
  • the metal layer 30 is formed in contact with the entire lower surface of the semiconductor substrate 32.
  • the metal layer 30 is formed by superimposing a first metal layer 30A on the semiconductor substrate 32 side and a second metal layer 30B on the opposite side.
  • the first metal layer 30A is formed by plating, for example, has a thickness of 30 ⁇ m or more and 60 ⁇ m or less, and has a Young's modulus of 80 GPa or more and 130 GPa or less.
  • the first metal layer may be composed of silver or copper, as an example but not limited to.
  • the second metal layer 30B is formed by plating, for example, has a thickness of 10 ⁇ m or more and 40 ⁇ m or less, and has a Young's modulus of 190 GPa or more and 220 GPa or less.
  • the second metal layer may be composed of nickel, as an example but not limited to.
  • the first metal layer 30A and the second metal layer 30B may contain a small amount of elements other than metal mixed as impurities in the manufacturing process of the metal material.
  • the transistor 10 is a first of one or more (six in this case), which is bonded to the upper surface of the semiconductor layer 40 via a bonding material at the time of face-down mounting.
  • Source pads 111 here, first source pads 111a, 111b, 111c, 111d, 111e, and 111f
  • first gate pad 119 the transistor 20 is bonded to the upper surface of the semiconductor layer 40 at the time of face-down mounting via a bonding material, and one or more (six in this case) second source pads 121 (here, second). 121a, 121b, 121c, 121d, 121e, and 121f), and a second gate pad 129.
  • the semiconductor layer 40 has a rectangular shape in a plan view, and the transistors 10 and 20 are arranged in the first direction.
  • the semiconductor layer 40 has one long side 91 parallel to the first direction and the other long side 92, and one short side 93 and the other short side in the direction orthogonal to the first direction. It is assumed that it has a rectangular shape having sides 94. That is, here, it is assumed that the semiconductor layer 40 has a rectangular shape having a long side in the first direction.
  • the center line 90 is a line that bisects the rectangular semiconductor layer 40 in the first direction in the plan view of the semiconductor layer 40. Therefore, the center line 90 is a straight line in the direction orthogonal to the first direction in the plan view of the semiconductor layer 40.
  • Boundary 90C is the boundary between the first region A1 and the second region A2.
  • the boundary 90C divides the semiconductor layer 40 into two equal parts by area in the plan view of the semiconductor layer 40, but the boundary 90C does not necessarily have to be a straight line. In the plan view of the semiconductor layer 40, the center line 90 and the boundary 90C may or may not match.
  • first gate pad 119 and the number of the second gate pads 129 are not necessarily limited to one illustrated in FIG.
  • the number of one or more first source pads 111 and the number of one or more second source pads 121 are not necessarily limited to the six illustrated in FIG. 2, and are six. It may be a number of 1 or more other than.
  • a first body region 18 containing a second conductive type impurity different from the first conductive type is formed in the first region A1 of the low concentration impurity layer 33.
  • a first source region 14, a first gate conductor 15, and a first gate insulating film 16 containing first conductive type impurities are formed in the first body region 18.
  • the first source electrode 11 is composed of a portion 12 and a portion 13, and the portion 12 is connected to the first source region 14 and the first body region 18 via the portion 13.
  • the first gate conductor 15 is electrically connected to the first gate pad 119.
  • the portion 12 of the first source electrode 11 is a layer that is bonded to the solder during reflow in face-down mounting, and is a metal material containing any one or more of nickel, titanium, tungsten, and palladium as an unrestricted example. It may be composed of.
  • the upper surface of the portion 12 may be plated with gold or the like.
  • the portion 13 of the first source electrode 11 is a layer connecting the portion 12 and the semiconductor layer 40, and as an example without limitation, a metal material containing any one or more of aluminum, copper, gold, and silver. It may be configured.
  • a second body region 28 containing a second conductive type impurity is formed in the second region A2 of the low-concentration impurity layer 33.
  • a second source region 24 containing first conductive type impurities, a second gate conductor 25, and a second gate insulating film 26 are formed in the second body region 28.
  • the second source electrode 21 is composed of a portion 22 and a portion 23, and the portion 22 is connected to the second source region 24 and the second body region 28 via the portion 23.
  • the second gate conductor 25 is electrically connected to the second gate pad 129.
  • Part 22 of the second source electrode 21 is a layer that is bonded to the solder during reflow in face-down mounting, and is, by way of example, a metal material containing one or more of nickel, titanium, tungsten, and palladium. It may be composed of.
  • the upper surface of the portion 22 may be plated with gold or the like.
  • the portion 23 of the second source electrode 21 is a layer connecting the portion 22 and the semiconductor layer 40, and as an example without limitation, a metal material containing any one or more of aluminum, copper, gold, and silver. It may be configured.
  • the low-concentration impurity layer 33 and the semiconductor substrate 32 function as a common drain region in which the first drain region of the transistor 10 and the second drain region of the transistor 20 are shared. do.
  • the first body region 18 is covered with an oxide film 34 having an opening, and a portion of the first source electrode 11 connected to the first source region 14 through the opening of the oxide film 34. 13 is provided.
  • the oxide film 34 and the portion 13 of the first source electrode 11 are covered with a protective layer 35 having an opening, and a portion 12 connected to the portion 13 of the first source electrode 11 through the opening of the protective layer 35 is provided. There is.
  • the second body region 28 is covered with an oxide film 34 having an opening, and a portion 23 of the second source electrode 21 connected to the second source region 24 through the opening of the oxide film 34 is provided.
  • the oxide film 34 and the portion 23 of the second source electrode 21 are covered with a protective layer 35 having an opening, and a portion 22 connected to the portion 23 of the second source electrode 21 through the opening of the protective layer 35 is provided. There is.
  • the first source electrode 11 and the second source electrode 21 are partially exposed on the upper surface of the semiconductor device 1, respectively.
  • the first gate pad 119 and the second gate pad 129 have a first gate electrode 19 (not shown in FIGS. 1 and 2) and a second gate electrode 29 (FIGS. 1 and 2, respectively).
  • FIG. 2 refers to a region partially exposed on the upper surface of the semiconductor device 1, a so-called terminal portion.
  • the source pad and the gate pad are collectively referred to as an "electrode pad".
  • the thickness of the semiconductor layer 40 is 10 to 90 ⁇ m
  • the thickness of the metal layer 30 is 40 to 100 ⁇ m
  • the oxide film 34 and the protective layer 35 are used.
  • the sum of the thicknesses with and is 3-13 ⁇ m.
  • the semiconductor device 1 is formed by individualizing a wafer on which a plurality of semiconductor element structures are formed.
  • individualizing a wafer means cutting the wafer and individually dividing a plurality of semiconductor element structures formed in an array on the wafer.
  • the first individualization method is executed for a wafer in which a plurality of semiconductor element structures are formed in an array.
  • the first individualization method includes a plurality of steps.
  • FIG. 3A is a schematic enlarged cross-sectional view of the vicinity of the cutting region of the wafer 100 at the time when the first individualization method is started, and FIGS. 3B to 3J are carried out in the first individualization method. It is a schematic enlarged cross-sectional view near the cutting region of the wafer 100 in each step.
  • the first individualization method includes the first step to the ninth step in order.
  • the first step is a step of forming the surface holding film 50 on the upper surface of the wafer 100.
  • This first step is performed in order to prevent the surface of the wafer 100 from being damaged by foreign matter or the like that may be generated in the second step described later, and the surface of the wafer 100 from being contaminated. ..
  • the surface retaining film 50 may be, for example, a back grind tape.
  • the first step is realized by, for example, attaching the back grind tape to the upper surface of the wafer 100.
  • the back grind tape may be, for example, an adhesive tape having an ethylene-vinyl acetate copolymer as a surface base material and an acrylic resin as an adhesive layer.
  • the second step is a step of thinning the lower surface of the wafer 100 to a thickness of the wafer 100 of 30 ⁇ m or less.
  • the second step is realized by, for example, grinding the lower surface of the wafer 100.
  • the process of grinding the lower surface of a wafer is also referred to as back grind. Therefore, in other words, the second step is realized by, for example, backgrinding the lower surface of the wafer 100.
  • the second step is realized by, for example, backgrinding the lower surface of the wafer 100.
  • the third step is a step of removing the surface holding film 50 formed on the upper surface of the wafer 100 in the first step from the upper surface of the wafer 100.
  • the third step is realized by, for example, peeling off the attached back grind tape from the upper surface of the wafer 100.
  • the third step it is difficult to completely remove the surface retaining film 50 formed on the upper surface of the wafer 100.
  • the fourth step is a step of forming the first metal layer 30A and the second metal layer 30B on the lower surface of the wafer 100 thinned in the second step in this order. That is, it is a step of forming the metal layer 30.
  • the first metal layer 30A and the second metal layer 30B may be composed of, for example, a single metal or an alloy composed of a plurality of metals, respectively. Further, the first metal layer 30A and the second metal layer 30B may be composed of a single layer made of one metal or one alloy, respectively, or may be made of a plurality of different metals or alloys. The layers may be superposed to each other.
  • the formation of the first metal layer 30A may be realized by, for example, depositing a metal on the lower surface of the wafer 100, or by plating a metal, for example, or by depositing a metal. Later, it may be realized by plating the same or different metals.
  • the formation of the second metal layer 30B may be realized by depositing a metal on the lower surface of the first metal layer 30A, for example, or by plating a metal, for example. However, it may be realized by plating the same or different metals after depositing the metal.
  • the fifth step is a step of attaching the dicing tape 52 to the lower surface of the metal layer 30 formed in the fourth step.
  • the dicing tape 52 may be, for example, an adhesive tape using a polyolefin, an acrylic urethane resin, an acrylic acid ester copolymer, or the like as a base material.
  • the sixth step is a step of applying a treatment to the upper surface of the wafer 100 to increase the hydrophilicity of the surface of the wafer 100.
  • the treatment for increasing the hydrophilicity is a step of cleaning the surface holding film 50 remaining without being completely removed from the surface of the wafer 100 in the third step, for example, a plasma treatment of dry cleaning using plasma.
  • a plasma treatment of dry cleaning using plasma It may be an organic solvent cleaning treatment in which wet cleaning is performed with an appropriate organic solvent, for example, acetone, a UV irradiation treatment for irradiating ultraviolet rays, or an ashing treatment. good.
  • the treatment for increasing hydrophilicity is plasma treatment by the atmospheric pressure plasma method using argon and oxygen as raw materials.
  • the surface of the wafer 100 is made relatively highly hydrophilic, and in the seventh step described later, the entire surface of the wafer 100 is covered with the water-soluble protective layer 51 (see FIG. 3H). It is a process to enable you to do it.
  • the sixth step is performed before the seventh step is started to bring the surface of the wafer 100 into a relatively highly hydrophilic state.
  • this sixth step is not performed before the seventh step, the hydrophilicity of the surface of the wafer 100 is lowered in the third step. Therefore, in the seventh step, The entire surface of the wafer 100 cannot be covered with the water-soluble protective layer 51.
  • the metal forming the metal layer 30 formed due to the irradiation of the laser beam in the eighth step described later is included. It is possible to prevent the formed product from adhering to the surface of the wafer 100.
  • the seventh step is a step of forming the water-soluble protective layer 51 on the surface of the wafer 100.
  • the formation of the water-soluble protective layer 51 on the surface of the wafer 100 is realized by, for example, coating the surface of the wafer 100 with a coating agent for forming the water-soluble protective layer 51 with a spin coater.
  • the coating agent that is, the water-soluble protective layer 51 may be, for example, 1-methoxy-2-propanol monopropylene glycol methyl ether.
  • Coating with a spin coater is realized, for example, by rotating the wafer 100 at a rotation speed faster than 500 rpm and dropping a coating agent of less than 100 ml onto the surface of the wafer 100.
  • the wafer 100 is stored in an environment where the wafer 100 is stored during the period from the treatment for increasing the hydrophilicity of the surface of the wafer 100 to the start of the seventh step on the upper surface of the wafer 100.
  • the wafer 100 be stored in a controlled environment during the period from the end of the sixth process to the start of the seventh process.
  • the wafer 100 is stored in an environment of 5000 or less particles of 0.5 ⁇ m per cubic foot, and 240 from the end of the sixth step. It is desirable to start the seventh step in less than an hour.
  • the cutting region which is a predetermined region of the wafer 100, is irradiated with a laser beam to cut the wafer 100, the first metal layer 30A, and the second metal layer 30B. It is a process to do.
  • the laser that irradiates the laser beam may be, for example, a Q-switched laser having a wavelength of 355 nm.
  • FIG. 4 is a schematic plan view of the wafer 100.
  • the cutting region which is a predetermined region of the wafer 100, is composed of a plurality of grid-like streets that individually divide the plurality of semiconductor element structures 230 in the plan view of the wafer 100.
  • the plurality of streets are the plurality of first streets 210 (here, the first streets 210A, 210B, which extend in the first direction (here, the left-right direction in FIG. 4) in the plan view of the wafer 100.
  • the second streets 220A, 220B, 220C, 220D, 220E, 220F, 220G, and 220H are the plurality of first streets 210 (here, the first streets 210A, 210B, which extend in the first direction (here, the left-right direction in FIG.
  • the tenth step of irradiating each of the plurality of first street 210s with the laser beam from one end to the other end or from the other end to one end of the first street 210 is performed a plurality of times.
  • the eleventh step and the twelfth step of irradiating each of the plurality of second streets 220 with the laser beam from one end to the other end or from the other end to the other end of the second street 220 are performed a plurality of times. Including the thirteenth step.
  • the eleventh step is performed on the first street 210 of one of the plurality of first streets 210 during the period from the start to the end of the tenth steps of the plurality of times. It is a step of not irradiating the other first street 210 with the laser beam, and the thirteenth step is a plurality of times of the second street 220 of one of the plurality of second streets 220. During the period from the start to the end of the 12 steps, the other second street 220 is not irradiated with the laser beam.
  • the first metal layer 30A and the second metal layer 30B have a bimetal structure made of two types of metals having different Young's moduluss from each other. Therefore, the wafer 100, the first metal layer 30A, and the second metal layer 30A in the next one street cannot be completely cut from the wafer 100, the first metal layer 30A, and the second metal layer 30B in one street.
  • the release of the warp stress inherent in the wafer occurs in a non-uniform state in the wafer, so that the street may be displaced.
  • the eleventh step after performing the tenth step a plurality of times with respect to one first street 210, the tenth step with respect to the next one first street 210 is started.
  • NS Therefore, after surely cutting the wafer 100 in the first street 210, the first metal layer 30A, and the second metal layer 30B, the wafer 100 and the first metal layer 30B in the next one first street 210 are completely cut. Cutting of the first metal layer 30A and the second metal layer 30B can be started.
  • the twelfth step after performing the twelfth step a plurality of times with respect to one second street 220, the twelfth step with respect to the next one second street 220 is started. NS. Therefore, in the thirteenth step, after the wafer 100, the first metal layer 30A, and the second metal layer 30B in the second street 220 are surely cut, the next one in the second street 220 Cutting of the wafer 100, the first metal layer 30A, and the second metal layer 30B can be started.
  • the eighth step includes the eleventh step and the thirteenth step to cut the wafer 100, the first metal layer 30A, and the second metal layer 30B in one street. It is possible to prevent the wafer 100, the first metal layer 30A, and the second metal layer 30B from starting to be cut in the next one street in the absence state.
  • a plurality of tenth steps performed on each of the plurality of first streets 210 are performed on the first street 210 at one end in the second direction (here, the first street 210).
  • a plurality of streets 210A) to the other end of the first street 210 are arranged in this order
  • each of the plurality of second streets 220 is subjected to a plurality of operations.
  • the twelfth step of the times is carried out from the second street 220 at one end (here, the second street 220A) to the second street 220 at the other end (here, the second street 220H) in the first direction. It may be done in the order in which they are lined up.
  • the wafer 100, the first metal layer 30A, and the second metal layer 30B can be efficiently cut in the plurality of first streets 210, and the plurality of second streets 220 can be cut.
  • the wafer 100, the first metal layer 30A, and the second metal layer 30B can be efficiently cut.
  • the wafer 100, the first metal layer 30A, and the first metal layer 30A in the first street 210 of 1 are obtained by performing the tenth step twice with respect to the first street 210 of 1.
  • the metal layer 30B of 2 can be surely cut off, and by performing the twelfth step twice with respect to the second street 220 of 1, the wafer 100 and the first street 220 of the second street 220 of 1 can be cut.
  • 5A and 5B are schematic plan views showing an example of irradiating the upper surface of the wafer 100 with a laser beam in the eighth step.
  • the tenth step is performed on the plurality of first streets 210 in the order of A1, B1, C1, D1, E1, F1, ....
  • one first outbound irradiation step (A1 in FIG. 5A) of irradiating the first street 210A with a laser beam from one end to the other end is performed, and then subsequently.
  • the first return irradiation step (B1 in FIG. 5A) of irradiating the laser beam from the other end to one end is performed.
  • the first street 210B is subjected to one first outbound irradiation step (C1 in FIG. 5A) of irradiating the laser beam from one end to the other end, and subsequently, the laser beam is emitted from the other end to the other end.
  • the first return irradiation step (D1 in FIG. 5A) is performed once.
  • the first street 210C is subjected to one first outbound irradiation step (E1 in FIG. 5A) of irradiating the laser beam from one end to the other end, and subsequently, the laser beam is emitted from the other end to the other end.
  • the first return irradiation step (F1 in FIG. 5A) is performed once.
  • a plurality of first streets 210 are cut by performing one first outbound irradiation step and one first inbound irradiation step.
  • the wafer 100, the first metal layer 30A, and the second metal layer 30B can be reliably cut. If possible, by performing one first outbound irradiation step and one first inbound irradiation step for each of the plurality of first streets 210, these two tenth steps are performed. The process can be carried out efficiently.
  • the irradiation condition of the laser beam in the first outbound irradiation step may be equal to the irradiation condition of the laser beam in the first inbound irradiation step.
  • the first metal layer 30A is cut in the first step (here, the first outward irradiation step) of the first outward irradiation step and the first return irradiation step. good.
  • the twelfth step is performed on the plurality of second streets 220 in the order of A2, B2, C2, D2, E2, F2, ....
  • the second street 220A is subjected to one second outbound irradiation step (A2 in FIG. 5B) of irradiating the second street 220A with the laser beam from one end to the other end, and subsequently.
  • a second return irradiation step (B2 in FIG. 5B) of irradiating the laser beam from the other end to one end is performed.
  • the second street 220B is subjected to one second outbound irradiation step (C2 in FIG. 5B) of irradiating the second street 220B with the laser beam from one end to the other end, and subsequently, the laser beam is emitted from the other end to the other end.
  • the second return irradiation step (D2 in FIG. 5B) is performed once.
  • the second street 220C is subjected to one second outbound irradiation step (E2 in FIG. 5B) of irradiating the second street 220C with the laser beam from one end to the other end, and subsequently, the laser beam is applied from the other end to the other end.
  • the second return irradiation step (F2 in FIG. 5B) is performed once.
  • a plurality of second streets 220 are cut by performing one second outbound irradiation step and one second inbound irradiation step.
  • the wafer 100, the first metal layer 30A, and the second metal layer 30B can be reliably cut. If possible, by performing one second outbound irradiation step and one second inbound irradiation step for each of the plurality of second streets 220, these two twelfth steps are performed. The process can be carried out efficiently.
  • the irradiation condition of the laser beam in the second outbound irradiation step may be equal to the irradiation condition of the laser beam in the second inbound irradiation step.
  • the first metal layer 30A is cut in the first step (here, the second outward irradiation step) of the second outward irradiation step and the second return irradiation step. good.
  • the number of times that the tenth step is performed on the first street 210 of 1 is the number of times that the wafer 100, the first metal layer 30A, and the second metal layer 30B can be surely cut.
  • one or more first outbound irradiation steps and one or more first inbound irradiation steps may be performed.
  • the wafer 100, the first metal layer 30A, and the second metal layer 30B cannot be reliably cut.
  • the number of times that the twelfth step is performed with respect to one second street 220 is the number of times that the wafer 100, the first metal layer 30A, and the second metal layer 30B can be reliably cut. Therefore, one or more second outbound irradiation steps and one or more second inbound irradiation steps may be performed.
  • the irradiation condition of the laser light in the first outbound irradiation step and the irradiation condition of the laser light in the first return irradiation step are equal to each other, and the irradiation condition of the laser light in the second outbound irradiation step and the second It may be the same as the irradiation condition of the laser beam in the return irradiation step.
  • the eighth step when the metal layer 30 is cut by irradiating the metal layer 30 with the laser light, the formation made of the metal constituting the metal layer 30 is scattered by the irradiation of the laser light, and the heat generated by the irradiation of the laser light.
  • the metal once liquefied or vaporized cools and hardens again, a phenomenon occurs in which a formation is formed.
  • FIG. 6 shows a state in which a formation made of metal constituting the metal layer 30 (hereinafter, also referred to as “debris”) is formed by the above phenomenon. That is, it is a schematic enlarged cross-sectional view of the semiconductor device 1 that has been individualized by the first individualization method.
  • the debris 62 (debris 62A and 62B in FIG. 6) is formed on the water-soluble protective layer 51 on the surface of the protective layer 35 among the formed products scattered by the irradiation of the laser beam. .. Debris is also generated by irradiating the semiconductor layer 40 with laser light. That is, the constituent material of debris is not limited to metal, but may include semiconductors such as silicon.
  • the debris 63 (debris 63A and 63B in FIG. 6) is formed on the water-soluble protective layer 51 on the surface of the semiconductor layer 40 among the formed products scattered by the irradiation of the laser beam.
  • the debris 64 is a film-like state formed by vapor deposition in which, among the formed products scattered by the irradiation of the laser beam, those adhered to the water-soluble protective layer 51 on the surface of the semiconductor layer 40 are connected. be.
  • Debris 65 is a metal that has been liquefied or vaporized by the heat generated by laser light irradiation, and is pulled upward along the cut surface by the intake air generated by upper suction, stretched, and then cooled and solidified as it is.
  • the debris 66 is a metal that has been liquefied or vaporized by heat generated by laser light, stretched to the surface side of the protective layer 35, and cooled and solidified in a region where the water-soluble protective layer 51 has disappeared by laser light irradiation. Is.
  • the debris 67 is a metal that is once liquefied or vaporized by the heat generated by irradiation with a laser beam, and then cooled and solidified on the side surfaces of the semiconductor layer 40 and the side surface of the metal layer 30.
  • the ninth step is a step of removing the water-soluble protective layer 51 from the surface of the wafer 100 using cleaning water.
  • the debris adhering to the water-soluble protective layer 51 is removed from the surface of the wafer 100 together with the water-soluble protective layer 51.
  • the ninth step is realized by injecting cleaning water having a predetermined water pressure onto the upper surface of the rotating wafer 100. At this time, it is preferable that the ninth step is carried out so that the water-soluble protective layer 51 can be efficiently removed by adjusting the predetermined water pressure stepwise.
  • FIG. 7 is a schematic enlarged cross-sectional view of the wafer 100, that is, the semiconductor device 1 that has been individualized by the first individualization method at the end of the ninth step.
  • the debris 65, the debris 66, and the debris 67 may remain without being removed by the ninth step, but the debris 62, the debris 63, and the debris 63, The debris 64 is removed together with the water-soluble protective layer 51.
  • the wafer 100 can be individualized without using a blade.
  • the semiconductor device 1 individualized by the first individualization method is suppressed from adhering to the metal-containing formations constituting the metal layer 30. Therefore, according to the first individualization method, the semiconductor device 1 that suppresses the adhesion of the metal-containing formation forming the metal layer 30 is provided.
  • the semiconductor device 1 according to the first embodiment is manufactured by individualizing the wafer 100 by the first individualizing method.
  • the wafer 100 is individualized by the second individualization method in which a part of the steps is changed from the first individualization method.
  • the semiconductor device according to the second embodiment, which is individualized by the second individualization method, and the semiconductor device 1 are a semiconductor substrate 32, a low-concentration impurity layer 33, an oxide film 34, and water-soluble. The shape is different from that of the sex protection layer 51.
  • the semiconductor substrate 32 is referred to as a semiconductor substrate 32A
  • the low-concentration impurity layer 33 is referred to as a low-concentration impurity layer 33A
  • the oxide film 34 is referred to as an oxide film 34A
  • the water-soluble protective layer 51 is water-soluble. It is referred to as a protective layer 51A.
  • the semiconductor layer 40 is referred to as a semiconductor layer 40A
  • the wafer 100 is referred to as a wafer 100A.
  • the second individualization method includes the 21st step to the 30th step in order. Of these steps, the 21st step to the 27th step turn the wafer 100 into a wafer 100A with respect to the first step to the seventh step of the first individualization method in the first embodiment, respectively.
  • the semiconductor substrate 32 is replaced with the semiconductor substrate 32A
  • the low-concentration impurity layer 33 is replaced with the low-concentration impurity layer 33A
  • the oxide film 34 is replaced with the oxide film 34A
  • the water-soluble protective layer 51 is replaced with the water-soluble protective layer. It is the same as the one in which the semiconductor layer 40 is replaced with the semiconductor layer 40A by replacing it with 51A. Therefore, here, it is abbreviated that the 21st step to the 27th step have already been described, and the 28th step to the 30th step will be described.
  • 8A to 8C are schematic enlarged cross-sectional views of the vicinity of the cutting region of the wafer 100A in the 28th to 30th steps, respectively.
  • the 28th step is a step of forming a groove in an inter-element structure region between a plurality of semiconductor element structures on the upper surface of the wafer 100A.
  • the 28th step is, for example, a step of forming a groove in an inter-element structure region by irradiating a region forming a groove on the upper surface of the wafer 100A with a laser beam.
  • the cutting region is included in the region inside the groove.
  • the wafer when the wafer is irradiated with a laser beam having an output capable of cutting the metal layer (here, the first metal layer 30A and the second metal layer 30B), the wafer is surrounded by a cutting region in the wafer, which is called HAZ.
  • a region where the semiconductor crystal is altered may be formed due to the thermal effect of the laser.
  • the region where HAZ formed by the laser beam in the 29th step can be generated can be removed in advance by the 28th step.
  • This provides a semiconductor device in which the formation of HAZ is suppressed.
  • the 29th step is a step of irradiating a cutting region, which is a predetermined region of the wafer 100A, with a laser beam to cut the metal layer 30.
  • the wafer 100 is replaced with the wafer 100A and the semiconductor substrate 32 is replaced with the semiconductor substrate 32A, which is lower than the eighth step in the first individualization method according to the first embodiment.
  • the concentration impurity layer 33 was read as the low concentration impurity layer 33A
  • the oxide film 34 was read as the oxide film 34A
  • the water-soluble protective layer 51 was read as the water-soluble protective layer 51A
  • the semiconductor layer 40 was read as the semiconductor layer 40A. It is the same process as the one.
  • the thirtieth step is a step of removing the water-soluble protective layer 51A from the surface of the wafer 100A using cleaning water.
  • This thirtieth step is lower than the ninth step in the first individualization method according to the first embodiment, in which the wafer 100 is replaced with the wafer 100A and the semiconductor substrate 32 is replaced with the semiconductor substrate 32A.
  • the concentration impurity layer 33 was read as the low concentration impurity layer 33A
  • the oxide film 34 was read as the oxide film 34A
  • the water-soluble protective layer 51 was read as the water-soluble protective layer 51A
  • the semiconductor layer 40 was read as the semiconductor layer 40A. It is the same process as the one.
  • the wafer 100A can be individualized without using a blade.
  • the formation of HAZ is suppressed in the semiconductor device individualized by the second individualization method. Therefore, according to the second individualization method, a semiconductor device in which the formation of HAZ is suppressed is provided.
  • the semiconductor device 1 according to the first embodiment is manufactured by individualizing the wafer 100 by the first individualizing method.
  • the wafer 100 is individualized by a third individualizing method in which a part of the steps is changed from the first individualizing method.
  • the semiconductor device according to the third embodiment, which is individualized by the third individualization method, and the semiconductor device 1 are a semiconductor substrate 32, a low-concentration impurity layer 33, an oxide film 34, and water-soluble. The shape is different from that of the sex protection layer 51.
  • the semiconductor substrate 32 is referred to as a semiconductor substrate 32B
  • the low-concentration impurity layer 33 is referred to as a low-concentration impurity layer 33B
  • the oxide film 34 is referred to as an oxide film 34B
  • the water-soluble protective layer 51 is water-soluble. It is referred to as a protective layer 51B.
  • the semiconductor layer 40 is referred to as a semiconductor layer 40B
  • the wafer 100 is referred to as a wafer 100B.
  • the third individualization method includes the 41st step to the 50th step in order. Of these steps, the 41st step to the 48th step turn the wafer 100 into a wafer 100B with respect to the first step to the eighth step of the first individualization method in the first embodiment, respectively.
  • the semiconductor substrate 32 is replaced with the semiconductor substrate 32B
  • the low-concentration impurity layer 33 is replaced with the low-concentration impurity layer 33B
  • the oxide film 34 is replaced with the oxide film 34B
  • the water-soluble protective layer 51 is replaced with the water-soluble protective layer. It is the same as the one in which the semiconductor layer 40 is replaced with the semiconductor layer 40B by replacing it with 51B. Therefore, here, it is abbreviated that the 41st step to the 48th step have already been described, and the 49th step to the 50th step will be described.
  • 9A, 9B, and 9C are schematic enlarged cross-sectional views of the vicinity of the cutting region of the wafer 100B in the 49th to 50th steps.
  • the 49th step is a cutting adjacent region (here, the first) within a predetermined range on both sides of the center line of the cutting region cut by the 8th step.
  • the cutting adjacent region and the second cutting adjacent region) are irradiated with a laser beam for trimming (hereinafter, also referred to as “second laser light”), and the cutting included in the cutting region is included in the plan view of the wafer 100B.
  • This is a step of irradiating the inner region with a laser beam for cleaning (hereinafter, also referred to as “third laser beam”).
  • the HAZ formed by irradiation with the laser beam (hereinafter, also referred to as “first laser beam”) in the 8th step is obtained in the 49th step. It can be removed by irradiation with a second laser beam.
  • the reason why the second laser beam is referred to as a trimming laser beam is for the purpose of removing only the portion where HAZ is likely to occur as the main function.
  • the metal-containing formation forming the metal layer 30 adheres as burrs to the inside of the cut region in the plan view of the wafer 100B. It may end up.
  • FIG. 9D is a schematic view of the vicinity of the cutting region of the wafer 100B in the case where it is assumed that only the second laser beam is irradiated and the third laser beam is not irradiated in the 49th step. It is an enlarged sectional view.
  • the formation containing the metal constituting the metal layer 30 is formed.
  • the burrs 60A and 60B may adhere to the inside of the cutting region of the wafer 100B in a plan view.
  • the burr can be removed by the irradiation of the third laser beam. ..
  • the first laser beam, the second laser beam, and the third laser beam may use one laser beam output device as a light source.
  • the third individualization method can be realized by one laser beam output device.
  • the first laser beam, the second laser beam, and the third laser beam will be described as using one laser beam output device as a light source.
  • the width of the region irradiated with the third laser beam is widened to the width of the cutting region, that is, the width of the cutting region is widened to the width of the cutting region. Therefore, the cutting region may be irradiated with a third laser beam. As a result, the entire cutting area can be cleaned.
  • FIG. 10 is a schematic enlarged plan view of the wafer 100B showing an example of irradiating the upper surface of the wafer 100B with the second laser beam and the third laser beam in the 49th step.
  • the cut adjacent region includes a first cut adjacent region on one side of the center line of the cut region and a second cut adjacent region on the other side.
  • the irradiation of the second laser beam to the cut adjacent region is the first of a plurality of (here, nine) obtained by branching a part of the laser beam output by one laser beam output device into a plurality of laser beams.
  • the first irradiation spots 301A, 301B, 301C, 301D, 301E, 301F, 301G, 301H, and 301I are irradiated to the first cutting adjacent region, and the laser light output device of 1.
  • Second irradiation spots 302 (here, second irradiation spots 302A, 302B, 302C, 302D) obtained by branching a part of the laser beam output by , 302E, 302F, 302G, 302H, and 302I) are applied to the second cutting adjacent region. Further, the irradiation of the third laser beam to the region inside the cutting is performed by branching a part of the laser beam output by one laser beam output device into a plurality of (eight in this case) third laser beam. (Here, the third irradiation spots 303A, 303B, 303C, 303D, 303E, 303F, 303G, and 303H) are irradiated to the inside region of the cut.
  • the number of the plurality of first irradiation spots 301 and the number of the plurality of second irradiation spots 302 are not necessarily limited to the nine illustrated in FIG. 10, respectively. Further, the number of the plurality of third irradiation spots 303 does not necessarily have to be limited to the eight illustrated in FIG.
  • the plurality of first irradiation spots 301, the plurality of second irradiation spots 302, and the plurality of third irradiation spots 303 are formed.
  • a plurality of first irradiation spots 301, a plurality of second irradiation spots 302, and a plurality of third irradiation spots so as to proceed relative to the wafer 100B along the cutting direction of the cutting region.
  • the 303 and the wafer 100B are advanced.
  • the plurality of first irradiation spots 301 and the plurality of second irradiation spots 302 are line-symmetrical with the center line of the cutting region as the target axis.
  • the plurality of first irradiation spots 301, the plurality of first irradiation spots 301, the plurality of second irradiation spots 302, and the plurality of third irradiation spots 303 are related to the wafer 100B.
  • the third irradiation spot 303 is located so as to monotonically increase the shortest distance from the center line from the front to the rear in the traveling direction relatively traveling along the cutting direction of the cutting region, and the third irradiation spot 303 is one or more. They are arranged in a straight line (here, a straight line of 1).
  • a straight line here, a straight line of 1
  • the phrase "positioned so that the shortest distance to the center line increases monotonically” means "positioned so that the shortest distance to the center line does not increase or change".
  • 11A to 11D are schematic enlarged plan views of the wafer 100B showing an example of irradiating the upper surface of the wafer 100B with a second laser beam.
  • the plurality of first irradiation spots 301 may be arranged in a straight line of 1
  • the plurality of second irradiation spots 302 may be arranged in a straight line of 1.
  • At least one of the plurality of first irradiation spots 301 is located in the cutting region, and at least one of the plurality of second irradiation spots 302 is in the cutting region. It may be located at.
  • the HAZ formed in the cutting region can be removed by irradiation with the second laser beam.
  • the plurality of first irradiation spots 301 are arranged on two or more sides, and the plurality of second irradiation spots 302 are on two or more sides. You may line up in.
  • At least one of the plurality of first irradiation spots 301 is located in front of the plurality of third irradiation spots 303 in the traveling direction, and the plurality of first irradiation spots 301 are located in front of the plurality of third irradiation spots 303.
  • At least one of the second irradiation spots 302 may be located in front of the plurality of third irradiation spots 303 in the traveling direction.
  • 12A, 12B, and 12C are schematic enlargements of the wafer 100B, showing another example of irradiating the upper surface of the wafer 100B with a second laser beam and a third laser beam in the 49th step. It is a plan view.
  • At least one of the plurality of third irradiation spots 303 is located in front of the plurality of first irradiation spots 301 in the traveling direction, and the plurality of third irradiation spots 303 are located in front of the plurality of first irradiation spots 301.
  • At least one of the third irradiation spots 303 may be located in front of the plurality of second irradiation spots 302 in the traveling direction.
  • the irradiation of the third laser beam, which precedes the second laser beam can raise the temperature of the planned processing region of the second laser beam in advance, so that the metal layer 30 can be efficiently vaporized. Therefore, the adhesion of the burr can be suppressed.
  • the plurality of third irradiation spots 303 may be arranged in a straight line of 2.
  • At least one of the plurality of third irradiation spots 303 is located behind the plurality of first irradiation spots 301 in the traveling direction, and the plurality of third irradiation spots 303 are located behind the plurality of first irradiation spots 301. At least one of the third irradiation spots 303 may be located behind the plurality of second irradiation spots 302 in the traveling direction.
  • the formation containing the metal constituting the metal layer 30 newly generated by the irradiation of the second laser beam can be more effectively removed by the third laser beam. Therefore, the adhesion of the burr can be suppressed.
  • the 50th step is a step of removing the water-soluble protective layer 51B from the surface of the wafer 100B using cleaning water.
  • This thirtieth step is lower than the ninth step in the first individualization method according to the first embodiment, in which the wafer 100 is read as the wafer 100B and the semiconductor substrate 32 is read as the semiconductor substrate 32B.
  • the concentration impurity layer 33 was read as the low concentration impurity layer 33B
  • the oxide film 34 was read as the oxide film 34B
  • the water-soluble protective layer 51 was read as the water-soluble protective layer 51B
  • the semiconductor layer 40 was read as the semiconductor layer 40B. It is the same process as the one.
  • the wafer 100B can be individualized without using a blade.
  • the formation of HAZ is suppressed in the semiconductor device individualized by the third individualization method. Therefore, according to the third individualization method, a semiconductor device in which the formation of HAZ is suppressed is provided.
  • the present disclosure can be widely used for semiconductor devices and the like in which a metal layer is formed on the lower surface.

Landscapes

  • Dicing (AREA)
  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Optics & Photonics (AREA)
  • Laser Beam Processing (AREA)
PCT/JP2021/005957 2020-02-21 2021-02-17 個片化方法 Ceased WO2021166963A1 (ja)

Priority Applications (6)

Application Number Priority Date Filing Date Title
JP2022501939A JP7062147B2 (ja) 2020-02-21 2021-02-17 個片化方法
CN202210985262.2A CN115332064B (zh) 2020-02-21 2021-02-17 单片化方法
CN202180005345.4A CN114424323B (zh) 2020-02-21 2021-02-17 单片化方法
JP2022032197A JP2022067118A (ja) 2020-02-21 2022-03-02 個片化方法
US17/722,993 US11488867B2 (en) 2020-02-21 2022-04-18 Chip singulation method
US17/951,021 US11646230B2 (en) 2020-02-21 2022-09-22 Chip singulation method

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US202062980033P 2020-02-21 2020-02-21
US62/980,033 2020-02-21

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US17/722,993 Continuation US11488867B2 (en) 2020-02-21 2022-04-18 Chip singulation method

Publications (1)

Publication Number Publication Date
WO2021166963A1 true WO2021166963A1 (ja) 2021-08-26

Family

ID=77391277

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2021/005957 Ceased WO2021166963A1 (ja) 2020-02-21 2021-02-17 個片化方法

Country Status (4)

Country Link
US (2) US11488867B2 (https=)
JP (2) JP7062147B2 (https=)
CN (2) CN115332064B (https=)
WO (1) WO2021166963A1 (https=)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111816602A (zh) * 2020-07-21 2020-10-23 上海韦尔半导体股份有限公司 一种芯片制备方法及芯片
JP7729003B1 (ja) * 2023-12-26 2025-08-25 ヌヴォトンテクノロジージャパン株式会社 半導体装置および半導体モジュール

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009188303A (ja) * 2008-02-08 2009-08-20 Lintec Corp レーザーダイシングシートおよびチップ体の製造方法
JP2010267638A (ja) * 2009-05-12 2010-11-25 Disco Abrasive Syst Ltd 保護膜の被覆方法及びウエーハのレーザ加工方法
JP2013524521A (ja) * 2010-04-02 2013-06-17 エレクトロ サイエンティフィック インダストリーズ インコーポレーテッド 脆性材料のレーザシンギュレーションのための改良された方法及び装置
JP2016139739A (ja) * 2015-01-28 2016-08-04 株式会社東芝 デバイスの製造方法
CN107214419A (zh) * 2017-07-14 2017-09-29 中国科学院微电子研究所 一种激光加工晶圆的方法及装置

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6420245B1 (en) * 1999-06-08 2002-07-16 Kulicke & Soffa Investments, Inc. Method for singulating semiconductor wafers
US6908784B1 (en) * 2002-03-06 2005-06-21 Micron Technology, Inc. Method for fabricating encapsulated semiconductor components
US7008861B2 (en) * 2003-12-11 2006-03-07 Cree, Inc. Semiconductor substrate assemblies and methods for preparing and dicing the same
US7129114B2 (en) * 2004-03-10 2006-10-31 Micron Technology, Inc. Methods relating to singulating semiconductor wafers and wafer scale assemblies
US7550367B2 (en) * 2004-08-17 2009-06-23 Denso Corporation Method for separating semiconductor substrate
US7435664B2 (en) * 2006-06-30 2008-10-14 Intel Corporation Wafer-level bonding for mechanically reinforced ultra-thin die
US8211781B2 (en) 2008-11-10 2012-07-03 Stanley Electric Co., Ltd. Semiconductor manufacturing method
JP5237764B2 (ja) * 2008-11-10 2013-07-17 スタンレー電気株式会社 半導体素子の製造方法
US8252682B2 (en) * 2010-02-12 2012-08-28 Taiwan Semiconductor Manufacturing Company, Ltd. Method for thinning a wafer
US8673741B2 (en) 2011-06-24 2014-03-18 Electro Scientific Industries, Inc Etching a laser-cut semiconductor before dicing a die attach film (DAF) or other material layer
US8642385B2 (en) * 2011-08-09 2014-02-04 Alpha & Omega Semiconductor, Inc. Wafer level package structure and the fabrication method thereof
US8643148B2 (en) * 2011-11-30 2014-02-04 Taiwan Semiconductor Manufacturing Company, Ltd. Chip-on-Wafer structures and methods for forming the same
US9559005B2 (en) * 2014-01-24 2017-01-31 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of packaging and dicing semiconductor devices and structures thereof
PT2974822T (pt) 2014-07-14 2017-11-14 Asm Tech Singapore Pte Ltd Método de divisão de substratos semicondutores finos
JP2017069243A (ja) * 2015-09-28 2017-04-06 日本特殊陶業株式会社 積層体のレーザ除去加工方法
JP6981800B2 (ja) * 2017-07-28 2021-12-17 浜松ホトニクス株式会社 積層型素子の製造方法
DE102017122650B4 (de) * 2017-09-28 2023-02-09 Infineon Technologies Ag Halbleiterchip einschliesslich einer selbstausgerichteten rückseitigen leitfähigen schicht und verfahren zum herstellen desselben
JP7109862B2 (ja) * 2018-07-10 2022-08-01 株式会社ディスコ 半導体ウェーハの加工方法
CN109065444A (zh) * 2018-08-06 2018-12-21 甬矽电子(宁波)股份有限公司 晶圆切割方法
TWI761740B (zh) 2018-12-19 2022-04-21 日商新唐科技日本股份有限公司 半導體裝置
KR102751333B1 (ko) * 2020-06-01 2025-01-07 삼성전자주식회사 반도체 패키지

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009188303A (ja) * 2008-02-08 2009-08-20 Lintec Corp レーザーダイシングシートおよびチップ体の製造方法
JP2010267638A (ja) * 2009-05-12 2010-11-25 Disco Abrasive Syst Ltd 保護膜の被覆方法及びウエーハのレーザ加工方法
JP2013524521A (ja) * 2010-04-02 2013-06-17 エレクトロ サイエンティフィック インダストリーズ インコーポレーテッド 脆性材料のレーザシンギュレーションのための改良された方法及び装置
JP2016139739A (ja) * 2015-01-28 2016-08-04 株式会社東芝 デバイスの製造方法
CN107214419A (zh) * 2017-07-14 2017-09-29 中国科学院微电子研究所 一种激光加工晶圆的方法及装置

Also Published As

Publication number Publication date
US11646230B2 (en) 2023-05-09
JP2022067118A (ja) 2022-05-02
CN114424323A (zh) 2022-04-29
US11488867B2 (en) 2022-11-01
US20220238378A1 (en) 2022-07-28
CN115332064A (zh) 2022-11-11
JP7062147B2 (ja) 2022-05-02
JPWO2021166963A1 (https=) 2021-08-26
CN115332064B (zh) 2025-01-21
US20230015582A1 (en) 2023-01-19
CN114424323B (zh) 2022-08-09

Similar Documents

Publication Publication Date Title
JP6982210B2 (ja) 個片化方法
US8633086B2 (en) Power devices having reduced on-resistance and methods of their manufacture
US7485547B2 (en) Method of fabricating semiconductor device
JP7407561B2 (ja) ウェーハの加工方法
JP2006253402A (ja) 半導体装置の製造方法
JP2005116844A (ja) 半導体装置の製造方法
CN102420195A (zh) 设有背面保护膜的半导体装置及其制造方法
JP7062147B2 (ja) 個片化方法
US12482785B2 (en) Trim free wafer bonding methods and devices
US7863104B2 (en) Method of producing a thin semiconductor chip
US7655539B2 (en) Dice by grind for back surface metallized dies
CN112397448B (zh) 封装的制造方法
CN111490011B (zh) 对准半导体晶圆以进行分割的方法
TW200941568A (en) Method for wafer cutting
JP2004179565A (ja) 電子部品の製造方法及びダイシング方法、並びにこれらを実施するための製造装置

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 21756948

Country of ref document: EP

Kind code of ref document: A1

ENP Entry into the national phase

Ref document number: 2022501939

Country of ref document: JP

Kind code of ref document: A

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 21756948

Country of ref document: EP

Kind code of ref document: A1