WO2021166748A1 - Élément de batterie solaire - Google Patents

Élément de batterie solaire Download PDF

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Publication number
WO2021166748A1
WO2021166748A1 PCT/JP2021/004824 JP2021004824W WO2021166748A1 WO 2021166748 A1 WO2021166748 A1 WO 2021166748A1 JP 2021004824 W JP2021004824 W JP 2021004824W WO 2021166748 A1 WO2021166748 A1 WO 2021166748A1
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semiconductor layer
layer
semiconductor
type
solar cell
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PCT/JP2021/004824
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English (en)
Japanese (ja)
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大介 藤嶋
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パナソニック株式会社
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
    • H01L31/0352—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
    • H01L31/072—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type
    • H01L31/0745—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells
    • H01L31/0747—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells comprising a heterojunction of crystalline and amorphous materials, e.g. heterojunction with intrinsic thin layer
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy

Definitions

  • the present disclosure relates to a solar cell, and more particularly to a so-called back surface bonding type solar cell in which a first semiconductor layer and a second semiconductor layer are provided on the back surface side of a semiconductor wafer.
  • a conventional solar cell including a back-junction type solar cell is used in the form of a solar cell module having a string of a plurality of solar cells connected in series.
  • a solar cell module having a string of a plurality of solar cells connected in series.
  • only a part of a plurality of solar cell cells may enter the shadow of an obstacle to block light, and the amount of light received may decrease.
  • the voltage generated by the power generation of other cells is applied to this cell as a reverse bias state, and the shaded solar cells generate heat, so-called hot spots. The phenomenon may occur.
  • the solar cell module is provided with a bypass diode for passing a current by bypassing the problematic solar cell in order to deal with the hot spot phenomenon.
  • Bypass diodes are generally provided for each substring, which is a unit of a predetermined number of solar cells connected in series.
  • the solar cell module is provided with a bypass diode, but depending on the degree of shadow on the solar cell, current does not flow through the diode, and a bypass path is formed that bypasses the shaded solar cell. It may not be done. In this case, a hot spot phenomenon in which the shaded solar cell generates heat may occur, and the cell may be damaged or other components of the solar cell module may be damaged.
  • An object of the present disclosure is to provide a back-junction type solar cell capable of suppressing the occurrence of a hot spot phenomenon.
  • the solar cell according to the present disclosure receives light received along a first direction and a second direction intersecting the first direction, and arranged in a third direction orthogonal to the first direction and the second direction.
  • a semiconductor wafer having a front surface and a back surface, and a first semiconductor layer provided along the first direction so as to cover the back surface of the semiconductor wafer and including a first conductive amorphous semiconductor or a polycrystalline semiconductor.
  • a second conductive type amorphous semiconductor or polycrystalline semiconductor that is provided along the first direction so as to cover the back surface of the semiconductor wafer and the side surface of the first semiconductor layer, and is different from the first conductive type.
  • a second semiconductor layer including the above, a first electrode layer provided on the first semiconductor layer, and a second electrode layer provided on the second semiconductor layer are provided, and the first semiconductor layer and the first semiconductor layer are provided.
  • a plurality of the two semiconductor layers are provided so as to be alternately arranged along the second direction, and in the adjacent first semiconductor layer and the second semiconductor layer, the second semiconductor layer of the first semiconductor layer is provided.
  • the distance from the back surface of the semiconductor wafer along the third direction to S2 is 15 nm or more, and the distance from the back surface of the semiconductor wafer to the interface S1 along the third direction is the interface from the back surface of the semiconductor wafer. It is longer than the distance along the third direction to S2.
  • the occurrence of the hot spot phenomenon can be suppressed. That is, in the solar cell module configured by using a plurality of solar cells according to the present disclosure, when only a part of the plurality of solar cells is shielded from light, the heat generation of the part of the cells can be suppressed. ..
  • FIG. 1 It is a rear view of the solar cell which is an example of an embodiment. It is a figure which shows a part of the cross section of AA line in FIG. It is an enlarged view of part B in FIG. It is sectional drawing of the main part of the solar cell which is another example of an embodiment. It is a figure for demonstrating the manufacturing method of the solar cell which is an example of Embodiment. It is a figure for demonstrating the manufacturing method of the solar cell which is an example of Embodiment. It is a figure for demonstrating the manufacturing method of the solar cell which is an example of Embodiment. It is sectional drawing of the solar cell which is a comparative example.
  • FIG. 1 is a rear view of the solar cell 10 which is an example of the embodiment
  • FIG. 2 is a view showing a part of the AA line cross section in FIG.
  • the solar cell 10 includes a semiconductor wafer 11 having a light receiving surface 11A and a back surface 11B.
  • the solar cell 10 has an n-type semiconductor layer 20 provided along the first direction ⁇ so as to cover the back surface 11B of the semiconductor wafer 11, and side surfaces of the back surface 11B and the n-type semiconductor layer 20 of the semiconductor wafer 11.
  • a p-type semiconductor layer 30 provided along the first direction ⁇ so as to cover S3 is provided.
  • the n-side electrode layer 23 is provided on the n-type semiconductor layer 20, and the p-side electrode layer 33 is provided on the p-type semiconductor layer 30.
  • the solar cell 10 is a back surface bonding type cell in which electrodes are provided only on the back surface 11B side of the semiconductor wafer 11.
  • a plurality of n-type semiconductor layers 20 and p-type semiconductor layers 30 are provided on the back surface 11B of the semiconductor wafer 11 so as to be alternately arranged in the second direction ⁇ . That is, on the back surface 11B of the semiconductor wafer 11, strip-shaped n-type semiconductor layers 20 and p-type semiconductor layers 30 extending in the first direction ⁇ are formed in stripes.
  • first direction ⁇ and the second direction ⁇ mean the directions along the light receiving surface 11A and the back surface 11B of the semiconductor wafer 11.
  • the direction in which the n-type semiconductor layer 20 and the p-type semiconductor layer 30 extend intersects the first direction ⁇ and the first direction ⁇ , and the direction in which the n-type semiconductor layer 20 and the p-type semiconductor layer 30 are alternately arranged is the second direction.
  • the first direction ⁇ and the second direction ⁇ are substantially orthogonal to each other.
  • the direction orthogonal to the first direction ⁇ and the second direction ⁇ and in which the light receiving surface 11A and the back surface 11B are lined up is defined as the third direction ⁇ .
  • the semiconductor wafer 11 is a substrate containing a semiconductor material such as silicon, gallium arsenide, or indium phosphide.
  • a suitable semiconductor wafer 11 is a crystalline silicon wafer, which may be a polycrystalline silicon wafer, but more preferably a single crystal silicon wafer.
  • the semiconductor wafer 11 may be a p-type single crystal silicon wafer, but in the present embodiment, it will be described as an n-type single crystal silicon wafer containing an n-type dopant.
  • the n-type dopant means an impurity such as phosphorus that functions as a donor.
  • the p-type dopant means an impurity such as boron that functions as an acceptor.
  • the semiconductor wafer 11 has, for example, a substantially square shape with four corners cut diagonally.
  • the thickness of the semiconductor wafer 11 is not particularly limited, and as an example, it is 100 ⁇ m or more and 500 ⁇ m or less.
  • the light receiving surface 11A of the semiconductor wafer 11 is formed with a texture structure (not shown) that suppresses surface reflection and increases the amount of light absorbed.
  • the texture structure can be formed by anisotropically etching the (100) plane of a single crystal silicon wafer with an alkaline solution. In this case, a pyramid-shaped surface uneven structure with the (111) plane as a slope is formed on the surface of the semiconductor wafer 11.
  • the texture structure may be formed on both sides of the light receiving surface 11A and the back surface 11B.
  • the i-type amorphous semiconductor layer 12 and the protective layer 13 are provided on the light receiving surface 11A of the semiconductor wafer 11 in this order.
  • the i-type amorphous semiconductor layer 12 is, for example, an amorphous silicon layer having a lower impurity concentration than the n-type semiconductor layer 20 or substantially containing no impurities, and functions as a passivation layer.
  • An example of the thickness of the i-type amorphous semiconductor layer 12 in the third direction ⁇ is 1 nm or more and 20 nm or less.
  • the "thickness" of the layer means the thickness in the third direction ⁇ .
  • the protective layer 13 is preferably made of a material having high light transmission. Specific examples include metal compound layers such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, and aluminum nitride, and among them, a layer of silicon nitride (hereinafter referred to as “SiN”) is preferable.
  • An example of the thickness of the protective layer 13 is 30 nm or more and 300 nm or less.
  • the i-type amorphous semiconductor layer 12 and the protective layer 13 are provided in the entire area except the peripheral portion of the light receiving surface 11A, for example.
  • N-side electrode layer 23 and p-side electrode layer 33 As described above, the back surface 11B of the semiconductor wafer 11 is provided with the n-side electrode layer 23 via the n-type semiconductor layer 20 and the p-side electrode layer 33 via the p-type semiconductor layer 30.
  • the n-side electrode layer 23 is a collector electrode that collects carriers from the n-type region (n-type semiconductor layer 20)
  • the p-side electrode layer 33 is a collector electrode that collects carriers from the p-type region (p-type semiconductor layer 30).
  • the n-side electrode layer 23 includes a plurality of fingers 23A and a bus bar 23B to which the plurality of fingers 23A are connected.
  • the p-side electrode layer 33 includes a plurality of fingers 33A and a bus bar 33B to which the plurality of fingers 33A are connected.
  • the plurality of fingers 23A and 33A extend substantially parallel to each other along the first direction ⁇ , and are arranged in a back-view comb-teeth shape so as to mesh with each other across the groove 15.
  • the n-side electrode layer 23 has a laminated structure of a transparent conductive layer 24 provided in contact with the n-type semiconductor layer 20 and a metal electrode layer provided in contact with the transparent conductive layer 24. ..
  • the metal electrode layer of the present embodiment has a structure in which the seed layer 25, the first plating layer 26, and the second plating layer 27 are laminated in this order from the transparent conductive layer 24 side.
  • the p-side electrode layer 33 has a laminated structure of a transparent conductive layer 34 provided in contact with the p-type semiconductor layer 30 and a metal electrode layer provided in contact with the transparent conductive layer 34, and the metal.
  • the electrode layer includes a seed layer 35, a first plating layer 36, and a second plating layer 37.
  • the transparent conductive layers 24 and 34 are generally layers of transparent conductive oxides (IWO, ITO, etc.) obtained by doping metal oxides such as indium oxide and zinc oxide with tungsten, tin, antimony, and the like.
  • the transparent conductive layers 24 and 34 are formed by, for example, sputtering.
  • An example of the thickness of the transparent conductive layers 24 and 34 is 30 nm or more and 300 nm or less.
  • the first plating layers 26 and 36 are provided by, for example, an electrolytic plating method after forming seed layers 25 and 35 on the transparent conductive layers 24 and 34.
  • An example of the thickness of the first plating layers 26 and 36 is 5 ⁇ m or more and 100 ⁇ m or less, and the thickness of the first plating layer 26 may be larger than the thickness of the first plating layer 36.
  • the constituent materials of the seed layers 25 and 35 and the first plating layers 26 and 36 are not particularly limited, but are preferably copper. In the case of the first plating layers 26 and 36 containing copper as a main component, it is preferable to provide the second plating layers 27 and 37 containing tin as a main component on the outermost surface in order to improve the corrosion resistance.
  • the solar cell 10 is used in the form of a solar cell module including a string of the solar cell 10 connected in series.
  • the string of the solar cell 10 is electrically formed by using a band-shaped wiring material in which the n-side electrode layer 23 of one solar cell 10 and the p-side electrode layer 33 of the other solar cell 10 are arranged adjacent to each other. It has a structure in which a plurality of solar cells 10 are connected in series.
  • the string of the solar cell 10 includes a plurality of clusters called substrings, and the solar cell module is provided with a bypass diode for each substring.
  • FIG. 3 is an enlarged view of part B in FIG.
  • the n-type semiconductor layer 20 is provided in the first region of the back surface 11B of the semiconductor wafer 11, and the p-type semiconductor layer 30 is provided in the second region of the back surface 11B of the semiconductor wafer 11.
  • the n-type semiconductor layer 20 and the p-type semiconductor layer 30 may be, for example, a polycrystalline semiconductor layer or may have a structure in which single crystal semiconductors are dispersed in a matrix of amorphous semiconductors, but are preferable. Is an amorphous semiconductor layer.
  • the area of each semiconductor layer in contact with the back surface 11B of the semiconductor wafer 11 may be the same, but in the present embodiment, the area of the p-type semiconductor layer 30 is slightly larger.
  • the n-type semiconductor layer 20 and the p-type semiconductor layer 30 are provided in the entire area excluding the peripheral edge portion of the back surface 11B of the semiconductor wafer 11, for example. Therefore, a part of the n-type semiconductor layer 20 and a part of the p-type semiconductor layer 30 overlap each other to form a film without a gap.
  • a part of the p-type semiconductor layer 30 is laminated on the n-type semiconductor layer 20 via the insulating layer 14, and both ends of the second direction ⁇ on the n-type semiconductor layer 20 are the insulating layer 14. It is covered with the p-type semiconductor layer 30. Further, the side surface S3 of the n-type semiconductor layer 20 is covered with a thinly formed p-type semiconductor layer 30.
  • the insulating layer 14 is a metal compound layer such as silicon oxide, silicon nitride, silicon nitride, aluminum oxide, and aluminum nitride, and is preferably a SiN layer.
  • An example of the thickness of the insulating layer 14 is 30 nm or more and 100 nm or less.
  • the thickness of the insulating layer 14 is, for example, larger than the thickness of the n-type semiconductor layer 20 and smaller than the thickness of the transparent conductive layer 24 constituting the n-side electrode layer 23.
  • the n-type semiconductor layer 20 includes an n-type amorphous semiconductor layer 21 containing an n-type dopant provided in contact with the transparent conductive layer 24 and an i-type amorphous semiconductor layer provided in contact with the semiconductor wafer 11. It has a laminated structure with 22. In other words, the n-type amorphous semiconductor layer 21 is provided on the back surface 11B of the semiconductor wafer 11 via the i-type amorphous semiconductor layer 22.
  • the n-type amorphous semiconductor layer 21 and the i-type amorphous semiconductor layer 22 are preferably amorphous silicon layers.
  • the n-type amorphous semiconductor layer 21 is an n-type high-concentration semiconductor layer containing an n-type dopant having a higher concentration than that of the i-type amorphous semiconductor layer 22.
  • the i-type amorphous semiconductor layer 22 is a low-concentration semiconductor layer having a lower n-type dopant concentration than the n-type amorphous semiconductor layer 21 or substantially containing no n-type dopant.
  • the concentration of the n-type dopant in the n-type amorphous semiconductor layer 21 is, for example, 1 ⁇ 10 19 atoms / cm 3 or more and 1 ⁇ 10 23 atoms / cm 3 or less.
  • the thickness of the n-type amorphous semiconductor layer 21 at the center of the second direction ⁇ is preferably 20 nm or more and 50 nm or less, and more preferably 25 nm or more and 40 nm or less.
  • the thickness of the n-type amorphous semiconductor layer 21 at both ends of the second direction ⁇ is preferably the same as that of the central portion.
  • the thickness of the i-type amorphous semiconductor layer 22 is smaller than the thickness of the n-type amorphous semiconductor layer 21, and for example, it is 1 nm or more and 10 nm or less, or 2 nm or more and 5 nm or less.
  • the p-type semiconductor layer 30 includes a p-type amorphous semiconductor layer 31 containing a p-type dopant provided in contact with the transparent conductive layer 34 and an i-type amorphous semiconductor layer provided in contact with the semiconductor wafer 11. It has a laminated structure with 32. In other words, the p-type amorphous semiconductor layer 31 is provided on the back surface 11B of the semiconductor wafer 11 via the i-type amorphous semiconductor layer 32.
  • the p-type amorphous semiconductor layer 31 and the i-type amorphous semiconductor layer 32 are preferably amorphous silicon layers.
  • the p-type amorphous semiconductor layer 31 is a p-type high-concentration semiconductor layer containing a high-concentration p-type dopant as compared with the i-type amorphous semiconductor layer 32.
  • the i-type amorphous semiconductor layer 32 is a low-concentration semiconductor layer having a lower p-type dopant concentration than the p-type amorphous semiconductor layer 31 or substantially containing no p-type dopant.
  • the concentration of the p-type dopant in the p-type amorphous semiconductor layer 31 is, for example, 1 ⁇ 10 19 atoms / cm 3 or more and 1 ⁇ 10 23 atoms / cm 3 or less.
  • the thickness of the p-type amorphous semiconductor layer 31 at the center of the second direction ⁇ is preferably 5 nm or more and 20 nm or less, and more preferably 6 nm or more and 15 nm or less. When the thickness of the p-type amorphous semiconductor layer 31 is within the range, it becomes easy to suppress the occurrence of the hot spot phenomenon while maintaining the basic performance of the solar cell 10 such as photoelectric conversion characteristics.
  • the thickness of the p-type amorphous semiconductor layer 31 at both ends of the second direction ⁇ is preferably the same as that of the central portion.
  • the thickness of the i-type amorphous semiconductor layer 32 is smaller than the thickness of the p-type amorphous semiconductor layer 31, and as an example, it is 1 nm or more and 10 nm or less.
  • the thickness of the i-type amorphous semiconductor layer 32 is larger than the thickness of the i-type amorphous semiconductor layer 22, for example.
  • the n-type semiconductor layer 20 and the p-type semiconductor layer 30 are provided in a striped manner alternately arranged in the second direction ⁇ .
  • the length of the n-type semiconductor layer 20 in the second direction ⁇ at the interface with the semiconductor wafer 11 (hereinafter referred to as “width”).
  • the sum of the width of the p-type semiconductor layer 30 and the width of the p-type semiconductor layer 30 is preferably 0.1 mm or more and 1 mm or less.
  • the leak path can be increased by reducing the total width of the n-type semiconductor layer 20 and the p-type semiconductor layer 30 to 1 mm or less to achieve a fine pitch.
  • the width of the n-type semiconductor layer 20 and the width of the p-type semiconductor layer 30 may be substantially the same, and as illustrated in FIG. 3, the width of the p-type semiconductor layer 30 is larger than the width of the n-type semiconductor layer 20. It may be large.
  • the interface S1 between the n-type semiconductor layer 20 and the n-side electrode layer 23 at the center of the second direction ⁇ of the n-type semiconductor layer 20 in the adjacent n-type semiconductor layer 20 and p-type semiconductor layer 30, the interface S1 between the n-type semiconductor layer 20 and the n-side electrode layer 23 at the center of the second direction ⁇ of the n-type semiconductor layer 20.
  • the distance D along the third direction ⁇ between the p-type semiconductor layer 30 and the interface S2 of the p-side electrode layer 33 at the center of the second direction ⁇ of the p-type semiconductor layer 30 is 15 nm or more.
  • the distance from the back surface 11B of the semiconductor wafer 11 to the interface S1 along the third direction ⁇ is longer than the distance along the third direction ⁇ from the back surface 11B of the semiconductor wafer 11 to the interface S2.
  • the interface S2 between the p-type semiconductor layer 30 and the p-side electrode layer 33 is located at least 15 nm from the interface S1 between the n-type semiconductor layer 20 and the n-side electrode layer 23 and near the back surface 11B of the semiconductor wafer 11.
  • the interface S1 is formed by the contact between the n-type amorphous semiconductor layer 21 and the transparent conductive layer 24.
  • the interface S2 is formed by the contact between the p-type amorphous semiconductor layer 31 and the transparent conductive layer 34.
  • the upper limit of the distance D between the interface S1 and the interface S2 is not particularly limited, but the effect of suppressing the hotspot phenomenon does not change much even if the distance D is lengthened to a predetermined value or more.
  • the distance D is preferably 100 nm or less, more preferably 50 nm or less, and more preferably 35 nm in order to suppress the hot spot phenomenon more effectively.
  • the following are particularly preferred.
  • the lower limit of the distance D is 15 nm, preferably 16 nm or 18 nm.
  • An example of a suitable range of the distance D is 15 nm or more and 35 nm or less, 16 nm or more and 30 nm or less, or 18 nm or more and 30 nm or less.
  • the thickness of the n-type semiconductor layer 20 is preferably larger than the thickness of the p-type semiconductor layer 30. Further, the thickness of the n-type amorphous semiconductor layer 21 is preferably larger than the thickness of the p-type amorphous semiconductor layer 31. In this case, it becomes easy to increase the distance D between the interface S1 and the interface S2. In the example shown in FIG. 3, the thickness of the i-type amorphous semiconductor layer 22 is smaller than the thickness of the i-type amorphous semiconductor layer 32.
  • the n-type semiconductor layer 20 and the p-side electrode layer 33 are second via the p-type amorphous semiconductor layer 31. Facing the direction ⁇ of.
  • the length of the facing portion along the third direction ⁇ is at least 15 nm. That is, in the second direction ⁇ , the side surface S3 of the n-type semiconductor layer 20 and the side surface S4 of the p-side electrode layer 33 face each other over a length of 15 nm or more across the p-type semiconductor layer 30. ..
  • An example of a preferable range of the length of the facing portion is 15 nm or more and 35 nm or less, 16 nm or more and 30 nm or less, or 18 nm or more and 30 nm or less.
  • the side surfaces S3 and S4 are surfaces substantially along the third direction ⁇ , they may not be formed perpendicular to the back surface 11B and may be inclined at a predetermined angle.
  • the p-type semiconductor layer 30 is provided so as to cover the side surface S3 of the n-type semiconductor layer 20, and is interposed between the side surface S3 of the n-type semiconductor layer 20 and the side surface S4 of the p-side electrode layer 33. It has a side covering portion 38.
  • the n-type amorphous semiconductor layer 21 and the transparent conductive layer 34 of the p-side electrode layer 33 are arranged in the second direction ⁇ via the side surface covering portion 38.
  • the side covering portion 38 for example, when the p-type semiconductor layer 30 is formed on the second region of the back surface 11B of the semiconductor wafer 11, the raw material gas also adheres to the side surface S3 of the n-type amorphous semiconductor layer 21. Is formed by.
  • the side surface covering portion 38 plays a role of preventing electrical contact between the n-type semiconductor layer 20 and the p-side electrode layer 33.
  • the side surface covering portion 38 is preferably formed thin in a range in which a current does not flow due to the tunnel effect.
  • the thickness of the side surface covering portion 38 is, for example, less than 10% of the thickness of the p-type semiconductor layer 30 in the third direction ⁇ .
  • the side surface covering portion 38 has a laminated structure of a p-type amorphous semiconductor layer 31 and an i-type amorphous semiconductor layer 32, similarly to the portion in contact with the back surface 11B of the semiconductor wafer 11.
  • the thickness of the p-type amorphous semiconductor layer 31 is larger than the thickness of the i-type amorphous semiconductor layer 32.
  • the side surface covering portion 38 also covers the side surface of the insulating layer 14 beyond the range of the side surface S3 of the n-type amorphous semiconductor layer 21.
  • the solar cell 10 having the above configuration, a current leak path is formed from the p-side electrode 33 to the n-type semiconductor layer 20 along the second direction ⁇ , and the breakdown voltage is greatly reduced. Therefore, in a solar cell module using a plurality of solar cell 10, when some of the solar cells 10 are in a reverse bias state due to the influence of shading or the like, heat generation of the cells can be suppressed. As a result of the studies by the present inventors, it was found that the occurrence of the hot spot phenomenon is specifically suppressed by setting the distance D to 15 nm or more. Further, according to the solar cell 10, it is possible to improve the power generation efficiency of the solar cell module.
  • Table 1 shows the dark state when the thickness (A) of the n-type amorphous semiconductor layer 21 and the thickness (B) of the p-type amorphous semiconductor layer 31 are changed to change the distance D shown in FIG.
  • the IV characteristic (average voltage at -2A) of the solar cell 10 is shown.
  • the average voltage at -2A indicates the average value of the voltage when a reverse bias voltage is applied to the solar cell 10 and a current of 2A flows in the opposite direction. When the voltage required to pass the current in the opposite direction is low, the occurrence of the hot spot phenomenon is suppressed.
  • the thickness of the i-type amorphous semiconductor layer 22 was 5 nm, and the thickness of the i-type amorphous semiconductor layer 32 was 5 nm.
  • Table 1 the average voltage at -2A changes significantly when the distance D is 15 nm or more, and specifically, the distance D changes significantly between 12 nm and 18 nm.
  • FIG. 8 shows the cross-sectional structure of the conventional solar cell 100 for comparison.
  • the thickness of the n-type semiconductor layer 120 is the p-type semiconductor layer 130 (p-type amorphous semiconductor layer 131 and i). It is larger than the thickness of the type amorphous semiconductor layer 132).
  • the distance between the interface 105 between the n-type semiconductor layer 120 and the n-side electrode layer 123 and the interface 106 between the p-type semiconductor layer 130 and the p-side electrode layer 133 is short along the third direction ⁇ , and the interface 105 is the interface. It is located on the back surface 11B side of the semiconductor wafer 11 with respect to 106.
  • the insulating layer 14 exists in the second direction ⁇ of the p-side electrode 133, and a leak path along the second direction ⁇ like the solar cell 10 is not formed. Therefore, it is considered that the solar cell 100 has a higher yield voltage than the solar cell 10 and generates a larger amount of heat when it is in a reverse bias state due to the influence of shading or the like.
  • FIG. 4 is a diagram showing a modified example of the above embodiment.
  • unevenness is formed on the back surface 11BX of the semiconductor wafer 11X, and the n-type semiconductor layer 20X (n-type amorphous semiconductor layer 21X and i-type amorphous semiconductor layer 22X) of the semiconductor wafer 11X is provided.
  • the thickness of the region to be formed is larger than the thickness of the region provided with the p-type semiconductor layer 30X (p-type amorphous semiconductor layer 31X and i-type amorphous semiconductor layer 32X) of the semiconductor wafer 11X. It is different from the form illustrated in.
  • the p-type semiconductor layer 30X is provided in the recess of the back surface 11BX.
  • the recess of the back surface 11BX is formed, for example, by etching the back surface 11BX.
  • DX is at least 15 nm.
  • the interface S2X is located at least 15 nm from the interface S1X and near the back surface 11BX of the semiconductor wafer 11X. In the example shown in FIG.
  • the thickness of the p-type semiconductor layer 30X is larger than the depth of the recess of the back surface 11BX, and the interface S2X is larger than the interface between the n-type amorphous semiconductor layer 21X and the i-type amorphous semiconductor layer 22X. Located on the back side.
  • the thickness of the n-type semiconductor layer 20X is larger than the thickness of the p-type semiconductor layer 30X, and an example of a preferable range of the distance DX is 15 nm or more and 35 nm or less, 16 nm or more and 30 nm or less, or 18 nm or more and 30 nm or less.
  • the n-type semiconductor layer 20X and the p-side electrode layer 33X face each other in the second direction ⁇ via the p-type amorphous semiconductor layer 31X, and the facing portion thereof.
  • the length along the third direction ⁇ is 15 nm or more. Also in the embodiment illustrated in FIG. 4, the heat generation of the solar cell 10 in the reverse bias state due to the influence of shading or the like can be suppressed, and the occurrence of the hot spot phenomenon can be suppressed.
  • FIGS. 5 to 7 are cross-sectional views showing a layer structure in the manufacturing process of the solar cell 10.
  • the amorphous semiconductor layer will be described as an amorphous silicon layer
  • the protective layer 13 and the insulating layer 14 will be described as a SiN layer.
  • the i-type amorphous semiconductor layer 12 and the protective layer 13 are formed in this order on the light receiving surface 11A of the semiconductor wafer 11, and the n-type semiconductor layer 20 (i) is formed on the back surface 11B.
  • the type amorphous semiconductor layer 22 and the n-type amorphous semiconductor layer 21) and the insulating layer 14 are formed in this order.
  • the i-type amorphous semiconductor layer 12 and the protective layer 13 are provided in the entire area except the peripheral portion of the light receiving surface 11A.
  • the n-type semiconductor layer 20 and the insulating layer 14 are formed on the entire surface of the back surface 11B except for the peripheral portion, and then patterned by etching to be provided on a part (first region) of the back surface 11B.
  • Each of the above layers such as the n-type semiconductor layer 20 is formed by a plasma CVD method or a sputtering method in which a clean semiconductor wafer 11 is installed in a vacuum chamber.
  • a plasma CVD method or a sputtering method in which a clean semiconductor wafer 11 is installed in a vacuum chamber.
  • the semiconductor wafer 11 an n-type single crystal silicon wafer is used. It is preferable to form a texture structure on at least the surface of the n-type single crystal silicon wafer to be the light receiving surface 11A.
  • a raw material gas obtained by diluting silane gas with hydrogen is used for the film formation of the i-type amorphous semiconductor layers 12 and 22 by CVD.
  • a raw material gas obtained by adding phosphine to silane and diluting with hydrogen is used for the film formation of the i-type amorphous semiconductor layers 12 and 22 by CVD.
  • a raw material gas obtained by adding phosphine to silane and diluting with hydrogen is used.
  • the concentration of the n-type dopant can be changed by controlling the mixed concentration of phosphine.
  • a silane / ammonia or a mixed gas of silane / nitrogen is used for the film formation of the protective layer 13 and the insulating layer 14 by CVD.
  • the patterning of the n-type semiconductor layer 20 and the insulating layer 14 can be performed in a conventionally known direction, for example, by using a photolithography process. By this patterning, a second region which is a part of the back surface 11B of the semiconductor wafer 11 is exposed, and a p-type semiconductor layer 30 is formed in this region in a subsequent process.
  • the insulating layer 14 can be etched with, for example, hydrofluoric acid. After the etching of the insulating layer 14 is completed, the resist film is removed, and the exposed n-type semiconductor layer 20 is removed by etching with an alkaline solution such as an aqueous sodium hydroxide solution using the patterned insulating layer 14 as a mask.
  • a p-type semiconductor layer 30 (p-type amorphous semiconductor layer 31 and i-type amorphous semiconductor layer 32) is formed on the back surface 11B of the semiconductor wafer 11. Specifically, after the p-type semiconductor layer 30 is formed on the second region of the back surface 11B and the insulating layer 14, a part of the p-type semiconductor layer 30 is etched and removed for patterning. As a result, the p-type semiconductor layer 30 is provided so as to cover both ends of the second region of the back surface 11B and the second direction ⁇ of the n-type semiconductor layer 20.
  • the p-type semiconductor layer 30 can be deposited by CVD in the same manner as the n-type semiconductor layer 20.
  • diborane is used as a doping gas.
  • the p-type semiconductor layer 30 is formed thinner than the n-type semiconductor layer 20 so that the distance D is 15 nm or more. At this time, the p-type semiconductor layer 30 is formed on the second region of the back surface 11B of the semiconductor wafer 11 and also on the side surface S3 of the n-type semiconductor layer 20. As a result, the side surface covering portion 38 that covers the side surface S3 of the n-type semiconductor layer 20 is formed. Then, by providing the transparent conductive layer 34 in the subsequent process, in the second direction ⁇ , the side surface S3 of the n-type amorphous semiconductor layer 21 and the side surface S4 of the transparent conductive layer 34 form the p-type semiconductor layer 30. Opposing layer structures are formed through them.
  • the portion exposed by patterning of the p-type semiconductor layer 30 is removed by etching.
  • the portion of the n-type semiconductor layer 20 excluding both ends in the second direction ⁇ is exposed, and the n-type semiconductor layer 20 and the n-side electrode layer 23 can be in contact with each other.
  • the etching of the insulating layer 14 is performed using the patterned p-type semiconductor layer 30 as a mask.
  • a transparent conductive layer 40 is formed so as to cover the entire n-type semiconductor layer 20 and the p-type semiconductor layer 30.
  • the transparent conductive layer 40 is patterned in a later step and separated into the transparent conductive layers 24 and 34.
  • the transparent conductive layer 40 can be formed into a film by, for example, a sputtering method.
  • a metal electrode layer (not shown) is formed on the transparent conductive layer 40.
  • the metal electrode layer has, for example, a laminated structure including a seed layer, a first plating layer, and a second plating layer, and is formed by an electrolytic plating method.
  • the n-side electrode layer 23 and the p-side electrode layer 33 are formed by forming a metal electrode layer that covers the entire transparent conductive layer 40, and then etching and removing the portions of the transparent conductive layer 40 and the metal electrode layer that are the grooves 15. Will be done.
  • etching of the metal electrode layer for example, an aqueous ferric chloride solution is used.
  • the transparent conductive layer 40 is etched using the patterned metal electrode layer as a mask.
  • hydrochloric acid, oxalic acid, or a mixture thereof is used for etching of the transparent conductive layer 40.
  • the groove 15 is thinned as compared with the process of forming the transparent conductive layers 24 and 34 and the seed layers 25 and 35 and then forming the first plating layers 26 and 36, for example. Can be done. That is, it is not necessary to set a wide interval between the transparent conductive layers 24 and 34 in consideration of the growth of the plating layer in the second direction ⁇ , which is advantageous for fine pitching of the n-type region and the p-type region, which in turn is advantageous. It also contributes to suppressing the hot spot phenomenon.
  • the design of the above embodiment can be appropriately changed as long as the object of the present disclosure is not impaired.
  • an electrode including a plurality of fingers 23A and 33B and a bus bar 23B and 33B has been illustrated, but the electrode may not have a bus bar and may be composed of only a plurality of fingers.
  • the n-type semiconductor layer 20 and the p-type semiconductor layer 30 having a two-layer structure are exemplified, they can also have a single layer or a layer structure of three or more layers.

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  • Engineering & Computer Science (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Sustainable Energy (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Photovoltaic Devices (AREA)

Abstract

L'invention concerne un élément de batterie solaire (10) qui est un exemple d'un mode de réalisation, comprenant une tranche semi-conductrice (11), une première couche semi-conductrice (20) qui est disposée le long d'une première direction (α) de manière à recouvrir une surface arrière (11B) de la tranche semi-conductrice, une seconde couche semi-conductrice (30) qui est disposée le long de la première direction (α) de manière à recouvrir la surface arrière (11B) de la tranche semi-conductrice et une surface latérale de la première couche semi-conductrice (20), une première couche d'électrode (23) et une seconde couche d'électrode (33). Dans la première couche semi-conductrice adjacente (20) et une seconde couche semi-conductrice (30), une distance le long d'une troisième direction (γ) entre une interface (S1) entre la première couche semi-conductrice (20) et une première couche d'électrode (23) et une interface (S2) entre la seconde couche semi-conductrice (30) et une seconde couche d'électrode (33) est de 15 nm ou plus, et une distance le long de la troisième direction (γ) de la surface arrière (11B) de la tranche semi-conductrice à l'interface (S1) est supérieure à une distance le long de la troisième direction (γ) depuis la surface arrière (11B) de la tranche semi-conductrice jusqu'à l'interface (S2).
PCT/JP2021/004824 2020-02-17 2021-02-09 Élément de batterie solaire WO2021166748A1 (fr)

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JP2020024568A JP2021129085A (ja) 2020-02-17 2020-02-17 太陽電池セル

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JP2018050006A (ja) * 2016-09-23 2018-03-29 株式会社カネカ 太陽電池セル、及び太陽電池セルの製造方法
WO2018116644A1 (fr) * 2016-12-20 2018-06-28 パナソニックＩｐマネジメント株式会社 Cellule solaire
WO2019181834A1 (fr) * 2018-03-23 2019-09-26 株式会社カネカ Procédé permettant de produire une cellule solaire, et cellule solaire
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Publication number Priority date Publication date Assignee Title
WO2012132834A1 (fr) * 2011-03-28 2012-10-04 三洋電機株式会社 Cellule solaire et procédé de production de cellule solaire
JP2013026269A (ja) * 2011-07-15 2013-02-04 Sanyo Electric Co Ltd 太陽電池及び太陽電池の製造方法
JP2013197555A (ja) * 2012-03-23 2013-09-30 Sharp Corp 光電変換素子およびその製造方法
JP2015065219A (ja) * 2013-09-24 2015-04-09 三洋電機株式会社 太陽電池
JP2015153934A (ja) * 2014-02-17 2015-08-24 シャープ株式会社 光電変換装置
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WO2017168910A1 (fr) * 2016-03-28 2017-10-05 パナソニックＩｐマネジメント株式会社 Cellule solaire et son procédé de fabrication
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WO2018116644A1 (fr) * 2016-12-20 2018-06-28 パナソニックＩｐマネジメント株式会社 Cellule solaire
WO2019181834A1 (fr) * 2018-03-23 2019-09-26 株式会社カネカ Procédé permettant de produire une cellule solaire, et cellule solaire
JP2019169599A (ja) * 2018-03-23 2019-10-03 株式会社カネカ 太陽電池の製造方法、および、太陽電池

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