WO2021164076A1 - 一种 goa 电路和显示面板 - Google Patents

一种 goa 电路和显示面板 Download PDF

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Publication number
WO2021164076A1
WO2021164076A1 PCT/CN2020/079145 CN2020079145W WO2021164076A1 WO 2021164076 A1 WO2021164076 A1 WO 2021164076A1 CN 2020079145 W CN2020079145 W CN 2020079145W WO 2021164076 A1 WO2021164076 A1 WO 2021164076A1
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Prior art keywords
signal
thin film
film transistor
level
cascade
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PCT/CN2020/079145
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English (en)
French (fr)
Inventor
朱静
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TCL China Star Optoelectronics Technology Co Ltd
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TCL China Star Optoelectronics Technology Co Ltd
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Priority to US16/757,504 priority Critical patent/US11361725B2/en
Publication of WO2021164076A1 publication Critical patent/WO2021164076A1/zh
Anticipated expiration legal-status Critical
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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0439—Pixel structures
    • G09G2300/0443—Pixel structures with several sub-pixels for the same colour in a pixel, not specifically used to display gradations
    • G09G2300/0447—Pixel structures with several sub-pixels for the same colour in a pixel, not specifically used to display gradations for multi-domain technique to improve the viewing angle in a liquid crystal display, such as multi-vertical alignment [MVA]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery

Definitions

  • This application relates to the field of display technology, in particular to the field of vertical alignment type display technology, and in particular to a GOA circuit and a display panel.
  • each pixel in the display area of the liquid crystal display panel is usually divided into a main pixel and a sub-pixel.
  • the present application provides a GOA circuit, which uses the 2G1D mode in the 8-domain display to increase the number of flip-chip films and sector leads in the GOA circuit.
  • the present application provides a GOA circuit.
  • the GOA circuit is provided with a plurality of cascaded GOA sub-circuits, wherein the N-th stage GOA sub-circuit includes a cascade control unit, a cascade signal generation unit, and a first scan driver.
  • a cascade control unit for generating the first driving signal according to the N-3th level scan signal and the N-3th level cascade signal
  • the cascade signal generation unit is connected to the cascade control unit , Used to generate the Nth level cascaded signal according to the first drive signal and the Nth level clock signal
  • the first scan drive unit connected to the cascade control unit and the first low level signal, is used to generate the Nth level clock signal according to the Nth level clock signal
  • the N+3 level cascade signal and the first drive signal generate the Nth level main pixel scanning signal to drive the main pixels in the Nth level pixel points
  • the second scan driving unit which is connected with the cascade control unit and the first
  • the low-level signal connection is used to generate the N-th level sub-pixel scanning signal according to a high-level signal, the N+3 level cascade signal and the first driving signal to drive the sub-pixels in the N-th level pixel point; wherein , N is a positive integer.
  • the Nth-stage GOA sub-circuit further includes: a first pull-down unit connected to the cascade control unit and a second low-level signal, and is configured to perform according to the first The N+3 cascade signal controls whether the first driving signal is in a low level state.
  • the N-level GOA sub-circuit further includes: a drive signal generating unit connected to the cascade control unit and the second low-level signal , Used to generate a second drive signal according to the first drive signal; and a second pull-down unit, connected to the cascade control unit, the second low level signal, and the drive signal generating unit, and used to control the first drive according to the second drive signal Whether the signal is in a low-level state; among them, when the first drive signal is in a high-level state, the second drive signal is in a low-level state; when the first drive signal is in a low-level state, the second drive signal is high Level status.
  • the N-level GOA sub-circuit further includes: a third pull-down unit, a cascade control unit, a first low-level signal, and The driving signal generating unit is connected and used for controlling whether the scanning signal of the N-th stage main pixel is in a low level state according to the second driving signal.
  • the N-level GOA sub-circuit further includes: a fourth pull-down unit, a cascade control unit, a first low-level signal, and The driving signal generating unit is connected and used for controlling whether the scanning signal of the Nth sub-pixel is in a low level state according to the second driving signal.
  • the cascade control unit includes a first thin film transistor; the gate of the first thin film transistor is used to access the N-3th cascade signal; the first thin film The drain of the transistor is used to connect to the N-3th level scanning signal; the source of the first thin film transistor is used to output the first driving signal.
  • the cascaded signal generating unit includes a second thin film transistor; the drain of the second thin film transistor is used to access the Nth level clock signal ; The gate of the second thin film transistor is connected to the source of the first thin film transistor to access the first driving signal; the source of the second thin film transistor is used to output the Nth cascade signal.
  • the first scan driving unit includes a capacitor, a third thin film transistor, and a fourth thin film transistor; the drain of the third thin film transistor is used for To connect to the Nth stage clock signal; the source of the first thin film transistor is connected to the gate of the third thin film transistor and the first end of the capacitor; the gate of the fourth thin film transistor is used to connect to the N+3th stage cascade Signal; the source of the fourth thin film transistor is connected with the first low-level signal; the source of the third thin film transistor is connected with the drain of the fourth thin film transistor and the second end of the capacitor.
  • the second scan driving unit includes a fifth thin film transistor and a sixth thin film transistor; the drain of the fifth thin film transistor is used for access Nth-level clock signal; the gate of the fifth thin film transistor is connected to the source of the first thin film transistor; the source of the fifth thin film transistor is connected to the source of the sixth thin film transistor; the gate of the sixth thin film transistor is used to connect Enter the N+3 cascade signal; the source of the sixth thin film transistor is connected to the first low-level signal.
  • the present application provides a display panel, which includes the GOA circuit in any of the above embodiments.
  • the GOA circuit provided by the present application outputs a first drive signal through a cascade control unit, and controls the first scan drive unit and the second scan drive unit through the first drive signal to simultaneously output main pixel scan signals and sub-pixel scan signals of different voltage waveforms , Thereby improving the chromatic aberration or color shift; at the same time, it also simplifies the GOA circuit structure and reduces the number of flip-chip films and fan-shaped leads in the GOA circuit.
  • FIG. 1 is a schematic structural diagram of a gate driving circuit of a main pixel or a sub-pixel adopted in a 2G1D mode in a conventional technical solution.
  • FIG. 2 is a schematic diagram of waveforms of related nodes in the gate driving circuit shown in FIG. 1.
  • FIG. 3 is a schematic diagram of the first structure of the GOA circuit provided by an embodiment of the application.
  • FIG. 4 is a schematic diagram of the second structure of the GOA circuit provided by the embodiment of the application.
  • FIG. 5 is a schematic diagram of a third structure of the GOA circuit provided by an embodiment of the application.
  • FIG. 6 is a schematic diagram of the fourth structure of the GOA circuit provided by the embodiment of the application.
  • FIG. 7 is a schematic diagram of a fifth structure of a GOA circuit provided by an embodiment of the application.
  • Fig. 8 is a circuit structure diagram of the GOA circuit shown in Fig. 7.
  • Fig. 9 is a schematic diagram of waveforms of relevant nodes in the GOA circuit shown in Fig. 8.
  • this embodiment provides a GOA circuit.
  • the GOA circuit is provided with a plurality of cascaded GOA sub-circuits, wherein the Nth-stage GOA sub-circuit includes a cascade control unit 100 and a cascade signal generation unit 200 , The first scan driving unit 300 and the second scan driving unit 400; the cascade control unit 100 is used to scan signals G(N-3) according to the N-3th level and the N-3th level cascade signal ST(N- 3) Generate the first drive signal Q(N); the cascade signal generation unit 200 is connected to the cascade control unit 100 and is used to generate the first drive signal Q(N) and the Nth stage clock signal CK(N) N-level cascade signal ST(N); the first scan driving unit 300 is connected to the cascade control unit 100 and the first low-level signal VSSG, and is used to respond to the N-level clock signal CK(N), the N+3th The cascade signal ST(N+3) and the first driving signal Q(N) generate the Nth level main
  • the control unit 100 is used to generate the first driving signal Q(N) according to the start signal; when N is a positive integer not less than 4, the cascade control unit 100 is used to generate the first drive signal Q(N) according to the N-3th level scanning signal G(N-3 ) And the N-3 th cascade signal ST(N-3) to generate the first driving signal Q(N).
  • the first driving signal Q(N) when the N-3th stage scanning signal G(N-3) and the N-3th stage cascade signal ST(N-3) are in a high level state, the first driving signal Q(N) is at a high level At this time, the first drive signal Q(N) controls the cascade signal generating unit 200 to output the Nth stage cascade signal ST(N) according to the Nth stage clock signal CK(N); at the same time, the first drive signal Q( N) Control the first scan driving unit 300 to output the Nth stage main pixel scanning signal GA(N) according to the Nth stage clock signal CK(N), and control the second scan driving unit 400 to output the Nth stage according to the high level signal VDD Sub-pixel scanning signal GB(N).
  • the N+3 cascade signal ST(N+3) controls the first scan driving unit 300 and the second scan driving unit 400 ,
  • the Nth level main pixel scanning signal GA(N) and the Nth level sub-pixel scanning signal GB(N) are pulled down to the same low level state as the first low level signal VSSG.
  • the GOA sub-circuit in this embodiment outputs the first driving signal Q(N) through the cascade control unit 100, and controls the first scan driving unit 300 and the second scan driving unit 400 to output simultaneously through the first driving signal Q(N)
  • the main pixel scan signal and sub-pixel scan signal of different voltage waveforms thereby improving the color difference or color shift; at the same time, the cascaded signal generating unit 200 generates the first drive signal Q(N) and the Nth level clock signal CK(N)
  • the N-th cascaded signal ST(N) provides conditions for cascading multiple GOA sub-circuits.
  • the GOA circuit provided in this embodiment simplifies the circuit structure of the 2G1D mode, thereby reducing the number of flip-chip films and sector leads in the GOA circuit, which is beneficial to achieve cost reduction and reduction Border width.
  • the Nth-stage GOA sub-circuit further includes: a first pull-down unit 500 connected to the cascade control unit 100 and the second low-level signal VSSQ, and is configured to perform according to the Nth stage.
  • the +3 level cascade signal ST(N+3) controls whether the first driving signal Q(N) is in a low level state.
  • the N+3 cascade signal ST(N+3) controls the first pull-down unit 500 to drive the first
  • the signal Q(N) is pulled down to the same low level state as the second low level signal VSSQ to clamp the first driving signal Q(N) to the same low level state as the second low level signal VSSQ.
  • the Nth-stage GOA sub-circuit further includes: a driving signal generating unit 600 connected to the cascade control unit 100 and the second low-level signal VSSQ for driving according to the first The signal Q(N) generates the second driving signal P(N); and the second pull-down unit 700 is connected to the cascade control unit 100, the second low-level signal VSSQ, and the driving signal generation unit 600 for driving according to the second The signal P(N) controls whether the first drive signal Q(N) is in a low level state; wherein, when the first drive signal Q(N) is in a high level state, the second drive signal P(N) is in a low level state. Flat state; when the first drive signal Q(N) is in a low level state, the second drive signal P(N) is in a high level state.
  • the second driving signal P(N) when the first driving signal Q(N) is in a low level state, at this time, the second driving signal P(N) is in a high level state, and the second driving signal P(N) controls the second pull-down unit 700
  • the first driving signal Q(N) is pulled down to the same low level state as the second low level signal VSSQ, so as to clamp the first driving signal Q(N) to a low level state.
  • the Nth-stage GOA sub-circuit further includes: a third pull-down unit 800 connected to the cascade control unit 100, the first low-level signal VSSG, and the drive signal generation unit 600, It is used to control whether the N-th stage main pixel scanning signal GA(N) is in a low level state according to the second driving signal P(N).
  • a third pull-down unit 800 connected to the cascade control unit 100, the first low-level signal VSSG, and the drive signal generation unit 600, It is used to control whether the N-th stage main pixel scanning signal GA(N) is in a low level state according to the second driving signal P(N).
  • the second driving signal P(N) when the first driving signal Q(N) is in a low level state, at this time, the second driving signal P(N) is in a high level state, and the second driving signal P(N) controls the third pull-down unit 800
  • the Nth level main pixel scanning signal GA(N) is pulled down to the same low level as the first low level signal VSSG, so as to clamp the Nth level main pixel scanning signal GA(N) to a low level state.
  • the Nth-stage GOA sub-circuit further includes: a fourth pull-down unit 900 connected to the cascade control unit 100, the first low-level signal VSSG, and the drive signal generation unit 600, It is used to control whether the Nth sub-pixel scanning signal GB(N) is in a low level state according to the second driving signal P(N).
  • a fourth pull-down unit 900 connected to the cascade control unit 100, the first low-level signal VSSG, and the drive signal generation unit 600, It is used to control whether the Nth sub-pixel scanning signal GB(N) is in a low level state according to the second driving signal P(N).
  • the second driving signal P(N) controls the fourth pull-down unit 900
  • the N-th level sub-pixel scanning signal GB(N) is pulled down to the same low level as the first low-level signal VSSG, so as to clamp the N-th level sub-pixel scanning signal GB(N) to a low level.
  • the cascade control unit 100 includes a first thin film transistor T1; the gate of the first thin film transistor T1 is used to access the N-3th cascade signal ST (N-3 ); The drain of the first thin film transistor T1 is used to connect to the N-3th level scanning signal G(N-3); the source of the first thin film transistor T1 is used to output the first driving signal Q(N).
  • the cascaded signal generating unit 200 includes a second thin film transistor T2; the drain of the second thin film transistor T2 is used to connect to the Nth stage clock signal CK(N); The gate of the thin film transistor T2 is connected to the source of the first thin film transistor T1 to access the first driving signal Q(N); the source of the second thin film transistor T2 is used to output the Nth cascade signal ST(N) .
  • the first scan driving unit 300 includes a capacitor Cb, a third thin film transistor T3, and a fourth thin film transistor T4; the drain of the third thin film transistor T3 is used to connect to the Nth thin film transistor T3.
  • Stage clock signal CK(N) the source of the first thin film transistor T1 is connected to the gate of the third thin film transistor T3 and the first end of the capacitor Cb; the gate of the fourth thin film transistor T4 is used to connect to the N+3th The cascade signal ST(N+3); the source of the fourth thin film transistor T4 is connected to the first low-level signal VSSG; the source of the third thin film transistor T3 is connected to the drain of the fourth thin film transistor T4 and the capacitor Cb The second end is connected.
  • the second scan driving unit 400 includes a fifth thin film transistor T5 and a sixth thin film transistor T6; the drain of the fifth thin film transistor T5 is used to connect to the Nth stage clock signal CK (N); The gate of the fifth thin film transistor T5 is connected to the source of the first thin film transistor T1; the source of the fifth thin film transistor T5 is connected to the source of the sixth thin film transistor T6; the gate of the sixth thin film transistor T6 It is used to connect to the N+3 cascade signal ST(N+3); the source of the sixth thin film transistor T6 is connected to the first low level signal VSSG.
  • the first pull-down unit 500 includes a seventh thin film transistor T7; the gate of the seventh thin film transistor T7 is used to connect to the N+3 cascade signal ST(N+ 3); The drain of the seventh thin film transistor T7 is connected to the source of the first thin film transistor T1; the source of the seventh thin film transistor T7 is connected to the second low-level signal VSSQ.
  • the driving signal generating unit 600 includes an eighth thin film transistor T8, a ninth thin film transistor T9, a tenth thin film transistor T10, and an eleventh thin film transistor T11; the high-level signal VDD and The gate of the eighth thin film transistor T8, the drain of the eighth thin film transistor T8, and the drain of the ninth thin film transistor T9 are connected; the source of the eighth thin film transistor T8 is connected to the gate of the ninth thin film transistor T9 and the tenth thin film transistor The drain of T10 is connected; the source of the ninth thin film transistor T9 is connected to the drain of the eleventh thin film transistor T11; the source of the first thin film transistor T1 is connected to the gate of the tenth thin film transistor T10 and the eleventh thin film transistor T11 The second low-level signal VSSQ is connected to the source of the tenth thin film transistor T10 and the source of the eleventh thin film transistor T11.
  • the second pull-down unit 700 includes a twelfth thin film transistor T12; the drain of the twelfth thin film transistor T12 is connected to the source of the first thin film transistor T1; The source of the transistor T12 is connected to the second low-level signal VSSQ; the gate of the twelfth thin film transistor T12 is connected to the drain of the eleventh thin film transistor T11.
  • the third pull-down unit 800 includes a thirteenth thin film transistor T13; the drain of the thirteenth thin film transistor T13 is connected to the drain of the fourth thin film transistor T4; The source of the transistor T13 is connected to the first low-level signal VSSG; the gate of the thirteenth thin film transistor T13 is connected to the drain of the eleventh thin film transistor T11.
  • the fourth pull-down unit 900 includes a fourteenth thin film transistor T14; the drain of the fourteenth thin film transistor T14 is connected to the drain of the sixth thin film transistor T6; The source of the transistor T14 is connected to the first low-level signal VSSG; the gate of the fourteenth thin film transistor T14 is connected to the drain of the eleventh thin film transistor T11.
  • this embodiment provides a display panel, which includes the GOA circuit in any of the above embodiments.

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  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
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Abstract

本申请公开了一种GOA电路，设置有多个级联的GOA子电路，其中，第N级GOA子电路包括：级联控制单元，用于根据第N-3级扫描信号和第N-3级级联信号生成第一驱动信号；级联信号产生单元，与级联控制单元连接；第一扫描驱动单元，与级联控制单元和第一低电平信号连接；以及第二扫描驱动单元，与级联控制单元和第一低电平信号连接。

Description

一种GOA电路和显示面板 技术领域
本申请涉及显示技术领域，尤其涉及垂直配向型显示技术领域，具体涉及一种GOA电路及显示面板。
 背景技术
随着显示技术的不断发展，大屏幕、高分辨率、及高刷新频率成为了液晶显示面板追求的目标。当用户从侧面观看垂直配向型的液晶显示面板时，特别是大尺寸的液晶显示面板时会出现色差或者色偏（color washout）的现象，且这种色偏会随着侧视观看角度的增大而增大。为了降低色偏，增大可视角度范围，通常都会将液晶显示面板的显示区域的每个像素点分成主像素和子像素。
但是，目前8畴（Domain）显示的像素设计中，大多采用2G1D（指的是两个栅驱动电路和1条数据线）模式的栅驱动电路来分别实现主像素和子像素的栅驱动电压，其同一像素点中主像素和子像素需要使用两个相同或者相似的栅驱动电路，该栅驱动电路如图1所示，以及该栅驱动电路的各信号输出时序如图2所示。这增加了GOA（Gate driver On Array，阵列基板行驱动）电路中的覆晶薄膜（COF）以及扇形引线(fanout)的数量，同时也导致增加了其制作成本以及边框（Border）宽度。其中，主像素和子像素的亮度可以通过不同的栅（Gate）驱动电压来单独控制，从而实现改善色差或者色偏的问题。
 技术问题
本申请提供一种GOA电路，解决的8畴显示中采用2G1D模式增加了GOA电路中覆晶薄膜及扇形引线的数量。
 技术解决方案
第一方面，本申请提供了一种GOA电路，GOA电路设置有多个级联的GOA子电路，其中，第N级GOA子电路包括级联控制单元、级联信号产生单元、第一扫描驱动单元以及第二扫描驱动单元；级联控制单元，用于根据第N-3级扫描信号和第N-3级级联信号生成第一驱动信号；级联信号产生单元，与级联控制单元连接，用于根据第一驱动信号和第N级时钟信号生成第N级级联信号；第一扫描驱动单元，与级联控制单元和第一低电平信号连接，用于根据第N级时钟信号、第N+3级级联信号以及第一驱动信号生成第N级主像素扫描信号，以驱动第N级像素点中的主像素；以及第二扫描驱动单元，与级联控制单元和第一低电平信号连接，用于根据一高电平信号、第N+3级级联信号以及第一驱动信号生成第N级子像素扫描信号，以驱动第N级像素点中的子像素；其中，N为正整数。
结合第一方面，在第一方面的第一种实施方式中，第N级GOA子电路还包括：第一下拉单元，与级联控制单元和第二低电平信号连接，用于根据第N+3级级联信号控制第一驱动信号是否处于低电平状态。
结合第一方面的第一种实施方式，在第一方面的第二种实施方式中，第N级GOA子电路还包括：驱动信号生成单元，与级联控制单元和第二低电平信号连接，用于根据第一驱动信号生成第二驱动信号；和第二下拉单元，与级联控制单元、第二低电平信号以及驱动信号生成单元连接，用于根据第二驱动信号控制第一驱动信号是否处于低电平状态；其中，当第一驱动信号为高电平状态时，第二驱动信号为低电平状态；当第一驱动信号为低电平状态时，第二驱动信号为高电平状态。
结合第一方面的第二种实施方式，在第一方面的第三种实施方式中，第N级GOA子电路还包括：第三下拉单元，与级联控制单元、第一低电平信号以及驱动信号生成单元连接，用于根据第二驱动信号控制第N级主像素扫描信号是否处于低电平状态。
结合第一方面的第二种实施方式，在第一方面的第四种实施方式中，第N级GOA子电路还包括：第四下拉单元，与级联控制单元、第一低电平信号以及驱动信号生成单元连接，用于根据第二驱动信号控制第N级子像素扫描信号是否处于低电平状态。
结合第一方面，在第一方面的第五种实施方式中，级联控制单元包括第一薄膜晶体管；第一薄膜晶体管的栅极用于接入第N-3级级联信号；第一薄膜晶体管的漏极用于接入第N-3级扫描信号；第一薄膜晶体管的源极用于输出第一驱动信号。
结合第一方面的第五种实施方式，在第一方面的第六种实施方式中，级联信号产生单元包括第二薄膜晶体管；第二薄膜晶体管的漏极用于接入第N级时钟信号；第二薄膜晶体管的栅极与第一薄膜晶体管的源极连接，以接入第一驱动信号；第二薄膜晶体管的源极用于输出第N级级联信号。
结合第一方面的第五种实施方式，在第一方面的第七种实施方式中，第一扫描驱动单元包括一电容、第三薄膜晶体管以及第四薄膜晶体管；第三薄膜晶体管的漏极用于接入第N级时钟信号；第一薄膜晶体管的源极与第三薄膜晶体管的栅极和电容的第一端连接；第四薄膜晶体管的栅极用于接入第N+3级级联信号；第四薄膜晶体管的源极与第一低电平信号连接；第三薄膜晶体管的源极与第四薄膜晶体管的漏极和电容的第二端连接。
结合第一方面的第五种实施方式，在第一方面的第八种实施方式中，第二扫描驱动单元包括第五薄膜晶体管和第六薄膜晶体管；第五薄膜晶体管的漏极用于接入第N级时钟信号；第五薄膜晶体管的栅极与第一薄膜晶体管的源极连接；第五薄膜晶体管的源极与第六薄膜晶体管的源极连接；第六薄膜晶体管的栅极用于接入第N+3级级联信号；第六薄膜晶体管的源极与第一低电平信号连接。
第二方面，本申请提供了一种显示面板，其包括上述任一实施方式中的GOA电路。
 有益效果
本申请提供的GOA电路，通过级联控制单元输出第一驱动信号，并通过第一驱动信号控制第一扫描驱动单元和第二扫描驱动单元同时输出不同电压波形的主像素扫描信号和子像素扫描信号，从而改善了色差或者色偏现象；同时也简化了GOA电路结构，减少了GOA电路中覆晶薄膜及扇形引线的数量。
 附图说明
图1为传统技术方案中2G1D模式采用的主像素或者子像素的栅驱动电路的结构示意图。
图2为图1所示的栅驱动电路中相关节点的波形示意图。
图3为本申请实施例提供的GOA电路的第一种结构示意图。
图4为本申请实施例提供的GOA电路的第二种结构示意图。
图5为本申请实施例提供的GOA电路的第三种结构示意图。
图6为本申请实施例提供的GOA电路的第四种结构示意图。
图7为本申请实施例提供的GOA电路的第五种结构示意图。
图8为图7中所示的GOA电路的电路结构图。
图9为图8所示的GOA电路中相关节点的波形示意图。
 本发明的实施方式
为使本申请的目的、技术方案及效果更加清楚、明确，以下参照附图并举实施例对本申请进一步详细说明。应当理解，此处所描述的具体实施例仅用以解释本申请，并不用于限定本申请。
如图3所示，本实施例提供了一种GOA电路，GOA电路设置有多个级联的GOA子电路，其中，第N级GOA子电路包括级联控制单元100、级联信号产生单元200、第一扫描驱动单元300以及第二扫描驱动单元400；级联控制单元100，用于根据第N-3级扫描信号G(N-3)和第N-3级级联信号ST(N-3)生成第一驱动信号Q(N)；级联信号产生单元200，与级联控制单元100连接，用于根据第一驱动信号Q(N)和第N级时钟信号CK(N)生成第N级级联信号ST(N)；第一扫描驱动单元300，与级联控制单元100和第一低电平信号VSSG连接，用于根据第N级时钟信号CK(N)、第N+3级级联信号ST(N+3)以及第一驱动信号Q(N)生成第N级主像素扫描信号GA(N)，以驱动第N级像素点中的主像素；以及第二扫描驱动单元400，与级联控制单元100和第一低电平信号VSSG连接，用于根据一高电平信号VDD、第N+3级级联信号ST(N+3)以及第一驱动信号Q(N)生成第N级子像素扫描信号GB(N)，以驱动第N级像素点中的子像素；其中，N为正整数。
具体地，当N为小于4的正整数时，第N-3级扫描信号G(N-3)和第N-3级级联信号ST(N-3)包含在一启动信号中，级联控制单元100用于根据该启动信号生成第一驱动信号Q(N)；当N为不小于4的正整数时，级联控制单元100用于根据第N-3级扫描信号G(N-3)和第N-3级级联信号ST(N-3)生成第一驱动信号Q(N)。
其中，当第N-3级扫描信号G(N-3)和第N-3级级联信号ST(N-3)为高电平状态时，第一驱动信号Q(N)为高电平状态，此时，第一驱动信号Q(N)控制级联信号产生单元200根据第N级时钟信号CK(N)输出第N级级联信号ST(N)；同时，第一驱动信号Q(N)控制第一扫描驱动单元300根据第N级时钟信号CK(N)输出第N级主像素扫描信号GA(N)，和控制第二扫描驱动单元400根据高电平信号VDD输出第N级子像素扫描信号GB(N)。当第N+3级级联信号ST(N+3)为高电平状态时，第N+3级级联信号ST(N+3)控制第一扫描驱动单元300和第二扫描驱动单元400，将第N级主像素扫描信号GA(N)和第N级子像素扫描信号GB(N)拉低到与第一低电平信号VSSG相同的低电平状态。
本实施例中的GOA子电路通过级联控制单元100输出第一驱动信号Q(N)，并通过第一驱动信号Q(N)控制第一扫描驱动单元300和第二扫描驱动单元400同时输出不同电压波形的主像素扫描信号和子像素扫描信号，从而改善了色差或者色偏现象；同时级联信号产生单元200根据第一驱动信号Q(N)和第N级时钟信号CK(N)生成了第N级级联信号ST(N)，为多个GOA子电路进行级联提供了条件。与图1中所示的2G1D模式相比，本实施例提供的GOA电路简化了2G1D模式的电路结构，从而减少了GOA电路中覆晶薄膜及扇形引线的数量，有利于实现降低成本和减小边框宽度。
如图4所示，在其中一个实施例中，第N级GOA子电路还包括：第一下拉单元500，与级联控制单元100和第二低电平信号VSSQ连接，用于根据第N+3级级联信号ST(N+3)控制第一驱动信号Q(N)是否处于低电平状态。
具体地，当第N+3级级联信号ST(N+3)为高电平状态时，第N+3级级联信号ST(N+3)控制第一下拉单元500将第一驱动信号Q(N)拉低到与第二低电平信号VSSQ相同的低电平状态，以将第一驱动信号Q(N)钳制在第二低电平信号VSSQ相同的低电平状态。
如图5所示，在其中一个实施例中，第N级GOA子电路还包括：驱动信号生成单元600，与级联控制单元100和第二低电平信号VSSQ连接，用于根据第一驱动信号Q(N)生成第二驱动信号P(N)；和第二下拉单元700，与级联控制单元100、第二低电平信号VSSQ以及驱动信号生成单元600连接，用于根据第二驱动信号P(N)控制第一驱动信号Q(N)是否处于低电平状态；其中，当第一驱动信号Q(N)为高电平状态时，第二驱动信号P(N)为低电平状态；当第一驱动信号Q(N)为低电平状态时，第二驱动信号P(N)为高电平状态。
具体地，当第一驱动信号Q(N)为低电平状态时，此时，第二驱动信号P(N)为高电平状态，第二驱动信号P(N)控制第二下拉单元700将第一驱动信号Q(N)拉低至与第二低电平信号VSSQ相同的低电平状态，以将第一驱动信号Q(N)钳制在低电平状态。
如图6所示，在其中一个实施例中，第N级GOA子电路还包括：第三下拉单元800，与级联控制单元100、第一低电平信号VSSG以及驱动信号生成单元600连接，用于根据第二驱动信号P(N)控制第N级主像素扫描信号GA(N)是否处于低电平状态。
具体地，当第一驱动信号Q(N)为低电平状态时，此时，第二驱动信号P(N)为高电平状态，第二驱动信号P(N)控制第三下拉单元800将第N级主像素扫描信号GA(N)拉低至与第一低电平信号VSSG相同的低电平状态，以将第N级主像素扫描信号GA(N)钳制在低电平状态。
如图7所示，在其中一个实施例中，第N级GOA子电路还包括：第四下拉单元900，与级联控制单元100、第一低电平信号VSSG以及驱动信号生成单元600连接，用于根据第二驱动信号P(N)控制第N级子像素扫描信号GB(N)是否处于低电平状态。
具体地，当第一驱动信号Q(N)为低电平状态时，此时，第二驱动信号P(N)为高电平状态，第二驱动信号P(N)控制第四下拉单元900将第N级子像素扫描信号GB(N)拉低至与第一低电平信号VSSG相同的低电平状态，以将第N级子像素扫描信号GB(N)钳制在低电平状态。
如图8所示，在其中一个实施例中，级联控制单元100包括第一薄膜晶体管T1；第一薄膜晶体管T1的栅极用于接入第N-3级级联信号ST(N-3)；第一薄膜晶体管T1的漏极用于接入第N-3级扫描信号G(N-3)；第一薄膜晶体管T1的源极用于输出第一驱动信号Q(N)。
如图8所示，在其中一个实施例中，级联信号产生单元200包括第二薄膜晶体管T2；第二薄膜晶体管T2的漏极用于接入第N级时钟信号CK(N)；第二薄膜晶体管T2的栅极与第一薄膜晶体管T1的源极连接，以接入第一驱动信号Q(N)；第二薄膜晶体管T2的源极用于输出第N级级联信号ST(N)。
如图8所示，在其中一个实施例中，第一扫描驱动单元300包括一电容Cb、第三薄膜晶体管T3以及第四薄膜晶体管T4；第三薄膜晶体管T3的漏极用于接入第N级时钟信号CK(N)；第一薄膜晶体管T1的源极与第三薄膜晶体管T3的栅极和电容Cb的第一端连接；第四薄膜晶体管T4的栅极用于接入第N+3级级联信号ST(N+3)；第四薄膜晶体管T4的源极与第一低电平信号VSSG连接；第三薄膜晶体管T3的源极与第四薄膜晶体管T4的漏极和电容Cb的第二端连接。
如图8所示，在其中一个实施例中，第二扫描驱动单元400包括第五薄膜晶体管T5和第六薄膜晶体管T6；第五薄膜晶体管T5的漏极用于接入第N级时钟信号CK(N)；第五薄膜晶体管T5的栅极与第一薄膜晶体管T1的源极连接；第五薄膜晶体管T5的源极与第六薄膜晶体管T6的源极连接；第六薄膜晶体管T6的栅极用于接入第N+3级级联信号ST(N+3)；第六薄膜晶体管T6的源极与第一低电平信号VSSG连接。
如图8所示，在其中一个实施例中，第一下拉单元500包括第七薄膜晶体管T7；第七薄膜晶体管T7的栅极用于接入第N+3级级联信号ST(N+3)；第七薄膜晶体管T7的漏极与第一薄膜晶体管T1的源极连接；第七薄膜晶体管T7的源极与第二低电平信号VSSQ连接。
如图8所示，在其中一个实施例中，驱动信号生成单元600包括第八薄膜晶体管T8、第九薄膜晶体管T9、第十薄膜晶体管T10以及第十一薄膜晶体管T11；高电平信号VDD与第八薄膜晶体管T8的栅极、第八薄膜晶体管T8的漏极以及第九薄膜晶体管T9的漏极连接；第八薄膜晶体管T8的源极与第九薄膜晶体管T9的栅极和第十薄膜晶体管T10的漏极连接；第九薄膜晶体管T9的源极与第十一薄膜晶体管T11的漏极连接；第一薄膜晶体管T1的源极与第十薄膜晶体管T10的栅极和第十一薄膜晶体管T11的栅极连接；第二低电平信号VSSQ与第十薄膜晶体管T10的源极和第十一薄膜晶体管T11的源极连接。
如图8所示，在其中一个实施例中，第二下拉单元700包括第十二薄膜晶体管T12；第十二薄膜晶体管T12的漏极与第一薄膜晶体管T1的源极连接；第十二薄膜晶体管T12的源极与第二低电平信号VSSQ连接；第十二薄膜晶体管T12的栅极与第十一薄膜晶体管T11的漏极连接。
如图8所示，在其中一个实施例中，第三下拉单元800包括第十三薄膜晶体管T13；第十三薄膜晶体管T13的漏极与第四薄膜晶体管T4的漏极连接；第十三薄膜晶体管T13的源极与第一低电平信号VSSG连接；第十三薄膜晶体管T13的栅极与第十一薄膜晶体管T11的漏极连接。
如图8所示，在其中一个实施例中，第四下拉单元900包括第十四薄膜晶体管T14；第十四薄膜晶体管T14的漏极与第六薄膜晶体管T6的漏极连接；第十四薄膜晶体管T14的源极与第一低电平信号VSSG连接；第十四薄膜晶体管T14的栅极与第十一薄膜晶体管T11的漏极连接。
如图9所示，在其中一个像素点中主像素和子像素同时进行充电时，其主像素和子像素的栅驱动电压波形不同，从而实现了主像素和子像素的充电差异，解决了侧视时出现的色差或者色偏的问题。
在其中一个实施例中，本实施例提供了一种显示面板，其包括上述任一实施例中的GOA电路。
可以理解的是，对本领域普通技术人员来说，可以根据本申请的技术方案及其发明构思加以等同替换或改变，而所有这些改变或替换都应属于本申请所附的权利要求的保护范围。

Claims (19)

  1. 一种GOA电路，其中，所述GOA电路设置有多个级联的GOA子电路，其中，第N级GOA子电路包括：
    级联控制单元，用于根据第N-3级扫描信号和第N-3级级联信号生成第一驱动信号；
    级联信号产生单元，与所述级联控制单元连接，用于根据所述第一驱动信号和第N级时钟信号生成第N级级联信号；
    第一扫描驱动单元，与所述级联控制单元和第一低电平信号连接，用于根据所述第N级时钟信号、第N+3级级联信号以及所述第一驱动信号生成第N级主像素扫描信号，以驱动第N级像素点中的主像素；以及
    第二扫描驱动单元，与所述级联控制单元和所述第一低电平信号连接，用于根据一高电平信号、所述第N+3级级联信号以及所述第一驱动信号生成第N级子像素扫描信号，以驱动所述第N级像素点中的子像素；
    所述GOA电路还包括第四下拉单元；所述第四下拉单元包括第十四薄膜晶体管；
    所述第十四薄膜晶体管的漏极与第六薄膜晶体管的漏极连接；所述第十四薄膜晶体管的源极与所述第一低电平信号连接；所述第十四薄膜晶体管的栅极与第十一薄膜晶体管的漏极连接；
    其中，N为正整数。
  2. 根据权利要求1所述的GOA电路，其中，所述第N级GOA子电路还包括：
    第一下拉单元，与所述级联控制单元和第二低电平信号连接，用于根据所述第N+3级级联信号控制所述第一驱动信号是否处于低电平状态。
  3. 根据权利要求2所述的GOA电路，其中，所述第N级GOA子电路还包括：
    驱动信号生成单元，与所述级联控制单元和所述第二低电平信号连接，用于根据所述第一驱动信号生成第二驱动信号；和
    第二下拉单元，与所述级联控制单元、所述第二低电平信号以及所述驱动信号生成单元连接，用于根据所述第二驱动信号控制所述第一驱动信号是否处于低电平状态；
    其中，当所述第一驱动信号为高电平状态时，所述第二驱动信号为低电平状态；当所述第一驱动信号为低电平状态时，所述第二驱动信号为高电平状态。
  4. 根据权利要求3所述的GOA电路，其中，所述第N级GOA子电路还包括：
    第三下拉单元，与所述级联控制单元、所述第一低电平信号以及所述驱动信号生成单元连接，用于根据所述第二驱动信号控制所述第N级主像素扫描信号是否处于低电平状态。
  5. 根据权利要求4所述的GOA电路，其中，所述级联控制单元包括第一薄膜晶体管；
    所述第一薄膜晶体管的栅极用于接入所述第N-3级级联信号；所述第一薄膜晶体管的漏极用于接入所述第N-3级扫描信号；所述第一薄膜晶体管的源极用于输出所述第一驱动信号。
  6. 一种GOA电路，其中，所述GOA电路设置有多个级联的GOA子电路，其中，第N级GOA子电路包括：
    级联控制单元，用于根据第N-3级扫描信号和第N-3级级联信号生成第一驱动信号；
    级联信号产生单元，与所述级联控制单元连接，用于根据所述第一驱动信号和第N级时钟信号生成第N级级联信号；
    第一扫描驱动单元，与所述级联控制单元和第一低电平信号连接，用于根据所述第N级时钟信号、第N+3级级联信号以及所述第一驱动信号生成第N级主像素扫描信号，以驱动第N级像素点中的主像素；以及
    第二扫描驱动单元，与所述级联控制单元和所述第一低电平信号连接，用于根据一高电平信号、所述第N+3级级联信号以及所述第一驱动信号生成第N级子像素扫描信号，以驱动所述第N级像素点中的子像素；
    其中，N为正整数。
  7. 根据权利要求6所述的GOA电路，其中，所述第N级GOA子电路还包括：
    第一下拉单元，与所述级联控制单元和第二低电平信号连接，用于根据所述第N+3级级联信号控制所述第一驱动信号是否处于低电平状态。
  8. 根据权利要求7所述的GOA电路，其中，所述第N级GOA子电路还包括：
    驱动信号生成单元，与所述级联控制单元和所述第二低电平信号连接，用于根据所述第一驱动信号生成第二驱动信号；和
    第二下拉单元，与所述级联控制单元、所述第二低电平信号以及所述驱动信号生成单元连接，用于根据所述第二驱动信号控制所述第一驱动信号是否处于低电平状态；
    其中，当所述第一驱动信号为高电平状态时，所述第二驱动信号为低电平状态；当所述第一驱动信号为低电平状态时，所述第二驱动信号为高电平状态。
  9. 根据权利要求8所述的GOA电路，其中，所述第N级GOA子电路还包括：
    第三下拉单元，与所述级联控制单元、所述第一低电平信号以及所述驱动信号生成单元连接，用于根据所述第二驱动信号控制所述第N级主像素扫描信号是否处于低电平状态。
  10. 根据权利要求9所述的GOA电路，其中，所述第N级GOA子电路还包括：
    第四下拉单元，与所述级联控制单元、所述第一低电平信号以及所述驱动信号生成单元连接，用于根据所述第二驱动信号控制所述第N级子像素扫描信号是否处于低电平状态。
  11. 根据权利要求10所述的GOA电路，其中，所述级联控制单元包括第一薄膜晶体管；
    所述第一薄膜晶体管的栅极用于接入所述第N-3级级联信号；所述第一薄膜晶体管的漏极用于接入所述第N-3级扫描信号；所述第一薄膜晶体管的源极用于输出所述第一驱动信号。
  12. 根据权利要求11所述的GOA电路，其中，所述级联信号产生单元包括第二薄膜晶体管；
    所述第二薄膜晶体管的漏极用于接入所述第N级时钟信号；所述第二薄膜晶体管的栅极与所述第一薄膜晶体管的源极连接，以接入所述第一驱动信号；所述第二薄膜晶体管的源极用于输出所述第N级级联信号。
  13. 根据权利要求12所述的GOA电路，其中，所述第一扫描驱动单元包括一电容、第三薄膜晶体管以及第四薄膜晶体管；
    所述第三薄膜晶体管的漏极用于接入所述第N级时钟信号；所述第一薄膜晶体管的源极与所述第三薄膜晶体管的栅极和所述电容的第一端连接；所述第四薄膜晶体管的栅极用于接入所述第N+3级级联信号；所述第四薄膜晶体管的源极与所述第一低电平信号连接；所述第三薄膜晶体管的源极与所述第四薄膜晶体管的漏极和所述电容的第二端连接。
  14. 根据权利要求13所述的GOA电路，其中，所述第二扫描驱动单元包括第五薄膜晶体管和第六薄膜晶体管；
    所述第五薄膜晶体管的漏极用于接入所述第N级时钟信号；所述第五薄膜晶体管的栅极与所述第一薄膜晶体管的源极连接；所述第五薄膜晶体管的源极与所述第六薄膜晶体管的源极连接；所述第六薄膜晶体管的栅极用于接入所述第N+3级级联信号；所述第六薄膜晶体管的源极与所述第一低电平信号连接。
  15. 根据权利要求14所述的GOA电路，其中，所述第一下拉单元包括第七薄膜晶体管；
    所述第七薄膜晶体管的栅极用于接入所述第N+3级级联信号；所述第七薄膜晶体管的漏极与所述第一薄膜晶体管的源极连接；所述第七薄膜晶体管的源极与所述第二低电平信号连接。
  16. 根据权利要求15所述的GOA电路，其中，所述驱动信号生成单元包括第八薄膜晶体管、第九薄膜晶体管、第十薄膜晶体管以及第十一薄膜晶体管；
    所述高电平信号与所述第八薄膜晶体管的栅极、所述第八薄膜晶体管的漏极以及所述第九薄膜晶体管的漏极连接；所述第八薄膜晶体管的源极与所述第九薄膜晶体管的栅极和所述第十薄膜晶体管的漏极连接；所述第九薄膜晶体管的源极与所述第十一薄膜晶体管的漏极连接；所述第一薄膜晶体管的源极与所述第十薄膜晶体管的栅极和所述第十一薄膜晶体管的栅极连接；所述第二低电平信号与所述第十薄膜晶体管的源极和所述第十一薄膜晶体管的源极连接。
  17. 根据权利要求16所述的GOA电路，其中，所述第二下拉单元包括第十二薄膜晶体管；
    所述第十二薄膜晶体管的漏极与所述第一薄膜晶体管的源极连接；所述第十二薄膜晶体管的源极与所述第二低电平信号连接；所述第十二薄膜晶体管的栅极与所述第十一薄膜晶体管的漏极连接。
  18. 根据权利要求15所述的GOA电路，其中，所述第三下拉单元包括第十三薄膜晶体管；
    所述第十三薄膜晶体管的漏极与所述第四薄膜晶体管的漏极连接；所述第十三薄膜晶体管的源极与所述第一低电平信号连接；所述第十三薄膜晶体管的栅极与所述第十一薄膜晶体管的漏极连接。
  19. 一种显示面板，其中，包括如权利要求6所述的GOA电路。
PCT/CN2020/079145 2020-02-21 2020-03-13 一种 goa 电路和显示面板 Ceased WO2021164076A1 (zh)

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