WO2021159880A1 - 一种体声波滤波器和多工器以及电子设备 - Google Patents

一种体声波滤波器和多工器以及电子设备 Download PDF

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Publication number
WO2021159880A1
WO2021159880A1 PCT/CN2020/141266 CN2020141266W WO2021159880A1 WO 2021159880 A1 WO2021159880 A1 WO 2021159880A1 CN 2020141266 W CN2020141266 W CN 2020141266W WO 2021159880 A1 WO2021159880 A1 WO 2021159880A1
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wafer
acoustic wave
filter
wave filter
bulk acoustic
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PCT/CN2020/141266
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English (en)
French (fr)
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庞慰
郑云卓
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诺思(天津)微系统有限责任公司
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Publication of WO2021159880A1 publication Critical patent/WO2021159880A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
    • H03H9/70—Multiple-port networks for connecting several sources or loads, working on different frequencies or frequency bands, to a common load or source
    • H03H9/703—Networks using bulk acoustic wave devices
    • H03H9/706—Duplexers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
    • H03H9/46—Filters

Definitions

  • the present invention relates to the technical field of filtering devices for communication, in particular to a bulk acoustic wave filter which is manufactured by using the principle of piezoelectric effect and can be assembled by gold wire bonding.
  • the small-size filter devices that can meet the needs of communication terminals are mainly piezoelectric acoustic wave filters.
  • the resonators that constitute this type of acoustic wave filter mainly include: FBAR (Film Bulk Acoustic Resonator), SMR (Solidly Mounted Resonator, solid-state assembly resonator), SAW (Surface Acoustic Wave, surface acoustic wave resonator) and BAW based on the principle of bulk acoustic wave FBAR and SMR.
  • SAW is a piezoelectric device made on a specific piezoelectric crystal, which is not compatible with the usual semiconductor silicon process. Therefore, most SAWs are made into plastic products by flip-chip CSP (chip-scale packaging).
  • the BAW manufacturing process is a general-purpose silicon wafer semiconductor process, which can seal and protect the internal resonator through wafer-level bonding, so micro-assembly can be achieved through gold wire bonding.
  • all bonding wires can be equivalent to an inductance of about 0.3nH to 1nH, especially the grounding inductance determines the position of the transmission zero point. , Thus affecting the far-band suppression of the filter, at the position of double frequency or triple frequency, the suppression will often reach -20dB or even worse.
  • it will be easily affected by external radio frequency interference, thereby deteriorating the out-of-band suppression or isolation characteristics.
  • the present invention provides a bulk acoustic wave filter and multiplexer and electronic equipment to achieve better grounding effects and good grounding shielding characteristics.
  • a bulk acoustic wave filter is provided.
  • the bulk acoustic wave filter of the present invention includes a carrier board and an upper wafer and a lower wafer located on the carrier board and arranged sequentially from top to bottom.
  • the upper surface and/or the lower surface of the upper wafer are provided with metal Shielding layer, the metal shielding layer is grounded.
  • the metal shielding layer on the upper surface of the upper wafer passes through a wafer-level bonding area, and a plurality of via holes of the upper wafer and the lower wafer, and is connected to the metal ground plane on the lower surface of the lower wafer. Connection; and/or, the metal shielding layer on the lower surface of the upper wafer is connected to the metal ground plane on the lower surface of the lower wafer through the wafer-level bonding area and the multiple vias of the lower wafer.
  • all the resonators of the filter are located in the metal shielding space formed by the metal shielding layer of the upper wafer, the upper wafer grounding via, the lower wafer grounding via, and the metal ground plane on the lower surface of the lower wafer. , So that the filter gets better electromagnetic isolation. In the case of using multiple vias, the ground inductance of the metal shielding layer constituting the above-mentioned shielding space will be smaller.
  • all the resonators of the filter are located on the upper surface of the lower wafer.
  • part or all of the resonators that need to be grounded in the filter are connected to the metal shielding layer on the upper surface of the upper wafer through a wafer-level bonding area and a plurality of via holes on the upper wafer.
  • part or all of the resonators in the filter that need to be grounded are connected to the metal shielding layer on the lower surface of the upper wafer through a wafer-level bonding area.
  • part or all of the resonators in the filter that need to be grounded are connected to the metal ground plane on the lower surface of the lower wafer through the via holes of the lower wafer.
  • At least one resonator is connected with multiple vias.
  • Connecting the resonator to the above-mentioned metal shielding layer helps to reduce the ground inductance of the resonator, so that the transmission zero point that forms out-of-band suppression moves to high frequency.
  • the transmission zero point moves to double frequency or even triple frequency, it will The out-of-band suppression and isolation characteristics of the corresponding position can be improved; when a certain resonator is connected through multiple vias, the ground inductance of the resonator can be further reduced.
  • the metal ground plane of the lower surface of the lower wafer is bonded to the ground plane of the carrier through conductive glue to be grounded.
  • a multiplexer including the bulk acoustic wave filter of the present invention.
  • an electronic device including the bulk acoustic wave filter of the present invention.
  • Figure 1 is a structural diagram of an existing filter
  • Figure 2 is a circuit diagram of a conventional filter
  • Fig. 3a is a simulation diagram of the amplitude-frequency response curve of the existing filter with the change of the mutual inductance M1 between IN and G1;
  • Fig. 3b is a simulation diagram of the amplitude-frequency response curve of the existing filter with the change of the mutual inductance M2 between G1 and G2;
  • FIG. 4 is a schematic diagram of the components of a conventional filter in a plan view
  • FIG. 5 and 6 are structural diagrams of a piezoelectric acoustic wave filter according to an embodiment of the present invention.
  • Fig. 7 is a structural diagram of a piezoelectric acoustic wave filter according to the second embodiment of the present invention.
  • Fig. 8 is a structural diagram of a piezoelectric acoustic wave filter according to the third embodiment of the present invention.
  • Figure 9a is a graph of the amplitude-frequency response of the filter near the stopband
  • Figure 9b is a graph of the amplitude-frequency response of the filter's far stop band
  • 10a and 10b are schematic diagrams of the influence of the ground inductance connected to the parallel resonator on the transmission zero point of the resonator.
  • Fig. 1 is a structural diagram of a conventional filter
  • Fig. 2 is a circuit diagram of a conventional filter.
  • IN is the input signal bonding wire
  • OUT is the output signal bonding wire
  • G1 is the ground bonding wire of the first-level parallel branch
  • G2 is the ground bonding wire of the second-level parallel branch. Since the bonding wires have a certain length, the lengths of the four bonding wires IN, OUT, G1, and G2 are generally between 0.5mm and 2mm, and the inductance introduced by them is generally between 0.4nH and 1.5nH. Due to the small size of the chip and the close spacing between the bonding wires, mutual inductance is inevitably introduced.
  • the mutual inductance is related to the inductance of the bonding wire itself and also to the distance between the bonding wires, generally 3pH ⁇ 20pH Between, the closer the distance, the greater the mutual inductance, the farther the distance, the smaller the mutual inductance. Because the input and output are generally the farthest distance, and are located on both sides of the chip, in the same direction, the mutual inductance between IN and OUT is the smallest and can be ignored.
  • M1 between IN and G1 the mutual inductance M2 between G1 and G2
  • M3 between G2 and OUT on the filter performance. From the perspective of the circuit, the filter can generally be regarded as a reciprocal network at both ends, so M1 and M3 have similar roles in the circuit, and M1 is represented here.
  • Fig. 3a is a simulation diagram of the amplitude-frequency response curve of the existing filter changing with the mutual inductance M1 between IN and G1;
  • Fig. 3b is a simulation diagram of the amplitude-frequency response curve of the existing filter changing with the mutual inductance M2 between G1 and G2 Figure:
  • the change of mutual inductance is 3pH ⁇ 18pH, and the step is 3pH. It can be seen from the simulation result of Fig. 3a that the change of M1 has almost no effect on the performance of the filter, and all the curves are almost overlapped. From the simulation results in Fig. 3b, it can be seen that the change of M2 has a greater impact on the transmission zero point outside the filter band.
  • Fig. 4 is a schematic diagram of the components of a conventional filter in a plan view. As shown in Figure 4, there are four pads distributed on the upper surface, the upper left corner is IN, the upper right corner is OUT, the lower left corner is G1, and the lower right corner is G2. There is a wafer-level bonding area on the pad, and a through-wafer hole is provided in the bonding area.
  • the filter has 3 series resonators, S1, S2, S3, and 2 parallel resonators P1 and P2.
  • the filter Based on the existing mutual inductance method of the bonding wires inside the filter, the filter will be exposed to a relatively harsh electromagnetic environment when micro-assembly is generally used. When there is an external interference signal, the performance of the filter will also be affected. deterioration.
  • the location of the filter's out-of-band suppression zero is closely related to the inductance of the ground bonding wire.
  • the greater the inductance of the ground the closer the transmission zeros on both sides of the filter are in the low frequency direction.
  • the far-band suppression on the high-frequency side becomes worse as the transmission zero position moves to the low-frequency direction, especially the position where the center frequency is doubled to tripled.
  • the smaller the grounding inductance the closer the transmission zeros on both sides of the filter are to the high-frequency direction.
  • the far-band suppression on the high-frequency side of the filter becomes better as the transmission zero position moves to high-frequency.
  • Figures 10a and 10b are schematic diagrams of the influence of the ground inductance connected to the parallel resonator on the transmission zero of the resonator.
  • the dashed line is the impedance response of the resonator and the inductance combined circuit when the ground inductance is 0.4nH, and the solid line is when the ground inductance is 0.2nH.
  • the impedance response of the resonator and inductor combined circuit It can be seen that the inductance is reduced by half, and the transmission zero point on the left and the transmission zero point on the right move in the direction shown by the arrow from low frequency to high frequency.
  • interference signals with a frequency equal to twice or three times the signal frequency will be generated.
  • the filter is particularly important for its suppression at the double or triple frequency. Therefore, how to achieve the performance of suppression and isolation of the filter outside the band of the filter, especially on the high frequency side, is a problem that needs to be solved.
  • the bonding wires that need to be interconnected with the carrier board are divided into two types, one is the signal bonding wire connected to the signal line on the carrier board to bond fingers, and the other is the signal bonding wire connected to the carrier board.
  • Ground bonding wire on the ground Connect the signal wire to the pad located on the front of the chip.
  • the ground wire is connected to the metallization plane on the back of the chip through the through hole.
  • the metalized plane on the back of the chip is glued to the ground plane of the package carrier through conductive adhesive, and the signal bonding pads on the front of the chip are connected to the signal bonding fingers on the carrier through bonding wires.
  • FIGS. 5 and 6 are structural diagrams of a piezoelectric acoustic wave filter according to an embodiment of the present invention.
  • Figure 6 shows the components in a plan view. It should be noted that Figures 5 and 6 are only schematic representations of the components and connection relationships. Both show the components and basic positions and connection relationships of the same piezoelectric acoustic wave filter, but the proportions and dimensions of each part of the two The cross-sectional view and the top view of the device are not formed correspondingly.
  • the piezoelectric acoustic wave filter mainly includes a carrier board 1 and an upper wafer 4, a lower wafer 5, a first metal shielding layer 13 and a sealing ring 7 on the carrier board 1.
  • the upper surface of the upper wafer 4 is provided with input signal bonding pads 3 and output signal bonding pads 11, and the carrier board 1 is provided with input signal bonding fingers 2 and output signal bonding fingers 12; upper wafer 4
  • the input signal bonding pad 3 on the upper surface of the wafer 4 is connected to the input signal bonding finger 2 of the carrier through the input signal bonding wire IN, and the output signal bonding pad 11 on the upper surface of the wafer 4 is connected through the output signal key
  • the bonding wire OUT is connected to the output signal bonding finger 12 of the carrier board, so as to realize the electrical interconnection between the chip and the carrier board.
  • the first metal shielding layer 13 almost covers the entire upper surface of the upper wafer 4, except for the bonding pads.
  • Figure 6 also shows the vias in the upper wafer 4 and the lower wafer 5. In fact, these vias cannot be seen in a top view. The location of these vias is shown in Figure 6 to show how much Through holes and staggered settings.
  • the first metal shielding layer 13 is located on the upper surface of the upper wafer 4, and a sealing ring 7 is provided between the lower surface of the upper wafer 4 and the upper surface of the lower wafer 5 to seal the sensitive circuit Between two wafers.
  • the sealing ring 7 is a kind of wafer-level bonding area, which, in addition to functioning as a conventional wafer-level bonding area (for example, the wafer-level bonding areas 71, 72 in the figure) to connect wafers, It also plays a role in sealing and shielding the gap between the wafers.
  • the upper surface of the lower wafer 5 is provided with a metal pattern connecting the sealing ring.
  • the metal pattern is an irregular metal layer (not shown in the figure), which serves as an electrical connection.
  • the resonance of the filter needs to be grounded.
  • the device is connected to the sealing ring 7 through the metal pattern to form an equipotential body with the same potential; a metal ground plane 8 is provided on the lower surface of the lower wafer 5, and the metal ground plane 8 on the lower surface of the lower wafer is glued 16 to On the ground plane 6 of the carrier board.
  • Two via holes 9 are provided in the lower wafer 5, which can be arranged symmetrically; the equipotential body is connected to the metal ground plane 8 on the lower surface of the lower wafer 5 through the two via holes 9; The metal ground plane 8 is glued to the ground plane 6 of the carrier board through the conductive glue 16.
  • the equipotential body and the metal ground plane 8 are connected in parallel, so that the geometric length of the conductor is reduced, thereby helping to reduce the common ground inductance, thereby also reducing the equipotentiality.
  • the potential difference between the body and the metal ground plane is provided in the lower wafer 5, which can be arranged symmetrically; the equipotential body is connected to the metal ground plane 8 on the lower surface of the lower wafer 5 through the two via holes 9; The metal ground plane 8 is glued to the ground plane 6 of the carrier board through the conductive glue 16.
  • the equipotential body is connected to the first metal shielding layer 13 on the upper surface of the upper wafer 4 through the two via holes 9 in the upper wafer 4.
  • the first metal shielding layer 13 is covered or almost covered on the upper surface of the upper wafer 4 except for the input signal bonding pad 3 and the output signal bonding pad 11, and is connected to the upper surface of the upper wafer 4 through two vias.
  • the equipotential body is connected, so as to realize the connection with the metal ground plane on the lower surface of the lower wafer 5, thereby realizing good grounding shielding characteristics.
  • the upper wafer 4 is provided with two symmetrically arranged vias 9 and the lower wafer 5 is also provided with two symmetrically arranged second vias 9;
  • the input signal line is connected to a via 9 in the upper wafer 4
  • the output signal line is connected to the output signal bonding pad 11 on the upper surface of the upper wafer through another via 9 in the upper wafer 4;
  • the ground lines G1 and G2 are respectively
  • the metal ground plane 8 on the lower surface of the lower wafer 5 is connected to the metal ground plane 8 on the lower surface of the lower wafer through the via 9 in the lower wafer 5;
  • the via holes in the upper wafer 4 and the lower wafer 5 provide the bonding area to enhance the wafer-level bonding effect, and realize the electrical interconnection between the two wafers.
  • the piezoelectric acoustic wave filter proposed in this embodiment realizes the minimization of grounding inductances G1 and G2, and its inductance can reach 0.05nH or even close to 0nH.
  • the reduction of grounding inductance makes it possible to form an out-of-band suppressed transmission zero point toward high frequency. Moving, when the transmission zero point moves to double frequency or even triple frequency, the out-of-band suppression and isolation characteristics of the corresponding position can be improved.
  • Fig. 7 is a structural diagram of a piezoelectric acoustic wave filter of the second embodiment.
  • the piezoelectric acoustic wave filter mainly includes a carrier board 1 and an upper wafer 4, a lower wafer 5, a first metal shielding layer 13, and a sealing ring 7 located on the carrier board 1.
  • the main difference between this embodiment and the first embodiment is that the metal shielding layer 13 is located on the lower surface of the upper wafer 4.
  • the upper surface of the lower wafer 5 is provided with a metal pattern (not shown in the figure) connected to the sealing ring 7.
  • the resonator in the filter that needs to be grounded is connected to the sealing ring 7 through the metal pattern to form an equipotential body with the same potential.
  • the equipotential body is connected to the first metal shielding layer 13 on the lower surface of the upper wafer 4 through the bonding area.
  • Two parallel vias 9 are used to connect the equipotential body and the metal ground plane 8 in parallel to shorten the geometric length of the grounded conductor, thereby reducing the common ground inductance, and then reducing the equipotential body and the metal ground plane. The potential difference between.
  • the multiple vias 9 in the upper wafer 4 and the lower wafer 5 provide the bonding area to enhance the wafer-level bonding effect, and realize the connection between the two wafers. Electrical interconnection.
  • multiple vias are connected in parallel, so that the inductance is much reduced compared to the prior art.
  • Fig. 8 is a structural diagram of the third piezoelectric acoustic wave filter of this embodiment.
  • the piezoelectric acoustic wave filter mainly includes a carrier board 1 and an upper wafer 4, a lower wafer 5, a first metal shielding layer 13, a second metal shielding layer 14 and a sealing ring located on the carrier board 1. 7.
  • the main difference from the foregoing embodiment is that in this embodiment, both the upper and lower surfaces of the upper wafer 4 are provided with metal shielding layers.
  • the other structure is similar to the foregoing embodiment.
  • Figures 9a and 9b are the loss comparison of the piezoelectric acoustic wave filter (solid line) proposed in the first embodiment and the existing piezoelectric acoustic wave filter (dashed line).
  • the center frequency of the filter is 6GHz
  • Figure 9a is the filter Near the stopband amplitude-frequency response curve
  • the arrow on the left side of the filter shows the effect of shifting the transmission zero on the left side of the passband to the high-frequency position after changing the bonding wire grounding to the filter structure proposed in the first embodiment.
  • Figure 9b is a graph of the amplitude-frequency response of the filter's far stop band.
  • the arrow on the right side of the filter shows the effect of shifting the transmission zero on the right side of the passband to the high-frequency position after changing the bonding wire grounding to the filter structure proposed in the first embodiment.
  • the far-band out-of-band suppression of the filter on the high frequency side is improved.
  • the out-of-band rejection is increased from the original -14dB to -46dB. Due to the existence of the isolation structure shown in the filter proposed in this embodiment, the main circuit of the filter is located inside the grounded shielding structure, which avoids the influence of external interference on it, and the performance in all aspects is greatly improved.
  • the embodiments of the present invention have been exemplified above in conjunction with several examples.
  • the details of the implementation of the present invention are not limited to the above-mentioned manners.
  • some of the resonators that need to be grounded in the filter can be directly connected to a metal ground plane without connecting to the sealing ring.
  • the resonator in the filter such as the thin film bulk acoustic wave resonator FBAR, is fabricated on the upper surface of the lower wafer, so the distance between the metal shielding layer 13 and the resonator FBAR is the upper wafer and the lower wafer The distance between them is about 2um ⁇ 20um.

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Abstract

一种压电声波滤波器，包括载板（1）和位于载板（1）上且由上至下依次设置的上晶圆（4）和下晶圆（5），在所述上晶圆（4）的上表面以及/或者下表面，设置有金属屏蔽层（13，14），该金属屏蔽层（13，14）接地。该压电声波滤波器具有更好地接地效果和良好的接地屏蔽特性。

Description

一种体声波滤波器和多工器以及电子设备 技术领域
本发明涉及通信用滤波类器件技术领域，特别地涉及一种利用压电效应原理制作的，可用金丝键合装配的体声波滤波器。
背景技术
目前，能够满足通讯终端使用的小尺寸滤波类器件主要是压电声波滤波器，构成此类声波滤波器的谐振器主要包括：FBAR(Film Bulk Acoustic Resonator，薄膜体声波谐振器)，SMR(Solidly Mounted Resonator，固态装配谐振器)，SAW(Surface Acoustic Wave，表面声波谐振器)和基于体声波原理FBAR和SMR制造的体声波谐振器BAW。
SAW是制作在特定的压电晶体上的压电器件，与通常的半导体硅工艺并不兼容，因此SAW大多采取倒装CSP(芯片级封装)的方式制作成塑封产品。
而BAW的制作工艺，是通用的硅晶圆半导体工艺，可以通过晶圆级的键合实现对内部谐振器的密封保护，因此可以通过金丝键合的方式实现微组装。但是BAW的键合微组装，存在一个不容易解决的技术问题是，首先，所有键合线都可以等效为一个0.3nH～1nH左右的电感，特别是接地的电感值决定了传输零点的位置，从而影响滤波器的远带抑制，在二倍频或三倍频的位置，抑制往往会到-20dB甚至更差。并且，键合线过多，也会容易受到外界射频干扰的影响，从而恶化带外抑制或隔离度特性。
大多数通信系统中，都会产生频率等于二倍或三倍于信号频率的干扰信号，滤波器作为重要的选频器件，其在二倍频或三倍频处的抑制就显得尤为重要。因此，如何在微组装条件下，实现BAW滤波器件的远带高抑制和高隔离度，仍是亟待解决的问题。
发明内容
为了解决现有技术存在问题，本发明提供一种体声波滤波器和多工器以及电子设备，实现更好地接地效果和良好的接地屏蔽特性。
为实现上述目的，根据本发明的一个方面，提供了一种体声波滤波器。
本发明的体声波滤波器，包括载板和位于载板上且由上至下依次设置的上晶圆和下晶圆，在所述上晶圆的上表面以及/或者下表面，设置有金属屏蔽层，该金属屏蔽层接地。通过增加上述金属屏蔽层，提高了滤波器的接地效果和屏蔽特性。
可选地，所述上晶圆的上表面的金属屏蔽层通过晶圆级键合区、和上晶圆及下晶圆的多个过孔，与所述下晶圆下表面的金属地平面连接；并且/或者，所述上晶圆的下表面的金属屏蔽层通过晶圆级键合区和下晶圆的多个过孔与所述下晶圆下表面的金属地平面连接。这样，滤波器的所有谐振器，均位于上晶圆的上述金属屏蔽层、上晶圆接地过孔、下晶圆接地过孔，以及下晶圆下表面的金属地平面构成的金属屏蔽空间内，使滤波器得到更好的电磁隔离。在采用多个过孔的情况下，构成上述的屏蔽空间的金属屏蔽层的接地电感会更小。
可选地，所述滤波器的所有谐振器位于下晶圆的上表面。
可选地，所述滤波器中部分或全部需要接地的谐振器通过晶圆级键合区以及上晶圆的多个过孔与上晶圆上表面的金属屏蔽层连接。
可选地，所述滤波器中部分或全部需要接地的谐振器通过晶圆级键合区与上晶圆下表面的金属屏蔽层连接。
可选地，所述滤波器中部分或全部需要接地的谐振器通过下晶圆的过孔与所述下晶圆的下表面的金属地平面连接。
可选地，所述需要接地的谐振器中，至少有一个谐振器连接有多个过孔。
将谐振器连接至上述金属屏蔽层，有助于降低谐振器的接地电感，使得形成带外抑制的传输零点向高频移动，当传输零点移动到二倍频，甚至三倍频的时候，就可以改善相应位置的带外抑制与隔离度特性；某谐振器通过多个过孔进行上述连接时，可进一步降低该谐振器的接地电感。
可选地，所述下晶圆的下表面的金属地平面通过导电胶粘接至所述载板的地平面从而接地。
根据本发明的另一方面，提供了一种多工器，包含本发明的体声波滤波器。
根据本发明的又一方面，提供了一种电子设备，包含本发明的体声波滤波器。
附图说明
附图用于更好地理解本发明，不构成对本发明的不当限定。其中：
图1是现有的滤波器的结构图；
图2是现有的滤波器的电路图；
图3a是现有的滤波器的幅频响应曲线随IN与G1之间互感M1变化的仿真图；
图3b是现有的滤波器的幅频响应曲线随G1与G2之间互感M2变化的仿真图；
图4是现有的滤波器的俯视状态下的组成部分的示意图；
图5和6是本发明实施例一压电声波滤波器的结构图；
图7是本发明实施例二压电声波滤波器的结构图；
图8是本发明实施例三压电声波滤波器的结构图；
图9a是滤波器临近阻带的幅频响应曲线图；
图9b是滤波器远阻带的幅频响应曲线图；
图10a和图10b是连接并联谐振器的接地电感对谐振器传输零点影响的示意图。
具体实施方式
下面结合附图与实施例对本发明作进一步说明。
图1是现有的滤波器的结构图；图2是现有的滤波器的电路图。图1中，IN为输入信号键合线，OUT为输出信号键合线，G1为第一级并联支路的接地键合线，G2为第二级并联支路的接地键合线。由于键合线具有一定长度，因此IN，OUT，G1，G2这四根键合线的长度一般为0.5mm～2mm之间，其所引入的电感量一般处于0.4nH～1.5nH之间。由于芯片尺寸较小，键合线之间的间距很近，不可避免的引入互感，互感量与键合线本身的电感量相关，也与键合线之间的距离相关，一般为3pH～20pH之间，距离越近，互感越大，距离越远，互感越小。因输入与输出之间一般为距离最远，且位于芯片的两侧，处于同一方向，因此IN和OUT之间的互感最小，可以忽略不计。这里只分析IN和G1之间的互感M1、G1和G2之间的互感M2、G2和OUT之间互感M3对滤波器性能的影响。因从电路角度看，滤波器一般可以认为是两端互易的网络，因此M1和M3在电路中的作用相近，这里以M1为代表。
图3a是现有的滤波器的幅频响应曲线随IN与G1之间互感M1变化的仿真图；图3b是现有的滤波器的幅频响应曲线随G1与G2之间互感M2变化的仿真图；互感的变化量均为3pH～18pH，步进为3pH。从图3a的仿真结果可以看出，M1的变化对滤波器性能几乎没有影响，所有曲线几乎重叠在一起。从图3b的仿真结果结果看出，M2的变化对滤波器带外的传输零点有较大影响，以2.27GHz为例，当M2＝3pH时，带外抑制约为-58dB，当M2＝18pH时，带外抑制约为-44dB，即使M2＝6pH，此处的带外抑制也会急剧恶化到-53dB，恶化了5dB。
在金线键合的装配方式中，因为键合线的长度，夹角，高度，方向均会存在较大的不一致性，以键合线位于载板上的第二落点为例，目前精度较高的自动键合机台，可以实现的键合点位置偏差为+/-25um，各种因素综合导致M2变化5pH甚至是20pH都是极有可能出现的，但键合因素不可避免。
图4是现有的滤波器的俯视状态下的组成部分的示意图。如图4所示，分布在上表面有四个焊盘，左上角是IN，右上角是OUT，左下角是G1，右下角是G2。焊盘上有晶圆级键合区，该键合区内有晶圆通孔。该滤波器有3个串联谐振器，分别是S1、S2、S3，以及2个并联谐振器P1和P2。
基于现有的滤波器内部的键合线的互感方式，一般采用微组装装配时，滤波器会暴露在较为恶劣的电磁环境中，当外部存在干扰信号的时候，同样也会引起滤波器性能的恶化。
同时，滤波器带外抑制零点的位置，与接地键合线的电感量大小关系密切，通常情况下，接地的电感量越大，滤波器两侧的传输零点越靠低频方向，此时滤波器高频一侧的远带抑制随传输零点位置向低频方向移动而变差，特别是中心频率二倍频到三倍频的位置。反之，接地的电感量越小，滤波器两侧的传输零点越靠近高频方向，此时滤波器高频一侧的远带抑制随传输零点位置向高频移动而变好。
图10a和图10b是连接并联谐振器的接地电感对谐振器传输零点影响的示意图，虚线是接地电感为0.4nH时，谐振器与电感组合电路的阻抗响应，实线是接地电感为0.2nH时，谐振器与电感组合电路的阻抗响应。可以看到，电感减小一半，左侧的传输零点和右侧的传输零点均按箭头所示方向，由低频向高频移动。
大多数通信系统中，都会产生频率等于二倍或三倍于信号频率的干扰信号，滤波器作为重要的选频器件，其在二倍频或三倍频处的抑制就显得尤为重要。因此，如何在键合线装配的条件，实现该滤波器带外，特别是高频一侧远阻带的抑制和隔离度的性能，是一个需要解决的问题。
在本发明实施方式中，将需要与载板互连的键合线分为两类，一类是连接到载板上信号线键合手指的信号键合线，另一类为连接到载板的地上的地键合线。将信号线导通到位于芯片正面的垫片上。通过制作位于晶圆中的导通孔，将地线通过导通孔连接到芯片背面的金属化平面上。微组装时，芯片背面的金属化平面通过导电胶粘到封装载板的地平面上，芯片正面的信号键合垫片，通过键合线连接到位于载板的信号键合手指上。
实施例一
图5和6是本发明实施例一压电声波滤波器的结构图。其中图6示出了俯视状态下的组成部分。需说明的是图5和图6仅为组成部分以及连接关系的示意，二者示出同一压电声波滤波器的组成部分以及基本的位置和连接关系，但二者中各部分的比例和尺寸并不对应地构成器件的剖视图与俯视图。
如图5所示，该压电声波滤波器主要包括载板1和位于载板1上由上晶圆4、下晶圆5、第一金属屏蔽层13和密封环7。上晶圆4的上表面上设置有输入信号键合垫片3和输出信号键合垫片11，载板1上设置有输入信号键合手指2和输出信号键合手指12；上晶圆4的上表面的输入信号键合垫片3通过输入信号键合线IN连接到载板的输入信号键合手指2上，上晶圆4的上表面的输出信号键合垫片11通过输出信号键合线OUT连接到载板的输出信号键合手指12上，从而实现芯片与载板之间的电学互连。
如图6所示，第一金属屏蔽层13几乎铺满上晶圆4的整个上表面，只是让出了键合垫片。图6中还示出了上晶圆4和下晶圆5内的过孔，实际上在俯视状态下看不到这些过孔，图6中是为了示出它们的位置，可以看出有多个过孔并且错开设置。
请再参考图5，第一金属屏蔽层13位于上晶圆4的上表面，上晶圆4的下表面与下晶圆5的上表面之间设置有密封环7，用于将敏感电路密闭在两片晶圆之间。密封环7是晶圆级键合区的一种，其除了起到常规的晶圆级键合区(例如图中的晶圆级键合区71、72)的连接晶 圆的作用之外，还起到密封和屏蔽晶圆间空隙的作用。下晶圆5的上表面设置有连接所述密封环的金属图形，该金属图形为不规则的金属层(图中未示出)，起到电学连接的作用，滤波器中的需要接地的谐振器通过该金属图形连接在密封环7上，形成电位相同的等势体；下晶圆5的下表面设置有金属地平面8，下晶圆下表面的金属地平面8通过导电胶粘16到载板的地平面6上。
下晶圆5中设置有两个过孔9，可对称设置；所述等势体通过两个过孔9连接到下晶圆5下表面的金属地平面8，所述下晶圆下表面的金属地平面8通过导电胶16粘到载板的地平面6上。通过两个并行设置的过孔9，使得等势体与金属地平面8并行连接，从而使导电体的几何长度减小，从而有助于减小共地电感，从而也减小所述等势体与金属地平面之间的电势差。
上晶圆4中设置有两个过孔9，所述等势体通过上晶圆4中两个过孔9连接到上晶圆4上表面的第一金属屏蔽层13。第一金属屏蔽层13铺满或几乎铺满了在上晶圆4上表面上除了输入信号键合垫片3和输出信号键合垫片11以外的区域，并通过两个过孔与所述等势体相连，从而实现与下晶圆5下表面的金属地平面相连，继而实现良好的接地屏蔽特性。
上晶圆4中设置有两个对称设置的过孔9，下晶圆5中也设置有两个对称设置的第二过孔9；输入信号线通过上晶圆4中一过孔9连接到上晶圆上表面的输入信号键合垫片3；输出信号线通过上晶圆4中另一过孔9连接到上晶圆上表面的输出信号键合垫片11；接地线G1和G2分别通过下晶圆5中过孔9连接到下晶圆下表面的金属地平面8上；下晶圆5下表面的金属地平面8通过导电胶粘到载板的地平面6上。上晶圆4和下晶圆5中过孔提供了键合区加强晶圆级键合的效果，实现两片晶圆之间的电学互连。
本实施例提出的压电声波滤波器，实现了接地电感G1和G2的最小化，其感值可以达到0.05nH甚至接近于0nH，接地电感的减少，使得形成带外抑制的传输零点向高频移动，当传输零点移动到二倍频， 甚至三倍频的时候，就可以改善相应位置的带外抑制与隔离度特性。
同时，从上述结构可以看出，滤波器的所有谐振器，均位于上晶圆上表面屏蔽地平面，上晶圆接地过孔，下晶圆接地过孔，以及下晶圆下表面的金属地平面构成的金属屏蔽空间内，只有输入输出信号键合垫片与芯片内部器件连接，并通过键合线连接到外部的载板上，这就使得滤波器的内部电路被金属屏蔽空间包裹从而得到更好的电磁隔离。
实施例二
图7是本实施例二压电声波滤波器的结构图。如图7所示，该压电声波滤波器主要包括载板1和位于载板1上由上晶圆4、下晶圆5、第一金属屏蔽层13和密封环7等。本实施例与实施例1主要不同之处是金属屏蔽层13位于上晶圆4的下表面。下晶圆5的上表面设置有连接密封环7的金属图形(图中未示出)，滤波器中需要接地的谐振器通过金属图形连接在密封环7上，形成电位相同的等势体，所述等势体通过键合区连接到位于上晶圆4下表面的第一金属屏蔽层13上。
通过两个并行设置的过孔9，使得等势体与金属地平面8并行连接，以缩短接地的导电体的几何长度，从而减小共地电感，继而减少所述等势体与金属地平面之间的电势差。
如图7所示，类似于实施例一，上晶圆4和下晶圆5中的多个过孔9提供了键合区加强晶圆级键合的效果，实现两片晶圆之间的电学互连。并且通过多个过孔并联，使得电感比现有技术减少很多。
同时，从上述结构可以看出，滤波器的所有谐振器，均被上晶圆下表面屏蔽地平面、上晶圆接地过孔、下晶圆接地过孔，以及下晶圆下表面的金属地平面构成的金属屏蔽空间内，只有输入输出信号键合垫片与芯片内部器件连接，并通过键合线连接到外部的载板上，这就使得滤波器的内部电路被金属屏蔽空间包裹从而得到电磁隔离，使其不受外部信号的干扰，以达到最好的滤波器性能。
实施例三
图8是本实施例三压电声波滤波器的结构图。如图8所示，该压 电声波滤波器主要包括载板1和位于载板1上由上晶圆4、下晶圆5、第一金属屏蔽层13、第二金属屏蔽层14和密封环7。与前述实施例的主要区别是，本实施例中，上晶圆4的上下表面皆设置有金属屏蔽层。其他结构与前述实施例类似。从图8的结构可以看出，滤波器的所有谐振器，均被第一金属屏蔽层13、第二金属屏蔽层14、上晶圆接地过孔、下晶圆接地过孔，以及下晶圆下表面的金属地平面构成的金属屏蔽空间内，只有输入输出信号键合垫片与芯片内部器件连接，并通过键合线连接到外部的载板上，这就使得滤波器的内部电路被金属屏蔽空间包裹从而得到更好的电磁隔离。
图9a和图9b是实施例一提出的压电声波滤波器(实线)与现有的压电声波滤波器(虚线)的损耗对比，该滤波器的中心频率为6GHz，图9a是滤波器临近阻带的幅频响应曲线图，滤波器左侧的箭头展示出了由键合线接地改为本实施例一提出的滤波器结构后，通带左侧传输零点向高频位置移动的效果。图9b是滤波器远阻带的幅频响应曲线图。滤波器右侧的箭头展示出了由键合线接地改为本实施例一提出的滤波器结构后，通带右侧传输零点向高频位置移动的效果。
可以看到，由于传输零点向高频移动，使得滤波器在高频一侧的远带带外抑制得以改善。特别的，在二倍频12GHz处，带外抑制由原来的-14dB提高到-46dB。由于本实施例提出的滤波器所示的隔离结构的存在，使得该滤波器的主体电路位于接地屏蔽结构内部，避免了外部干扰对其的影响，各方面的性能均得到大幅提高。
以上结合若干实例对本发明的实施方式进行了举例说明。本发明在实现中的细节不限于上述各方式。例如，滤波器中可以有部分需接地的谐振器直接连接至某个金属地平面，而不必与密封环连接。另外在本发明实施方式中，滤波器中的谐振器例如薄膜体声波谐振器FBAR制作在下晶圆的上表面，这样金属屏蔽层13与谐振器FBAR之间的距离为上晶圆与下晶圆之间的距离，约为2um～20um。这是考虑到金属屏蔽层13与谐振器FBAR之间的距离过近的时候，会因为寄生电容的存 在略微改变滤波器的回波损耗特性，但是远带抑制的特性几乎不变，因此作出上述距离设置。
上述虽然结合附图对本发明的具体实施方式进行了描述，但并非对本发明保护范围的限制，所属领域技术人员应该明白，在本发明的技术方案的基础上，本领域技术人员不需要付出创造性劳动即可做出的各种修改或变形仍在本发明的保护范围以内。

Claims (10)

  1. 一种体声波滤波器，包括载板和位于载板上且由上至下依次设置的上晶圆和下晶圆，其特征在于，
    在所述上晶圆的上表面以及/或者下表面，设置有金属屏蔽层，该金属屏蔽层接地。
  2. 根据权利要求1所述的体声波滤波器，其特征在于，
    所述上晶圆的上表面的金属屏蔽层通过晶圆级键合区、和上晶圆及下晶圆的多个过孔，与所述下晶圆下表面的金属地平面连接；并且/或者，
    所述上晶圆的下表面的金属屏蔽层通过晶圆级键合区和下晶圆的多个过孔与所述下晶圆下表面的金属地平面连接。
  3. 根据权利要求1或2所述的体声波滤波器，其特征在于，所述滤波器的所有谐振器位于下晶圆的上表面。
  4. 根据权利要求3所述的体声波滤波器，其特征在于，所述滤波器中部分或全部需要接地的谐振器通过晶圆级键合区以及上晶圆的多个过孔与上晶圆上表面的金属屏蔽层连接。
  5. 根据权利要求3所述的体声波滤波器，其特征在于，所述滤波器中部分或全部需要接地的谐振器通过晶圆级键合区与上晶圆下表面的金属屏蔽层连接。
  6. 根据权利要求1所述的体声波滤波器，其特征在于，
    所述滤波器中部分或全部需要接地的谐振器通过下晶圆的过孔与所述下晶圆的下表面的金属地平面连接。
  7. 根据权利要求6所述的体声波滤波器，其特征在于，所述需要接地的谐振器中，至少有一个谐振器连接有多个过孔。
  8. 根据权利要求2所述的体声波滤波器，其特征在于，所述下晶圆的下表面的金属地平面通过导电胶粘接至所述载板的地平面从而接地。
  9. 一种多工器，其特征在于，包含权利要求1至8中任一项所述的体声波滤波器。
  10. 一种电子设备，其特征在于，包含权利要求1至8中任一项所述的体声波滤波器。
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