WO2021157419A1 - Dispositif de stockage à semi-conducteurs - Google Patents

Dispositif de stockage à semi-conducteurs Download PDF

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Publication number
WO2021157419A1
WO2021157419A1 PCT/JP2021/002578 JP2021002578W WO2021157419A1 WO 2021157419 A1 WO2021157419 A1 WO 2021157419A1 JP 2021002578 W JP2021002578 W JP 2021002578W WO 2021157419 A1 WO2021157419 A1 WO 2021157419A1
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Prior art keywords
voltage
memory
row
fuse
selection
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PCT/JP2021/002578
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English (en)
Japanese (ja)
Inventor
野田　敏史
秀男 葛西
谷口　泰弘
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株式会社フローディア
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Priority claimed from JP2020017455A external-priority patent/JP6721205B1/ja
Priority claimed from JP2020110035A external-priority patent/JP7517683B2/ja
Application filed by 株式会社フローディア filed Critical 株式会社フローディア
Publication of WO2021157419A1 publication Critical patent/WO2021157419A1/fr

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/06—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using diode elements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
    • G11C17/16—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
    • G11C17/18—Auxiliary circuits, e.g. for writing into memory

Definitions

  • the present invention relates to a semiconductor storage device.
  • An anti-fuse memory that can write data only once is known (see, for example, Patent Document 1).
  • data is written by electrically insulatingly breaking the memory gate insulating film, which is the insulating film of the memory capacitor.
  • Patent Document 1 describes a semiconductor storage device in which a plurality of anti-fuse memories including a diode-connected N-type MOS transistor (rectifying element) and a memory capacitor are arranged in a matrix.
  • the memory capacitor has a configuration in which a memory gate insulating film and a memory gate electrode, which are dielectrically broken down by the voltage difference between the word line and the bit line, are laminated on the active region.
  • a word line is provided for each row of the anti-fuse memory, and a bit line is provided for each column.
  • a bit wire is connected to a diffusion region provided at one end of an active region, and a source region of a MOS transistor is connected to a memory gate electrode. Further, in the MOS transistor, the gate electrode and the drain region are connected to each other and connected by a diode, and these gate electrodes and the drain region are connected to the word line.
  • a voltage of 0 V is applied to the bit line connected to the anti-fuse memory to write the data.
  • a voltage of 5V is applied to the word line.
  • Voltages of 3V and 0V are applied to the other bit lines and word lines, respectively.
  • the anti-fuse memory (hereinafter, non-selective anti-fuse) that does not write data connected to the same word line as the anti-fuse memory that writes data (hereinafter referred to as selective anti-fuse memory)
  • a voltage of 5 V for writing is applied from the word line to the gate electrode and the drain region of the MOS transistor, as in the selective anti-fuse memory.
  • the MOS transistor is turned on and a voltage of 5 V is applied to the memory gate electrode of the memory capacitor.
  • a voltage of 3 V is applied to the bit wire connected to the non-selective anti-fuse memory so that the memory gate insulating film is not dielectrically broken, but a voltage difference of about 2 V is applied between the memory gate electrode and the diffusion region. Occurs.
  • the memory gate insulating film of the non-selective anti-fuse memory is already dielectrically broken, there is a problem that a leak current flows from the word line to the bit line through the non-selective anti-fuse memory.
  • the present invention has been made in view of the above circumstances, and an object of the present invention is to provide a semiconductor storage device capable of suppressing a leakage current at the time of writing data.
  • the semiconductor storage device of the present invention has an active region, a memory gate insulating film formed on the active region, a memory gate electrode formed on the memory gate insulating film, and a diffusion region formed in the active region.
  • a memory array in which a plurality of anti-fuse memories having a memory capacitor, a gate electrode, a source region, and a drain region, and a MOS transistor having the source region connected to the memory gate electrode are arranged in a matrix, and the above.
  • Each row of the plurality of anti-fuse memories is provided so as to extend in the row direction, and each is connected to the drain area in the row, and the anti-fuse memory to be written among the plurality of anti-fuse memories is connected.
  • the first selection column voltage which is the voltage that turns on the MOS transistor, is connected to one word line that is provided, is connected to the gate electrode in the row, and is connected to the anti-fuse memory to be written.
  • a plurality of applied word lines and each row of the plurality of anti-fuse memories are provided so as to extend in the column direction and are connected to the diffusion area in the row, respectively, and the anti-fuse memory to be written is to be written.
  • the well voltage is higher than the well voltage applied to the well in which the active region is formed, and if the MOS transistor is P-type, the well is connected to one source line.
  • a first-selection source-line voltage equal to or lower than the voltage is applied, and is an intermediate voltage between the first-selection source-line voltage and the first-selection line voltage to the source line to which the anti-fuse memory to be written is not connected.
  • First non-selective source line A plurality of source lines to which a voltage is applied are provided.
  • the semiconductor storage device of the present invention has an active region, a memory gate insulating film formed on the active region, a memory gate electrode formed on the memory gate insulating film, and a diffusion region formed in the active region.
  • a memory array in which a plurality of anti-fuse memories having a memory capacitor, a gate electrode, a source region, and a drain region, and a MOS transistor having the source region connected to the memory gate electrode are arranged in a matrix, and the above.
  • Each row of the plurality of anti-fuse memories is provided so as to extend in the row direction, and each is connected to the drain area in the row, and the anti-fuse memory to be written among the plurality of anti-fuse memories is connected.
  • the first selection column voltage which is the voltage that turns on the MOS transistor, is connected to one word line that is provided, is connected to the gate electrode in the row, and is connected to the anti-fuse memory to be written.
  • a plurality of applied word lines and each row of the plurality of anti-fuse memories are provided so as to extend in the column direction and are connected to the diffusion area in the row, respectively, and the anti-fuse memory to be written is to be written.
  • the well voltage is equal to or higher than the well voltage applied to the well in which the active region is formed, and when the MOS transistor is P-type, the well is connected to one source line.
  • a first-select source line voltage equal to or lower than the voltage is applied, and the source line to which the anti-fuse memory to be written is not connected is provided with a plurality of source lines in which the source line is in a floating state.
  • the semiconductor storage device of the present invention has an active region, a memory gate insulating film formed on the active region, a memory gate electrode formed on the memory gate insulating film, and a diffusion region formed in the active region.
  • a memory array in which a plurality of anti-fuse memories having a memory capacitor, a gate electrode, a source region, and a drain region, and a MOS transistor having the source region connected to the memory gate electrode are arranged in a matrix, and the above.
  • the memory gate insulating film is insulated to one bit wire to which a plurality of connected source wires and an anti-fuse memory to be written among the plurality of anti-fuse memories among the plurality of bit wires are connected.
  • the MOS transistor is turned on to one word line to which the bit line driver that applies the first selection line voltage, which is the voltage to be destroyed, and the anti-fuse memory to be written are connected among the plurality of word lines.
  • the MOS transistor is N-type to one source line to which the word line driver that applies the first selection column voltage, which is the voltage to be applied, and the anti-fuse memory to be written are connected among the plurality of source lines.
  • a first-choice source line voltage equal to or higher than the well voltage applied to the well in which the active region is formed and lower than or equal to the well voltage when the MOS transistor is P-type is applied, and the writing target is described.
  • a source line driver that applies a first non-selection source line voltage, which is an intermediate voltage between the first selection source line voltage and the first selection line voltage, to a source line to which an anti-fuse memory is not connected. Is.
  • the semiconductor storage device of the present invention has an active region, a memory gate insulating film formed on the active region, a memory gate electrode formed on the memory gate insulating film, and a diffusion region formed in the active region.
  • a memory array in which a plurality of anti-fuse memories having a memory capacitor, a gate electrode, a source region, and a drain region, and a MOS transistor having the source region connected to the memory gate electrode are arranged in a matrix, and the above.
  • a plurality of bit wires connected to the drain area in each row and a plurality of bit lines extending in the row direction are provided for each row of the plurality of anti-fuse memories, and each row of the plurality of anti-fuse memories extends in the column direction.
  • a plurality of word lines connected to the gate electrode in the row and each row of the plurality of anti-fuse memories extending in the row direction are provided in the diffusion region in the row.
  • the memory gate insulating film is insulated to one bit wire to which a plurality of connected source wires and an anti-fuse memory to be written among the plurality of anti-fuse memories among the plurality of bit wires are connected.
  • the MOS transistor is turned on to one word line to which the bit line driver that applies the first selection line voltage, which is the voltage to be destroyed, and the anti-fuse memory to be written are connected among the plurality of word lines.
  • the MOS transistor is N-type to one source line to which the word line driver for applying the first selection column voltage, which is the voltage to be used, and the anti-fuse memory to be written are connected among the plurality of source lines.
  • a first-choice source line voltage equal to or higher than the well voltage applied to the well in which the active region is formed and lower than or lower than the well voltage when the MOS transistor is P-type is applied, and the writing target is described. It includes a source line driver that floats the source line to which the anti-fuse memory is not connected.
  • the first-select source line voltage applied to the source line to which the anti-fuse memory to be written is connected to the source line to which the anti-fuse memory to be written is not connected, and the anti-fuse to be written.
  • the first non-selective source line voltage which is an intermediate voltage between the first selected line voltage applied to the bit line to which the memory is connected, is applied, or the source line to which the anti-fuse memory to be written is not connected is not connected is not connected. Since it is in a floating state, the leakage current of the anti-fuse memory can be suppressed.
  • the semiconductor storage device 1 includes a memory array CA, a bit line BL, a word line WL, and a source line SL.
  • a plurality of anti-fuse memories (memory cells) M are arranged in a matrix in the memory array CA.
  • the bit line BL is provided corresponding to each row of the anti-fuse memory M
  • the word line WL and the source line SL are provided corresponding to each column of the anti-fuse memory M. That is, one bit line BL is shared by the anti-fuse memory M arranged in the row direction, and one word line WL and one source line SL are shared by the anti-fuse memory M arranged in the column direction. ..
  • anti-fuse memory Mij when distinguishing individual anti-fuse memories M, i and j will be referred to as 1, 2, 3 ..., And those in column i, row j will be described as anti-fuse memory Mij. Further, when the word line WL and the source line SL are distinguished into those in a specific column, those in the i-th column will be described as the word line WLi and the source line SLi. Similarly, when distinguishing the bit line BL into those of a specific line, the one of the jth line will be described as the bit line BLj.
  • the former is referred to as a selected anti-fuse memory M and the latter is referred to as a non-selective anti-fuse memory M. I will explain.
  • the anti-fuse memory M has the same configuration, and has a memory capacitor 10 and a MOS transistor 20, respectively.
  • Each word line WL and each source line SL are connected to each anti-fuse memory M in the corresponding column.
  • Each bit line BL is connected to each anti-fuse memory M in the corresponding row. Therefore, the anti-fuse memory Mij in the i-th column and the j-th row is connected to the word line WLi, the source line SLi, and the bit line BLj, respectively.
  • the bit line BL extends in the row direction
  • the word line WL and the source line SL extend in the column direction and are orthogonal to each other.
  • the semiconductor storage device 1 includes a column selection circuit 25, a row selection circuit 26, and a sense amplifier 27.
  • the bit line BL is connected to the row selection circuit 26 and the sense amplifier 27, respectively, and the word line WL and the source line SL are connected to the column selection circuit 25, respectively.
  • the gate electrode 20a of the MOS transistor 20 is connected to the word line WL
  • the source area 20b is connected to the memory gate electrode 10a of the memory capacitor 10
  • the drain area 20c is connected to the bit line BL.
  • the diffusion region 10b of the memory capacitor 10 is connected to the source line SL.
  • the memory capacitor 10 has a memory gate electrode 10a, a diffusion region 10b, and a memory gate insulating film 10c (see FIG. 3), and 1-bit data is non-volatile depending on the presence or absence of dielectric breakdown of the memory gate insulating film 10c. Hold. That is, the memory capacitor 10 has an insulating state in which the memory gate insulating film 10c is not dielectrically broken down and the memory gate electrode 10a and the diffusion region 10b are electrically insulated, and the memory gate insulating film 10c is dielectric breakdown. The short-circuited state in which the memory gate electrode 10a and the diffusion region 10b are electrically short-circuited corresponds to "0" and "1" of the 1-bit data.
  • the dielectric breakdown of the memory gate insulating film 10c to bring it into a short-circuit state is referred to as writing data of the anti-fuse memory M.
  • data reading means detecting whether the memory capacitor 10 is in an insulated state or a short-circuited state.
  • the column selection circuit 25 applies a voltage to the word line WL and the source line SL, and the row selection circuit 26 applies a voltage to the bit line BL.
  • the voltage applied to the word line WL includes a first selection column voltage and a first non-selection column voltage at the time of writing, and a second selection column voltage and a second non-selection column voltage at the time of reading.
  • the voltage applied to the source line SL includes a first source line voltage at the time of writing and a second source line voltage at the time of reading.
  • the voltage applied to the bit line BL includes a first selective line voltage and a first non-selective line voltage at the time of writing, and a second selective line voltage and a second non-selective line voltage at the time of reading.
  • the column selection circuit 25 receives various voltages from the power supply unit PS at the time of writing, and selects the first selection column voltage and the first non-selection column voltage with respect to the word line WL.
  • the line selection circuit 26 has a word line driver 25a for applying the voltage and a source line driver 25b for applying the first source line voltage to the source line SL, and the line selection circuit 26 supplies various voltages from the power supply unit PS at the time of writing. It has a bit line driver 26a that receives and selectively applies a first selective line voltage and a first non-selective line voltage to the bit line BL.
  • the first selective row voltage is 5V
  • the first selective column voltage is 6V
  • these three types of voltages are used. Is supplied as a writing voltage from the power supply unit PS to the word line driver 25a, the source line driver 25b, and the bit line driver 26a. Further, at the time of writing, 0V from the power supply unit PS is supplied to the well S2 (see FIG. 3) through the well voltage application unit 28, and the voltage of the well S2 is set to 0V. Details of these voltages will be described later.
  • the power supply unit PS described above has, for example, a plurality of voltage generation circuits that generate a voltage for writing, and outputs the voltage generated by each of these voltage generation circuits. In this example, it has three voltage generation circuits that generate 0V, 5V, and 6V. These voltage generation circuits may be provided for each required writing voltage. Further, in reality, the voltage to be applied to the word line WL, the source line SL, the bit line BL and the well S2 at the time of reading, and the column selection circuit 25 itself, the row selection circuit 26, and the well voltage application unit 28 itself, respectively. The driving voltage for driving is supplied from the power supply unit PS to the column selection circuit 25, the row selection circuit 26, and the well voltage application unit 28, but these are not shown in FIG.
  • a precharge method is used to read the data.
  • the sense amplifier 27 acquires 1-bit data written in the anti-fuse memory M based on the change in the potential of the bit line BL precharged to the second selection line voltage. For example, the sense amplifier 27 detects whether or not the potential of the bit line BL drops below a predetermined threshold potential within a certain period of time.
  • the precharge method is used for reading the data, but the method for reading the data is not particularly limited.
  • FIG. 3 shows an example of the cross-sectional structure of the anti-fuse memory M.
  • the anti-fuse memories M adjacent to each other in the row direction are arranged line-symmetrically with respect to the column direction. Therefore, the anti-fuse memory M has an arrangement shown in FIG. 3 and a line-symmetrical arrangement thereof.
  • the anti-fuse memory M is formed in a P-shaped well S2 on the semiconductor substrate S1.
  • the P-shaped well S2 is provided with a first active region 31 and a second active region 32 separated in the row direction by an element separation membrane IL formed of an insulating material.
  • a memory capacitor 10 is formed in the first active region 31.
  • a diffusion region 10b in which an N-type dopant is heavily doped is formed at a predetermined interval from the device separation membrane IL.
  • the diffusion region 10b acts as a source line SL.
  • a memory gate insulating film 10c is formed on the first active region 31 between the element separation membrane IL and the diffusion region 10b.
  • a memory gate electrode 10a is provided across the upper surfaces of the memory gate insulating film 10c and the element separation membrane IL.
  • a sidewall SW1 made of an insulating material is provided on both side walls of the memory gate electrode 10a.
  • a MOS transistor 20 is formed in the second active region 32.
  • a source region 20b in which an N-type dopant is heavily doped is formed so as to be adjacent to the device separation membrane IL.
  • a drain region 20c in which a high concentration of N-type dopant is doped is formed at a predetermined interval from the source region 20b.
  • a gate insulating film 20d is formed on the second active region 32 between the source region 20b and the drain region 20c, and the gate electrode 20a is formed on the gate insulating film 20d. As will be described later, the gate electrode 20a acts as a word line WL.
  • Gate insulating film 20d is determined according to the voltage of the first selection column so as not to cause dielectric breakdown when writing data, and is larger than that of the memory gate insulating film 10c.
  • a contact C1 is provided straddling the source region 20b of the MOS transistor 20 and the memory gate electrode 10a of the memory capacitor 10.
  • the contact C1 connects the memory gate electrode 10a of the memory capacitor 10 and the source region 20b of the MOS transistor 20.
  • contacts may be provided on the memory gate electrode 10a and the source region 20b, and the respective contacts may be connected by wiring.
  • a contact C2 is provided in the drain region 20c, and the contact C2 is connected to a bit wire BL composed of metal wiring provided in a metal wiring layer above the gate electrode 20a.
  • the contact C2 is composed of a contact C2a formed in the same layer as the contact C1 and a contact C2b formed on the upper portion of the contact C2a.
  • the contact C2 may be formed by one contact.
  • the bit line BL extends in the row direction.
  • the memory gate electrode 10a, the gate electrode 20a, the contact C1, the contact C2, and the bit wire BL are covered with an interlayer insulating film.
  • the memory gate electrode 10a of the memory capacitor 10 and the gate electrode 20a of the MOS transistor 20 are wirings of the same wiring layer (same layer) formed in the same process.
  • FIG. 4 shows an example of the plane layout of the anti-fuse memory M.
  • a plurality of anti-fuse memories M are arranged in a matrix to form a memory array CA.
  • the arrangement of each element of the anti-fuse memory M adjacent in the row direction is axisymmetric with respect to the column direction as described above. Further, the arrangement of each element of the anti-fuse memory M in each line is the same.
  • a plurality of first active regions 31 extending in the row direction are formed in the well S2.
  • the first active region 31 is doped with an N-type dopant at a high concentration to form a source line SL.
  • a contact C3 is formed on the first active region 31 at the end of the memory array, and the source line SL is connected to the column selection circuit 25 via the contact C3, metal wiring (not shown), etc., and the first source line voltage, the first Two source line voltages are given.
  • the source line SL extends in the column direction and is shared by the anti-fuse memory M adjacent in the row direction.
  • a plurality of rectangular second active regions 32 long in the row direction are arranged in the column direction at predetermined intervals in the wells S2 between the first active regions 31 adjacent to each other.
  • the second active region 32 is integrated with that of the anti-fuse memory M adjacent in the row direction.
  • the memory gate electrode 10a of the memory capacitor 10 is formed in a rectangular shape long in the row direction, and one end thereof extends into the first active region 31. The other end is between the first active region 31 and the second active region 32, but may extend into the second active region 32.
  • the contact C1 is formed across the memory gate electrode 10a and the second active region 32, and the memory gate electrode 10a and the source region 20b of the MOS transistor 20 provided in the second active region 32 are electrically connected. ..
  • one end of the memory gate electrode 10a extends to the first active region 31, and the gate edge on the one end side is arranged on the first active region 31.
  • the gate edge has a shape in which itself or its corners are curved or bent. Therefore, when the first selective row voltage is applied to the memory gate electrode 10a, the electric field at the gate edge on one end side of the memory gate electrode 10a becomes strong, which promotes dielectric breakdown of the memory gate insulating film 10c. Therefore, such an arrangement can lower the first selective row voltage.
  • the memory capacitor is a transistor type capacitor, since the memory gate electrode crosses the active region, only the straight portion of the memory gate electrode is arranged on the active region, and a curved or bent gate edge exists. do not.
  • the gate edge is arranged on the first active region 31 and does not cross the first active region 31.
  • the anti-fuse memory M The cell size becomes smaller.
  • the diffusion region of one memory capacitor 10 can be set as one diffusion region 10b, and the source line. Only one contact for supplying power to the diffusion region 10b acting as SL may be provided, the number of contacts per cell can be reduced, and the cell size of the anti-fuse memory M can be reduced.
  • a word line WL As wiring shared by the anti-fuse memory M arranged in the row direction, a word line WL extending in the row direction is provided for each row. Each word line WL is arranged so as to traverse the second active region 32 in the column direction. The portion of the word line WL on the second active region 32 becomes the gate electrode 20a of the MOS transistor 20.
  • a contact C4 is formed on the word line WL at the end of the memory array, and the word line WL is connected to the column selection circuit 25 via the contact C4, metal wiring (not shown), etc., and has a first selection column voltage and a first non-selection voltage. A selective column voltage, a second selective column voltage, and a second non-selective column voltage are given.
  • Contact C2 is formed in the center of the second active region 32 in the row direction.
  • the contact C2 is shared by the anti-fuse memory M adjacent in the row direction.
  • Bit lines BL are provided for each row as wiring shared by the anti-fuse memory M arranged in the row direction.
  • Each bit line BL extends in the row direction and is orthogonal to the word line WL and the source line SL.
  • the bit line BL is connected to the drain region 20c of the MOS transistor 20 provided in the second active region 32 by the contact C2.
  • the bit line BL is connected to the row selection circuit 26 and is given a first selective row voltage, a first non-selective row voltage, a second selective row voltage, and a second non-selective row voltage.
  • the first selection column voltage is applied to the word line WL which is the selection word line connected to the selection anti-fuse memory M.
  • the first non-selective column voltage is applied to the word line WL which is the other non-selective word line.
  • the first selection line voltage is applied to the bit line BL which is the selection bit line connected to the selective anti-fuse memory M
  • the first non-selection line voltage is applied to the bit line BL which is the other non-selection bit line. do.
  • the first source line voltage is applied to both the source line SL which is the selected source line and the source line SL which is the other non-selected source line connected to the selective anti-fuse memory M.
  • the first selection column voltage is a gate voltage that can turn on the MOS transistor 20 to which the first selection row voltage is applied as the drain voltage, and is set to be equal to or higher than the threshold voltage of the MOS transistor 20.
  • the first non-selective column voltage is a gate voltage that turns off the MOS transistor 20.
  • the first selective row voltage and the first non-selective row voltage are applied as the drain voltage of the MOS transistor 20.
  • the first selective row voltage insulates and breaks down the memory gate insulating film 10c between the memory gate electrode 10a to which this voltage is applied via the MOS transistor 20 and the diffusion region 10b to which the first source line voltage is applied. It is set as a voltage that causes a voltage difference.
  • the first selection line voltage is set higher than the first source line voltage.
  • the first non-selective line voltage is used to prevent dielectric breakdown of the memory gate insulating film 10c and prevent leakage current from flowing from the bit line BL to the source line SL via the non-selective anti-fuse memory M. It is set to the same as the source line voltage.
  • the first selection row voltage is 5V and the first selection column voltage is 6V.
  • the first non-selective column voltage, the first non-selective row voltage, and the first source line voltage are 0 V, which is the same as the well voltage (potential).
  • the first selective column voltage from the word line WL is applied to the gate electrode 20a, and the first selective row voltage from the bit line BL is applied to the drain region 20c.
  • the MOS transistor 20 is turned on, and the first selective line voltage of the bit line BL is applied to the memory gate electrode 10a via the MOS transistor 20.
  • the first source line voltage is applied from the source line SL to the diffusion region 10b of the memory capacitor 10.
  • Word lines WL1 to 6V are applied to the gate electrode 20a of the MOS transistor 20 of the anti-fuse memory M11, and bit lines BL1 to 5V are applied to the drain region 20c.
  • the MOS transistor 20 is turned on, and 5V applied to the drain region 20c is applied to the memory gate electrode 10a via the source region 20b of the MOS transistor 20.
  • the memory gate insulating film 10c is dielectrically broken down between the memory gate electrode 10a and the channel formed in the first active region 31 directly below the memory gate electrode 10a as described above. A voltage difference of 5V occurs.
  • the memory gate insulating film 10c is dielectrically broken down, the memory capacitor 10 is short-circuited, and data is written to the anti-fuse memory M11.
  • the first non-selective column voltage is applied from the word line WL to the gate electrode 20a to turn off the MOS transistor 20, or the bit line BL shifts to the drain region 20c of the MOS transistor 20. Either or both of the first non-selective column voltages are applied.
  • the voltage from the bit line BL is not applied to the memory gate electrode 10a via the MOS transistor 20, and in the latter case, the voltage is applied to the memory gate electrode 10a via the MOS transistor 20.
  • the non-selective line voltage becomes the same as the first source line voltage applied from the source line SL to the diffusion region 10b. Therefore, in any case, in the non-selective anti-fuse memory M, there is no voltage difference between the memory gate electrode 10a and the first active region 31 immediately below the memory gate electrode 10a in which the memory gate insulating film 10c is dielectrically broken down. , The memory gate insulating film 10c remains in an insulated state without dielectric breakdown, and a state in which no data is written is maintained. Further, the leakage current from the bit line BL to the source line SL is prevented from flowing through the non-selective anti-fuse memory M.
  • non-selective anti-fuse memory M in the same row as selected anti-fuse memory M (B) non-selective anti-fuse memory M in the same column as selected anti-fuse memory M, and (C) selected anti-fuse memory M.
  • a row and column non-selective anti-fuse memory M will be described.
  • the memory capacitor 10 may be in a short-circuited state.
  • a conventional semiconductor storage device composed of a conventional anti-fuse memory in which a gate electrode of a MOS transistor and a drain region are connected, a non-selective anti in the same row as a selective anti-fuse memory sharing a word line. Since the MOS transistor of the fuse memory is turned on, there is a problem that a leak current flows from the word line to the bit line through the memory capacitor in the short-circuit state. Even in this semiconductor storage device 1, when the MOS transistors 20 of the anti-fuse memories M21, M31 ...
  • bit lines BL1 are transferred to the source lines SL2, SL3 ... Through the MOS transistors 20 and the memory capacitor 10. Leakage current will flow. However, in this semiconductor storage device 1, a voltage can be applied independently to the bit line BL and the word line WL, and the first non-selection is made to the gate electrode 20a of the MOS transistor 20 of the antifuse memories M21, M31 ... Since the column voltage is applied to turn it off, such a leak current does not occur.
  • the range of destruction of the memory capacitor 10 is well. It may extend to the inside of S2.
  • the well in addition to the normal leakage current path that flows to the source line SL via the memory gate electrode 10a, the memory gate insulating film 10c, and the surface of the well S2, the well is passed through the memory gate insulating film 10c from the memory gate electrode 10a.
  • a leak path flowing through S2 is formed. The leak current flowing through the source line SL can be stopped by adjusting the voltage of the source line SL, but the leak current flowing through the well S2 cannot be stopped because the well potential needs to be set to 0V.
  • the MOS transistor of the non-selective anti-fuse memory in the same row as the selected anti-fuse memory is turned on. Therefore, if there is a leak path flowing through the well, the memory capacitor in the short-circuited state The problem arises that a leak current flows from the ward line through the well to the well. For this reason, in the conventional semiconductor storage device, precise adjustment and control of the applied voltage for data writing and the like are indispensable so as to avoid excessive breakdown in the memory capacitor and to perform appropriate dielectric breakdown.
  • a voltage can be applied independently to the bit line BL and the word line WL, and the voltage is applied to the gate electrode 20a of the MOS transistor 20 of the antifuse memories M21, M31 ... 1 Since the non-selective row voltage is applied to turn off the state, even if there is a leak path flowing through the well S2, no leak current flows through the leak path. This means that the formation of a leak path to the well S2 is allowed when writing data, and data writing conditions such as the first selection column voltage and the first selection row voltage can be easily determined. At the same time, it is advantageous for reliable dielectric breakdown.
  • the leakage current to the source lines SL2, SL3 ... Through a part or all of the anti-fuse memories M21, M31 ... Is suppressed by the MOS transistor 20 in the off state as described above, the source. It is not necessary to suppress the leakage current by setting the voltage set to the lines SL2, SL3, ... To higher than 0V. Therefore, the potential of the diffusion region 10b of the anti-fuse memory M22, M32 ..., M23, M33 ..., Which is the non-selective anti-fuse memory M connected to the source lines SL2, SL3 ... Therefore, it is possible to prevent erroneous writing from being made to other anti-fuse memories M22, M32 ..., M23, M33 ..., etc. connected to the source lines SL2, SL3 ...
  • a row and column non-selective anti-fuse memory M different from the selected anti-fuse memory M that is, an anti-fuse in which all of the connected bit line BL, word line WL, and source line SL are different from the anti-fuse memory M11.
  • the second source line voltage is set for each source line SL.
  • the second selection line voltage is applied to the bit line BL to which the selection anti-fuse memory M is connected, and the bit line BL is pre-set to the second selection line voltage. Charge.
  • the other bit line BL is not precharged as the second non-selective line voltage.
  • the bit line BL is electrically disconnected from the row selection circuit 26. After that, the second selection column voltage is set in the word line WL to which the selection anti-fuse memory M is connected, and the second non-selection column voltage is set in the other word line WL. Then, the sense amplifier 27 detects the change in the potential of the bit line BL at this time.
  • the second selection column voltage is determined as the gate voltage that turns on the MOS transistor 20, and is set to be equal to or higher than the threshold voltage of the MOS transistor 20. In this example, the second selection column voltage is set lower than the first selection column voltage.
  • the second non-selective row voltage is the gate voltage that turns off the MOS transistor 20.
  • the second non-selective line voltage is set to the same voltage as the second source line voltage. In this example, the second selective row voltage and the second selective column voltage are 3 V, the second non-selective row voltage, the second non-selective column voltage, and the second source line voltage are 0 V, which is the same as the well voltage.
  • the MOS transistor 20 of the anti-fuse memory M11 is turned on when the word line WL1 to 3V is applied to the gate electrode 20a. As a result, the voltage of the bit line BL1 is applied to the memory gate electrode 10a via the MOS transistor 20.
  • the potential of the bit line BL1 is determined by whether or not the memory capacitor 10 of the antifuse memory M11, which is the selected antifuse memory M, is in a short-circuited state. If the memory capacitor 10 of the anti-fuse memory M11 is in a short-circuited state, the potential of the bit line BL1 drops with the lapse of time from the time when the second selection line voltage is applied.
  • the range of destruction of the memory capacitor 10 extends to the inside of the well S2, and the leakage of the current flowing from the memory gate electrode 10a through the memory gate insulating film 10c to the well S2. Pathways may be formed.
  • the potential of a bit line connected to the diffusion region of a memory capacitor is detected by a sense amplifier and read out. Specifically, when the memory capacitor is in a short-circuited state, the voltage applied to the word line is applied to the memory gate electrode of the memory capacitor through the MOS transistor (rectifying element), a current flows through the memory capacitor, and the potential of the bit line. Rise. If the memory capacitor is in an insulated state, even if the voltage applied to the word line is applied to the memory gate electrode of the memory capacitor through the MOS transistor (rectifying element), no current flows through the memory capacitor and the potential of the bit line does not change. ..
  • this semiconductor storage device 1 when the memory capacitor 10 is in a short-circuit state, there is a leakage path of a current flowing from the memory gate electrode 10a through the memory gate insulating film 10c to the well S2, and the bit line BL1 to MOS Even if the current does not flow in the source line SL1 direction through the transistor 20 and the memory capacitor 10 and the current flows in the well S2, the potential of the bit line BL1 drops. Therefore, when writing data to the selective antifuse memory M, the range of destruction of the memory capacitor 10 extends to the inside of the well S2, and a leak path of the current flowing from the memory gate electrode 10a through the memory gate insulating film 10c to the well S2 is formed. Even if this is done, it is possible to determine whether or not data is written in the anti-fuse memory M11 by detecting the change in the potential of the bit line BL1 with the sense amplifier 27.
  • the first non-selective row voltage can be set to about 3V.
  • the gate electrode 20a is formed on the surface of the gate electrode 20a to which the first selective column voltage is applied from the word line WL and the second active region 32 directly below the gate electrode 20a, and is formed from the bit line BL through the drain region 20c.
  • the voltage difference from the channel to which the selected row voltage (intermediate voltage) is applied can be made smaller than in the above example. Therefore, the thickness of the gate insulating film 20d can be reduced, and for example, the memory gate insulating film 10c and the gate insulating film 20d can be made the same thickness.
  • the intermediate voltage is set so that the voltage difference from the well voltage is lower than the voltage that breaks down the memory gate insulating film 10c. ..
  • 0 V is set as the first source line voltage for each source line SL, but the voltage of each source line SL not connected to the selected anti-fuse memory M is , Not limited to this.
  • the voltage of each source line SL not connected to the selective anti-fuse memory M may be an intermediate voltage higher than 0V and lower than the first selection line voltage.
  • the voltage of the first selection line can be set to 5V, and the voltage of each source line SL not connected to the selection antifuse memory M can be set to, for example, about 3V.
  • the off characteristic of the MOS transistor 20 is insufficient and a part of the first selection line voltage of the bit line BL is applied to the memory gate electrode 10a of the memory capacitor 10, the off characteristic is not affected. Since the voltage difference between the memory gate electrode 10a and the source line SL becomes small, the leakage current flowing through the short-circuited memory capacitor 10 can be reduced.
  • the first active region 31 extending in the column direction may be formed for each column, and each may be the source line SL. Needless to say.
  • the first non-selected column voltage is set to a voltage higher than 0 V and lower than the first selected column voltage. Then, the first non-voltage drop occurs in the MOS transistor 20 so that the voltage applied to the memory gate electrode 10a from the bit line BL to which the first selection column voltage is applied passes through the MOS transistor 20 is equal to or less than the intermediate voltage.
  • the selected column voltage may be set.
  • the first selective column voltage can be set to 6 V
  • the first selective row voltage can be set to 5 V
  • the intermediate voltage can be set to 3 V
  • the first non-selected column voltage can be set to, for example, 3 V or less.
  • the MOS transistor 20 of the non-selective anti-fuse memory M in the same row as the selective anti-fuse memory M is turned on as in the conventional semiconductor storage device, but the voltage and source applied to the memory gate electrode 10a. Since the voltage difference from the intermediate voltage of the wire SL is small, the leakage current in the non-selective anti-fuse memory M connected to the same bit wire BL as the selective anti-fuse memory M can be suppressed.
  • the second selection column voltage and the second selection row voltage are the same, but the voltage is not limited to this and may be different.
  • the second selection column voltage may be higher than the second selection row voltage, and the second selection row voltage can be set to 3V and the second selection column voltage can be set to 5V.
  • the diffusion region 10b of the memory capacitor 10 may be configured to have the same potential as the well S2.
  • a diffusion region in which a P-type dopant is heavily doped may be formed.
  • the diffusion region may not be formed in the first active region 31.
  • the memory gate insulating film 10c When writing data with such a configuration, the memory gate insulating film 10c is destroyed by the voltage difference between the memory gate electrode 10a and the first active region 31 (well S2), and when reading data, it is insulated from the memory gate electrode 10a. A current from the bit line BL1 is passed through the first active region 31 through the destroyed memory gate insulating film 10c. According to such a semiconductor storage device 1A, the source line SL can be abolished and the circuit scale can be reduced.
  • an N-type memory capacitor in which a memory gate insulating film and a memory gate electrode are laminated on a P-type well (first active region) and a gate insulating film on a P-type well (second active region).
  • the anti-fuse memory is composed of an N-type MOS transistor in which a gate electrode is laminated, but the present invention is not limited to this, and the anti-fuse memory is composed of a P-type memory capacitor and a P-type MOS transistor. You may.
  • the P-type memory capacitor the memory gate insulating film and the memory gate electrode are laminated on the first active region provided in the N-type well, and the P-type dopant is high-concentrated doped in the first active region.
  • the configuration may be such that a diffusion region is formed. Similar to the above example, the diffusion region of this P-type memory capacitor does not form a diffusion region even if it is configured by high-concentration doping of the P-type dopant and high-concentration doping of the N-type dopant. It may be configured.
  • the P-type MOS transistor may have a gate insulating film and a gate electrode laminated on an N-type well to form a drain region and a source region in which a P-type dopant is highly concentrated.
  • the voltage applied to the non-selected source line when writing data is an intermediate voltage between the voltage applied to the selected source line and the voltage applied to the selected bit line. be.
  • the semiconductor storage device of the second embodiment is the same as that of the first embodiment except that the details will be described below. In the following description, substantially the same components as those in the first embodiment are designated by the same reference numerals, and detailed description thereof will be omitted.
  • the anti-fuse memory is composed of an N-type memory capacitor and an N-type MOS transistor will be described.
  • the power supply unit PS is used for writing to the word line driver 25a of the column selection circuit 25, the source line driver 25b, the bit line driver 26a of the row selection circuit 26, and the well voltage application unit 28.
  • Supply voltage A first selective column voltage (V SWL ) and a first non-selective column voltage (V UWL ) are supplied to the word line driver 25a.
  • the source line driver 25b is supplied with the first selection source line voltage (V SSL ) and the first non-selection source line voltage ( VUSL).
  • the first selection source line voltage is the voltage applied to the source line SL connected to the selection antifuse memory M, that is, the selection source line when writing data, and the first non-selection source line voltage is the selection antifuse memory. This is the voltage applied to the source line SL not connected to M, that is, the non-selected source line.
  • a first selective row voltage (V SBL ) and a first non-selective row voltage (V UBL ) are supplied to the bit line driver 26a. Further, the well voltage (V WEL ) applied to the well S2 is supplied to the well voltage application unit 28 from the power supply unit PS. The well voltage application unit 28 applies a well voltage to the well S2 when writing data.
  • the well voltage is set to be equal to or lower than the first-choice source line voltage (V WEL ⁇ V SSL ), but the well voltage is preferably set to be lower than the first-choice source line voltage.
  • the first non-selective column voltage is set to be equal to or higher than the first selected source line voltage (V SSL ⁇ V UWL ), but the first non-selected column voltage is preferably set to a voltage higher than the first selected source line voltage. Further, although the first selection column voltage is set to be equal to or higher than the first selection row voltage (V SBL ⁇ V SWL ), it is preferable that the first selection column voltage is set to a voltage higher than the first selection row voltage.
  • the first non-selective column voltage is lower than the first selective row voltage and lower than the first selective column voltage (V UWL ⁇ V SBL , V UWL ⁇ V SWL ).
  • the first-selection line voltage breaks down the memory gate insulating film 10c between the memory gate electrode 10a to which this voltage is applied via the MOS transistor 20 and the diffusion region 10b to which the first-selection source line voltage is applied. It is a voltage that causes a voltage difference, and is set higher than the first-choice source line voltage (V SSL ⁇ V SBL ).
  • Table 1 shows a specific example (voltage example) of the above-mentioned writing voltage combination.
  • the first non-selection source line voltage is set to an intermediate voltage between the first selection source line voltage and the first selection line voltage.
  • the first selection source line voltage and the first non-selection line voltage are the same.
  • the voltage example N2 and the voltage example N4 have different individual voltages, but have the same relative high-low relationship of each voltage.
  • the voltage example N6 and the voltage example N8 although the individual voltages are different, the relative height relations of the respective voltages are the same.
  • the voltage examples N1 to N4 have the same first-selection source line voltage and the first non-selection column voltage, and the voltage examples N5 to N8 have the first-selection source line voltage. Is lower than the first non-selective column voltage.
  • the first-select source line voltage and the well voltage are the same, but in the voltage examples N3 and N7, the well voltage is lower than the first-select source line voltage.
  • the first selection row voltage and the first selection column voltage are the same, but in the voltage examples N2 to N4 and N6 to N8, the first selection column voltage is set from the first selection row voltage. Is also high.
  • the well voltage is the lowest -2V and the first selective column voltage is the highest 6V.
  • the first-selection source line voltage is 0V, which is the same as the first non-selection line voltage, and the well voltage is lower than the first-selection source line voltage.
  • the first non-selection column voltage is 0V, and the first non-selection column voltage and the first selection source line voltage are the same.
  • the first selection row voltage is 5V, and the first selection column voltage is higher than this first selection row voltage.
  • the first non-selection source line voltage is 3V, which is an intermediate voltage between the first selection source line voltage and the first selection line voltage set as described above.
  • the first non-selective column voltage is 0V, which is lower than the 5V first selective row voltage and the 6V first selective column voltage.
  • the well S2 is the well voltage of -2V
  • the word line WL1 is the first selection column.
  • the word lines WL2, WL3 ... Are set to 6V, which is the voltage, and 0V, which is the first non-selective column voltage.
  • the bit line BL1 is set to 5V, which is the first selective line voltage
  • the bit lines BL2, BL3, ... Are set to 0V, which is the first non-selective line voltage.
  • the source line SL1 is set to 0V, which is the first selection source line voltage
  • the anti-fuse memory M11 is subjected to the first selection line from the bit line BL1 to the memory gate electrode 10a via the MOS transistor 20 that has been turned on, as in the case of the first embodiment.
  • the first-select source line voltage of the source line SL1 is applied to the diffusion region 10b of the anti-fuse memory M11.
  • a voltage difference of 5 V that dielectrically breaks the memory gate insulating film 10c between the memory gate electrode 10a and the channel formed in the first active region 31 directly below the memory gate electrode 10a. Is generated, the memory gate insulating film 10c is dielectrically broken down, and data is written to the anti-fuse memory M11.
  • the first non-selective column voltage is applied from the word line WL to the gate electrode 20a to turn off the MOS transistor 20, or the bit line BL to the drain region 20c of the MOS transistor 20. Either or both of the first non-selective column voltages are applied.
  • the MOS transistor 20 is turned off, so that the first selective row voltage is not applied to the memory gate electrode 10a. Therefore, the memory gate insulating film 10c is not dielectrically broken.
  • the MOS transistor 20 is turned on, and the first non-selective row voltage (0V) from the bit line BL is applied to the memory gate electrode 10a.
  • the first source line voltage (0V) from the source line SL is applied to the diffusion region 10b of the memory capacitor 10. Therefore, there is no voltage difference between the memory gate electrode 10a and the diffusion region 10b that causes dielectric breakdown of the memory gate insulating film 10c. Therefore, the memory gate insulating film 10c is not dielectrically broken down.
  • the first non-selection source line voltage is set to 3V, and the intermediate voltage between the 1st selection source line voltage of 0V and the 1st selection line voltage of 5V is set.
  • the non-selective anti-fuse memory M in which the data in the non-selective column is written, even if the off characteristic of the MOS transistor 20 is insufficient, one of the first selected row voltages is passed through the MOS transistor 20.
  • the voltage difference between the memory gate electrode 10a to which the portion is applied and the source line SL becomes small. As a result, the leakage current flowing between the source line SL and the bit line BL through the short-circuited memory capacitor 10 and the MOS transistor 20 is reduced.
  • the first non-selection source line voltage is set as an intermediate voltage between the first selection source line voltage and the first selection line voltage. Therefore, the leakage current is reduced in the same manner as described above.
  • the first non-selection line voltage is 0V, which is the same as the first selection source line voltage.
  • the first-choice source line voltage is 0V
  • the well voltage is -2V
  • the well voltage is lower than the first-choice source line voltage.
  • the first-select source line voltage and the well voltage reverse-bias the MOS transistor 20. Therefore, the threshold voltage of the MOS transistor 20 increases due to the substrate bias effect, and the cutoff characteristic is improved. As a result, the leakage current between the bit line BL and the source line SL in the non-selective anti-fuse memory M in the non-selective column is reduced. The same effect can be obtained in the voltage example N7.
  • the first-selection source line voltage becomes an intermediate voltage between the well voltage and the first non-selection source line voltage due to the high-low relationship between the first-selection source line voltage and the well voltage as described above.
  • the first non-selection source line voltage is an intermediate voltage between the first selection source line voltage and the first selection line voltage. Therefore, the well voltage, the first selection source line voltage, the first non-selection source line voltage, and the first selection line voltage have a high-low relationship of the voltage at which the voltage increases in this order (V WEL ⁇ V SSL ⁇ V USL ⁇ V SBL ).
  • the first selection column voltage is 6V with respect to the first selection row voltage of 5V, and the first selection column voltage is higher than the first selection row voltage.
  • the voltage drop when the first selective row voltage is applied to the memory gate electrode 10a of the memory capacitor 10 through the MOS transistor 20 is reduced.
  • the voltage examples N2, N4, and N6 to N8 since the first selection column voltage is higher than the first selection row voltage, the same effect can be obtained.
  • the word lines WL2, WL3 ... are the first non-selective column voltages as shown in FIG. It is set to 1.5V.
  • the voltage applied to the other word lines WL1, source lines SL1, 2 ..., bit lines BL1, BL2 ..., And well voltage is the same as in the case of voltage example N3.
  • the first non-selection column voltage is made higher than the first selection source line voltage.
  • the electric field at the end of the drain region 20c can be reduced to reduce the junction leakage current (GIDL: Gate-Induced Drain Leakage).
  • GIDL Gate-Induced Drain Leakage
  • the first non-selected column voltage is set lower than the first selected row voltage and the first selected column voltage. Therefore, in voltage examples N5 to N8, the first non-selected column voltage is an intermediate voltage between the first selected source line voltage and the first selected row voltage, and the first selected source line voltage and the first selected column. It is an intermediate voltage between the voltage and the voltage. Of course, the first non-selective column voltage is a voltage that turns off the MOS transistor 20.
  • the first selection source line voltage is an intermediate voltage between the well voltage and the first non-selection source line voltage.
  • the first non-selection source line voltage is an intermediate voltage between the first selection source line voltage and the first selection line voltage. Therefore, the well voltage, the first selection source line voltage, the first non-selection source line voltage, and the first selection line voltage have a high-low relationship of the voltage at which the voltage increases in this order (V WEL ⁇ V SSL ⁇ V USL ⁇ V SBL ).
  • the first non-selective column voltage is 1.5 V, which is an intermediate voltage between the first selected source line voltage of 0 V and the first non-selected source line voltage of 3 V. .. Therefore, the well voltage, the first selection source line voltage, the first non-selection column voltage, the first non-selection source line voltage, and the first selection row voltage have a high-low relationship of the voltage at which the voltage increases in this order. (V WEL ⁇ V SSL ⁇ V UWL ⁇ V USL ⁇ V SBL ).
  • FIG. 1 When data is written to the anti-fuse memory M using the above-mentioned writing voltage, for example, when six types of writing voltages are used as in voltage example N7, an example is shown in FIG.
  • the power supply unit PS those provided with voltage generation units Pa to Pf corresponding to six types of writing voltages can be used.
  • the voltage generation units Pa to Pf output the voltages Va to Vf.
  • the voltages Va, Vb, Vc, Vd, Ve, and Vf have lower voltages in this order (Va> Vb> Vc> Vd> Ve> Vf).
  • voltage Va is 6V
  • voltage Vb is 5V
  • voltage Vc 3V
  • voltage Vd 1.5V
  • voltage Ve is 0V
  • voltage Vf -2V
  • the voltage generation unit Pa and the voltage generation unit Pd are connected to the word line driver 25a, the voltage Va from the voltage generation unit Pa is set as the first selection column voltage, and the voltage Vd from the voltage generation unit Pd is first. Supplied as a non-selective column voltage.
  • the voltage generation unit Pc and the voltage generation unit Pe are connected to the source line driver 25b, the voltage Ve from the voltage generation unit Pe is used as the first selection source line voltage, and the voltage Vc from the voltage generation unit Pc is the first non-voltage generation unit Pc.
  • the voltage generation unit Pb and the voltage generation unit Pe are connected to the bit line driver 26a, the voltage Vb from the voltage generation unit Pb is used as the first selection line voltage, and the voltage Ve from the voltage generation unit Pe is first non-selection. It is supplied as a row voltage.
  • a voltage generation unit Pf is connected to the well voltage application unit 28 to supply the voltage Vf as a well voltage.
  • a power supply unit PS that outputs three types of writing voltages may be provided by providing voltage generating units Pb, Pc, and Pe.
  • the voltage generation unit Pb and the voltage generation unit Pe are connected to the word line driver 25a, and the voltage Vb from the voltage generation unit Pb is used as the first selection column voltage, and the voltage Ve from the voltage generation unit Pe. Is supplied as the first non-selective column voltage.
  • the voltage generation unit Pc and the voltage generation unit Pe are connected to the source line driver 25b, the voltage Ve from the voltage generation unit Pe is set as the first selection source line voltage, and the voltage Vc from the voltage generation unit Pc is set as the first selection.
  • the voltage generation unit Pb and the voltage generation unit Pe are connected to the bit line driver 26a, the voltage Vb from the voltage generation unit Pb is used as the first selection line voltage, and the voltage Ve from the voltage generation unit Pe is first. Supplied as a non-selective line voltage.
  • a voltage generation unit Pe is connected to the well voltage application unit 28 to supply the voltage Ve as a well voltage.
  • the voltages Vb, Vc, and Ve are set to 5V, 3V, and 0V.
  • voltage generation units Pa, Pb, Pc, and Pe When using four types of writing voltages such as voltage examples N2 and N4, if voltage generating units Pa, Pb, Pc, and Pe are provided and a power supply unit PS that outputs four types of writing voltages is used. good.
  • the voltage generation unit Pa and the voltage generation unit Pe are connected to the word line driver 25a, the voltage Va from the voltage generation unit Pa is supplied as the first selection column voltage, and the voltage Ve from the voltage generation unit Pe. Is supplied as the first non-selective column voltage. Others are the same as in the case of voltage example N1.
  • the voltages Va, Vb, Vc, and Ve are 6V, 5V, 3V, and 0V in the voltage example N2, and 3V, 2V, 0V, and -3V in the voltage example N4.
  • voltage generation unit Pe is connected to the well voltage application unit 28 to supply the voltage Ve as the well voltage.
  • the voltages Va, Vb, Vc, Ve, and Vf are 6V, 5V, 3V, 0V, and -2V.
  • a power supply unit PS that outputs four types of writing voltages by providing voltage generating units Pb, Pc, Pd, and Pe may be used.
  • the voltage generation unit Pb and the voltage generation unit Pd are connected to the word line driver 25a, the voltage Vb from the voltage generation unit Pb is supplied as the first selection column voltage, and the voltage Vd from the voltage generation unit Pd. Is supplied as the first non-selective column voltage. Others are the same as in the case of voltage example N1.
  • the voltages Vb, Vc, Vd, and Ve are 5V, 3V, 1.5V, and 0V.
  • voltage generating units Pa, Pb, Pc, Pd, and Pe are provided, and a power supply unit PS that outputs five types of writing voltages is provided. It may be used.
  • the voltage generation unit Pa and the voltage generation unit Pd are connected to the word line driver 25a, the voltage Va from the voltage generation unit Pa is supplied as the first selection column voltage, and the voltage Vd from the voltage generation unit Pd is first non-selected. Supplied as a column voltage. Others are the same as in the case of voltage example N2.
  • the voltages Va, Vb, Vc, Vd, and Ve are 6V, 5V, 3V, 1.5V, and 0V in the voltage example N6, and 3V, 2V, 0V, -1.5V, and -3V in the voltage example N8. And.
  • the voltage for writing can be set to be the reverse of the above case in which the anti-fuse memory is composed of an N-type memory capacitor and a MOS transistor. good. Therefore, the high-low relationship of the voltages Va to Vf output from the power supply unit may be reversed.
  • the first non-selection source line voltage is lower than the first selection source line voltage and higher than the first selection line voltage (V SSL > V USL > V SBL ). That is, the first non-selection source line voltage is set to an intermediate voltage between the first selection source line voltage and the first selection line voltage.
  • the well voltage is set to be equal to or higher than the first-choice source line voltage (V WEL ⁇ V SSL ), but the well voltage is preferably set to be higher than the first-choice source line voltage.
  • the first non-selective column voltage is set to be equal to or lower than the first selected source line voltage (V SSL ⁇ V UWL ), but the first non-selected column voltage is preferably set to a voltage lower than the first selected source line voltage.
  • the first non-selective column voltage is higher than the first selective row voltage and higher than the first selective column voltage (V UWL > V SBL , V UWL > V SWL ). Further, it is also preferable that the first selection column voltage is equal to or lower than the first selection row voltage (V SBL ⁇ V SWL ), and the first selection column voltage is lower than the first selection row voltage (V SBL > V SWL ). It is also preferable.
  • the first non-selected source line voltage is set to an intermediate voltage between the first selected source line voltage and the first selected line voltage.
  • the first-selection source line voltage is lower than the well voltage (well voltage is higher than the first-selection source line voltage).
  • the first non-selection column voltage is made lower than the first selection source line voltage.
  • one type of voltage is applied to the source line SL to which the selective anti-fuse memory M is not connected when writing data, but different voltages are applied depending on the row. There may be two types.
  • the semiconductor storage device of the third embodiment floats the non-selected source line when writing data. Since the components are the same as those of the second embodiment except that the details will be described below, the components substantially the same as those of the second embodiment are designated by the same reference numerals, and the detailed description thereof will be omitted. Further, a case where the anti-fuse memory is composed of an N-type memory capacitor and an N-type MOS transistor will be described.
  • the first selection column voltage (V SWL ) and the first non-selection column voltage (V) are supplied from the power supply unit PS to the word line driver 25a of the column selection circuit 25.
  • UWL and is supplied, a first selected source line voltage (V SSL) is supplied to the source line driver 25b.
  • the bit line driver 26a of the row selection circuit 26 is supplied with a first selective row voltage (VSBL ) and a first non-selective row voltage ( VUBL) from the power supply unit PS.
  • the well voltage (V WEL ) is supplied from the power supply unit PS to the well voltage application unit 28.
  • the source line driver 25b applies the first selection source line voltage to the source line SL to which the selection anti-fuse memory M is connected, and applies the first selection source line voltage to the source line SL to which the selection anti-fuse memory M is not connected. It is in a floating state electrically disconnected from the voltage source including the power supply PS.
  • the writing voltage in this example is set to the following high-low relationship.
  • the well voltage is set to be equal to or lower than the first-choice source line voltage (V WEL ⁇ V SSL ), but the well voltage is preferably set to be lower than the first-choice source line voltage.
  • the first selection column voltage is set to be equal to or higher than the first selection row voltage (V SBL ⁇ V SWL )
  • it is preferable that the first selection column voltage is set to a voltage higher than the first selection row voltage.
  • the first non-selective column voltage is lower than the first selective row voltage and lower than the first selective column voltage (V UWL ⁇ V SBL , V UWL ⁇ V SWL ).
  • the source line driver 25b is provided with a switching unit 41 for each source line SL.
  • the switching unit 41 is composed of switching elements such as one or a plurality of MOS transistors. It is either off, which electrically disconnects the wire SL and puts its source wire SL in a floating state.
  • Table 3 shows a specific example (voltage example) of the above-mentioned writing voltage combination.
  • the source line SL to which the selection anti-fuse memory M is not connected is floated, and the first selection source line voltage, the first non-selection line voltage, and the first non-selection are made.
  • the column voltage is the same.
  • the well voltage and the first-selection source line voltage are the same, and in the voltage example N11, the well voltage is lower than the first-selection source line voltage.
  • the first selection column voltage and the first selection row voltage are made the same, and in the voltage examples N10 and N11, the first selection column voltage is made higher than the first selection row voltage.
  • the well S2 is the well voltage of -2V
  • the word line WL1 is the first selection column voltage.
  • the word lines WL2, WL3 ... Are set to 3V, which is the first non-selective column voltage
  • the bit line BL1 is set to 5V, which is the first selective line voltage
  • the switching unit 41 connected to the source line SL1 is turned on, the source line SL1 is set to 0V, which is the first selection source line voltage, and each switching unit 41 connected to the source lines SL2, 3, ... Is turned off. As a result, the source lines SL2, 3, ... Are placed in a floating state.
  • the leakage current between the bit line BL and the source line SL is suppressed. That is, even when the off characteristic of the MOS transistor 20 is insufficient, the source line SL connected to the memory capacitor 10 floats in the non-selective anti-fuse memory M in which the data in the non-selective column is written. Since the state is established, no leakage current flows between the bit line BL and the source line SL through the MOS transistor 20 and the short-circuited memory capacitor 10.
  • the first non-selective column voltage is set to the same voltage as the first selected source line voltage in each non-selective anti-fuse memory M in the same row as the selected anti-fuse memory M (hereinafter referred to as the selected row).
  • MOS transistor 20 does not turn on.
  • the bit line BL is in a floating state so as to charge the capacitance component of the source line SL which is in the floating state. Leakage current flows toward the source line SL.
  • the memory in the non-selected anti-fuse memory M in the same column as the selected anti-fuse memory M is the same as in the second embodiment. Dielectric breakdown of the gate insulating film 10c is prevented, and leakage current is prevented from flowing from the bit line BL to the source line SL via the non-selective anti-fuse memory M.
  • the well voltage is made lower than the first-select source line voltage to reverse bias the MOS transistor 20, and the substrate bias effect increases the threshold voltage of the MOS transistor 20 to improve the cutoff characteristic. .. Further, in the voltage examples N10 and N11, since the first selection column voltage is higher than the first selection row voltage, when the first selection row voltage is applied to the memory gate electrode 10a of the memory capacitor 10 through the MOS transistor 20. The voltage drop is reduced.
  • the source line to which the selected anti-fuse memory is not connected can be floated.
  • an anti-fuse memory is composed of a P-type memory capacitor and a MOS transistor
  • the high-low relationship of the writing voltage is the opposite of the case where the anti-fuse memory is composed of the N-type memory capacitor and the MOS transistor. good.
  • the well voltage is set to be equal to or higher than the first-choice source line voltage (V WEL ⁇ V SSL ), but the well voltage is preferably set to be higher than the first-choice source line voltage.
  • the first non-selective column voltage is higher than the first selective row voltage and higher than the first selective column voltage (V UWL > V SBL , V UWL > V SWL ).
  • the voltage of the first selection column is the same as the voltage of the first selection row.
  • Well voltage first selection source line voltage, first non-selection source line voltage, first selection column voltage, first non-selection column voltage, first when an anti-fuse memory is composed of P-type memory capacitors and MOS transistors.
  • Table 4 shows voltage examples P7 and P8 as specific examples of the combination of the selected row voltage and the first non-selected row voltage.
  • the first-selection source line voltage and the well voltage are the same, and in the voltage example P8, the first-selection source line voltage is set to be equal to or lower than the well voltage.
  • a plurality of anti-fuse memories are arranged in a matrix of a plurality of rows and a plurality of columns, but the number of rows and columns may be one or more, for example, a matrix of one row and a plurality of columns. It may be a matrix of multiple rows and one column.
  • Memory capacitor 10a Memory gate electrode 10b Diffusion area 10c Memory gate insulation film 20 MOS transistor 20a Gate electrode 20b Source area 20c Drain area 20d Gate insulation film 25a Word line driver 25b Source line driver 26a Bit line driver 27 Sense amplifier 28-well voltage application part 31, 32 Active area 41 Switching part BL Bit line SL Source line WL Word line M Anti-fuse memory PS Power supply part

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  • Read Only Memory (AREA)
  • Semiconductor Memories (AREA)

Abstract

L'invention concerne un dispositif de stockage à semi-conducteurs dans lequel le courant de fuite pendant l'écriture de données est supprimé. Un dispositif de stockage à semi-conducteurs 1 comprend une pluralité de mémoires anti-fusibles disposées en rangées et en colonnes. Les mémoires anti-fusibles M comprennent chacune un condensateur de mémoire 10 et un transistor MOS 20. Le condensateur de mémoire 10 comporte une électrode de grille de mémoire 10a connectée à une région de source 20b du transistor MOS 20, et une région de diffusion 10b connectée à une ligne de source SL pour chaque colonne. Le transistor MOS 20 a une électrode de grille 20a connectée à une ligne de mot WL pour chaque colonne, et une région de drain 20c connectée à une ligne de bit BL pour chaque rangée. Les tensions appliquées sont commandées indépendamment.
PCT/JP2021/002578 2020-02-04 2021-01-26 Dispositif de stockage à semi-conducteurs WO2021157419A1 (fr)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP2020017455A JP6721205B1 (ja) 2020-02-04 2020-02-04 半導体記憶装置
JP2020-017455 2020-02-04
JP2020-110035 2020-06-25
JP2020110035A JP7517683B2 (ja) 2020-06-25 2020-06-25 半導体記憶装置

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070076463A1 (en) * 2005-09-30 2007-04-05 Ali Keshavarzi Dual gate oxide one time programmable (OTP) antifuse cell
JP2009290189A (ja) * 2008-01-18 2009-12-10 Nec Electronics Corp 不揮発性半導体記憶装置
JP2018006525A (ja) * 2016-06-30 2018-01-11 ルネサスエレクトロニクス株式会社 半導体装置

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070076463A1 (en) * 2005-09-30 2007-04-05 Ali Keshavarzi Dual gate oxide one time programmable (OTP) antifuse cell
JP2009290189A (ja) * 2008-01-18 2009-12-10 Nec Electronics Corp 不揮発性半導体記憶装置
JP2018006525A (ja) * 2016-06-30 2018-01-11 ルネサスエレクトロニクス株式会社 半導体装置

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