WO2021143676A1 - 显示屏变频方法、ddic芯片、显示屏模组及终端 - Google Patents

显示屏变频方法、ddic芯片、显示屏模组及终端 Download PDF

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Publication number
WO2021143676A1
WO2021143676A1 PCT/CN2021/071286 CN2021071286W WO2021143676A1 WO 2021143676 A1 WO2021143676 A1 WO 2021143676A1 CN 2021071286 W CN2021071286 W CN 2021071286W WO 2021143676 A1 WO2021143676 A1 WO 2021143676A1
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Prior art keywords
frequency
refresh frequency
refresh
vfp
display screen
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PCT/CN2021/071286
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English (en)
French (fr)
Inventor
杨乐
崔志佳
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Oppo广东移动通信有限公司
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Application filed by Oppo广东移动通信有限公司 filed Critical Oppo广东移动通信有限公司
Priority to EP21741489.5A priority Critical patent/EP4089666A4/en
Publication of WO2021143676A1 publication Critical patent/WO2021143676A1/zh
Priority to US17/812,599 priority patent/US11893929B2/en

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/06—Adjustment of display parameters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2340/00—Aspects of display data processing
    • G09G2340/04—Changes in size, position or resolution of an image
    • G09G2340/0407—Resolution change, inclusive of the use of different resolutions for different screen areas
    • G09G2340/0435—Change or adaptation of the frame rate of the video stream

Definitions

  • the embodiments of the present application relate to the field of display technology, and in particular, to a display screen frequency conversion method, a display driver integrated circuit (DDIC), a display screen module, and a terminal.
  • DDIC display driver integrated circuit
  • AMOLED Active-Matrix Organic Light-Emitting Diode
  • AP application processor
  • Panel application processor
  • AMOLED display Self-luminous characteristics, in related technologies, it is necessary to manually or semi-automatically adjust the refresh rate of the AMOLED display.
  • the DDIC chip still needs the control panel to refresh at a high refresh rate, which increases the power consumption of the display screen.
  • the embodiments of the application provide a display frequency conversion method, a DDIC chip, a display module, and a terminal.
  • the technical solution is as follows:
  • an embodiment of the present application provides a display screen frequency conversion method, the method is used for a DDIC chip of an OLED display screen, and the method includes:
  • the first refresh frequency is adjusted Is a second refresh frequency, and the second refresh frequency is less than the first refresh frequency;
  • the display screen parameter is adjusted according to the second refresh frequency.
  • an embodiment of the present application provides a display screen frequency conversion method, the method is used for a DDIC chip of an OLED display screen, and the method includes:
  • the current time and the decrease of the n-th luminescence start signal (EM Start Virtical, ESTV) are acquired The time interval between edges, where the nth ESTV is the next ESTV at the current moment;
  • the VFP is adjusted according to the time interval, where the timing of the gate start signal (Gate Start Virtical, GSTV) after adjusting the VFP matches the timing of the ESTV.
  • an embodiment of the present application provides a DDIC chip, the DDIC chip is applied to an OLED display screen, and the DDIC chip is used for:
  • the first refresh frequency is adjusted to the second refresh frequency, and the second refresh The frequency is less than the first refresh frequency
  • the display screen parameter is adjusted according to the second refresh frequency.
  • an embodiment of the present application provides a DDIC chip, the DDIC chip is applied to an OLED display screen, and the DDIC chip is used for:
  • the time interval between the current moment and the falling edge of the nth ESTV is acquired, and the first n ESTVs are the next ESTV at the current moment;
  • the VFP is adjusted according to the time interval, where the timings of GSTV and ESTV are matched after the VFP is adjusted.
  • an embodiment of the present application provides a display screen module, the display screen module includes an OLED display screen and a DDIC chip, the DDIC chip is used for driving the OLED display screen, and the DDIC chip is used for Realize the display frequency conversion method as described in the above aspect.
  • an embodiment of the present application provides a terminal.
  • the terminal includes an AP, an OLED display, and a DDIC chip.
  • the AP and the DDIC chip communicate with each other through the Mobile Industry Processor Interface (MIPI). ) Is connected, and the DDIC chip is used to implement the display frequency conversion method as described in the above aspect.
  • MIPI Mobile Industry Processor Interface
  • FIG. 1 is a timing diagram of the gate signal and the EM signal under different Gate-FR shown in an exemplary embodiment of the present application;
  • Figure 2 is a timing diagram of Vsync, VFP, VBP and Vact;
  • Figure 3 is a flow chart of the DDIC chip performing frequency conversion process according to the frequency conversion instruction in the related technology
  • Fig. 4 shows a flowchart of a display frequency conversion method shown in an exemplary embodiment of the present application
  • Figure 5 is a flow chart of the DDIC chip in the related technology to realize the small-range frequency conversion process
  • Fig. 6 shows a flowchart of a display frequency conversion method shown in another exemplary embodiment of the present application
  • Fig. 7 is a flowchart of a display frequency conversion process provided by an exemplary embodiment of the present application.
  • FIG. 8 is a flowchart of a process of AP issuing an EM frequency conversion instruction to a DDIC chip according to an exemplary embodiment of the present application
  • Fig. 9 shows a flowchart of a display frequency conversion method shown in another exemplary embodiment of the present application.
  • Fig. 10 is a flowchart of a display frequency conversion process provided by another exemplary embodiment of the present application.
  • FIG. 11 shows a structural block diagram of a terminal provided by an exemplary embodiment of the present application.
  • the "plurality” mentioned herein means two or more.
  • “And/or” describes the association relationship of the associated objects, indicating that there can be three types of relationships, for example, A and/or B, which can mean: A alone exists, A and B exist at the same time, and B exists alone.
  • the character “/” generally indicates that the associated objects before and after are in an "or” relationship.
  • Tearing Effect (TE) signal a signal generated by a DDIC chip to prevent tearing when the image is refreshed during image display.
  • the DDIC chip When ready to refresh the next frame of image, the DDIC chip generates the TE signal.
  • the AP monitors the rising edge of the TE signal or, after detecting that the TE signal is at a high level, sends the next frame to the DDIC chip Image data.
  • Gate signal a panel row switch signal, used to control the source (Source) voltage to enter the channel of the current row of pixel circuits, so as to realize the data refresh of the current row of pixels.
  • the gate signal timing (Gate-Timing) is used to indicate the related timing of the gate signal, and mainly refers to the gate start signal (Gate Start Virtical, GSTV), and one frame includes a GSTV.
  • EM signal A panel row switch signal, used to control whether the current row of pixels emit light.
  • EM-Timing is used to indicate related timing of EM signals, and mainly refers to EM Start Virtical (ESTV), in which one frame contains multiple ESTVs.
  • EM pulse number (EM-Pulse-No): In order to achieve pulse width modulation (PWM) to adjust the brightness of the display at low brightness, the EM signal frequency (EM-FRequency, EM-FR) is usually (Gate-FRequency) , Gate-FR), that is, multiple EM switches are performed in one Gate frame.
  • EM-Pulse-No indicates the number of EM frames in one Gate frame. For example, when Gate-FR is 60Hz, EM-FR is 240Hz, and EM-Pulse-No is 4.
  • Vporch includes vertical synchronization signal (Vertical Synchronous Signal, Vsync), column forward interval (Vertical Front Porch, VFP), and column backward interval (Vertical Back Porch, VBP).
  • Vsync Vertical Synchronous Signal
  • VFP column forward interval
  • VBP Vertical Back Porch
  • the AP side For an OLED display with AP-DDIC-Panel architecture, after the AP side renders and generates image data, the image data is sent to the DDIC chip, and the DDIC chip controls the Panel to display the image according to the image data.
  • the AP side In a high refresh rate display scene, the AP side generates high-frequency image data.
  • the Panel side performs high-frequency image refresh based on the image data, thereby improving the smoothness of the screen.
  • high frame rate is mainly used in a small number of fast sliding scenes such as desktop sliding and photo album browsing.
  • the purpose is to improve the smoothness of the screen when users perform fast sliding operations.
  • Spend takes a small proportion of time in practical applications, and most of the usage scenarios are still static display, low-speed sliding, and low frame rate video playback scenes.
  • the image rendering speed on the AP side is reduced, while the Panel side still maintains a high refresh rate for image refresh (when the AP side does not send new image data, the single frame image will be displayed repeatedly), and the picture will not be improved.
  • the fluency of the display will increase the power consumption of the display.
  • the user when the terminal is running a high frame rate game, the user can manually set the refresh rate of the display to 120Hz, and when exiting the high frame rate game, the user can manually set the refresh rate of the display to 60Hz.
  • the AP side determines that frequency conversion is required (either manually triggered by the user or the AP automatically recognizes according to the scene), it sends a frequency conversion instruction to the DDIC chip through MIPI.
  • the DDIC chip adjusts the display refresh rate according to the frequency conversion instruction. The process is shown in Figure 3.
  • Step 301 Enter the Standby mode.
  • Step 302 Detect whether a wake-up (Sleep out) or power-on (Power on) command is received. If it is detected, go to step 303; if it is not detected, go to step 301.
  • Step 303 Initialize the display screen parameters according to the archived bits in the frame rate register.
  • the frame rate register stores the frame rate gear supported by the display screen (ie, the refresh rate gear), for example, the gear stored in the frame rate register includes 60Hz/90Hz/120Hz.
  • the initialized display parameters include VFP, EM-Pulse-No, Gamma and Demura.
  • the DDIC chip is initialized according to the display screen parameters corresponding to the frame frequency range of 60 Hz.
  • Step 304 Perform TE signal inversion according to the initialized frame rate.
  • the TE signal is pulled low at Vact and pulled high at Vporch.
  • Step 305 Receive MIPI data sent by the AP.
  • the MIPI data is image data rendered on the AP side, and the MIPI data is sent through MIPI when the AP detects the rising edge of the TE signal and the image data is ready.
  • Step 306 Pull down the TE signal after VBP, and perform Gate and EM scanning.
  • DDIC controls EM-Timing and matches Gate-Timing.
  • Step 307 After the Gate scan is completed, the TE signal is pulled up, and the EM scan continues.
  • Step 308 Detect whether a frequency conversion instruction sent by the AP is received. If the frequency conversion instruction is received, step 309 is executed; if the frequency conversion instruction is not received, step 310 is executed.
  • Step 309 Adjust the display screen parameters according to the frequency conversion instruction.
  • the frequency conversion instruction includes the target frame rate
  • DDIC obtains the target display screen parameters corresponding to the target frame rate from the frame rate register, and adjusts the parameters according to the target display screen parameters to reduce the influence of frequency conversion on the screen display.
  • Step 310 continue to use the original display screen parameters.
  • the DDIC chip continues to scan the image according to the initialized display screen parameters.
  • Step 311 It is detected whether the MIPI data sent by the AP is received. If the MIPI data sent by the AP is received, step 312 is executed; if the MIPI data sent by the AP is not received, step 313 is executed.
  • Step 312 Pull down the TE signal after VBP, and perform Gate and EM scans according to the current MIPI data.
  • the DDIC chip will control the display screen to update the screen according to the MIPI data.
  • Step 313 Pull down the TE signal after VBP, and perform Gate and EM scans based on historical MIPI data.
  • the DDIC chip will repeatedly display the previous frame according to the MIPI data corresponding to the previous frame of image.
  • Step 314 After the Gate scan is completed, the TE signal is pulled up, and the EM scan continues.
  • Step 315 Detect whether a power off or sleep in command is received. If it is detected, the process ends, and if it is not detected, step 308 is executed in a loop.
  • the user when the above-mentioned manual frequency conversion scheme is adopted, the user (or AP) needs to determine to reduce or increase the refresh frequency of the display screen according to the current application scenario, and trigger it manually. For example, when using a terminal to read e-books, because most of the e-book reading scenes display static text, the user manually sets the refresh rate of the display to 30Hz; when using the terminal to play games, because the game scene is mostly high frame Therefore, the user manually sets the refresh rate of the display to 120Hz.
  • the above adjustment process is complicated (especially in a fast sliding scene, such as a system desktop sliding scene), and the accuracy is low (the user artificially judges that there is an error in the timing of the refresh frequency switching).
  • the embodiments of this application provide an adaptive frame rate (AFR) solution.
  • AFR adaptive frame rate
  • the DDIC chip uses the VFP automatic delay mechanism while waiting for the AP to send image data.
  • the panel refresh rate is automatically reduced, which realizes the adaptive matching of the panel side refresh rate and the AP side rendering rate, and reduces the panel power consumption; in addition, it automatically increases when the AP rendering speed is detected to increase
  • the refresh rate of the Panel improves the smoothness of the screen display.
  • the entire adjustment process is automatically completed by the DDIC chip according to the rendering rate on the AP side (not triggered by the frequency conversion instruction sent by the AP), without manual triggering by the user, which simplifies the adjustment process and improves the accuracy and timeliness of the frequency conversion.
  • Illustrative embodiments are used for description below.
  • FIG. 4 shows a flowchart of a display screen frequency conversion method according to an exemplary embodiment of the present application.
  • the method is applied to a DDIC chip of an OLED display screen as an example.
  • the method includes:
  • Step 401 Initialize the display screen parameters according to the first refresh frequency.
  • the OLED display screen supports at least two refresh frequencies.
  • the DDIC chip in the standby mode, when a wake-up command or a power-on command is received (for example, when the screen is turned on when the screen is off), the DDIC chip is based on the default gear stored in the frame rate register. (I.e. the first refresh frequency) to initialize the display screen parameters.
  • the OLED display screen supports three refresh frequencies of 60Hz, 90Hz, and 120Hz, and the DDIC chip initializes the parameters according to the display screen parameters corresponding to 120Hz.
  • the display screen parameters initialized by the DDIC chip include Gamma parameters and Demura parameters.
  • the DDIC chip is initialized according to the Gamma parameters and Demura parameters corresponding to the first refresh frequency.
  • Step 402 When the first image data sent by the AP is received, perform image scanning according to the first refresh frequency.
  • the image scan includes Gate scan and EM scan.
  • the DDIC chip controls the AMOLED display screen to perform image scanning according to the first refresh frequency.
  • the AP may send data other than image data to the DDIC chip
  • the DDIC chip receives the data sent by the AP, it analyzes the data, and when the analysis reaches 0x2C, the data is determined Is the image data.
  • the DDIC chip needs to keep the timing matching of Gate-Timing and EM-Timing to meet the EM requirements of the OLED display.
  • Step 403 If the second image data sent by the AP is not received within the preset delay time of the VFP corresponding to the first refresh frequency, the first refresh frequency is adjusted to the second refresh frequency, and the second refresh frequency is less than the first refresh frequency. frequency.
  • the frequency conversion of the display screen is dominated by the AP.
  • the DDIC chip can only perform passive frequency conversion after receiving the frequency conversion instruction issued by the AP.
  • the DDIC chip is waiting for the AP to send the image data of the next frame of image ( That is to say, the second image data) process, according to the built-in VFP timeout (Timeout) timer to determine whether the image data is sent overtime, if the sending is not overtime (that is, the second image data is received within the VFP duration corresponding to the first refresh frequency), then Continue to update the image according to the first refresh frequency; if the sending timeout (the second image data is not received within the preset delay time of the VFP corresponding to the first refresh frequency, that is, the second image data is not received in the VFP corresponding to the first refresh frequency) 2.
  • Image data, and the second image data has not been received within the preset delay time after the VFP), it is determined that the AP side image rendering rate is lower than the current refresh frequency of the display screen, so
  • the second refresh rate is the lowest refresh rate supported by the OLED display, that is, the DDIC chip directly reduces the refresh rate to the minimum, or ,
  • the second refresh frequency is the next refresh frequency of the first refresh frequency, that is, the DDIC chip gradually reduces the refresh frequency to the lowest level.
  • the DDIC chip when the OLED display is set with three refresh frequencies, namely 60Hz, 90Hz, and 120Hz, the DDIC chip first scans the image at 120Hz. If the refresh frequency is 120Hz, it corresponds to the preset delay time of VFP. If the second image data sent by the AP is not received, the refresh frequency of the OLED display screen is adjusted to 90 Hz.
  • Step 404 Adjust the display screen parameters according to the second refresh frequency.
  • the DDIC chip adjusts the refresh frequency of the display screen
  • the parameter adjustment is performed according to the display screen parameters corresponding to the second refresh frequency in the frame rate register.
  • the display parameters corresponding to the first refresh frequency (120 Hz) are Gamma_120 Hz and Demura_120 Hz, respectively.
  • the DDIC chip adjusts the display parameters to Gamma_90 Hz and Demura_90 Hz.
  • the AP and the fixed frame rate (that is, the fixed refresh frequency of the display screen) are consistent with the work flow, and there is no need to send the DDIC
  • the chip issues a frequency conversion instruction, and the DDIC chip can also adjust the refresh frequency of the display screen adaptively according to the rendering rate on the AP side without the user's perception, eliminating the process of issuing a frequency conversion instruction by the AP.
  • the AP sends image data, there is no need to strictly match the timing of the DDIC chip, and no frequency conversion logic judgment is required, which simplifies the processing flow of the AP during the frequency conversion process.
  • the DDIC chip initializes the display screen parameters according to the first refresh frequency of the OLED display screen, and performs image scanning on the first image data sent by the AP according to the first refresh frequency.
  • the refresh rate corresponds to the second image data sent by the AP is not received within the preset delay time of the VFP, that is, when the AP's image rendering speed drops, the DDIC chip lowers the refresh rate of the OLED display and adjusts the display parameters accordingly; through the introduction VFP automatic delay mechanism, and adaptively adjust the refresh frequency of the display according to the speed of AP transmission of image data, so that the refresh frequency of the display matches the image rendering speed of the AP, thus realizing the adaptive dynamic frequency conversion of the OLED display. Help reduce the power consumption of the OLED display.
  • the AP renders the static system desktop at low speed.
  • the DDIC chip automatically Adjust the refresh rate of the display to 60 Hz.
  • the AP When the user clicks the game application icon on the system desktop, the AP renders the game screen at the highest rendering rate. At this time, the DDIC chip increases the refresh rate of the display to 120 Hz according to the AP rendering rate to ensure the smoothness of the game screen.
  • the DDIC chip When exiting the game application, the DDIC chip will gradually lower the refresh rate from 120Hz to 60Hz due to the reduction in the screen rendering rate of the AP. If the user performs a sliding operation process on the system desktop, the AP increases the screen rendering rate, and accordingly, the DDIC chip automatically increases the refresh rate of the display to 120Hz, which improves the fluency of the system desktop when sliding.
  • performing image scanning according to the first refresh frequency includes:
  • the first GSTV and the first ESTV are matched in timing, and the gate scan is performed according to the first refresh frequency.
  • adjusting the first refresh frequency to the second refresh frequency includes:
  • the VFP is automatically extended
  • the first refresh rate is adjusted to the second refresh rate, and the preset delay duration is determined according to the VFP corresponding to the second refresh rate.
  • the method further includes:
  • the method further includes:
  • the TE signal is set high and the TE signal is kept in a high level state.
  • the AP is used to send the generated image data when the TE signal is in a high level state.
  • the method further includes:
  • the method further includes:
  • the TE signal is flipped according to the preset flip frequency, and the preset flip frequency is higher than the first refresh frequency.
  • the method further includes:
  • the method further includes:
  • the second refresh frequency is adjusted to the first refresh frequency
  • the first refresh rate is the highest refresh rate of the OLED display screen.
  • adjusting the first refresh frequency to the second refresh frequency includes:
  • the step-by-step adjustment method is adopted to adjust the first refresh frequency to the second refresh frequency, and the second refresh frequency and the first refresh frequency are adjacent refresh frequencies.
  • the method is used for a DDIC chip of an OLED display screen in a mobile terminal.
  • the DDIC chip adapts the way the TE signal is generated.
  • the rendering rate of the AP has a small delay.
  • the AP detects whether the image data is ready. If the preparation is complete, the image data is sent to the DDIC chip through MIPI; if the preparation is not complete, the calculation The timeout duration (that is, how long does it take to be ready), and a timeout command (Timeout Command) is sent to the DDIC chip through MIPI, so that the DDIC chip can adjust related parameters according to the timeout command.
  • Step 501 Enter the standby mode.
  • Step 502 Detect whether a wake-up or power-on instruction is received. If it is detected, go to step 503; if it is not detected, go to step 501.
  • Step 503 Initialize the display screen parameters according to the archived bits of the frame rate register.
  • Step 504 Perform TE signal inversion according to the initialized frame rate.
  • Step 505 Receive MIPI data sent by the AP.
  • Step 506 Pull down the TE signal after VBP, and perform Gate and EM scans.
  • Step 507 After the Gate scan is completed, the TE signal is pulled up, and the EM scan continues.
  • Step 508 Detect whether a timeout instruction sent by the AP is received. If the timeout instruction is received, step 509 is executed; if the timeout instruction is not received, step 510 is executed.
  • Step 509 Adjust related parameters according to the timeout instruction.
  • the relevant parameters adjusted by the DDIC chip according to the timeout command are VFP and EM-Pulse-No.
  • Step 510 continue to use the original parameters.
  • Step 511 It is detected whether the MIPI data sent by the AP is received. If the MIPI data sent by the AP is received, step 512 is executed; if the MIPI data sent by the AP is not received, step 513 is executed.
  • Step 512 Pull down the TE signal after VBP, and perform Gate and EM scans according to the current MIPI data.
  • the DDIC chip will control the display screen to update the screen according to the MIPI data.
  • Step 513 Pull down the TE signal after VBP, and perform Gate and EM scans based on historical MIPI data.
  • the DDIC chip will repeatedly display the previous frame according to the MIPI data corresponding to the previous frame of image.
  • Step 514 After the Gate scan is completed, the TE signal is pulled up, and the EM scan continues.
  • Step 515 Detect whether a power off or sleep in command is received. If it is detected, the process ends, and if it is not detected, step 508 is executed in a loop.
  • the AP needs to consider not only the rendering speed when calculating the timeout period, but also the EM timing to ensure that GSTV and ESTV strictly match, and the calculation process is complicated.
  • the above-mentioned small-range frequency conversion mode and wide-range frequency conversion mode cannot be performed at the same time.
  • the small-range frequency conversion scheme and the large-range frequency conversion scheme can be compatible, which expands the application scenarios of display frequency conversion.
  • Illustrative embodiments are used for description below.
  • FIG. 6 shows a flowchart of a display screen frequency conversion method according to another exemplary embodiment of the present application.
  • the method is applied to a DDIC chip of an OLED display screen as an example.
  • the method includes:
  • Step 601 Initialize the display screen parameters according to the first refresh frequency.
  • the DDIC chip determines the maximum refresh rate supported by the OLED display screen as the first refresh comment, and initializes the display screen parameters.
  • Step 602 Perform TE signal inversion according to the first refresh frequency.
  • the DDIC chip flips the TE signal according to the first refresh frequency, pulls the TE signal low during the Vact period (that is, the TE signal remains low during the Vact period), and pulls it high during the Vporch period.
  • TE signal that is, the TE signal remains high during Vporch.
  • the AP performs TE high-level state detection (detection is performed after the image data is rendered). If it detects that the TE signal is in a high-level state, it sends image data to the DDIC chip through MIPI; if it detects that the TE signal is in a low-level state, Level state, then continue TE high-level state detection.
  • TE high-level state detection detection is performed after the image data is rendered. If it detects that the TE signal is in a high-level state, it sends image data to the DDIC chip through MIPI; if it detects that the TE signal is in a low-level state, Level state, then continue TE high-level state detection.
  • the DDIC chip performs TE signal inversion at 120 Hz.
  • Step 603 When receiving the first image data sent by the AP, generate V sync according to the VFP corresponding to the first refresh frequency.
  • the DDIC chip When receiving the first image data sent by the AP, in order to keep the image rendering and image display consistent, the DDIC chip generates V sync according to the first refresh frequency, so that the AP performs image rendering according to V sync.
  • the DDIC chip determines the timing position of V sync according to the VFP corresponding to the first refresh frequency, thereby generating V sync .
  • the DDIC chip generates V sync according to the VFP corresponding to 120 Hz.
  • Step 604 Perform timing matching between the first ESTV and VBP, and perform EM scanning according to the EM frequency, and the position of the VBP is determined according to the position of the V sync .
  • the EM frequency is an integer multiple of the first refresh frequency.
  • the DDIC chip first performs timing matching (matching with VBP) on the first ESTV, and then matches the first GSTV (gate start signal) with the first GSTV (gate start signal).
  • An ESTV performs timing matching.
  • timing location determined length DDIC VBP timing based on the time position of the V sync and V sync, then the first ESTV (closed state) with a timing matched VBP.
  • the DDIC chip After completing the ESTV timing matching, the DDIC chip performs EM scanning according to the EM frequency and keeps the frequency unchanged.
  • the EM frequency is an integer multiple of the refresh frequency of the display screen. For example, when the refresh frequency of the display screen includes 1 Hz, 30 Hz, 60 Hz, 90 Hz, or 120 Hz, the EM frequency is 360 Hz.
  • Step 605 Perform timing matching between the first GSTV and the first ESTV, and perform Gate scan according to the first refresh frequency.
  • the DDIC chip When matching the GSTV timing, the DDIC chip will match the timing of the first GSTV with the first ESTV to meet the EM requirements of the OLED display.
  • the DDIC chip After the GSTV timing matching is completed, the DDIC chip performs Gate scanning according to the first refresh frequency, thereby displaying the image corresponding to the first image data on the OLED display screen. It should be noted that when the gate scan is started, the DDIC chip pulls the TE signal low to prevent the AP from sending image data during the gate scan; when the gate scan is completed, the DDIC pulls the TE signal high so that the AP can send the prepared signal Image data.
  • Step 606 Set the TE signal high after the image scanning is completed, and keep the TE signal in a high level state.
  • the AP is used to send the generated image data when detecting that the TE signal is in a high level state.
  • the AP can only send the prepared image data to the DDIC chip when it detects that the TE signal is at a high level, and in this embodiment of the application, the frequency conversion process is fully controlled by the DDIC chip.
  • the TE signal is still inverted according to the first refresh frequency, and the image data prepared by the AP will be issued with a delay. Therefore, in the embodiment of the present application, after the DDIC chip completes the display of the first image data, the TE signal is set high and maintained The TE signal is in a high level state, so that the AP can send the image data in time after preparing the image data.
  • Step 607 If the second image data is not received in the VFP corresponding to the first refresh frequency, the VFP is automatically extended.
  • a timeout timer is set according to the VFP corresponding to the first refresh frequency; when the timeout timer reaches the timer duration, the DDIC chip determines the AP side rendering rate Lower than the refresh rate of the display, and automatically extend the VFP. For example, the DDIC chip sets a timeout timer according to VFP_120Hz corresponding to 120Hz.
  • the VFP is extended in units of Horizon scanning time.
  • steps 608 to 610 are executed; if the second image data is received within the preset delay time, steps 611 to 612 are executed.
  • Step 608 If the extended duration reaches the preset delay duration and the second image data is not received, the first refresh frequency is adjusted to the second refresh frequency, and the preset delay duration is determined according to the VFP corresponding to the second refresh frequency.
  • the DDIC chip adopts a step-by-step adjustment method to adjust the first refresh frequency to the second refresh frequency, and the second refresh frequency and the first refresh frequency are adjacent refresh frequencies. For example, for a display screen that supports five refresh rates of 1/30/60/90/120 Hz, when the first refresh rate is 120 Hz, the second refresh rate is 90 Hz.
  • the DDIC chip determines that the refresh frequency of the display screen needs to be reduced in a large range, so as to reduce the refresh rate of the display screen.
  • the first refresh rate is adjusted to the second refresh rate.
  • the accurately calculated extended duration is stored in the DDIC chip.
  • the DDIC chip sets and starts the timer according to the extended duration.
  • the DDIC chip adjusts the first refresh frequency to the second refresh frequency.
  • the DDIC chip stores the first VFP extension duration, the second VFP extension duration, and the third VFP extension duration.
  • the duration and the fourth VFP extension duration where the first VFP extension duration is calculated based on the VFP corresponding to 90Hz and 120Hz (such as VFP_90Hz-VFP_120Hz), and the second VFP extension duration is calculated based on the VFP corresponding to 60Hz and 90Hz (such as VFP_60Hz-VFP_90Hz) ), the third VFP extension duration is calculated according to the VFP corresponding to 600 Hz and 30 Hz (for example, VFP_30Hz-VFP_60Hz), and the fourth VFP extension duration is calculated according to the VFP corresponding to 1 Hz and 30 Hz (for example, VFP_1Hz-VFP_30Hz).
  • the DDIC chip sets the first timer according to the first VFP extension duration. If the second image frame data is not received within the timer duration of the first timer, the refresh frequency of the display screen is adjusted from 120 Hz to 90 Hz, and the second timer is set according to the second VFP extended duration. If the second image frame data is not received within the timer duration of the second timer, the refresh frequency of the display screen is adjusted from 90 Hz to 60 Hz, and so on, until the minimum refresh frequency is adjusted (the second image has not been received. In the case of image data).
  • Step 609 Adjust the VFP according to the position of the next ESTV, where the timing of the GSTV and the next ESTV after the adjustment of the VFP matches.
  • the DDIC chip In order to avoid the influence of frequency conversion on the picture, while adjusting the refresh frequency, the DDIC chip still needs to keep the timing matching between GSTV and ESTV. In a more possible implementation manner, the DDIC chip adjusts the VFP duration according to the position of the next ESTV, so that the adjusted GSTV matches the timing of the next ESTV.
  • Step 610 Adjust the display screen parameters according to the second refresh frequency.
  • step 609 can be performed together with step 610, which is not limited in this embodiment.
  • Step 611 If the second image data sent by the AP is received within the preset delay time of the VFP corresponding to the first refresh frequency, the time interval between the current moment and the falling edge of the nth ESTV is acquired, and the nth ESTV is It is the next ESTV at the current moment.
  • the DDIC chip obtains the time interval (EM_Distance) between the current moment (that is, the moment when the second image data is received) and the falling edge of the next ESTV, so that it can be subsequently based on this time. Adjust the VFP interval.
  • the DDIC chip needs to pull down TE.
  • Step 612 Adjust the VFP according to the time interval, where the timings of GSTV and ESTV after adjusting the VFP match.
  • the DDIC chip In order to enable GSTV to match the timing of ESTV, the DDIC chip needs to adjust the VFP duration so that the timing of GSTV and ESTV match, and then control the display screen to update the image according to the second image data.
  • this step may include the following sub-steps.
  • the DDIC chip when adjusting the VFP, obtains the respective durations of VFP, V sync, and VBP corresponding to the first refresh frequency, and calculates the sum of the durations of the three (VFP+V synsc +VBP).
  • the DDIC chip detects whether the time interval is greater than the sum of the durations. If it is greater, it indicates that the image update preparation can be completed before the next ESTV, and then executes step two; if it is less, it indicates that the image update preparation cannot be completed before the next ESTV, so execute Step three.
  • the first method is used to adjust the VFP. After the first method is used to adjust the VFP, the timing of GSTV matches the nth ESTV.
  • the DDIC chip adjusts the VFP duration so that the adjusted GSTV matches the timing of the next ESTV.
  • the second method is used to adjust the VFP, where after the second method is used to adjust the VFP, the timing of GSTV matches the n+1th ESTV.
  • the DDIC chip determines that it needs to delay one EM signal period, so as to adjust the VFP duration so that the adjusted GSTV matches the timing of the next ESTV.
  • the DDIC chip uses the VFP delay mechanism to automatically lower the refresh rate of the display screen to reduce power consumption when it recognizes that the AP side image rendering rate has a large range of delay; and when it recognizes that the AP side image rendering rate has a small range
  • VFP delay mechanism to automatically lower the refresh rate of the display screen to reduce power consumption when it recognizes that the AP side image rendering rate has a large range of delay; and when it recognizes that the AP side image rendering rate has a small range
  • the DDIC chip uses the VFP delay mechanism to automatically lower the refresh rate of the display screen to reduce power consumption when it recognizes that the AP side image rendering rate has a large range of delay; and when it recognizes that the AP side image rendering rate has a small range
  • the DDIC chip can be compatible with small-range frequency conversion and large-range frequency conversion at the same time, which expands the application scenarios of adaptive frequency conversion.
  • the DDIC chip automatically reduces the display refresh rate to reduce power consumption when the display refresh frequency is higher than the image rendering rate on the AP side.
  • the DDIC chip needs to be automatically upscaled.
  • the DDIC chip adjusts the display screen parameters according to the second refresh rate
  • the second refresh rate is adjusted to The first refresh frequency
  • the display screen parameters are adjusted according to the first refresh frequency
  • the up-conversion delay of the DDIC chip is related to the EM frequency.
  • the up-conversion delay is 2.1 ms
  • the up-conversion delay is 2.8 ms, which can achieve the effect of real-time up-conversion.
  • the DDIC chip lowers the refresh rate of the display screen from 120Hz to 90Hz, if the third image data sent by the AP is received within VFP_120Hz (less than VFP_90Hz), it indicates that the rendering rate on the AP side has increased.
  • the display screen is up-converted, and the refresh frequency is increased from 90Hz to 120Hz, so that the image refresh rate matches the image rendering rate, and the smoothness of the picture is improved.
  • the process of dynamic frequency conversion by the DDIC chip includes the following step.
  • Step 701 Enter the standby mode.
  • Step 702 Detect whether a wake-up or power-on instruction is received. If it is detected, go to step 703; if it is not detected, go to step 701.
  • Step 703 Initialize the display screen parameters (such as Gamma_120Hz and Demura_120Hz) according to the highest refresh frequency (such as 120Hz).
  • Step 704 Perform TE signal inversion according to the initialized highest refresh frequency.
  • Step 705 Receive the first image data sent by the AP.
  • Step 706 Generate V sync according to the highest refresh frequency.
  • Step 707 Match the first ESTV to VBP, and perform EM scanning according to the preset EM-FR (such as 360 Hz); at the same time, match the first GSTV to the timing of the first ESTV, start Gate scanning and pull down TE.
  • the preset EM-FR such as 360 Hz
  • step 708 after the Gate scan ends (that is, after Vact), the TE is set high, and the high level state is maintained.
  • Step 709 Automatically extend the VFP and wait for the second image data.
  • Step 710 Detect whether the second image data is received within the VFP delay time. If it is received, step 711 is executed, and if it is not received, step 715 is executed.
  • Step 711 Calculate the distance EM_Distance from the current moment to the next falling edge of ESTV, and pull down TE.
  • Step 712 Check whether EM_Distance is greater than or equal to VFP+V sync +VBP. If it is greater than or equal to, step 713 is executed, if less than, step 714 is executed.
  • Step 713 Adjust VFP so that GSTV matches the next ESTV.
  • Step 714 Adjust VFP so that GSTV matches the next ESTV.
  • Step 715 It is detected whether the second image data is received within the VFP delay time corresponding to the second highest refresh rate (for example, 90 Hz). If it is received, go to step 716; if it is not received, go to step 717.
  • the second highest refresh rate for example, 90 Hz
  • Step 716 Adjust the current display screen parameters to display screen parameters (such as Gamma_90Hz and Demura_90Hz) corresponding to the second highest refresh rate (such as 90Hz).
  • display screen parameters such as Gamma_90Hz and Demura_90Hz
  • Step 717 It is detected whether the second image data is received within the VFP delay time corresponding to the mid-range refresh rate (for example, 60 Hz). If it is received, go to step 718; if it is not received, go to step 719.
  • the mid-range refresh rate for example, 60 Hz
  • Step 718 Adjust the current display screen parameters to display screen parameters (such as Gamma_60Hz and Demura_60Hz) corresponding to the mid-range refresh rate (such as 60Hz).
  • display screen parameters such as Gamma_60Hz and Demura_60Hz
  • Step 719 It is detected whether the second image data is received within the VFP delay time corresponding to the second lowest refresh rate (for example, 30 Hz). If it is received, go to step 720; if it is not received, go to step 721.
  • the second lowest refresh rate for example, 30 Hz
  • Step 720 Adjust the current display screen parameters to display screen parameters (such as Gamma_30Hz and Demura_30Hz) corresponding to the second lowest refresh rate (such as 30Hz).
  • display screen parameters such as Gamma_30Hz and Demura_30Hz
  • Step 721 It is detected whether the second image data is received within the VFP delay time corresponding to the lowest refresh rate (for example, 1 Hz). If it is received, go to step 722; if it is not received, go back to step 709.
  • the lowest refresh rate for example, 1 Hz
  • Step 722 Adjust the current display screen parameters to the display screen parameters (such as Gamma_1 Hz and Demura_1 Hz) corresponding to the lowest refresh rate (such as 1 Hz).
  • the display screen parameters such as Gamma_1 Hz and Demura_1 Hz
  • Step 723 pull down the TE signal and adjust VFP so that GSTV matches the next ESTV.
  • step 724 after the Gate scan (ie after Vact) is completed, the TE signal is set high, and the EM scan continues.
  • Step 725 Detect whether a power-off or hibernation instruction is received. If it is detected, the process ends, and if it is not detected, step 709 is executed in a loop.
  • the embodiment of the present application only uses the display screen with five variable frequency gears, the corresponding Gate-FR is 1/30/60/90/120Hz, and the EM-FR is 360Hz as an example for schematic illustration.
  • the display screen can also be set to three, four or more than five variable frequency gears (for example, set the 15Hz gear between 1Hz and 30Hz), and ensure that EM-FR is Gate-FR An integer multiple is sufficient, and the embodiment of the present application does not limit the number of variable frequency gears, the frequency of Gate-FR and EM-FR.
  • EM-FR is an integer multiple of Gate-FR.
  • DDIC chips cannot guarantee that EM-FR is an integer multiple of all Gate-FR (for example, 360Hz EM-FR is not an integer multiple of 48Hz Gate-FR).
  • the AP issues an EM frequency conversion instruction to the DDIC chip when the EM-FR is not an integer multiple of the current refresh frequency according to the refresh frequency of the image in the current scene and the EM-FR of the DDIC chip. Instruct the DDIC chip to adjust the EM-FR to ensure that the adjusted EM-FR is an integer multiple of the current refresh frequency (that is, Gate-FR).
  • Step 801 It is detected whether the rendering of the image data is completed.
  • the AP detects whether the image data is rendered (Frame buffer ready). In this embodiment, the AP first detects whether the rendering of the image data is completed, and if the rendering is completed, execute the step 802. If the rendering is not completed, perform step 801 again.
  • Step 802 Detect whether the TE signal is in a high level state.
  • the AP when it detects the rising edge of the TE signal, it sends image data to the DDIC chip.
  • the DDIC chip will keep the TE signal at a high level during the Vporch period.
  • the AP passes the detection The level state of the TE signal determines whether to send image data to the DDIC chip. If it is detected that the TE signal is in a high level state, step 803 is executed; if it is detected that the TE signal is in a low level state, step 802 is executed again.
  • Step 803 It is detected whether the EM frequency needs to be adjusted.
  • the AP obtains the refresh frequency of the image in the current scene and the current EM frequency of the DDIC chip. If the EM frequency is an integer multiple of the refresh frequency, it is determined that the EM frequency does not need to be adjusted, and step 805 is executed; if EM If the frequency is not an integer multiple of the refresh frequency, it is determined that the EM frequency needs to be adjusted, and step 804 is executed.
  • Step 804 issue an EM frequency conversion instruction to the DDIC chip.
  • the EM frequency conversion instruction is issued through MIPI.
  • the EM frequency conversion command issued by the AP includes the current refresh frequency. Accordingly, the DDIC chip receives the EM frequency conversion command issued by the AP, and adjusts the EM frequency according to the refresh frequency contained in the EM frequency conversion command. Ensure that the adjusted EM frequency is an integer multiple of the current refresh frequency.
  • the DDIC chip adjusts the EM frequency
  • the EM duty cycle (EM-Duty) is kept unchanged, so as to avoid sudden changes in the brightness of the display before and after the EM frequency adjustment.
  • the DDIC chip adjusts the EM frequency from 360 Hz to 480 Hz.
  • Step 805 Send the image data to the DDIC chip.
  • the AP sends the rendered image data to the DDIC chip through MIPI, so that the DDIC chip controls the display screen to refresh the image.
  • the AP sends an EM frequency conversion command to the DDIC chip, and the DDIC chip adjusts the EM frequency according to the EM frequency conversion command, so that the adjusted EM frequency is an integer multiple of the current refresh frequency to ensure the stability of the image display in each scene.
  • the DDIC chip instructs the AP to issue the generated image data by setting the TE signal high.
  • the DDIC chip can also invert the TE signal by high frequency. , Instruct the AP to deliver the generated image data.
  • FIG. 9 shows a flowchart of a display screen frequency conversion method according to another exemplary embodiment of the present application.
  • the method is applied to a DDIC chip of an OLED display screen as an example.
  • the method includes:
  • Step 901 Initialize the display screen parameters according to the first refresh frequency.
  • step 902 the TE signal is inverted according to the first refresh frequency, and the AP is used to determine whether there is generated image data when the rising edge of the TE signal is detected.
  • the DDIC chip flips the TE signal according to the first refresh frequency, pulls the TE signal low during the Vact period (that is, the TE signal remains low during the Vact period), and pulls it high during the Vporch period.
  • TE signal that is, the TE signal remains high during Vporch.
  • the AP detects the rising edge of TE (ie, the TE signal is pulled high). If the rising edge of TE is detected, the AP further detects whether the image data is ready, if the preparation is complete, it sends the image data to the DDIC chip through MIPI; When the TE rising edge is reached, but the image data is not ready, continue to detect the TE rising edge, until the TE rising edge is detected and the image data is ready, the image data is sent to the DDIC chip.
  • the rising edge of TE ie, the TE signal is pulled high. If the rising edge of TE is detected, the AP further detects whether the image data is ready, if the preparation is complete, it sends the image data to the DDIC chip through MIPI; When the TE rising edge is reached, but the image data is not ready, continue to detect the TE rising edge, until the TE rising edge is detected and the image data is ready, the image data is sent to the DDIC chip.
  • the DDIC chip performs TE signal inversion at 120 Hz.
  • Step 903 When the first image data sent by the AP is received, Vsync is generated according to the VFP corresponding to the first refresh frequency.
  • Step 904 Perform timing matching of the first ESTV and VBP, and perform EM scanning according to the luminous frequency, and the position of the VBP is determined according to the position of the Vsync.
  • Step 905 Perform timing matching between the first GSTV and the first ESTV, and perform Gate scan according to the first refresh frequency.
  • steps 903 to 905 For the implementation manner of the above steps 903 to 905, reference may be made to steps 603 to 605, which will not be repeated in this embodiment.
  • Step 906 Perform TE signal inversion according to the preset inversion frequency, and the preset inversion frequency is higher than the first refresh frequency.
  • the AP can only send the prepared image data to the DDIC chip when the TE rising edge is detected, and in this embodiment of the application, the frequency conversion process is fully controlled by the DDIC chip. If the TE signal is still inverted according to the first refresh frequency, The delivery of the image data prepared by the AP will cause delays (for example, when the first TE rising edge is detected, the image data is not ready, and the image data is ready within a very short time after the first TE rising edge. The TE signal is reversed at the first refresh frequency, and the prepared image data needs to be delivered on the next TE rising edge, and the delay is relatively high). Therefore, in the embodiment of the present application, after the DDIC chip completes the display of the first image data, Control the TE signal to flip according to the preset flip frequency, thereby increasing the frequency at which the AP side detects the rising edge of TE.
  • the preset flip frequency is preset and higher than the first refresh frequency.
  • the time for the AP to upload image data is increased, so that the image data rendered by the AP can be delivered to the DDIC chip with a lower delay, and the image display rate is increased.
  • Step 907 If the second image data is not received in the VFP corresponding to the first refresh frequency, the VFP is automatically extended.
  • Step 908 If the extended duration reaches the VFP delay duration and the second image data is not received, the first refresh frequency is adjusted to the second refresh frequency, and the VFP delay duration is determined according to the VFP corresponding to the second refresh frequency.
  • Step 909 Adjust the VFP according to the position of the next ESTV, where the timing of the GSTV and the next ESTV after the adjustment of the VFP matches.
  • Step 910 Adjust the display screen parameters according to the second refresh frequency.
  • Step 911 If the second image data sent by the AP is received within the preset delay time of the VFP corresponding to the first refresh frequency, the time interval between the current moment and the falling edge of the nth ESTV is acquired, and the nth ESTV is It is the next ESTV at the current moment.
  • Step 912 Adjust the VFP according to the time interval, where the timing of the GSTV and the ESTV match after the VFP is adjusted.
  • steps 907 to 912 For the implementation of steps 907 to 912 above, reference may be made to steps 607 to 612, which are not described in detail in this embodiment.
  • the process of dynamic frequency conversion of the DDIC chip includes the following steps.
  • Step 1001 enter the standby mode.
  • Step 1002 It is detected whether a wake-up or power-on command is received. If it is detected, go to step 1003; if it is not detected, go to step 1001.
  • Step 1003 initialize the display screen parameters (such as Gamma_120Hz and Demura_120Hz) according to the highest refresh frequency (such as 120Hz).
  • the display screen parameters such as Gamma_120Hz and Demura_120Hz
  • Step 1004 Perform TE signal inversion according to the initialized highest refresh frequency.
  • Step 1005 Receive the first image data sent by the AP.
  • step 1006 Vsync is generated according to the highest refresh frequency.
  • Step 1007 Match the first ESTV to VBP, and perform EM scanning according to the preset EM-FR (such as 360 Hz); at the same time, match the first GSTV to the timing of the first ESTV, start Gate scanning and pull down TE.
  • the preset EM-FR such as 360 Hz
  • Step 1008 after the Gate scan, the TE is pulled up.
  • Step 1009 Invert the TE signal according to the preset inversion frequency and duty cycle (for example, 2000 Hz/50% duty cycle), and automatically extend the VFP, and wait for the second image data.
  • the preset inversion frequency and duty cycle for example, 2000 Hz/50% duty cycle
  • Step 1010 Detect whether the second image data is received within the VFP delay time. If it is received, go to step 1011, if it is not received, go to step 1015.
  • Step 1011 Calculate the distance EM_Distance from the current moment to the next falling edge of ESTV, and pull down TE.
  • Step 1012 Check whether EM_Distance is greater than or equal to VFP+Vsync+VBP. If it is greater than or equal to, step 1013 is executed, and if less than, step 1014 is executed.
  • Step 1013 Adjust VFP so that GSTV matches the next ESTV.
  • Step 1014 Adjust VFP so that GSTV matches the next ESTV.
  • Step 1015 It is detected whether the second image data is received within the VFP delay time corresponding to the mid-range refresh rate (for example, 90 Hz). If it is received, go to step 1016; if it is not received, go to step 1017.
  • the mid-range refresh rate for example, 90 Hz
  • Step 1016 Adjust the current display screen parameters to display screen parameters (such as Gamma_90Hz and Demura_90Hz) corresponding to the mid-range refresh rate (such as 90Hz). .
  • Step 1017 It is detected whether the second image data is received within the VFP delay time corresponding to the lowest refresh rate (for example, 60 Hz). If it is received, go to step 718; if it is not received, go back to step 709.
  • the lowest refresh rate for example, 60 Hz
  • Step 1018 Adjust the current display screen parameters to the display screen parameters (such as Gamma_60Hz and Demura_60Hz) corresponding to the lowest refresh rate (such as 60Hz).
  • the display screen parameters such as Gamma_60Hz and Demura_60Hz
  • Step 1019 pull down the TE signal and adjust VFP to make GSTV match the next ESTV.
  • Step 1020 After the Gate scan is completed, the TE signal is pulled up, and the EM scan continues.
  • Step 1021 Detect whether a power-off or hibernation instruction is received. If it is detected, the process ends. If it is not detected, then step 1009 is executed cyclically.
  • the embodiment of this application only uses the display screen with three frequency conversion gears, the corresponding Gate-FR is 120/90/60Hz, and the EM-FR is 360Hz as an example for schematic illustration.
  • the display screen can also be set with two frequency conversion gears or three or more frequency conversion gears.
  • other Gate-FR such as 30Hz, 45Hz, etc.
  • EM-FR is an integer multiple of Gate-FR, and the embodiment of the present application does not limit the number of frequency conversion gears, the frequency of Gate-FR and EM-FR.
  • the method provided in the embodiments of the present application is applied to a mobile terminal, that is, the DDIC chip of the OLED display screen in the mobile terminal executes the above-mentioned display frequency conversion method. Since the mobile terminal is usually powered by a battery, and the battery has a limited amount of power (which is more sensitive to power consumption), the method provided by the embodiment of the present application is applied to the mobile terminal, while improving the display quality of the mobile terminal, it can reduce the display quality of the mobile terminal. Power consumption.
  • the mobile terminal may include a smart phone, a tablet computer, a wearable device (such as a smart watch), a portable personal computer, etc.
  • the embodiment of the present application does not limit the specific type of the mobile terminal.
  • the method provided in the embodiment of the present application can also be used in other non-battery-powered terminals, such as a TV, a monitor, or a personal computer, etc., which is not limited in the embodiment of the present application.
  • the embodiment of the application also provides a DDIC chip, the DDIC chip is applied to an OLED display screen, and the DDIC chip is used for:
  • the first refresh frequency is adjusted to the second refresh frequency, The second refresh frequency is less than the first refresh frequency
  • the display screen parameter is adjusted according to the second refresh frequency.
  • the DDIC chip is used for:
  • the DDIC chip is used for:
  • the VFP is automatically extended
  • the first refresh rate is adjusted to the second refresh rate, and the preset delay duration is based on the second refresh rate.
  • the VFP corresponding to the refresh frequency is determined.
  • the DDIC chip is also used for:
  • the VFP is adjusted according to the position of the next ESTV, where the timing of the GSTV and the next ESTV match after the VFP is adjusted.
  • the DDIC chip is also used for:
  • the high tearing effect TE signal is set and the TE signal is kept at a high level.
  • the AP is used to send the generated image data when detecting that the TE signal is at a high level.
  • the DDIC chip is also used for:
  • Performing TE signal inversion according to the first refresh frequency, and the AP is used to determine whether there is generated image data when the rising edge of the TE signal is detected;
  • the method further includes:
  • the TE signal inversion is performed according to a preset inversion frequency, and the preset inversion frequency is higher than the first refresh frequency.
  • the DDIC chip is also used for:
  • the EM frequency is adjusted according to the EM frequency conversion instruction, where the adjusted EM frequency is an integer multiple of the current refresh frequency.
  • the DDIC chip is also used for:
  • the display screen parameter is adjusted according to the first refresh frequency.
  • the first refresh frequency is the highest refresh frequency of the OLED display screen.
  • the DDIC chip is used for:
  • the first refresh frequency is adjusted to the second refresh frequency, and the second refresh frequency and the first refresh frequency are adjacent refresh frequencies.
  • the DDIC chip is a DDIC chip of an OLED display screen in a mobile terminal.
  • the embodiment of the application also provides a DDIC chip, the DDIC chip is applied to an OLED display screen, and the DDIC chip is used for:
  • the second image data sent by the AP is received within the preset delay time of the column forward interval VFP corresponding to the first refresh frequency, the current time and the falling edge of the nth light-emitting start signal ESTV are acquired The time interval between, the nth ESTV is the next ESTV at the current moment;
  • the VFP is adjusted according to the time interval, wherein the timing of the gate start signal GSTV and the ESTV after adjusting the VFP match.
  • the DDIC chip is used for:
  • the DDIC chip is used for:
  • the VFP is adjusted in a second manner, wherein after the VFP is adjusted in the second manner, the timing of the GSTV and the n+1th ESTV match.
  • the embodiments of the present application also provide a display module, the display module includes an AMOLED display and a DDIC chip, the DDIC chip is used to drive the AMOLED display, and the DDIC chip is used to implement the various method embodiments described above The display frequency conversion method.
  • FIG. 11 shows a structural block diagram of a terminal 1100 according to an exemplary embodiment of the present application.
  • the terminal 1100 may be a smart phone, a tablet computer, a notebook computer, or the like.
  • the terminal 1100 in this application may include one or more of the following components: a processor 1110, a memory 1120, and a display module 1130.
  • the processor 1110 may include one or more processing cores.
  • the processor 1110 uses various interfaces and lines to connect various parts of the entire terminal 1100, and executes the terminal by running or executing instructions, programs, code sets, or instruction sets stored in the memory 1120, and calling data stored in the memory 1120. 1100's various functions and processing data.
  • the processor 1110 may adopt at least one of digital signal processing (Digital Signal Processing, DSP), Field-Programmable Gate Array (Field-Programmable Gate Array, FPGA), and Programmable Logic Array (Programmable Logic Array, PLA).
  • DSP Digital Signal Processing
  • FPGA Field-Programmable Gate Array
  • PLA Programmable Logic Array
  • the processor 1110 can integrate one or more of the central processing unit (CPU), graphics processing unit (GPU), neural network processing unit (NPU), modem, etc.
  • the CPU mainly processes the operating system, user interface and application programs; the GPU is used to render and draw the content that needs to be displayed by the touch display module 1130; the NPU is used to implement artificial intelligence (AI) functions; the modem Used to handle wireless communication. It is understandable that the above-mentioned modem may not be integrated into the processor 1110, but may be implemented by a chip alone.
  • the memory 1120 may include random access memory (RAM), or read-only memory (ROM).
  • the memory 1120 includes a non-transitory computer-readable storage medium.
  • the memory 1120 may be used to store instructions, programs, codes, code sets or instruction sets.
  • the memory 1120 may include a program storage area and a data storage area, where the program storage area may store instructions for implementing the operating system and instructions for at least one function (such as touch function, sound playback function, image playback function, etc.), Instructions for implementing various method embodiments of the present application, etc.; the storage data area can store data (such as audio data, phone book) created according to the use of the terminal 1100, and the like.
  • the display screen module 1130 is a display component used for image display, and is usually arranged on the front panel of the terminal 1100.
  • the display module 1130 can be designed as a full screen, a curved screen, a special-shaped screen, a double-sided screen or a folding screen.
  • the display screen module 1130 can also be designed as a combination of a full screen and a curved screen, or a combination of a special-shaped screen and a curved screen, which is not limited in this embodiment.
  • the display screen module 1130 includes a DDIC chip 1131 and a display screen 1132 (panel).
  • the display screen 1132 is an OLED display screen, which may be a Low Temperature Poly-Silicon (LTPS) AMOLED display screen or a Low Temperature Polycrystalline Oxide (LTPO) AMOLED display screen.
  • LTPS Low Temperature Poly-Silicon
  • LTPO Low Temperature Polycrystalline Oxide
  • the DDIC chip 1131 is used to drive the display screen 1132 for image display, and the DDIC chip 1131 is used to implement the display screen frequency conversion method provided by the foregoing embodiments.
  • the DDIC chip 1131 is connected to the processor 1110 through an MIPI interface, and is used to receive image data and instructions issued by the processor 1110.
  • the display screen module 1130 also has a touch function.
  • the touch function the user can use any suitable object such as a finger or a touch pen to perform touch operations on the display screen module 1130.
  • the structure of the terminal 1100 shown in the above drawings does not constitute a limitation on the terminal 1100, and the terminal may include more or less components than those shown in the figure, or a combination of certain components. Components, or different component arrangements.
  • the terminal 1100 also includes components such as a microphone, a speaker, a radio frequency circuit, an input unit, a sensor, an audio circuit, a wireless fidelity (Wireless Fidelity, WiFi) module, a power supply, a Bluetooth module, etc., which will not be repeated here.
  • the functions described in the embodiments of the present application may be implemented by hardware, software, firmware, or any combination thereof. When implemented by software, these functions can be stored in a computer-readable medium or transmitted as one or more instructions or codes on the computer-readable medium.
  • the computer-readable medium includes a computer storage medium and a communication medium, where the communication medium includes any medium that facilitates the transfer of a computer program from one place to another.
  • the storage medium may be any available medium that can be accessed by a general-purpose or special-purpose computer.

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Abstract

一种显示屏(1132)变频方法、DDIC芯片(1131)、显示屏模组(1130)及终端(1100)。方法包括：根据第一刷新频率初始化显示屏参数(401)；当接收到AP发送的第一图像数据时，根据第一刷新频率进行图像扫描(402)；若在第一刷新频率对应的列向前延间隔(VFP)的预设延迟时长内未接收到AP发送的第二图像数据，则将第一刷新频率调整为第二刷新频率，第二刷新频率小于第一刷新频率(403)；根据第二刷新频率调整显示屏参数(404)。DDIC芯片(1131)根据AP传输图像数据的速度，自适应调整显示屏(1132)的刷新频率，实现显示屏(1132)的自适应动态变频，降低显示屏(1132)的功耗。

Description

显示屏变频方法、DDIC芯片、显示屏模组及终端
本申请要求于2020年01月14日提交，申请号为202010039097.2、发明名称为“显示屏变频方法、DDIC芯片、显示屏模组及终端”的中国专利申请，于2020年01月14日提交，申请号为202010039092.X、发明名称为“显示屏变频方法、DDIC芯片、显示屏模组及终端”的中国专利申请，以及于2020年09月30日提交，申请号为202011061844.9、发明名称为“显示屏变频方法、DDIC芯片、显示屏模组及终端”的中国专利申请的优先权，其全部内容通过引用结合在本申请实施例中。
技术领域
本申请实施例涉及显示技术领域，特别涉及一种显示屏变频方法、显示驱动电路(Display Driver Integrated Circuit，DDIC)、显示屏模组及终端。
背景技术
随着显示屏技术的不断发展，越来越多的高刷新率显示屏应运而生，在运行高帧率应用程序或在滑动操作过程中，通过将显示屏设置为高刷新率模式能够提高画面的流畅度。
对于主动矩阵有机发光二极体(Active-Matrix Organic Light-Emitting Diode，AMOLED)显示屏，受限于应用处理器(Application Processor，AP)-DDIC-面板(Panel)的驱动架构以及AMOLED显示屏的自发光特点，相关技术中，需要通过手动或半自动方式调节AMOLED显示屏的刷新率。
然而，采用上述刷新率调节方式，若未及时调节刷新率，当AP的渲染速度降低时，DDIC芯片仍然需要控制面板按照高刷新频率进行刷新，增加了显示屏的功耗。
发明内容
本申请实施例提供了一种显示屏变频方法、DDIC芯片、显示屏模组及终端。所述技术方案如下：
一方面，本申请实施例提供了一种显示屏变频方法，所述方法用于OLED显示屏的DDIC芯片，所述方法包括：
根据第一刷新频率初始化显示屏参数；
当接收到AP发送的第一图像数据时，根据所述第一刷新频率进行图像扫描；
若在所述第一刷新频率对应的列向前延间隔(Vertical Front Porch，VFP)的预设延迟时长内未接收到所述AP发送的第二图像数据，则将所述第一刷新频率调整为第二刷新频率，所述第二刷新频率小于所述第一刷新频率；
根据所述第二刷新频率调整所述显示屏参数。
另一方面，本申请实施例提供了一种显示屏变频方法，所述方法用于OLED显示屏的DDIC芯片，所述方法包括：
根据第一刷新频率初始化显示屏参数；
当接收到AP发送的第一图像数据时，根据所述第一刷新频率进行图像扫描；
若在所述第一刷新频率对应的VFP的预设延迟时长内接收到所述AP发送的第二图像数据，则获取当前时刻与第n个发光起始信号(EM Start Virtical，ESTV)的下降沿之间的时间间隔，所述第n个ESTV是所述当前时刻的下一个ESTV；
根据所述时间间隔调整VFP，其中，调整VFP后栅极起始信号(Gate Start Virtical，GSTV)与ESTV的时序匹配。
另一方面，本申请实施例提供了一种DDIC芯片，所述DDIC芯片应用于OLED显示屏，所述DDIC芯片用于：
根据第一刷新频率初始化显示屏参数；
当接收到AP发送的第一图像数据时，根据所述第一刷新频率进行图像扫描；
若在所述第一刷新频率对应的VFP的预设延迟时长内未接收到所述AP发送的第二图像数据，则将所述第一刷新频率调整为第二刷新频率，所述第二刷新频率小于所述第一刷新频率；
根据所述第二刷新频率调整所述显示屏参数。
另一方面，本申请实施例提供了一种DDIC芯片，所述DDIC芯片应用于OLED显示屏，所述DDIC芯片用于：
根据第一刷新频率初始化显示屏参数；
当接收到AP发送的第一图像数据时，根据所述第一刷新频率进行图像扫描；
若在所述第一刷新频率对应的VFP的预设延迟时长内接收到所述AP发送的第二图像数据，则获取当前时刻与第n个ESTV的下降沿之间的时间间隔，所述第n个ESTV是所述当前时刻的下一个ESTV；
根据所述时间间隔调整VFP，其中，调整VFP后GSTV与ESTV的时序匹配。
另一方面，本申请实施例提供了一种显示屏模组，所述显示屏模组包括OLED显示屏和DDIC芯片，所述DDIC芯片用于驱动所述OLED显示屏，所述DDIC芯片用于实现如上述方面所述的显示屏变频方法。
另一方面，本申请实施例提供了一种终端，所述终端包括AP、OLED显示屏和DDIC芯片，所述AP与所述DDIC芯片之间通过移动产业处理器接口(Mobile Industry Processor Interface，MIPI)相连，所述DDIC芯片用于实现如上述方面所述的显示屏变频方法。
附图说明
图1是本申请示例性实施例示出的不同Gate-FR下，Gate信号与EM信号的时序关系图；
图2是Vsync、VFP、VBP以及Vact的时序关系图；
图3是相关技术中DDIC芯片根据变频指令进行变频过程的流程图；
图4示出了本申请一个示例性实施例示出的显示屏变频方法的流程图；
图5是相关技术中DDIC芯片实现小范围变频过程的流程图；
图6示出了本申请另一个示例性实施例示出的显示屏变频方法的流程图；
图7是本申请一个示例性实施例提供的显示屏变频过程的流程图；
图8是本申请一个示例性实施例提供的AP向DDIC芯片下发EM变频指令过程的流程图；
图9示出了本申请另一个示例性实施例示出的显示屏变频方法的流程图；
图10是本申请另一个示例性实施例提供的显示屏变频过程的流程图；
图11示出了本申请一个示例性实施例提供的终端的结构方框图。
具体实施方式
为使本发明的目的、技术方案和优点更加清楚，下面将结合附图对本发明实施方式作进一步地详细描述。
在本文中提及的“多个”是指两个或两个以上。“和/或”，描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B这三种情况。字符“/”一般表示前后关联对象是一种“或”的关系。
为了方便理解，下面对本申请实施例中涉及的名词进行说明。
撕裂效应(Tearing Effect，TE)信号：一种由DDIC芯片产生的信号，用于防止图像显示过程中画面刷新时的撕裂问题。当准备好刷新下一帧图像时，DDIC芯片即产生TE信号，可选的，AP在监听到TE信号上升沿，或，检测到TE信号处于高电平状态后，向DDIC芯片发送下一帧图像数据。
Gate信号：一种面板行开关信号，用于控制源(Source)电压进入当前行像素电路的通道，从而实现当前行像素的数据刷新。相应的，栅信号时序(Gate-Timing)用于指示Gate信号相关时序，主要指栅极起始信号(Gate Start Virtical，GSTV)，其中一帧内包含一个GSTV。
EM信号：一种面板行开关信号，用于控制当前行像素是否发光。相应的，发光信号时序(EM-Timing)用于指示EM信号相关时序，主要指发光起始信号(EM Start Virtical，ESTV)，其中一帧内包含多个ESTV。
EM脉冲数量(EM-Pulse-No)：为了在低亮度下实现脉冲宽度调制(Pulse width modulation，PWM)调节显示屏亮度，EM信号频率(EM-FRequency，EM-FR)通常为(Gate-FRequency，Gate-FR)的整数倍，即在Gate一帧内进行多次EM开关，相应的，EM-Pulse-No即指示一个Gate帧内EM帧的数量。比如Gate-FR为60Hz时，EM-FR为240Hz，EM-Pulse-No为4。需要说明的是，由于AMOLED显示屏的自发光特点，在同一帧中，ESTV需要严格匹配GSTV(第一个EM信号的关闭时序需要匹配Gate-Timing)，其余EM信号则由DDIC芯片平均分配。
示意性的，不同Gate-FR下，Gate信号与EM信号的时序关系如图1所示。其中，EM-FR和占空比保持稳定，从而避免Gate-FR变化时引起的亮度突变。图1中，Gate-FR为60Hz/90Hz/120Hz时，EM-FR和占空比均保持不变(360Hz)。同时，为了最大程度降低Gate-FR变化对Gamma以及去除不均匀(Demura)参数的影响，需要保持Gate扫描速度不变，即Gate扫描一行的时间不变，完成一帧刷新所用时间不变，仅延长垂直间隔(Vertical Porch，Vporch)。图1中，当Gate-FR为60Hz/90Hz/120Hz时，每一帧扫描均在8.3ms内完成。
Vporch：包括垂直同步信号(Vertical Synchronous Signal，Vsync)、列向前延间隔(Vertical Front Porch，VFP)以及列向后延间隔(Vertical Back Porch，VBP)。示意性的，Vsync、VFP、VBP以及列向有效行数 (Vertical active，Vact)之间的关系如图2所示。上述延长垂直间隔时，即主要对VFP进行延长。
对于采用AP-DDIC-Panel架构的OLED显示屏，AP侧渲染生成图像数据后，将图像数据发送至DDIC芯片，由DDIC芯片控制Panel根据图像数据进行图像显示。在高刷新率显示场景下，AP侧高频生成图像数据，相应的，Panel侧根据图像数据进行高频图像刷新，从而提高画面的流畅度。
在实际应用过程中，除了在高帧率游戏内实现高刷新率外，高帧率主要应用在桌面滑动、相册浏览等少量快速滑动场景，其目的是为了提高用户执行快速滑动操作时画面的流畅度。然而，快速滑动在实际应用中所占的时间比例较小，大多数使用场景仍旧是静态显示、低速滑动以及低帧率视频播放场景。在上述使用场景下，AP侧的图像渲染速度降低，而Panel侧仍旧保持高刷新率进行图像刷新(当AP侧未发送新的图像数据时，单帧图像将重复显示)，并不会提升画面的流畅度，反而会增加显示屏的功耗。
相关技术中，为了降低高刷新率显示屏的功耗，通常采用手动变频(Manual Frame Rate，MFR)的方式调整高刷新率显示屏的刷新率，即需要用户根据当前应用场景手动指示调整刷新率，从而触发AP向DDIC芯片发送变频指令(command)，由DDIC芯片根据变频指令调整Panel的刷新率。
比如，当终端运行高帧率游戏时，用户可以手动将显示屏的刷新率设置为120Hz，当退出高帧率游戏时，用户可以手动将显示屏的刷新率设置为60Hz。
在一个示意性的例子中，AP侧确定需要进行变频时(用户手动触发或者AP根据场景自动识别)，通过MIPI向DDIC芯片发送变频指令，相应的，DDIC芯片根据变频指令调节显示屏刷新率的过程如图3所示。
步骤301，进入待机(Standby)模式。
步骤302，检测是否收到唤醒(Sleep out)或上电(Power on)指令。若检测到，则执行步骤303；若未检测到，则执行步骤301。
步骤303，根据帧频寄存器所存档位进行显示屏参数初始化。
其中，帧频寄存器中存储有显示屏所支持的帧频档位(即刷新率档位)，比如，该帧频寄存器中存储的档位包括60Hz/90Hz/120Hz。相应的，初始化的显示屏参数包括VFP、EM-Pulse-No、Gamma以及Demura。比如，DDIC芯片根据60Hz这一帧频档位对应的显示屏参数进行初始化。
步骤304，根据初始化的帧频进行TE信号翻转。
其中，TE信号在Vact时拉低，在Vporch时拉高。
步骤305，接收AP发送的MIPI数据。
其中，该MIPI数据为AP侧渲染的图像数据，该MIPI数据是AP检测到TE信号上升沿，且图像数据准备好时通过MIPI发送的。
步骤306，在VBP后拉低TE信号，并进行Gate和EM扫描。
其中，在进行Gate和EM扫描时，DDIC控制EM-Timing与匹配Gate-Timing。
步骤307，完成Gate扫描后拉高TE信号，EM扫描持续进行。
步骤308，检测是否接收到AP发送的变频指令。若接收到变频指令，则执行步骤309；若未接收到变频指令，则执行步骤310。
步骤309，根据变频指令调整显示屏参数。
可选的，变频指令中包含目标帧频，DDIC即从帧频寄存器中获取目标帧频对应的目标显示屏参数，并根据该目标显示屏参数进行参数调整，降低变频对画面显示造成的影响。
步骤310，继续使用原有的显示屏参数。
若为接收到变频指令，DDIC芯片继续根据初始化后的显示屏参数进行图像扫描。
步骤311，检测是否接收到AP发送的MIPI数据。若接收到AP发送的MIPI数据，则执行步骤312；若未接收到AP发送的MIPI数据，则执行步骤313。
步骤312，在VBP后拉低TE信号，并根据当前MIPI数据进行Gate和EM扫描。
若接收到AP发送的新的MIPI数据，DDIC芯片即根据该MIPI数据，控制显示屏进行画面更新。
步骤313，在VBP后拉低TE信号，并根据历史MIPI数据进行Gate和EM扫描。
若未接收到AP发送的新的MIPI数据，DDIC芯片即根据上一帧图像对应的MIPI数据，重复显示上一帧画面。
步骤314，完成Gate扫描后拉高TE信号，EM扫描持续进行。
步骤315，检测是否收到下电(Power off)或休眠(Sleep in)指令。若检测到，则结束流程，若未检测到，则循环执行步骤308。
显然，采用上述手动变频方案时，用户(或者AP)需要根据当前应用场景确定降低或提高显示屏的 刷新频率，并通过手动触发。比如，当使用终端阅读电子书时，由于电子书阅读场景下多为显示静态文字，因此用户手动将显示屏的刷新频率设置为30Hz；当使用终端进行游戏时，由于游戏场景下多为高帧率的动态画面，因此用户手动将显示屏的刷新率设置为120Hz。
然后，上述调整流程复杂(尤其是在快速滑动场景下，比如系统桌面滑动场景)，且准确性较低(用户人为判断刷新频率切换时机存在错误)。
为了解决上述技术问题，本申请实施例提供了一种自适应变频(Adaptive Frame Rate，AFR)方案，在该方案下，DDIC芯片在等待AP发送图像数据的过程中，通过VFP自动延迟机制，在检测到AP渲染速度过慢时，自动降低Panel的刷新率，实现了Panel侧刷新率与AP侧渲染速率的自适应匹配，降低Panel功耗；此外，在检测到AP渲染速度提高时，自动提高Panel的刷新率，提高画面显示流畅度。
整个调整过程均由DDIC芯片根据AP侧的渲染速率自动完成(并非由AP发送的变频指令触发)，无需用户手动触发，简化了调整流程，并提高了变频的准确性和及时性。下面采用示意性的实施例进行说明。
请参考图4，其示出了本申请一个示例性实施例示出的显示屏变频方法的流程图。本实施例以该方法应用于OLED显示屏的DDIC芯片来举例说明。该方法包括：
步骤401，根据第一刷新频率初始化显示屏参数。
本申请实施例中，OLED显示屏支持至少两种刷新频率。在一种可能的实施方式中，待机模式下，当接收到唤醒指令或上电指令时(比如由在熄屏状态下点亮屏幕时)，DDIC芯片即根据帧频寄存器中存储的默认档位(即第一刷新频率)进行显示屏参数初始化。
在一个示意性的例子中，OLED显示屏支持60Hz、90Hz和120Hz三种刷新频率，DDIC芯片即根据120Hz对应的显示屏参数进行参数初始化。
可选的，DDIC芯片初始化的显示屏参数包括Gamma参数和Demura参数，相应的，DDIC芯片即根据第一刷新频率对应的Gamma参数和Demura参数进行初始化。
步骤402，当接收到AP发送的第一图像数据时，根据第一刷新频率进行图像扫描。
可选的，图像扫描包括Gate扫描和EM扫描。
在一种可能的实施方式中，完成显示屏参数初始化后，若接收到AP发送的图像数据，DDIC芯片即根据第一刷新频率，控制AMOLED显示屏进行图像扫描。
可选的，由于AP可能会向DDIC芯片发送除图像数据以外的数据，因此本申请实施例中，DDIC芯片接收到AP发送的数据后，对数据进行解析，当解析到0x2C时，确定该数据为图像数据。
需要说明的是，在进行图像扫描时，DDIC芯片需要保持Gate-Timing与EM-Timing的时序匹配，满足OLED显示屏对EM的要求。
步骤403，若在第一刷新频率对应的VFP的预设延迟时长内未接收到AP发送的第二图像数据，则将第一刷新频率调整为第二刷新频率，第二刷新频率小于第一刷新频率。
不同于相关技术中，显示屏变频由AP主导，DDIC芯片在接收到AP下发的变频指令后才能进行被动变频，本申请实施例中，DDIC芯片在等待AP发送下一帧图像的图像数据(即第二图像数据)过程中，根据内置VFP超时(Timeout)计时器确定图像数据是否发送超时，若发送未超时(即在第一刷新频率对应的VFP时长内接收到第二图像数据)，则继续按照第一刷新频率进行图像更新；若发送超时(在第一刷新频率对应的VFP的预设延迟时长内未接收到第二图像数据，即在第一刷新频率对应的VFP内未接收到第二图像数据，且在该VFP后的预设延迟时长内仍未接收到第二图像数据)，则确定AP侧图像渲染速率低于显示屏当前的刷新频率，从而调整OLED显示屏的刷新频率。
在一种可能的实施方式中，DDIC芯片将第一刷新频率调整为第二刷新频率时，第二刷新频率为OLED显示屏支持的最低刷新频率，即DDIC芯片直接将刷新频率降低至最低，或者，第二刷新频率为第一刷新频率的下一级刷新频率，即DDIC芯片逐级将刷新频率降低至最低。
在一个示意性的例子中，当OLED显示屏设置有三种刷新频率，分别为60Hz、90Hz和120Hz时，DDIC芯片首先以120Hz进行图像扫描，若在120Hz这一刷新频率对应VFP的预设延迟时长内未接收到AP发送的第二图像数据，则将OLED显示屏的刷新频率调整为90Hz。
步骤404，根据第二刷新频率调整显示屏参数。
为了避免大范围降频对画面显示造成的影响，在一种可能的实施方式中，DDIC芯片调整显示屏的刷新频率后，根据帧频寄存器中第二刷新频率对应的显示屏参数进行参数调整。
示意性的，第一刷新频率(120Hz)对应的显示参数分别为Gamma_120Hz和Demura_120Hz，当将第一刷新频率调整为第二刷新频率(90Hz)时，DDIC芯片将显示参数调整为Gamma_90Hz和Demura_90Hz。
显然，相较于相关技术中需要由AP主动发送变频指令以触发DDIC芯片进行变频，本实施例中，AP与固定帧频(即显示屏固定刷新频率)下的工作流程保持一致，无需向DDIC芯片下发变频指令，DDIC 芯片也可以根据AP侧的渲染速率，在用户无感知的情况下实现自适应调节显示屏的刷新频率，免去了AP下发变频指令的流程。并且，AP发送图像数据时，无需严格匹配DDIC芯片的时序，且无需进行变频逻辑判断，简化了变频过程中AP的处理流程。
综上所述，本申请实施例中，DDIC芯片根据OLED显示屏的第一刷新频率进行显示屏参数初始化，并根据第一刷新频率对AP发送的第一图像数据进行图像扫描，若在第一刷新频率对应VFP的预设延迟时长内未接收到AP发送的第二图像数据，即AP的图像渲染速度下降时，DDIC芯片则下调OLED显示屏的刷新频率，并相应调整显示屏参数；通过引入VFP自动延迟机制，并根据AP传输图像数据的速度，自适应调整显示屏的刷新频率，使得显示屏的刷新频率与AP的图像渲染速度相匹配，从而实现了OLED显示屏的自适应动态变频，有助于降低OLED显示屏的功耗。
在一个示意性的应用场景下，将上述实施例提供的显示屏变频方法应用与配置有AMOLED显示屏的终端后，用户点亮显示屏后，AP低速渲染静态系统桌面，此时，DDIC芯片自动将显示屏的刷新频率调整为60Hz。
当用户点击系统桌面上游戏应用图标后，AP以最高渲染速率渲染游戏画面，此时DDIC芯片根据AP的渲染速率，将显示屏的刷新频率提高至120Hz，保证游戏画面的流畅性。
当退出游戏应用时，由于AP的画面渲染速率降低，因此DDIC芯片将刷新频率由120Hz逐级下调至60Hz。若用户在系统桌面进行滑动操作过程，AP提高画面渲染速率，相应的，DDIC芯片自动将显示屏的刷新频率提高至120Hz，提高滑动时系统桌面的流畅性。
在一种可能的实施方式中，根据第一刷新频率进行图像扫描，包括：
根据第一刷新频率对应的VFP产生V sync；
将第一个ESTV与VBP进行时序匹配，并根据EM频率进行EM扫描，VBP的位置根据V sync的位置确定；
将第一个GSTV与第一个ESTV进行时序匹配，并根据第一刷新频率进行Gate扫描。
在一种可能的实施方式中，若在第一刷新频率对应的VFP的预设延迟时长内未接收到AP发送的第二图像数据，则将第一刷新频率调整为第二刷新频率，包括：
若在第一刷新频率对应的VFP内未接收到第二图像数据，则自动延长VFP；
若延长时长达到预设延迟时长，且未接收到第二图像数据，则将第一刷新频率调整为第二刷新频率，预设延迟时长根据第二刷新频率对应的VFP确定。
在一种可能的实施方式中，将第一刷新频率调整为第二刷新频率之后，所述方法还包括：
根据下一个ESTV的位置调整VFP，其中，调整VFP后GSTV与下一个ESTV的时序匹配。
在一种可能的实施方式中，所述方法还包括：
在图像扫描完成后置高TE信号，并保持TE信号处于高电平状态，AP用于在检测到TE信号处于高电平状态时下发已生成的图像数据。
在一种可能的实施方式中，根据第一刷新频率初始化显示屏参数之后，所述方法还包括：
根据第一刷新频率进行TE信号翻转，AP用于在检测到TE信号的上升沿时确定是否存在已生成的图像数据；
根据第一刷新频率进行图像扫描之后，所述方法还包括：
根据预设翻转频率进行TE信号翻转，预设翻转频率高于第一刷新频率。
在一种可能的实施方式中，所述方法还包括：
接收AP下发的EM变频指令；
根据EM变频指令调节EM频率，其中，调节后的EM频率为当前刷新频率的整数倍。
在一种可能的实施方式中，根据第二刷新频率调整显示屏参数之后，所述方法还包括：
若在第一刷新频率对应的VFP内接收到AP发送的第三图像数据，则将第二刷新频率调整为第一刷新频率；
根据第一刷新频率调整显示屏参数。
在一种可能的实施方式中，第一刷新频率为OLED显示屏的最高刷新频率。
在一种可能的实施方式中，将第一刷新频率调整为第二刷新频率，包括：
采用逐级调整方式，将第一刷新频率调整为第二刷新频率，第二刷新频率和第一刷新频率为相邻刷新频率。
在一种可能的实施方式中，所述方法用于移动终端中OLED显示屏的DDIC芯片。
相关技术中，为满足AMOLED显示屏对EM的严苛要求，需要保证EM-Timing匹配Gate-Timing，而采用本申请实施例提供的方法调节显示屏刷新频率时，DDIC芯片以EM-Timing和EM-FR为主导，不再需要匹配Gate-Timing而是由Gate-Timing主动匹配EM-Timing的时序。
并且，当AP渲染出现短暂延迟时，为了使AP渲染完成的图像数据能够及时下发至DDIC芯片进行图像扫描，DDIC芯片对TE信号的产生方式进行适应性调整。
此外，除了大范围变频这种场景下，存在部分小范围变频场景(即AP的渲染速率存在小幅度延迟)。相关技术中，在小范围变频场景下，AP在检测到TE上升沿后，检测图像数据是否准备完毕，若准备完毕，则通过MIPI向DDIC芯片下发该图像数据；若未准备完毕，则计算超时时长(即还需要多久能够准备完毕)，并通过MIPI向DDIC芯片发送超时指令(Timeout Command)，以便由DDIC芯片根据超时指令调整相关参数。
在一个示意性的例子中，DDIC芯片进行小范围变频的过程如图5所示。
步骤501，进入待机模式。
步骤502，检测是否收到唤醒或上电指令。若检测到，则执行步骤503；若未检测到，则执行步骤501。
步骤503，根据帧频寄存器所存档位进行显示屏参数初始化。
步骤504，根据初始化的帧频进行TE信号翻转。
步骤505，接收AP发送的MIPI数据。
步骤506，在VBP后拉低TE信号，并进行Gate和EM扫描。
步骤507，完成Gate扫描后拉高TE信号，EM扫描持续进行。
步骤508，检测是否接收到AP发送的超时指令。若接收到超时指令，则执行步骤509；若未接收到超时指令，则执行步骤510。
步骤509，根据超时指令调整相关参数。
可选的，由于小范围变频对Gamma和Demura的影响可以忽略不计，因此DDIC芯片根据超时指令调节的相关参数为VFP和EM-Pulse-No。
步骤510，继续使用原有的参数。
步骤511，检测是否接收到AP发送的MIPI数据。若接收到AP发送的MIPI数据，则执行步骤512；若未接收到AP发送的MIPI数据，则执行步骤513。
步骤512，在VBP后拉低TE信号，并根据当前MIPI数据进行Gate和EM扫描。
若接收到AP发送的新的MIPI数据，DDIC芯片即根据该MIPI数据，控制显示屏进行画面更新。
步骤513，在VBP后拉低TE信号，并根据历史MIPI数据进行Gate和EM扫描。
若未接收到AP发送的新的MIPI数据，DDIC芯片即根据上一帧图像对应的MIPI数据，重复显示上一帧画面。
步骤514，完成Gate扫描后拉高TE信号，EM扫描持续进行。
步骤515，检测是否收到下电(Power off)或休眠(Sleep in)指令。若检测到，则结束流程，若未检测到，则循环执行步骤508。
然而，采用上述方式实现小范围变频时，AP计算超时时长时不仅需要考虑渲染速度，还需要考虑EM时序，保证GSTV与ESTV严格匹配，计算过程复杂。并且，上述小范围变频模式与大范围变频模式无法同时进行。
而本申请实施例中，能够兼容小范围变频方案与大范围变频方案，扩大了显示屏变频的应用场景。下面采用示意性的实施例进行说明。
请参考图6，其示出了本申请另一个示例性实施例示出的显示屏变频方法的流程图。本实施例以该方法应用于OLED显示屏的DDIC芯片来举例说明。该方法包括：
步骤601，根据第一刷新频率初始化显示屏参数。
在一种可能的实施方式中，DDIC芯片将OLED显示屏支持的最大刷新频率确定为第一刷新评论，并进行显示屏参数初始化。
步骤602，根据第一刷新频率进行TE信号翻转。
本实施例中，完成显示屏参数初始化后，DDIC芯片即根据第一刷新频率进行TE信号翻转，在Vact期间拉低TE信号(即TE信号在Vact期间保持低电平)，在Vporch期间拉高TE信号(即TE信号在Vporch期间保持高电平)。
相应的，AP进行TE高电平状态检测(完成图像数据渲染后进行检测)，若检测到TE信号处于高电平状态，则通过MIPI向DDIC芯片发送图像数据；若检测到TE信号处于低电平状态，则继续进行TE高电平状态检测。
在一个示意性的例子中，DDIC芯片按照120Hz进行TE信号翻转。
步骤603，当接收到AP发送的第一图像数据时，根据第一刷新频率对应的VFP产生V sync。
当接收到AP发送的第一图像数据时，为了使图像渲染和图像显示保持一致，DDIC芯片根据第一刷新频率产生V sync，以便AP根据V sync进行图像渲染。可选的，由于Vporch中V sync、VBP和Vact通常保持不变，因此DDIC芯片根据第一刷新频率对应的VFP确定V sync的时序位置，从而产生V sync。
在一个示意性的例子中，DDIC芯片根据120Hz对应的VFP产生V sync。
步骤604，将第一个ESTV与VBP进行时序匹配，并根据EM频率进行EM扫描，VBP的位置根据V sync的位置确定。
其中，EM频率是第一刷新频率的整数倍。
不同于相关技术中EM信号匹配Gate信号的时序，本实施例中，DDIC芯片首先对第一个ESTV进行时序匹配(与VBP匹配)，然后将第一个GSTV(栅极起始信号)与第一个ESTV进行时序匹配。
其中，在匹配ESTV时序时，DDIC根据V sync的时序位置以及的V sync时长确定VBP的时序位置，然后将第一个ESTV(的关闭状态)与VBP进行时序匹配。
完成ESTV时序匹配后，DDIC芯片按照EM频率进行EM扫描，并保持频率不变。此外，本申请实施例中，EM频率为显示屏刷新频率的整数倍，比如，当显示屏的刷新频率包括1Hz、30Hz、60Hz、90Hz、120Hz时，EM频率为360Hz。
步骤605，将第一个GSTV与第一个ESTV进行时序匹配，并根据第一刷新频率进行Gate扫描。
在匹配GSTV时序时，DDIC芯片即将第一个GSTV与第一个ESTV进行时序匹配，满足OLED显示屏对EM的要求。
完成GSTV时序匹配后，DDIC芯片根据第一刷新频率进行Gate扫描，从而将第一图像数据对应的图像显示在OLED显示屏上。需要说明的是，开始Gate扫描时，DDIC芯片将TE信号拉低，避免AP在Gate扫描过程中下发图像数据；当完成Gate扫描时，DDIC将TE信号拉高，以便AP下发准备好的图像数据。
步骤606，在图像扫描完成后置高TE信号，并保持TE信号处于高电平状态，AP用于在检测到TE信号处于高电平状态时下发已生成的图像数据。
本申请实施例中，由于AP只有在检测到TE信号处于高电平状态时，才能将准备好的图像数据下发至DDIC芯片，而本申请实施例中，变频过程由DDIC芯片完全控制，若仍旧根据第一刷新频率进行TE信号翻转，AP准备好的图像数据下发将会产生延迟，因此，本申请实施例中，DDIC芯片完成对第一图像数据的显示后，置高TE信号并保持TE信号处于高电平状态，使得AP能够在准备好图像数据后及时发送图像数据。
步骤607，若在第一刷新频率对应的VFP内未接收到第二图像数据，则自动延长VFP。
在一种可能的实施方式中，DDIC芯片等待第二图像数据的过程中，根据第一刷新频率对应的VFP设置超时定时器；当超时定时器达到定时器时长时，DDIC芯片确定AP侧渲染速率低于显示屏的刷新频率，并自动延长VFP。比如，DDIC芯片根据120Hz对应的VFP_120Hz设置超时定时器。
其中，在DDIC芯片以行(Horizon)扫描时长为单位延长VFP。
若在预设延迟时长内未接收到第二图像数据，则执行步骤608至610；若在预设延迟时长内接收到第二图像数据，则执行步骤611至612。
步骤608，若延长时长达到预设延迟时长，且未接收到第二图像数据，则将第一刷新频率调整为第二刷新频率，预设延迟时长根据第二刷新频率对应的VFP确定。
可选的，为了避免变频范围过大导致显示异常，DDIC芯片采用逐级调整方式，将第一刷新频率调整为第二刷新频率，第二刷新频率和第一刷新频率为相邻刷新频率。比如当对于支持1/30/60/90/120Hz五种刷新频率的显示屏，当第一刷新频率为120Hz时，第二刷新频率为90Hz。
在一种可能的实施方式中，当延长时长达到预设延迟时长，但是DDIC芯片仍未接收到AP发送的第二图像数据时，DDIC芯片确定需要大范围降低显示屏的刷新频率，从而将第一刷新频率调整为第二刷新频率。
可选的，DDIC芯片中存储有精确计算得到的延长时长，在自动延长VFP时，DDIC芯片即根据延长时长设置并启动定时器。相应的，若在定时器时长内未接收到第二图像数据，DDIC芯片则将第一刷新频率调整为第二刷新频率。
在一种可能的实施方式中，对于支持1/30/60/90/120Hz五种刷新频率的显示屏而言，DDIC芯片存储有第一VFP延长时长、第二VFP延长时长、第三VFP延长时长和第四VFP延长时长，其中，第一VFP延长时长根据90Hz以及120Hz对应的VFP计算得到(比如VFP_90Hz-VFP_120Hz)，第二VFP延长时长根据60Hz以及90Hz对应的VFP计算得到(比如VFP_60Hz-VFP_90Hz)，第三VFP延长时长根据600Hz以及30Hz对应的VFP计算得到(比如VFP_30Hz-VFP_60Hz)，第四VFP延长时长根据1Hz以及30Hz 对应的VFP计算得到(比如VFP_1Hz-VFP_30Hz)。
相应的，若在VFP_120Hz内未接收到第二图像帧数据，DDIC芯片即根据第一VFP延长时长设置第一定时器。若在第一定时器的定时器时长内未接收到第二图像帧数据，则将显示屏的刷新频率由120Hz调整为90Hz，并根据第二VFP延长时长设置第二定时器。若在第二定时器的定时器时长内未接收到第二图像帧数据，则将显示屏的刷新频率由90Hz调整为60Hz，以此类推，直至调节至最低刷新频率(一直未收到第二图像数据的情况下)。
步骤609，根据下一个ESTV的位置调整VFP，其中，调整VFP后GSTV与下一个ESTV的时序匹配。
为了避免变频对画面造成影响，调节刷屏频率同时，DDIC芯片仍旧需要保持GSTV与ESTV之间的时序匹配。在一种更可能的实施方式中，DDIC芯片根据下一个ESTV的位置，调整VFP的时长，使调后GSTV与下一个ESTV的时序匹配。
步骤610，根据第二刷新频率调整显示屏参数。
本步骤的实施方式可以参考上述步骤404，本实施例在此不再赘述。并且本步骤与步骤609之间并不存在严格的时序关系，即步骤609可以与步骤610共同执行，本实施例对此不做限定。
步骤611，若在第一刷新频率对应的VFP的预设延迟时长内接收到AP发送的第二图像数据，则获取当前时刻与第n个ESTV的下降沿之间的时间间隔，第n个ESTV是当前时刻的下一个ESTV。
若在VFP延迟时长内接收到AP下发的第二图像数据，表明AP渲染存在小幅度延迟，即此时并不需要调整显示屏的刷新频率。此时，为了满足显示屏对EM的严格要求，DDIC芯片获取当前时刻(即接收到第二图像数据的时刻)与下一个ESTV的下降沿之间的时间间隔(EM_Distance)，以便后续基于该时间间隔对VFP进行调整。
需要说明的是，在获取时间间隔时，DDIC芯片需要拉低TE。
步骤612，根据时间间隔调整VFP，其中，调整VFP后GSTV与ESTV的时序匹配。
为了使GSTV能够匹配ESTV的时序，DDIC芯片需要调整VFP时长，使得GSTV与ESTV的时序匹配，进而根据第二图像数据控制显示屏进行图像更新。
在一种可能的实施方式中，本步骤可以包括如下子步骤。
一、获取第一刷新频率对应的VFP、V sync与VBP的时长之和。
可选的，在调整VFP时，DDIC芯片获取第一刷新频率对应的VFP、V sync与VBP各自对应的时长，并计算三者的时长之和(VFP+V synsc+VBP)。
进一步的，DDIC芯片检测该时间间隔是否大于时长之和，若大于，表明可以在下一个ESTV之前完成图像更新准备，从而执行步骤二；若小于，表明在下一个ESTV之前无法完成图像更新准备，从而执行步骤三。
二、若时间间隔大于时长之和，则采用第一方式调整VFP，其中，采用第一方式调整VFP后，GSTV与第n个ESTV的时序匹配。
若EM_Distance≥VFP+V synsc+VBP，DDIC芯片则调整VFP时长，使调整后GSTV与下一个ESTV的时序匹配。
三、若时间间隔小于时长之和，则采用第二方式调整VFP，其中，采用第二方式调整VFP后，GSTV与第n+1个ESTV的时序匹配。
若EM_Distance＜VFP+V synsc+VBP，DDIC芯片确定需要延迟一个EM信号周期，从而调整VFP时长，使调整后GSTV与下下一个ESTV的时序匹配。
需要说明的是，由于小幅度变频对Gamma和Demura的影响较小(可以忽略不计)，因此通过上述步骤611和612调整VFP的同时，可以保持显示屏的刷新频率保持不变。
本实施例中，DDIC芯片通过VFP延迟机制，当识别出AP侧图像渲染速率存在大范围延迟时，自动下调显示屏的刷新频率以降低功耗；而在识别出AP侧图像渲染速率存在小范围延迟时，保持当前刷新频率并调整VFP保证GSTV和ESTV时序匹配，使DDIC芯片能够同时兼容小范围变频与大范围变频，扩大了自适应变频的应用场景。
上述实施例中，以DDIC芯片在显示屏刷新频率高于AP侧的图像渲染速率时，自动降低显示屏刷新频率以降低功耗为例进行说明，在其他可能的应用场景下，当显示屏刷新频率低于AP侧的图像渲染速率时，为了提高画面显示的流畅度，DDIC芯片需要自动进行升频。
在一种可能的实施方式中，DDIC芯片根据第二刷新频率调整显示屏参数之后，若在第一刷新频率对应的VFP内接收到AP发送的第三图像数据，则将第二刷新频率调整为第一刷新频率，并根据第一刷新频率调整显示屏参数。
其中，DDIC芯片的升频延迟与EM频率相关，当EM频率为480Hz时升频延迟为2.1ms，当EM频 率为360Hz时升频延迟为2.8ms，能够达到实时升频的效果。
比如，当DDIC芯片将显示屏的刷新频率由120Hz下调至90Hz后，若在VFP_120Hz(小于VFP_90Hz)内接收到AP发送的第三图像数据，表明AP侧的渲染速率提高，相应的，DDIC芯片对显示屏进行升频，将刷新频率由90Hz上调至120Hz，使得图像刷新速率与图像渲染速率相匹配，提高画面的流畅度。
在一个示意性的例子中，对于设置有1/30/60/90/120Hz五种刷新频率，且EM频率为360Hz的AMOLED显示屏，如图7所示，DDIC芯片进行动态变频的过程包括如下步骤。
步骤701，进入待机模式。
步骤702，检测是否收到唤醒或上电指令。若检测到，则执行步骤703；若未检测到，则执行步骤701。
步骤703，根据最高刷新频率(如120Hz)初始化显示屏参数(如Gamma_120Hz和Demura_120Hz)。
步骤704，根据初始化的最高刷新频率进行TE信号翻转。
步骤705，接收AP发送的第一图像数据。
步骤706，按照最高刷新频率产生V sync。
步骤707，将第1个ESTV匹配VBP，并按照预设EM-FR(如360Hz)进行EM扫描；同时将第1个GSTV匹配第一个ESTV的时序，开始Gate扫描并拉低TE。
步骤708，Gate扫描结束(即Vact后)后置高TE，并保持高电平状态。
步骤709，自动延长VFP，等待第二图像数据。
步骤710，检测是否在VFP延迟时长内接收到第二图像数据。若接收到，则执行步骤711，若未接收到，则执行步骤715。
步骤711，计算当前时刻到下一个ESTV下降沿的距离EM_Distance，并拉低TE。
步骤712，检测EM_Distance是否大于等于VFP+V sync+VBP。若大于等于，则执行步骤713，若小于，则执行步骤714。
步骤713，调整VFP，使GSTV匹配下一个ESTV。
步骤714，调整VFP，使GSTV匹配下下一个ESTV。
步骤715，检测是否在次高刷新率(如90Hz)对应的VFP延迟时长内接收到第二图像数据。若接收到，则执行步骤716；若未接收到，则执行步骤717。
步骤716，将当前显示屏参数调整为次高刷新率(如90Hz)对应的显示屏参数(如Gamma_90Hz和Demura_90Hz)。
步骤717，检测是否在中档刷新率(如60Hz)对应的VFP延迟时长内接收到第二图像数据。若接收到，则执行步骤718；若未接收到，则执行步骤719。
步骤718，将当前显示屏参数调整为中档刷新率(如60Hz)对应的显示屏参数(如Gamma_60Hz和Demura_60Hz)。
步骤719，检测是否在次低刷新率(如30Hz)对应的VFP延迟时长内接收到第二图像数据。若接收到，则执行步骤720；若未接收到，则执行步骤721。
步骤720，将当前显示屏参数调整为次低刷新率(如30Hz)对应的显示屏参数(如Gamma_30Hz和Demura_30Hz)。
步骤721，检测是否在最低刷新率(如1Hz)对应的VFP延迟时长内接收到第二图像数据。若接收到，则执行步骤722；若未接收到，则返回执行步骤709。
步骤722，将当前显示屏参数调整为最低刷新率(如1Hz)对应的显示屏参数(如Gamma_1Hz和Demura_1Hz)。
步骤723，拉低TE信号并调整VFP，使GSTV匹配下一个ESTV。
步骤724，完成Gate扫描(即Vact后)后置高TE信号，EM扫描持续进行。
步骤725，检测是否收到下电或休眠指令。若检测到，则结束流程，若未检测到，则循环执行步骤709。
需要说明的是，本申请实施例仅以显示屏设置有五种变频档位，对应的Gate-FR分别为1/30/60/90/120HzHz，且EM-FR为360Hz为例进行示意性说明，在其他可能的实施方式中，显示屏也可以设置三种、四种或五种以上变频档位(比如在1Hz至30Hz之间设置15Hz档位)，并保证EM-FR为Gate-FR的整数倍即可，本申请实施例并不对变频档位的数量、Gate-FR以及EM-FR的频率构成限定。
在刷新频率稳定的场景下(比如视频播放场景下刷新频率稳定在48Hz)，为了保证画面显示质量，需要保证EM-FR是Gate-FR的整数倍，然而，由于OLED显示屏的变频范围较广(尤其是LTPO AMOLED显示屏)，DDIC芯片无法保证EM-FR是所有Gate-FR的整数倍(比如360Hz EM-FR并不是48Hz Gate-FR的整数倍)。
为了解决上述问题，本申请实施例中，AP根据当前场景下图像的刷新频率以及DDIC芯片的EM-FR，在EM-FR不是当前刷新频率的整数倍时，向DDIC芯片下发EM变频指令，指示DDIC芯片对EM-FR进行调整，保证调整后EM-FR是当前刷新频率(即Gate-FR)的整数倍。
示意性，AP向DDIC芯片下发EM变频指令的过程如图8所示。
步骤801，检测图像数据是否渲染完成。
不同于相关技术中，AP在检测到TE信号上升沿后，检测图像数据是否渲染完成(Frame buffer ready)，本实施例中，AP侧首先检测图像数据是否渲染完成，若渲染完成，则执行步骤802，若未渲染完成，则再次执行步骤801。
步骤802，检测TE信号是否处于高电平状态。
不同于相关技术中，AP在检测到TE信号上升沿时，向DDIC芯片发送图像数据，本实施例中，DDIC芯片会在Vporch期间将TE信号保持为高电平状态，相应的，AP通过检测TE信号的电平状态，确定是否向DDIC芯片下发图像数据。若检测到TE信号处于高电平状态，则执行步骤803；若检测到TE信号处于低电平状态，则再次执行步骤802。
步骤803，检测是否需要调节EM频率。
在一种可能的实施方式中，AP获取当前场景下图像的刷新频率以及DDIC芯片当前的EM频率，若EM频率为刷新频率的整数倍，则确定无需调节EM频率，并执行步骤805；若EM频率不是刷新频率的整数倍，则确定需要调节EM频率，并执行步骤804。
步骤804，向DDIC芯片下发EM变频指令。
其中，该EM变频指令通过MIPI下发。
在一种可能的实施方式中，AP下发的EM变频指令中包括当前刷新频率，相应的，DDIC芯片接收AP下发的EM变频指令，根据EM变频指令中包含的刷新频率，调节EM频率，保证调整后EM频率为当前刷新频率的整数倍。
需要说明的是，DDIC芯片调节EM频率时，保持EM占空比(EM-Duty)不变，从而避免EM频率调节前后显示屏的亮度发生突变。
在一个示意性的例子中，若当前刷新频率为48Hz，DDIC芯片则将EM频率由360Hz调整为480Hz。
步骤805，向DDIC芯片下发图像数据。
进一步的，AP通过MIPI将渲染完成的图像数据下发至DDIC芯片，以便DDIC芯片控制显示屏进行图像刷新。
本实施例中，通过AP向DDIC芯片发送EM变频指令，由DDIC芯片根据EM变频指令调整EM频率，使调整后EM频率为当前刷新频率的整数倍，保证各场景下图像显示的稳定性。
图6所示实施例中，DDIC芯片通过置高TE信号的方式，指示AP下发已生成的图像数据，在另一种可能的实施方式中，DDIC芯片还可以通过高频翻转TE信号的方式，指示AP下发已生成的图像数据。
请参考图9，其示出了本申请另一个示例性实施例示出的显示屏变频方法的流程图。本实施例以该方法应用于OLED显示屏的DDIC芯片来举例说明。该方法包括：
步骤901，根据第一刷新频率初始化显示屏参数。
步骤902，根据第一刷新频率进行TE信号翻转，AP用于在检测到TE信号的上升沿时确定是否存在已生成的图像数据。
本实施例中，完成显示屏参数初始化后，DDIC芯片即根据第一刷新频率进行TE信号翻转，在Vact期间拉低TE信号(即TE信号在Vact期间保持低电平)，在Vporch期间拉高TE信号(即TE信号在Vporch期间保持高电平)。
相应的，AP进行TE上升沿(即TE信号拉高)检测，若检测到TE上升沿，AP则进一步检测图像数据是否准备完毕，若准备完毕，则通过MIPI向DDIC芯片发送图像数据；若检测到TE上升沿，但是图像数据未准备完毕，则继续检测TE上升沿，直到检测到TE上升沿且图像数据准备完毕时，向DDIC芯片发送图像数据。
在一个示意性的例子中，DDIC芯片按照120Hz进行TE信号翻转。
步骤903，当接收到AP发送的第一图像数据时，根据第一刷新频率对应的VFP产生Vsync。
步骤904，将第一个ESTV与VBP进行时序匹配，并根据发光频率进行EM扫描，VBP的位置根据Vsync的位置确定。
步骤905，将第一个GSTV与第一个ESTV进行时序匹配，并根据第一刷新频率进行Gate扫描。
上述步骤903至905的实施方式可以参考步骤603至605，本实施例在此不再赘述。
步骤906，根据预设翻转频率进行TE信号翻转，预设翻转频率高于第一刷新频率。
由于AP只有在检测到TE上升沿时才能将准备好的图像数据下发至DDIC芯片，而本申请实施例中，变频过程由DDIC芯片完全控制，若仍旧根据第一刷新频率进行TE信号翻转，AP准备好的图像数据下发将会产生延迟(比如在检测到第一个TE上升沿时未准备好图像数据，而在第一个TE上升沿后极短时间内准备好图像数据，若按照第一刷新频率进行TE信号翻转，准备好的图像数据需要在下一个TE上升沿时才能下发，延迟较高)，因此，本申请实施例中，DDIC芯片完成对第一图像数据的显示后，控制TE信号按照预设翻转频率进行翻转，从而增加AP侧检测到TE上升沿的频率。
可选的，预设翻转频率为预先设置，且高于第一刷新频率。比如，预设翻转频率为2000Hz/50％占空比的PWM方波。
通过提高TE信号的翻转频率，增加了AP上传图像数据的时机，使得AP渲染好的图像数据能够以较低延迟下发至DDIC芯片，提高图像显示的速率。
步骤907，若在第一刷新频率对应的VFP内未接收到第二图像数据，则自动延长VFP。
步骤908，若延长时长达到VFP延迟时长，且未接收到第二图像数据，则将第一刷新频率调整为第二刷新频率，VFP延迟时长根据第二刷新频率对应的VFP确定。
步骤909，根据下一个ESTV的位置调整VFP，其中，调整VFP后GSTV与下一个ESTV的时序匹配。
步骤910，根据第二刷新频率调整显示屏参数。
步骤911，若在第一刷新频率对应的VFP的预设延迟时长内接收到AP发送的第二图像数据，则获取当前时刻与第n个ESTV的下降沿之间的时间间隔，第n个ESTV是当前时刻的下一个ESTV。
步骤912，根据时间间隔调整VFP，其中，调整VFP后GSTV与ESTV的时序匹配。
上述步骤907至912的实施方式可以参考步骤607至612，本实施例在此不再赘述。
在一个示意性的例子中，对于设置有60/90/120Hz三种刷新频率，且EM频率为360Hz的AMOLED显示屏，如图10所示，DDIC芯片进行动态变频的过程包括如下步骤。
步骤1001，进入待机模式。
步骤1002，检测是否收到唤醒或上电指令。若检测到，则执行步骤1003；若未检测到，则执行步骤1001。
步骤1003，根据最高刷新频率(如120Hz)初始化显示屏参数(如Gamma_120Hz和Demura_120Hz)。
步骤1004，根据初始化的最高刷新频率进行TE信号翻转。
步骤1005，接收AP发送的第一图像数据。
步骤1006，按照最高刷新频率产生Vsync。
步骤1007，将第1个ESTV匹配VBP，并按照预设EM-FR(如360Hz)进行EM扫描；同时将第1个GSTV匹配第一个ESTV的时序，开始Gate扫描并拉低TE。
步骤1008，Gate扫描结束后拉高TE。
步骤1009，按照预设翻转频率和占空比(如2000Hz/50％占空比)翻转TE信号，并自动延长VFP，等待第二图像数据。
步骤1010，检测是否在VFP延迟时长内接收到第二图像数据。若接收到，则执行步骤1011，若未接收到，则执行步骤1015。
步骤1011，计算当前时刻到下一个ESTV下降沿的距离EM_Distance，并拉低TE。
步骤1012，检测EM_Distance是否大于等于VFP+Vsync+VBP。若大于等于，则执行步骤1013，若小于，则执行步骤1014。
步骤1013，调整VFP，使GSTV匹配下一个ESTV。
步骤1014，调整VFP，使GSTV匹配下下一个ESTV。
步骤1015，检测是否在中档刷新率(如90Hz)对应的VFP延迟时长内接收到第二图像数据。若接收到，则执行步骤1016；若未接收到，则执行步骤1017。
步骤1016，将当前显示屏参数调整为中档刷新率(如90Hz)对应的显示屏参数(如Gamma_90Hz和Demura_90Hz)。。
步骤1017，检测是否在最低刷新率(如60Hz)对应的VFP延迟时长内接收到第二图像数据。若接收到，则执行步骤718；若未接收到，则返回执行步骤709。
步骤1018，将当前显示屏参数调整为最低刷新率(如60Hz)对应的显示屏参数(如Gamma_60Hz和Demura_60Hz)。
步骤1019，拉低TE信号并调整VFP，使GSTV匹配下一个ESTV。
步骤1020，完成Gate扫描后拉高TE信号，EM扫描持续进行。
步骤1021，检测是否收到下电或休眠指令。若检测到，则结束流程，若未检测到，则循环执行步骤 1009。
需要说明的是，本申请实施例仅以显示屏设置有三种变频档位，对应的Gate-FR分别为120/90/60Hz，且EM-FR为360Hz为例进行示意性说明，在其他可能的实施方式中，显示屏也可以设置两种变频档位或三种以上变频档位，相应的，还可以采用除120/90/60Hz外的其他Gate-FR(比如30Hz，45Hz等等)，并保证EM-FR为Gate-FR的整数倍即可，本申请实施例并不对变频档位的数量、Gate-FR以及EM-FR的频率构成限定。
总的来说，如表一所示，本申请实施例相较于相关技术提供的显示屏变频方案存在如下区别点和优点。
表一
Figure PCTCN2021071286-appb-000001
在一些实施例中，本申请实施例提供的方法应用于移动终端，即由移动终端中OLED显示屏的DDIC芯片执行上述显示屏变频方法。由于移动终端通常由电池进行供电，且电池的电量有限(对功耗较为敏感)，因此将本申请实施例提供的方法用于移动终端后，在提高移动终端显示质量的同时，能够降低移动终端的功耗。其中，该移动终端可以包括智能手机、平板电脑、可穿戴式设备(比如智能手表)、便携式个人计算机等等，本申请实施例并不对移动终端的具体类型进行限定。
当然，本申请实施例提供的方法还可以用于其他非电池供电的终端，比如电视、显示器或个人计算机等等，本申请实施例对此不作限定。
本申请实施例还提供了一种DDIC芯片，所述DDIC芯片应用于OLED显示屏，所述DDIC芯片用于：
根据第一刷新频率初始化显示屏参数；
当接收到应用处理器AP发送的第一图像数据时，根据所述第一刷新频率进行图像扫描；
若在所述第一刷新频率对应的列向前延间隔VFP的预设延迟时长内未接收到所述AP发送的第二图像数据，则将所述第一刷新频率调整为第二刷新频率，所述第二刷新频率小于所述第一刷新频率；
根据所述第二刷新频率调整所述显示屏参数。
可选的，所述DDIC芯片，用于：
根据所述第一刷新频率对应的VFP产生垂直同步信号V sync；
将第一个发光起始信号ESTV与列向后延间隔VBP进行时序匹配，并根据EM频率进行EM扫描，所述VBP的位置根据所述V sync的位置确定；
将第一个栅极起始信号GSTV与所述第一个ESTV进行时序匹配，并根据所述第一刷新频率进行Gate扫描。
可选的，所述DDIC芯片，用于：
若在所述第一刷新频率对应的VFP内未接收到所述第二图像数据，则自动延长VFP；
若延长时长达到所述预设延迟时长，且未接收到所述第二图像数据，则将所述第一刷新频率调整为所述第二刷新频率，所述预设延迟时长根据所述第二刷新频率对应的VFP确定。
可选的，所述DDIC芯片还用于：
根据下一个ESTV的位置调整VFP，其中，调整VFP后所述GSTV与所述下一个ESTV的时序匹配。
可选的，所述DDIC芯片还用于：
在图像扫描完成后置高撕裂效应TE信号，并保持TE信号处于高电平状态，所述AP用于在检测到 TE信号处于高电平状态时下发已生成的图像数据。
可选的，所述DDIC芯片还用于：
根据所述第一刷新频率进行TE信号翻转，所述AP用于在检测到TE信号的上升沿时确定是否存在已生成的图像数据；
所述根据所述第一刷新频率进行图像扫描之后，所述方法还包括：
根据预设翻转频率进行TE信号翻转，所述预设翻转频率高于所述第一刷新频率。
可选的，所述DDIC芯片还用于：
接收所述AP下发的EM变频指令；
根据所述EM变频指令调节EM频率，其中，调节后的所述EM频率为当前刷新频率的整数倍。
可选的，所述DDIC芯片还用于：
若在所述第一刷新频率对应的VFP内接收到所述AP发送的第三图像数据，则将所述第二刷新频率调整为第一刷新频率；
根据所述第一刷新频率调整所述显示屏参数。
可选的，所述第一刷新频率为所述OLED显示屏的最高刷新频率。
可选的，所述DDIC芯片，用于：
采用逐级调整方式，将所述第一刷新频率调整为所述第二刷新频率，所述第二刷新频率和所述第一刷新频率为相邻刷新频率。
可选的，所述DDIC芯片为移动终端中OLED显示屏的DDIC芯片。
本申请实施例还提供了一种DDIC芯片，所述DDIC芯片应用于OLED显示屏，所述DDIC芯片用于：
根据第一刷新频率初始化显示屏参数；
当接收到应用处理器AP发送的第一图像数据时，根据所述第一刷新频率进行图像扫描；
若在所述第一刷新频率对应的列向前延间隔VFP的预设延迟时长内接收到所述AP发送的第二图像数据，则获取当前时刻与第n个发光起始信号ESTV的下降沿之间的时间间隔，所述第n个ESTV是所述当前时刻的下一个ESTV；
根据所述时间间隔调整VFP，其中，调整VFP后栅极起始信号GSTV与ESTV的时序匹配。
可选的，所述DDIC芯片，用于：
根据所述第一刷新频率对应的VFP产生垂直同步信号V sync；
将第一个ESTV与列向后延间隔VBP进行时序匹配，并根据EM频率进行EM扫描，所述VBP的位置根据所述V sync的位置确定；
将第一个栅极起始信号GSTV与所述第一个ESTV进行时序匹配，并根据所述第一刷新频率进行Gate扫描。
可选的，所述DDIC芯片，用于：
获取所述第一刷新频率对应的VFP、所述Vsync与所述VBP的时长之和；
若所述时间间隔大于所述时长之和，则采用第一方式调整VFP，其中，采用所述第一方式调整VFP后，所述GSTV与所述第n个ESTV的时序匹配；
若所述时间间隔小于所述时长之和，则采用第二方式调整VFP，其中，采用所述第二方式调整VFP后，所述GSTV与第n+1个ESTV的时序匹配。
上述DDIC芯片在实现显示屏变频方法的详细过程可以参考上述各个方法实施例，本实施例在此不再赘述。
此外，本申请实施例还提供了一种显示屏模组，该显示屏模组包括AMOLED显示屏和DDIC芯片，DDIC芯片用于驱动AMOLED显示屏，DDIC芯片用于实现如上述各个方法实施例提供的显示屏变频方法。
请参考图11，其示出了本申请一个示例性实施例提供的终端1100的结构方框图。该终端1100可以是智能手机、平板电脑、笔记本电脑等。本申请中的终端1100可以包括一个或多个如下部件：处理器1110、存储器1120、显示屏模组1130。
处理器1110可以包括一个或者多个处理核心。处理器1110利用各种接口和线路连接整个终端1100内的各个部分，通过运行或执行存储在存储器1120内的指令、程序、代码集或指令集，以及调用存储在存储器1120内的数据，执行终端1100的各种功能和处理数据。可选地，处理器1110可以采用数字信号处理(Digital Signal Processing，DSP)、现场可编程门阵列(Field－Programmable Gate Array，FPGA)、可编程逻辑阵列(Programmable Logic Array，PLA)中的至少一种硬件形式来实现。处理器1110可集成中央处理器(Central Processing Unit，CPU)、图像处理器(Graphics Processing Unit，GPU)、神经网络处理器 (Neural-network Processing Unit，NPU)和调制解调器等中的一种或几种的组合。其中，CPU主要处理操作系统、用户界面和应用程序等；GPU用于负责触摸显示屏模组1130所需要显示的内容的渲染和绘制；NPU用于实现人工智能(Artificial Intelligence，AI)功能；调制解调器用于处理无线通信。可以理解的是，上述调制解调器也可以不集成到处理器1110中，单独通过一块芯片进行实现。
存储器1120可以包括随机存储器(Random Access Memory，RAM)，也可以包括只读存储器(Read-Only Memory，ROM)。可选地，该存储器1120包括非瞬时性计算机可读介质(non-transitory computer-readable storage medium)。存储器1120可用于存储指令、程序、代码、代码集或指令集。存储器1120可包括存储程序区和存储数据区，其中，存储程序区可存储用于实现操作系统的指令、用于至少一个功能的指令(比如触控功能、声音播放功能、图像播放功能等)、用于实现本申请各个方法实施例的指令等；存储数据区可存储根据终端1100的使用所创建的数据(比如音频数据、电话本)等。
显示屏模组1130是用于进行图像显示的显示组件，通常设置在终端1100的前面板。显示屏模组1130可被设计成为全面屏、曲面屏、异型屏、双面屏或折叠屏。显示屏模组1130还可被设计成为全面屏与曲面屏的结合，异型屏与曲面屏的结合，本实施例对此不加以限定。
本申请实施例中，显示屏模组1130包括DDIC芯片1131和显示屏1132(面板)。其中，显示屏1132为OLED显示屏，其可以是低温多晶硅(Low Temperature Poly-Silicon，LTPS)AMOLED显示屏或低温多晶氧化物(Low Temperature Polycrystalline Oxide，LTPO)AMOLED显示屏。
DDIC芯片1131用于驱动显示屏1132进行图像显示，且DDIC芯片1131用于实现上述各个实施例提供的显示屏变频方法。此外，DDIC芯片1131与处理器1110之间通过MIPI接口相连，用于接收处理器1110下发的图像数据以及指令。
在一种可能的实现方式中，该显示屏模组1130还具有触控功能，通过触控功能，用户可以使用手指、触摸笔等任何适合的物体在显示屏模组1130上进行触控操作。
除此之外，本领域技术人员可以理解，上述附图所示出的终端1100的结构并不构成对终端1100的限定，终端可以包括比图示更多或更少的部件，或者组合某些部件，或者不同的部件布置。比如，终端1100中还包括麦克风、扬声器、射频电路、输入单元、传感器、音频电路、无线保真(Wireless Fidelity，WiFi)模块、电源、蓝牙模块等部件，在此不再赘述。
本领域技术人员应该可以意识到，在上述一个或多个示例中，本申请实施例所描述的功能可以用硬件、软件、固件或它们的任意组合来实现。当使用软件实现时，可以将这些功能存储在计算机可读介质中或者作为计算机可读介质上的一个或多个指令或代码进行传输。计算机可读介质包括计算机存储介质和通信介质，其中通信介质包括便于从一个地方向另一个地方传送计算机程序的任何介质。存储介质可以是通用或专用计算机能够存取的任何可用介质。
以上所述仅为本申请的可选实施例，并不用以限制本申请，凡在本申请的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本申请的保护范围之内。

Claims (30)

  1. 一种显示屏变频方法，所述方法用于有机发光二极体OLED显示屏的显示驱动电路DDIC芯片，所述方法包括：
    根据第一刷新频率初始化显示屏参数；
    当接收到应用处理器AP发送的第一图像数据时，根据所述第一刷新频率进行图像扫描；
    若在所述第一刷新频率对应的列向前延间隔VFP的预设延迟时长内未接收到所述AP发送的第二图像数据，则将所述第一刷新频率调整为第二刷新频率，所述第二刷新频率小于所述第一刷新频率；
    根据所述第二刷新频率调整所述显示屏参数。
  2. 根据权利要求1所述的方法，其中，所述根据所述第一刷新频率进行图像扫描，包括：
    根据所述第一刷新频率对应的VFP产生垂直同步信号V sync；
    将第一个发光起始信号ESTV与列向后延间隔VBP进行时序匹配，并根据EM频率进行EM扫描，所述VBP的位置根据所述V sync的位置确定；
    将第一个栅极起始信号GSTV与所述第一个ESTV进行时序匹配，并根据所述第一刷新频率进行Gate扫描。
  3. 根据权利要求2所述的方法，其中，所述若在所述第一刷新频率对应的VFP的预设延迟时长内未接收到所述AP发送的第二图像数据，则将所述第一刷新频率调整为第二刷新频率，包括：
    若在所述第一刷新频率对应的VFP内未接收到所述第二图像数据，则自动延长VFP；
    若延长时长达到所述预设延迟时长，且未接收到所述第二图像数据，则将所述第一刷新频率调整为所述第二刷新频率，所述预设延迟时长根据所述第二刷新频率对应的VFP确定。
  4. 根据权利要求2所述的方法，其中，所述将所述第一刷新频率调整为第二刷新频率之后，所述方法还包括：
    根据下一个ESTV的位置调整VFP，其中，调整VFP后所述GSTV与所述下一个ESTV的时序匹配。
  5. 根据权利要求1至4任一所述的方法，其中，所述方法还包括：
    在图像扫描完成后置高撕裂效应TE信号，并保持TE信号处于高电平状态，所述AP用于在检测到TE信号处于高电平状态时下发已生成的图像数据。
  6. 根据权利要求1至4任一所述的方法，其中，所述根据第一刷新频率初始化显示屏参数之后，所述方法还包括：
    根据所述第一刷新频率进行TE信号翻转，所述AP用于在检测到TE信号的上升沿时确定是否存在已生成的图像数据；
    所述根据所述第一刷新频率进行图像扫描之后，所述方法还包括：
    根据预设翻转频率进行TE信号翻转，所述预设翻转频率高于所述第一刷新频率。
  7. 根据权利要求1至4任一所述的方法，其中，所述方法还包括：
    接收所述AP下发的EM变频指令；
    根据所述EM变频指令调节EM频率，其中，调节后的所述EM频率为当前刷新频率的整数倍。
  8. 根据权利要求1至4任一所述的方法，其中，所述根据所述第二刷新频率调整所述显示屏参数之后，所述方法还包括：
    若在所述第一刷新频率对应的VFP内接收到所述AP发送的第三图像数据，则将所述第二刷新频率调整为第一刷新频率；
    根据所述第一刷新频率调整所述显示屏参数。
  9. 根据权利要求1至4任一所述的方法，其中，所述第一刷新频率为所述OLED显示屏的最高刷新频率。
  10. 根据权利要求9所述的方法，其中，所述将所述第一刷新频率调整为第二刷新频率，包括：
    采用逐级调整方式，将所述第一刷新频率调整为所述第二刷新频率，所述第二刷新频率和所述第一刷新频率为相邻刷新频率。
  11. 根据权利要求1至4任一所述的方法，其中，所述方法用于移动终端中OLED显示屏的DDIC芯片。
  12. 一种显示屏变频方法，所述方法用于有机发光二极体OLED显示屏的显示驱动电路DDIC芯片，所述方法包括：
    根据第一刷新频率初始化显示屏参数；
    当接收到应用处理器AP发送的第一图像数据时，根据所述第一刷新频率进行图像扫描；
    若在所述第一刷新频率对应的列向前延间隔VFP的预设延迟时长内接收到所述AP发送的第二图像数 据，则获取当前时刻与第n个发光起始信号ESTV的下降沿之间的时间间隔，所述第n个ESTV是所述当前时刻的下一个ESTV；
    根据所述时间间隔调整VFP，其中，调整VFP后栅极起始信号GSTV与ESTV的时序匹配。
  13. 根据权利要求12所述的方法，其中，所述根据所述第一刷新频率进行图像扫描，包括：
    根据所述第一刷新频率对应的VFP产生垂直同步信号V sync；
    将第一个ESTV与列向后延间隔VBP进行时序匹配，并根据EM频率进行EM扫描，所述VBP的位置根据所述V sync的位置确定；
    将第一个栅极起始信号GSTV与所述第一个ESTV进行时序匹配，并根据所述第一刷新频率进行Gate扫描。
  14. 根据权利要求13所述的方法，其中，所述根据所述时间间隔调整VFP，包括：
    获取所述第一刷新频率对应的VFP、所述Vsync与所述VBP的时长之和；
    若所述时间间隔大于所述时长之和，则采用第一方式调整VFP，其中，采用所述第一方式调整VFP后，所述GSTV与所述第n个ESTV的时序匹配；
    若所述时间间隔小于所述时长之和，则采用第二方式调整VFP，其中，采用所述第二方式调整VFP后，所述GSTV与第n+1个ESTV的时序匹配。
  15. 一种显示驱动电路DDIC芯片，所述DDIC芯片应用于有机发光二极体OLED显示屏，所述DDIC芯片用于：
    根据第一刷新频率初始化显示屏参数；
    当接收到应用处理器AP发送的第一图像数据时，根据所述第一刷新频率进行图像扫描；
    若在所述第一刷新频率对应的列向前延间隔VFP的预设延迟时长内未接收到所述AP发送的第二图像数据，则将所述第一刷新频率调整为第二刷新频率，所述第二刷新频率小于所述第一刷新频率；
    根据所述第二刷新频率调整所述显示屏参数。
  16. 根据权利要求15所述的DDIC芯片，其中，所述DDIC芯片，用于：
    根据所述第一刷新频率对应的VFP产生垂直同步信号V sync；
    将第一个发光起始信号ESTV与列向后延间隔VBP进行时序匹配，并根据EM频率进行EM扫描，所述VBP的位置根据所述V sync的位置确定；
    将第一个栅极起始信号GSTV与所述第一个ESTV进行时序匹配，并根据所述第一刷新频率进行Gate扫描。
  17. 根据权利要求16所述的DDIC芯片，其中，所述DDIC芯片，用于：
    若在所述第一刷新频率对应的VFP内未接收到所述第二图像数据，则自动延长VFP；
    若延长时长达到所述预设延迟时长，且未接收到所述第二图像数据，则将所述第一刷新频率调整为所述第二刷新频率，所述预设延迟时长根据所述第二刷新频率对应的VFP确定。
  18. 根据权利要求16所述的DDIC芯片，其中，所述DDIC芯片还用于：
    根据下一个ESTV的位置调整VFP，其中，调整VFP后所述GSTV与所述下一个ESTV的时序匹配。
  19. 根据权利要求15至18任一所述的DDIC芯片，其中，所述DDIC芯片还用于：
    在图像扫描完成后置高撕裂效应TE信号，并保持TE信号处于高电平状态，所述AP用于在检测到TE信号处于高电平状态时下发已生成的图像数据。
  20. 根据权利要求15至18任一所述的DDIC芯片，其中，所述DDIC芯片还用于：
    根据所述第一刷新频率进行TE信号翻转，所述AP用于在检测到TE信号的上升沿时确定是否存在已生成的图像数据；
    所述根据所述第一刷新频率进行图像扫描之后，所述方法还包括：
    根据预设翻转频率进行TE信号翻转，所述预设翻转频率高于所述第一刷新频率。
  21. 根据权利要求15至18任一所述的DDIC芯片，其中，所述DDIC芯片还用于：
    接收所述AP下发的EM变频指令；
    根据所述EM变频指令调节EM频率，其中，调节后的所述EM频率为当前刷新频率的整数倍。
  22. 根据权利要求15至18任一所述的DDIC芯片，其中，所述DDIC芯片还用于：
    若在所述第一刷新频率对应的VFP内接收到所述AP发送的第三图像数据，则将所述第二刷新频率调整为第一刷新频率；
    根据所述第一刷新频率调整所述显示屏参数。
  23. 根据权利要求15至18任一所述的DDIC芯片，其中，所述第一刷新频率为所述OLED显示屏的最高刷新频率。
  24. 根据权利要求23所述的DDIC芯片，其中，所述DDIC芯片，用于：
    采用逐级调整方式，将所述第一刷新频率调整为所述第二刷新频率，所述第二刷新频率和所述第一刷新频率为相邻刷新频率。
  25. 根据权利要求15至18任一所述的DDIC芯片，其中，所述DDIC芯片为移动终端中OLED显示屏的DDIC芯片。
  26. 一种显示驱动电路DDIC芯片，所述DDIC芯片应用于有机发光二极体OLED显示屏，所述DDIC芯片用于：
    根据第一刷新频率初始化显示屏参数；
    当接收到应用处理器AP发送的第一图像数据时，根据所述第一刷新频率进行图像扫描；
    若在所述第一刷新频率对应的列向前延间隔VFP的预设延迟时长内接收到所述AP发送的第二图像数据，则获取当前时刻与第n个发光起始信号ESTV的下降沿之间的时间间隔，所述第n个ESTV是所述当前时刻的下一个ESTV；
    根据所述时间间隔调整VFP，其中，调整VFP后栅极起始信号GSTV与ESTV的时序匹配。
  27. 根据权利要求26所述的DDIC芯片，其中，所述DDIC芯片，用于：
    根据所述第一刷新频率对应的VFP产生垂直同步信号V sync；
    将第一个ESTV与列向后延间隔VBP进行时序匹配，并根据EM频率进行EM扫描，所述VBP的位置根据所述V sync的位置确定；
    将第一个栅极起始信号GSTV与所述第一个ESTV进行时序匹配，并根据所述第一刷新频率进行Gate扫描。
  28. 根据权利要求27所述的DDIC芯片，其中，所述DDIC芯片，用于：
    获取所述第一刷新频率对应的VFP、所述Vsync与所述VBP的时长之和；
    若所述时间间隔大于所述时长之和，则采用第一方式调整VFP，其中，采用所述第一方式调整VFP后，所述GSTV与所述第n个ESTV的时序匹配；
    若所述时间间隔小于所述时长之和，则采用第二方式调整VFP，其中，采用所述第二方式调整VFP后，所述GSTV与第n+1个ESTV的时序匹配。
  29. 一种显示屏模组，所述显示屏模组包括有机发光二极体OLED显示屏和显示驱动电路DDIC芯片，所述DDIC芯片用于驱动所述OLED显示屏，所述DDIC芯片用于实现如权利要求1至11任一所述的显示屏变频方法，或，实现如权利要求12至14任一所述的显示屏变频方法。
  30. 一种终端，所述终端包括应用处理器AP、有机发光二极体OLED显示屏和显示驱动电路DDIC芯片，所述AP与所述DDIC芯片之间通过移动产业处理器接口MIPI相连，所述DDIC芯片用于实现如权利要求1至11任一所述的显示屏变频方法，或，实现如权利要求12至14任一所述的显示屏变频方法。
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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113805831A (zh) * 2021-09-15 2021-12-17 Oppo广东移动通信有限公司 图像数据传输方法、装置、终端及介质
CN114333691A (zh) * 2021-12-30 2022-04-12 利亚德光电股份有限公司 图像显示的控制方法、装置以及图像显示设备
CN114648951A (zh) * 2022-02-28 2022-06-21 荣耀终端有限公司 控制屏幕刷新率动态变化的方法及电子设备
CN116700653A (zh) * 2022-02-28 2023-09-05 荣耀终端有限公司 帧率切换方法及相关装置

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111968582B (zh) 2020-01-14 2022-04-15 Oppo广东移动通信有限公司 显示屏变频方法、ddic芯片、显示屏模组及终端
KR20220017296A (ko) * 2020-08-04 2022-02-11 삼성전자주식회사 디스플레이를 포함하는 전자 장치 및 그의 동작 방법
CN111933071B (zh) * 2020-08-10 2022-04-01 昆山国显光电有限公司 显示面板的驱动方法和驱动装置
CN112365839B (zh) * 2020-11-24 2022-04-12 昆山国显光电有限公司 伽马曲线的调节方法、装置以及显示装置
CN112565620A (zh) * 2020-11-26 2021-03-26 京东方科技集团股份有限公司 显示屏幕的光学补偿方法、装置、存储介质及电子设备
CN112365832A (zh) * 2020-12-08 2021-02-12 深圳市华星光电半导体显示技术有限公司 伽玛电压校正方法及装置
CN113178158A (zh) * 2021-04-21 2021-07-27 京东方科技集团股份有限公司 显示面板的驱动方法、装置、存储介质及电子设备
CN113160769A (zh) * 2021-04-25 2021-07-23 Tcl华星光电技术有限公司 显示面板的驱动系统及驱动方法
CN113421512A (zh) * 2021-06-18 2021-09-21 京东方科技集团股份有限公司 一种显示装置的补偿方法和装置
CN115696522A (zh) * 2021-07-21 2023-02-03 荣耀终端有限公司 数据传输方法及可穿戴设备
CN113608713B (zh) * 2021-07-30 2023-09-26 Oppo广东移动通信有限公司 变频显示方法、ddic、显示屏模组及终端
US20230072161A1 (en) * 2021-09-07 2023-03-09 Novatek Microelectronics Corp. Method of display control and related display driver circuit and application processor
CN113805832B (zh) * 2021-09-15 2024-08-06 Oppo广东移动通信有限公司 图像数据传输方法、装置、终端及介质
CN113781949B (zh) * 2021-09-26 2023-10-27 Oppo广东移动通信有限公司 图像显示方法、显示驱动芯片、显示屏模组及终端
CN114020376B (zh) * 2021-09-29 2024-07-23 联想(北京)有限公司 一种处理方法及设备
CN116645933A (zh) * 2021-10-15 2023-08-25 Oppo广东移动通信有限公司 显示屏刷新帧率的调整方法、装置、处理器、芯片和终端
CN114187867A (zh) * 2021-12-10 2022-03-15 北京欧铼德微电子技术有限公司 显示亮度控制方法及装置、电子设备
CN115240594A (zh) * 2022-07-11 2022-10-25 Oppo广东移动通信有限公司 显示屏的控制方法、装置、电子设备及存储介质
CN118298780A (zh) * 2023-01-05 2024-07-05 荣耀终端有限公司 一种刷新率切换方法及电子设备
CN116578261B (zh) * 2023-07-10 2024-03-29 荣耀终端有限公司 电子设备及其显示方法

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08248925A (ja) * 1995-03-10 1996-09-27 Sharp Corp 電子機器
CN105760132A (zh) * 2016-02-03 2016-07-13 广东欧珀移动通信有限公司 实现帧率动态刷新的方法、装置及移动设备
CN106933526A (zh) * 2017-03-10 2017-07-07 广东欧珀移动通信有限公司 一种动态调节屏幕刷新率的方法、装置及移动终端
CN108922466A (zh) * 2018-06-25 2018-11-30 深圳市沃特沃德股份有限公司 屏幕帧率设置方法与装置
CN109272931A (zh) * 2018-11-23 2019-01-25 京东方科技集团股份有限公司 显示面板的显示控制方法、显示控制装置、显示设备
CN110675824A (zh) * 2019-10-09 2020-01-10 京东方科技集团股份有限公司 一种信号输出电路、驱动ic、显示装置及其驱动方法
CN111968582A (zh) * 2020-01-14 2020-11-20 Oppo广东移动通信有限公司 显示屏变频方法、ddic芯片、显示屏模组及终端

Family Cites Families (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100489933C (zh) * 2006-06-09 2009-05-20 友达光电股份有限公司 面板模块及其省电方法
US8451279B2 (en) * 2006-12-13 2013-05-28 Nvidia Corporation System, method and computer program product for adjusting a refresh rate of a display
GB2458958B (en) * 2008-04-04 2010-07-07 Sony Corp Driving circuit for a liquid crystal display
KR20120129335A (ko) * 2011-05-19 2012-11-28 삼성디스플레이 주식회사 화소 및 이를 포함하는 표시장치, 및 그 구동방법
CN103000159B (zh) * 2011-09-13 2015-06-24 联想(北京)有限公司 一种显示控制方法、显示控制装置及显示器
CN102543023B (zh) * 2012-01-10 2014-04-02 硅谷数模半导体（北京）有限公司 接收设备、视频刷新频率的控制方法、装置及系统
US8749541B2 (en) * 2012-04-05 2014-06-10 Apple Inc. Decreasing power consumption in display devices
US20130335309A1 (en) * 2012-06-19 2013-12-19 Sharp Laboratories Of America, Inc. Electronic devices configured for adapting display behavior
US8797340B2 (en) * 2012-10-02 2014-08-05 Nvidia Corporation System, method, and computer program product for modifying a pixel value as a function of a display duration estimate
CN104134415B (zh) * 2013-05-03 2016-12-28 联咏科技股份有限公司 显示方法与显示系统
CN104269155A (zh) * 2014-09-24 2015-01-07 广东欧珀移动通信有限公司 一种调整屏幕刷新频率的方法及装置
KR102290613B1 (ko) * 2015-06-30 2021-08-19 엘지디스플레이 주식회사 유기발광 표시장치와 그 구동방법
KR102485453B1 (ko) * 2015-11-24 2023-01-06 엘지디스플레이 주식회사 표시장치와 이의 구동방법
US10019968B2 (en) * 2015-12-31 2018-07-10 Apple Inc. Variable refresh rate display synchronization
CN106020717B (zh) * 2016-05-05 2020-10-27 联想(北京)有限公司 数据处理方法及电子设备
TWI587280B (zh) * 2016-10-18 2017-06-11 友達光電股份有限公司 信號控制方法與應用此方法的顯示面板
CN106910448B (zh) 2017-02-23 2021-08-10 惠州Tcl移动通信有限公司 一种基于移动终端的显示屏刷新率控制方法及系统
CN107422915B (zh) * 2017-07-26 2019-05-28 Oppo广东移动通信有限公司 触摸屏的响应控制方法、装置、存储介质及终端
TW201915940A (zh) * 2017-10-06 2019-04-16 廣達電腦股份有限公司 雙鏡頭影像處理裝置及方法
CN107799053A (zh) * 2017-11-13 2018-03-13 合肥京东方光电科技有限公司 控制刷新频率的方法和装置、时序控制器、显示装置
CN107818772B (zh) 2017-11-14 2018-09-14 嵊州市万智网络科技有限公司 自适应刷新频率切换方法
KR102509591B1 (ko) * 2018-07-27 2023-03-14 매그나칩 반도체 유한회사 플랫 패널의 구동장치 및 그 구동방법
CN109412704B (zh) * 2018-10-31 2020-08-25 Oppo广东移动通信有限公司 电磁干扰控制方法及相关产品
CN109640168B (zh) * 2018-11-27 2020-07-24 Oppo广东移动通信有限公司 视频处理方法、装置、电子设备和计算机可读介质
CN109597574B (zh) * 2018-11-27 2021-09-24 深圳市酷开网络科技股份有限公司 分布式数据存储方法、服务器及可读存储介质
CN109828686B (zh) * 2019-01-16 2022-06-24 北京集创北方科技股份有限公司 触摸显示屏的控制方法及控制装置
CN110174969A (zh) * 2019-05-28 2019-08-27 Oppo广东移动通信有限公司 控制方法、显示模组和电子设备

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08248925A (ja) * 1995-03-10 1996-09-27 Sharp Corp 電子機器
CN105760132A (zh) * 2016-02-03 2016-07-13 广东欧珀移动通信有限公司 实现帧率动态刷新的方法、装置及移动设备
CN106933526A (zh) * 2017-03-10 2017-07-07 广东欧珀移动通信有限公司 一种动态调节屏幕刷新率的方法、装置及移动终端
CN108922466A (zh) * 2018-06-25 2018-11-30 深圳市沃特沃德股份有限公司 屏幕帧率设置方法与装置
CN109272931A (zh) * 2018-11-23 2019-01-25 京东方科技集团股份有限公司 显示面板的显示控制方法、显示控制装置、显示设备
CN110675824A (zh) * 2019-10-09 2020-01-10 京东方科技集团股份有限公司 一种信号输出电路、驱动ic、显示装置及其驱动方法
CN111968582A (zh) * 2020-01-14 2020-11-20 Oppo广东移动通信有限公司 显示屏变频方法、ddic芯片、显示屏模组及终端

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP4089666A4

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113805831A (zh) * 2021-09-15 2021-12-17 Oppo广东移动通信有限公司 图像数据传输方法、装置、终端及介质
CN113805831B (zh) * 2021-09-15 2024-01-30 Oppo广东移动通信有限公司 图像数据传输方法、装置、终端及介质
CN114333691A (zh) * 2021-12-30 2022-04-12 利亚德光电股份有限公司 图像显示的控制方法、装置以及图像显示设备
CN114648951A (zh) * 2022-02-28 2022-06-21 荣耀终端有限公司 控制屏幕刷新率动态变化的方法及电子设备
CN116700653A (zh) * 2022-02-28 2023-09-05 荣耀终端有限公司 帧率切换方法及相关装置
CN116700653B (zh) * 2022-02-28 2024-03-19 荣耀终端有限公司 帧率切换方法及相关装置

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