WO2022105485A1 - 图像显示方法、ddic芯片、ap、显示屏模组及终端 - Google Patents

图像显示方法、ddic芯片、ap、显示屏模组及终端 Download PDF

Info

Publication number
WO2022105485A1
WO2022105485A1 PCT/CN2021/123585 CN2021123585W WO2022105485A1 WO 2022105485 A1 WO2022105485 A1 WO 2022105485A1 CN 2021123585 W CN2021123585 W CN 2021123585W WO 2022105485 A1 WO2022105485 A1 WO 2022105485A1
Authority
WO
WIPO (PCT)
Prior art keywords
compensation
frame data
ddic chip
image
image frame
Prior art date
Application number
PCT/CN2021/123585
Other languages
English (en)
French (fr)
Inventor
高延凯
王磊
蔡辉跃
Original Assignee
Oppo广东移动通信有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oppo广东移动通信有限公司 filed Critical Oppo广东移动通信有限公司
Priority to EP21893634.2A priority Critical patent/EP4246950A4/en
Publication of WO2022105485A1 publication Critical patent/WO2022105485A1/zh
Priority to US18/198,517 priority patent/US20230290298A1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N1/00—Scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission; Details thereof
    • H04N1/04—Scanning arrangements, i.e. arrangements for the displacement of active reading or reproducing elements relative to the original or reproducing medium, or vice versa
    • H04N1/047—Detection, control or error compensation of scanning velocity or position
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G09G3/2096—Details of the interface to the display terminal specific for a flat panel
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/003—Details of a display terminal, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G09G5/006—Details of the interface to the display terminal
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • G09G5/395—Arrangements specially adapted for transferring the contents of the bit-mapped memory to the screen
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N1/00—Scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission; Details thereof
    • H04N1/024—Details of scanning heads ; Means for illuminating the original
    • H04N1/028—Details of scanning heads ; Means for illuminating the original for picture information pick-up
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0237—Switching ON and OFF the backlight within one frame
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0247—Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0271—Adjustment of the gradation levels within the range of the gradation scale, e.g. by redistribution or clipping
    • G09G2320/0276—Adjustment of the gradation levels within the range of the gradation scale, e.g. by redistribution or clipping for the purpose of adaptation to the characteristics of a display device, i.e. gamma correction
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2340/00—Aspects of display data processing
    • G09G2340/04—Changes in size, position or resolution of an image
    • G09G2340/0407—Resolution change, inclusive of the use of different resolutions for different screen areas
    • G09G2340/0435—Change or adaptation of the frame rate of the video stream
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00—Aspects of the architecture of display systems
    • G09G2360/18—Use of a frame buffer in a display terminal, inclusive of the display panel
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2370/00—Aspects of data communication
    • G09G2370/10—Use of a protocol of communication by packets in interfaces along the display data pipeline
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2370/00—Aspects of data communication
    • G09G2370/14—Use of low voltage differential signaling [LVDS] for display data communication
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • the embodiments of the present application relate to the field of display technology, and in particular, to an image display method, a Display Driver Integrated Circuit (DDIC) chip, an Application Processor (AP), a display screen module, and a terminal.
  • DDIC Display Driver Integrated Circuit
  • AP Application Processor
  • the DDIC chip can dynamically adjust the refresh rate of the display screen according to the image drawing speed of the AP.
  • the refresh rate of the display screen can be increased to improve the smoothness of the screen;
  • the power consumption of the terminal can be reduced by lowering the refresh rate of the display screen.
  • the DDIC chip in order to avoid screen flickering during large-scale frequency conversion, after the DDIC chip completes the image scanning, it will perform optical compensation in units of frames.
  • the embodiments of the present application provide an image display method, a DDIC chip, an AP, a display screen module, and a terminal, which can reduce display delay while avoiding screen flicker caused by wide-range frequency conversion.
  • the technical solution is as follows:
  • an embodiment of the present application provides an image display method, the method is used for a DDIC chip with a display screen, and the method includes:
  • stop frame compensation In response to the stop compensation instruction issued by the AP, stop frame compensation and wait for the AP to issue image frame data, and the stop compensation instruction is used to instruct the AP to prepare to issue new image frame data;
  • an embodiment of the present application provides an image display method, the method is used for an AP, and the AP is electrically connected to a DDIC chip of a display screen, and the method includes:
  • the DDIC chip is configured to perform image scanning and frame compensation according to the first image frame data
  • Delivering second image frame data to the DDIC chip where the DDIC chip is configured to perform image scanning according to the second image frame data and restore frame compensation.
  • an embodiment of the present application provides a DDIC chip, the DDIC chip is applied to a display screen, and the DDIC chip is used for:
  • stop frame compensation In response to the stop compensation instruction issued by the AP, stop frame compensation and wait for the AP to issue image frame data, and the stop compensation instruction is used to instruct the AP to prepare to issue new image frame data;
  • an embodiment of the present application provides an AP, the AP is electrically connected to a DDIC chip of a display screen, and the AP is used for:
  • the DDIC chip is configured to perform image scanning and frame compensation according to the first image frame data
  • Delivering second image frame data to the DDIC chip where the DDIC chip is configured to perform image scanning according to the second image frame data and restore frame compensation.
  • an embodiment of the present application provides a display screen module, the display screen module includes a display screen and a DDIC chip, the DDIC chip is used to drive the display screen, and the DDIC chip is used to realize the The image display method described in the above aspect.
  • an embodiment of the present application provides a terminal, where the terminal includes an AP, a display screen, and a DDIC chip, and the AP and the DDIC chip pass through a Mobile Industry Processor Interface (MIPI) connected, the DDIC chip is used to implement the image display method on the DDIC chip side as described above, and the AP is used to implement the image display method on the AP side as described above.
  • MIPI Mobile Industry Processor Interface
  • Fig. 1 is the schematic diagram of the image display process under the AP-DDCI-Panel architecture
  • FIG. 2 is a schematic diagram of the implementation of a low-precision ADFR scheme shown in an exemplary embodiment of the present application
  • FIG. 3 is a schematic diagram of the implementation of a high-precision ADFR solution shown in an exemplary embodiment of the present application
  • FIG. 4 shows a flowchart of an image display method according to an exemplary embodiment of the present application
  • FIG. 5 shows an implementation schematic diagram of an implementation process of an image display method according to an exemplary embodiment of the present application
  • FIG. 6 is a flowchart of an interaction process between an AP and a DDIC chip according to an exemplary embodiment of the present application
  • FIG. 7 shows a flowchart of an image display method according to another exemplary embodiment of the present application.
  • FIG. 8 is a schematic diagram of the implementation of a high-precision ADFR scheme shown in another exemplary embodiment of the present application.
  • FIG. 9 shows a flowchart of an image display method according to another exemplary embodiment of the present application.
  • FIG. 10 shows a schematic diagram of an implementation process of an image display method according to another exemplary embodiment of the present application.
  • FIG. 11 shows a structural block diagram of a terminal provided by an exemplary embodiment of the present application.
  • plural refers to two or more.
  • “And/or”, which describes the association relationship of the associated objects, means that there can be three kinds of relationships, for example, A and/or B, which can mean that A exists alone, A and B exist at the same time, and B exists alone.
  • the character “/” generally indicates that the associated objects are an "or" relationship.
  • the AP side first performs layer rendering and rendering through the application (Application, App), and then uses SurfaceFlinger (layer compositor) to draw the resulting image.
  • the layer is synthesized to obtain image data, and then the image data is sent to (written) DDIC through MIPI.
  • the DDIC stores the image data sent by the AP in the buffer (Buffer), and controls the Panel to refresh the image (Display) by scanning (reading) the image data in the Buffer.
  • the DDIC When implementing adaptive frequency conversion, the DDIC will adaptively adjust the refresh rate according to the output frame rate of the AP (that is, the amount of image data the AP sends to the DDIC per unit time, or the speed at which the AP sends image data to the DDIC). For example, when the output frame rate of the AP decreases, the DDIC decreases the refresh rate, and when the output frame rate of the AP increases, the DDIC increases the refresh rate.
  • the output frame rate of the AP that is, the amount of image data the AP sends to the DDIC per unit time, or the speed at which the AP sends image data to the DDIC. For example, when the output frame rate of the AP decreases, the DDIC decreases the refresh rate, and when the output frame rate of the AP increases, the DDIC increases the refresh rate.
  • the tearing effect (TE) signal is a signal generated by the DDIC chip to prevent the tearing problem when the screen is refreshed during the image display process.
  • the DDIC chip When ready to refresh the next frame of image, the DDIC chip generates a TE signal.
  • the AP sends the next frame to the DDIC chip after monitoring the rising edge of the TE signal, or after detecting that the TE signal is in a high state image data.
  • the EM signal is a panel row switch signal used to control whether the current row of pixels emits light.
  • the EM frequency is the reporting frequency for generating the EM signal.
  • the EM frequency is an integer multiple of the Gate frequency, that is, multiple EM switches are performed within one frame of the Gate. For example, when the Gate frequency is 60Hz, the EM frequency is 240Hz.
  • the display frequency conversion technology automatically realized by the DDIC chip within the frequency conversion range is called Adaptive Dynamic Frame Rate (ADFR).
  • the DDIC chip implements ADFR in units of frames, and the TE signal generated by the DDIC chip is consistent with the base frame rate (Base Frame Rate) of the display screen.
  • the AP performs image drawing according to the frequency of the TE signal, Transfer the drawn image frame data to the DDIC chip, and the DDIC chip performs image scanning (or called image updating) according to the image frame data.
  • Perform frame compensation (compensating) wherein the frame compensation is a process of optically compensating the display image according to a gamma (Gamma) parameter, so as to avoid sudden change of image brightness during non-image scanning.
  • Gamma gamma
  • ADFR can be divided into low-precision ADFR and high-precision ADFR.
  • low-precision ADFR is performed in frame units.
  • the DDIC chip reports the TE signal to the AP according to the basic refresh rate (such as 120Hz).
  • the AP detects the rising edge of the TE signal
  • the prepared image frame data is sent to the DDIC chip.
  • Image scanning and frame compensation are performed by the DDIC chip;
  • high-precision ADFR is performed in units of the emission (Emission) cycle of the display screen (one frame can contain multiple Emissions), and the DDIC chip can be refreshed according to the emission (EM) frequency (based on The TE signal is reported to the AP.
  • Emission emission
  • EM emission
  • the AP When the AP detects the rising edge of the TE signal, the AP sends the prepared image frame data to the DDIC chip, and the DDIC chip performs image scanning.
  • the high-precision ADFR reports the TE signal more frequently, so the flexibility of the frequency conversion process can be improved, and the picture delay and freeze can be reduced.
  • each frame contains three emission pulses as an example, as shown in Figure 2, when the low-precision ADFR scheme (120Hz) is used, the DDIC chip will use the low-precision ADFR scheme (120Hz). Report the TE signal to the AP every 8.3ms. When the image frame data is ready and the rising edge of the TE signal is detected, the AP sends the image frame data to the DDIC chip, and the DDIC chip scans the image. After that, frame compensation is performed in units of frames.
  • the DDIC chip needs to perform frequency conversion in units of frames.
  • the AP does not complete the data preparation for the C frame during the first frame compensation of the B frame, but completes the C frame data preparation after the second frame compensation of the B frame starts, it needs to perform the second frame compensation.
  • the image frame data of the C frame can be delivered to the DDIC chip, resulting in a large delay in the image display of the C frame.
  • the DDIC chip When using the high-precision ADFR scheme (360Hz), as shown in Figure 3, the DDIC chip reports the TE signal to the AP every 2.77ms (ie the EM frequency), and the AP is ready when the image frame data is ready and detects the rising edge of the TE signal.
  • the image frame data is sent to the DDIC chip, the image scan is performed by the DDIC chip (the TE signal is kept low during the image scanning process), but the frame compensation cannot be performed in frame units after the image scanning is completed.
  • the DDIC chip performs frequency conversion in units of Emission Pulse.
  • the AP after the AP completes the preparation of the C frame data, because the DDIC chip reports the TE signal to the AP at a high frequency, the AP can detect the rising edge of the TE signal in time, so as to send the image frame data of the C frame to the DDIC chip.
  • the image scanning is performed by the DDIC chip (the TE signal is kept at a low level during the image scanning process) to shorten the image display delay of the C frame.
  • low-precision ADFR can perform frame compensation after image scanning, so as to avoid the problem of picture flicker during large-scale frequency conversion, while high-precision ADFR cannot perform frame compensation, resulting in large-scale frequency conversion.
  • high-precision ADFR cannot perform frame compensation, resulting in large-scale frequency conversion.
  • screen flickering There is a problem with screen flickering.
  • the frequency conversion accuracy of high-precision ADFR is higher than that of low-precision ADFR, so the screen display delay and freeze can be reduced.
  • an embodiment of the present application proposes a scheme compatible with low-precision frame compensation and high-precision frequency conversion.
  • the AP monitors the preparation progress of the image frame data.
  • the image frame data When the image frame data is about to be prepared (that is, before preparing to send the image frame data), it sends a stop compensation command to the DDIC chip, instructing the DDIC chip to stop the frame compensation, and Waiting for the AP to send new image frame data, avoiding the problem that the frame compensation causes the AP to delay sending the image frame data, and reducing the screen display delay; and, when the DDIC chip receives the image frame data sent by the AP, it is scanning the image. Then restore frame compensation again, and wait for the stop compensation command issued by the subsequent AP to avoid the problem of screen flicker caused by large-scale frequency conversion.
  • the DDIC chip performs low-precision ADFR and frame compensation when no new image frame data is received, and performs high-precision ADFR when new image frame data is received, thereby realizing the combination of frame compensation and high-precision frequency conversion.
  • Low-precision ADFR and frame compensation when no new image frame data is received
  • high-precision ADFR when new image frame data is received
  • FIG. 4 shows a flowchart of an image display method according to an exemplary embodiment of the present application.
  • the method is applied to a DDIC chip of a display screen as an example for illustration.
  • the method includes:
  • Step 401 Perform image scanning according to the first image frame data sent by the AP, and perform frame compensation.
  • the DDIC chip after receiving the first image frame data sent by the AP, the DDIC chip is in a low-precision ADFR mode, performs image scanning based on the first image frame data, and performs frame compensation after the image scanning is completed .
  • the DDIC chip performs image scanning and frame compensation on the first image frame data at a frequency corresponding to the low-precision ADFR mode.
  • the DDIC chip performs optical compensation in units of frames, so as to avoid the problem of picture flickering in the process of large-scale frequency conversion.
  • the embodiments of the present application do not limit the specific implementation of frame compensation.
  • the TE signal is reported to the AP according to the TE frequency corresponding to the low-precision ADFR.
  • each frame contains three Emission Pulses as an example, as shown in Figure 5, after the DDIC chip receives the image frame data of the A frame sent by the AP, After the image is scanned and no new image frame data is received, frame compensation is performed on the A frame, and the DDIC chip reports the TE signal to the AP at a frequency of 120Hz every 8.3ms.
  • Step 402 in response to the stop compensation instruction issued by the AP, stop frame compensation and wait for the AP to issue image frame data, and the stop compensation instruction is used to instruct the AP to prepare to issue new image frame data.
  • the AP monitors the drawing progress during the process of image drawing, and when the monitoring reaches a specified drawing stage, the AP determines that new image frame data is about to be issued. In order to avoid a large delay in sending image frame data by the AP due to continuous frame compensation, in this embodiment, the AP sends a stop compensation instruction to the DDIC chip before preparing to send new image frame data.
  • the DDIC chip stops frame compensation, and waits for the AP to deliver image frame data during the stop frame compensation process.
  • the DDIC chip stops frame compensation and enters the high-precision ADFR mode, thereby reporting the TE signal to the AP by using the TE signal reporting method corresponding to the high-precision ADFR.
  • the TE signal reporting mode corresponding to the high-precision ADFR is used to report the TE signal, the delay in sending the image frame data by the AP according to the TE signal is reduced (compared to the low-precision ADFR mode).
  • the DDIC chip when the AP prepares the image frame data of the B frame, the DDIC chip performs frame compensation on the A frame.
  • the DDIC chip stops the frame compensation after completing the current frame compensation, and waits for the AP to send the image frame data of the B frame. Since the AP has completed the preparation of the image frame data of the B frame during the current frame compensation process, when the AP detects the rising edge of the TE signal, the AP sends the B frame image data to the DDIC chip, and the DDIC chip performs the B frame image data. scanning.
  • the DDIC chip receives the stop compensation instruction sent by the AP again, and the DDIC chip stops the frame compensation after completing the current frame compensation.
  • the DDIC chip adjusts the reporting frequency of the TE signal, so that the AP can send the image frame data of the C frame to the DDIC chip in time according to the rising edge position of the TE signal after completing the preparation of the image frame data of the C frame.
  • Step 403 when receiving the second image frame data sent by the AP, perform image scanning according to the second image frame data, and restore frame compensation.
  • the stop compensation command issued by the AP is only valid before the DDIC chip receives the image frame data.
  • the DDIC chip restores frame compensation after receiving the new image frame data sent by the AP, that is, from the high-precision ADFR mode without frame compensation mechanism to the low-precision ADFR mode with frame compensation mechanism.
  • the AP sends a stop compensation instruction to the DDIC chip according to its own image frame data preparation progress, before preparing to send the image frame data, so that the DDIC chip can
  • This command stops frame compensation and prepares to receive image frame data, which can significantly reduce the image display delay caused by frame compensation; and, while reducing the image display delay, the frame compensation mechanism in low-precision ADFR mode is still maintained , to ensure the stability of the picture brightness during the large-scale frequency conversion process, avoid the problem of picture flicker, and improve the picture display quality during the frequency conversion process.
  • the AP when the AP is ready to deliver new image frame data, it sends a stop compensation instruction to the DDIC chip to instruct the DDIC chip to stop frame compensation and wait for the AP to deliver the image frame data, so as to avoid the
  • the frame compensation performed by the DDIC chip causes the AP to delay the delivery of image frame data, which leads to the problem of display delay.
  • the DDIC chip receives the image frame data sent by the AP, the frame compensation is restored after the image scanning is performed to avoid the occurrence of large errors.
  • the problem of screen flicker caused by range frequency conversion.
  • stop frame compensation in response to the stop compensation instruction sent by the AP, stop frame compensation and wait for the AP to send image frame data, including:
  • stop the next frame compensation In response to receiving the stop compensation instruction issued by the AP during the frame compensation process, after the low level of the TE signal ends, stop the next frame compensation, wherein the frame compensation is performed during the low level of the TE signal;
  • the TE signal is reported to the AP in a preset manner, and the preset manner is used to reduce the delay of the AP delivering the image frame data.
  • the DDIC chip reports the TE signal to the AP at the first frequency during the image scanning and frame compensation process
  • reporting the TE signal to the AP in a preset manner including:
  • the TE signal is reported to the AP at the second frequency, the second frequency is higher than the first frequency, and the AP is used to send the image frame data when the rising edge of the TE signal is detected.
  • the EM frequency of the DDIC chip is an integer multiple of the second frequency.
  • the DDIC chip reports the TE signal to the AP at the first frequency during the image scanning and frame compensation process
  • the AP In the process of waiting for the AP to send the image frame data, the AP reports a continuous high-level TE signal to the AP, and the AP is used to send the image frame data when it detects the high level of the TE signal.
  • the method also includes:
  • the frame compensation is resumed.
  • the maximum duration is the duration of a single frame corresponding to the first frequency.
  • the display screen is an organic light emitting diode OLED display screen.
  • the display screen is a low temperature polycrystalline oxide LTPO display screen.
  • the method is used for a DDIC chip of a display screen in a mobile terminal.
  • FIG. 6 the interaction process between the DDIC chip and the AP during the image display process is shown in FIG. 6 .
  • Step 601 the AP delivers the first image frame data to the DDIC chip.
  • Step 602 the DDIC chip performs image scanning according to the first image frame data sent by the application processor AP, and performs frame compensation.
  • Step 603 the AP sends a stop compensation instruction to the DDIC chip, and the stop compensation instruction is used to instruct the AP to prepare to issue new image frame data.
  • Step 604 in response to the stop compensation instruction sent by the AP, the DDIC chip stops frame compensation and waits for the AP to send the image frame data.
  • Step 605 the AP delivers the second image frame data to the DDIC chip.
  • Step 606 when receiving the second image frame data sent by the AP, the DDIC chip performs image scanning according to the second image frame data, and restores frame compensation.
  • the foregoing step 603 may include the following sub-steps.
  • SurfaceFlinger is used to synthesize multiple layers (surfaces) passed by the upper layer (application), where each surface corresponds to a window (window) of the upper layer, such as dialog boxes, status bars, activities ( Activity).
  • each surface corresponds to a window (window) of the upper layer, such as dialog boxes, status bars, activities ( Activity).
  • the AP performs image synthesis through SurfaceFlinger, it indicates that the AP is about to complete the preparation of image frame data. Therefore, in order to notify the DDIC chip in advance to stop frame compensation, the AP generates a stop compensation command when performing image synthesis through SurfaceFlinger.
  • the AP Since there is a certain time interval between sending the stop compensation command and sending the image frame data (that is, the AP still needs to send the image frame data after a period of time), in some embodiments, the AP is powered down when the next TE signal is low.
  • a stop compensation instruction is issued to the DDIC, that is, the DDIC chip receives the stop compensation instruction during the frame compensation process, and the AP prepares the image frame data during the frame compensation process of the DDIC chip.
  • the DDIC chip reports the TE signal to the AP in a preset way (changing the low-precision ADFR mode to report TE signal mode), thereby reducing the delay in sending image frame data by the AP.
  • the DDIC chip can report the TE signal to the AP in a multiple TE (multiple TE) or single TE (single TE) manner during the stop compensation period. Exemplary embodiments are respectively used for description below.
  • FIG. 7 shows a flowchart of an image display method according to another exemplary embodiment of the present application.
  • the method is applied to a DDIC chip of an organic light-emitting diode (Organic Light-Emitting Diode, OLED) display screen for illustration.
  • OLED Organic Light-Emitting Diode
  • Step 701 Perform image scanning according to the first image frame data sent by the AP, and perform frame compensation, wherein the DDIC chip reports the TE signal to the AP at the first frequency during the process of image scanning and frame compensation.
  • the DDIC chip reports the TE signal to the AP according to the first frequency during the image scanning and frame compensation process in the low-precision ADFR mode, and the AP prepares and sends the image frame data according to the TE signal. .
  • the DDIC chip reports the TE signal to the AP at the frequency of 120 Hz during the process of image scanning and frame compensation.
  • Step 702 in response to receiving the stop compensation instruction issued by the AP during the frame compensation process, after the TE signal low level ends, stop the next frame compensation, wherein the frame compensation is performed during the TE signal low level period.
  • the AP sends a stop compensation instruction when the TE signal is at a low level
  • the DDIC chip since the DDIC chip is performing frame compensation during the period when the TE signal is at a low level, in order not to affect the ongoing frame compensation, After the DDIC chip completes the current frame compensation, it stops the next frame compensation after the low level of the TE signal ends.
  • the DDIC chip continues to complete the current frame compensation for the A frame, and when the current TE signal is low After the level ends, stop the next frame compensation for the A frame; if it receives the stop compensation command issued by the AP during the frame compensation for the B frame, the DDIC chip continues to complete the current frame compensation for the B frame, and After the low level of the current TE signal ends, the next frame compensation for the B frame is stopped.
  • Step 703 while waiting for the AP to send the image frame data, report the TE signal to the AP at the second frequency, the second frequency is higher than the first frequency, and the AP is used to send the image frame data when the rising edge of the TE signal is detected.
  • the TE signal is still reported to the AP according to the first frequency in the low-precision ADFR mode, because the reporting frequency of the TE signal is low, it is easy for the AP to miss a TE signal and need to wait for a long time. It takes a long time to receive the next TE signal, so that the prepared image frame data needs to be sent to the DDIC chip after a relatively high delay.
  • the DDIC chip reports the TE signal to the AP at a second frequency higher than the first frequency, that is, the high frequency is performed during the stop frame compensation period.
  • the TE signal is toggled. Because the reporting frequency of TE signals is increased, even if the AP misses a TE signal, it can receive the next TE signal in a short time, so that the image frame data can be sent to the DDIC chip as soon as possible, and the image frame data preparation is completed. Time interval between delivery.
  • the EM frequency (ie, the light-emitting scanning frequency) of the DDIC chip is an integer multiple of the second frequency.
  • the EM frequency of the DDIC chip is 360Hz
  • the DDIC chip will report the TE signal at a frequency of 360Hz during the stop frame compensation period.
  • the AP can send the prepared image frame data after a delay of at most 2.77ms. to the DDIC chip.
  • the DDIC chip reports the TE signal at a frequency of 360Hz, and before receiving the B frame image frame data, a total of one TE signal is reported;
  • the DDIC chip reports the TE signal at a frequency of 360 Hz, and reports two TE signals in total before receiving the C-frame image frame data.
  • the DDIC chip may also report the TE signal according to other frequencies (for example, an integer multiple of the EM frequency), which is not limited in this embodiment.
  • Step 704 when receiving the second image frame data sent by the AP, perform image scanning according to the second image frame data, and restore frame compensation.
  • the DDIC chip when receiving the second image frame data sent by the AP, performs image scanning according to the second image frame data, and restores frame compensation after the image scanning. Report the TE signal.
  • the DDIC chip receives the image frame data of the C frame, it performs image scanning on the C frame, and after the image scanning, the frame compensation is performed in units of frames, and the TE signal reporting frequency of 120 Hz is restored. .
  • the DDIC chip in order to prevent the DDIC chip from waiting for a long time due to prematurely sending a stop compensation command by the AP, when the DDIC chip reports the TE signal to the AP at the second frequency for a duration that reaches the duration threshold, the DDIC chip resumes frame compensation, thereby avoiding The brightness of the picture changes because the frame compensation is not performed for a long time, and the display quality is improved.
  • the duration threshold may be the duration of a single frame corresponding to the first frequency, which is not limited in this embodiment.
  • the DDIC chip increases the reporting frequency of the TE signal during the stop frame compensation period, so that the AP can send the prepared image frame data in time according to the high-frequency TE signal, thereby reducing the screen display delay and realizing high-precision ADFR.
  • the DDIC chip can realize high-precision ADFR through single TE.
  • the AP reports the continuous high-level TE signal to the AP, so that the AP can detect the TE by When the signal level is high, the image frame data is sent in time, thereby reducing the image display delay (but also unable to achieve frame compensation).
  • FIG. 9 shows a flowchart of an image display method according to another exemplary embodiment of the present application.
  • the method is applied to a DDIC chip of a display screen as an example for illustration.
  • the method includes:
  • Step 901 Perform image scanning and frame compensation according to the first image frame data sent by the AP, wherein the DDIC chip reports the TE signal to the AP at the first frequency during the process of image scanning and frame compensation.
  • Step 902 in response to receiving the stop compensation instruction issued by the AP during the frame compensation process, after the TE signal low level ends, stop the next frame compensation, wherein the frame compensation is performed during the TE signal low level period.
  • steps 901 to 902 For the implementation of the foregoing steps 901 to 902, reference may be made to steps 701 to 702, and details are not described herein again in this embodiment.
  • Step 903 in the process of waiting for the AP to send the image frame data, report the continuous high-level TE signal to the AP, and the AP is used to send the image frame data when detecting the high level of the TE signal.
  • multiple high-frequency TE signals are generated during the waiting period for image frame data.
  • the DDIC chip reports a continuous high-level TE signal to the AP during the waiting period for image frame data.
  • the AP sends the image frame data to the DDIC chip by detecting the high level of the TE signal.
  • the continuous high-level TE signal is set to a maximum duration.
  • the DDIC chip executes step 904.
  • Step 904 When the second image frame data sent by the AP is received within the maximum duration of the continuous high-level TE signal
  • the DDIC chip will perform step 905.
  • Step 905 if the continuous high level If the second image frame data delivered by the AP is not received within the maximum duration of the TE signal, frame compensation is restored.
  • the maximum duration is the duration of a single frame corresponding to the first frequency.
  • the DDIC chip performs image scanning and frame compensation at 120 Hz, the DDIC chip reports a continuous high-level TE signal of up to 8.3 ms during the period of waiting for image frame data.
  • the developer may also set the duration according to actual requirements, which is not limited in this embodiment.
  • the DDIC chip when receiving the stop compensation instruction issued by the AP during the frame compensation process for the A frame, the DDIC chip continues to complete the current frame compensation for the A frame, and completes the current frame compensation for the A frame. After the end, stop the next frame compensation for the A frame, and report a continuous high-level TE signal to the AP. Since the AP completes the image frame data preparation during the frame compensation process of the A frame, the DDIC chip receives the image frame data of the B frame at the initial stage of reporting the continuous high-level TE signal, so as to perform the B frame scan, and according to the 120Hz frequency frequency for frame compensation.
  • the DDIC chip When receiving the stop compensation instruction sent by the AP during the frame compensation for the B frame, the DDIC chip stops the next frame compensation for the B frame after completing the current frame compensation for the B frame, and reports the continuous frame to the AP. High level TE signal. Because the AP has not yet completed the image frame data preparation during the frame compensation process of the B frame, the DDIC chip receives the image frame data of the C frame sent by the AP after reporting the continuous high-level TE signal for a period of time.
  • Step 904 when the second image frame data sent by the AP is received within the maximum duration of the continuous high-level TE signal, perform image scanning according to the second image frame data, and restore frame compensation.
  • the DDIC chip When receiving the second image frame data sent by the AP within the maximum duration of the continuous high-level TE signal, the DDIC chip stops reporting the continuous high-level TE signal, and re-reports the TE signal to the AP according to the first frequency. The image scan is thus performed and frame compensation is restored. Among them, the DDIC chip needs to ensure that the gate timing and the EM timing match when performing image scanning.
  • Step 905 if the second image frame data sent by the AP is not received within the maximum duration of the continuous high-level TE signal, restore frame compensation.
  • the DDIC chip restores the frame compensation and re-accords to the The first frequency reports the TE signal and waits for the AP to deliver new image frame data.
  • the DDIC chip when the DDIC chip does not receive the second image frame data sent by the AP within 8.3 ms, the DDIC chip restores frame compensation and re-reports the TE signal at a frequency of 120 Hz.
  • the DDIC chip reports a continuous high level of TE to the AP during the stop frame compensation period, so that the AP can timely deliver the prepared image frame data according to the high level of the TE signal, thereby reducing the screen display delay and achieving high precision ADFR.
  • the DDIC chip restores frame compensation by setting the maximum duration of the continuous high-level TE signal, and when the image frame data is not received within the maximum duration, to avoid the large change of the picture brightness caused by the slow drawing of the AP, and improve the The stability of the screen display during the frequency conversion process is improved.
  • the method provided by the embodiments of the present application is applied to a mobile terminal, that is, the above-mentioned image display method is performed by a DDIC chip of a display screen in the mobile terminal. Since the mobile terminal is usually powered by a battery, and the battery has limited power (sensitive to power consumption), after the method provided by the embodiments of the present application is applied to the mobile terminal, it can be compatible with the frame compensation of low-precision ADFR and the frame compensation of high-precision ADFR. Low display delay, and reduce the power consumption of mobile terminals (dynamic frequency conversion can reduce the power consumption of the display screen).
  • the mobile terminal may include a smart phone, a tablet computer, a wearable device (such as a smart watch), a portable personal computer, etc., and the embodiment of the present application does not limit the specific type of the mobile terminal.
  • the method provided in the embodiment of the present application may also be used for other terminals that are not powered by batteries, such as a television, a monitor, or a personal computer, etc., which is not limited in the embodiment of the present application.
  • the display screen is a low temperature polycrystalline oxide (Low Temperature Polycrystalline Oxide, LTPO) display screen. Due to the particularity of the design of the LTPO display screen, it will flicker during a large-scale frequency conversion, so this can be applied.
  • the solutions provided by the application examples improve the display effect of the large-scale frequency conversion on the LTPO display screen.
  • the embodiment of the present application also provides a DDIC chip, the DDIC chip is applied to a display screen, and the DDIC chip is used for:
  • stop frame compensation In response to the stop compensation instruction issued by the AP, stop frame compensation and wait for the AP to issue image frame data, and the stop compensation instruction is used to instruct the AP to prepare to issue new image frame data;
  • the DDIC chip is used for:
  • stop the next frame compensation In response to receiving the stop compensation instruction issued by the AP during the frame compensation process, after the tearing effect ends at the low level of the TE signal, stop the next frame compensation, wherein the frame compensation is during the low level of the TE signal conduct;
  • the TE signal is reported to the AP in a preset manner, and the preset manner is used to reduce the delay of the AP delivering the image frame data.
  • the DDIC chip is configured to report the TE signal to the AP at the first frequency during image scanning and frame compensation;
  • the DDIC chip is also used for:
  • the AP In the process of waiting for the AP to send the image frame data, report the TE signal to the AP at the second frequency, the second frequency is higher than the first frequency, the AP is used to detect the rise of the TE signal The image frame data is sent along the edge.
  • the luminescence EM frequency of the DDIC chip is an integer multiple of the second frequency.
  • the DDIC chip is configured to report the TE signal to the AP at the first frequency during image scanning and frame compensation;
  • the DDIC chip is also used for:
  • a continuous high-level TE signal is reported to the AP, and the AP is configured to send the image frame data when the high-level TE signal is detected.
  • the DDIC chip is used for:
  • the maximum duration is a single frame duration corresponding to the first frequency.
  • the DDIC chip is a DDIC chip in an OLED display screen.
  • the DDIC chip is a DDIC chip in a low temperature polycrystalline oxide LTPO display screen.
  • the DDIC chip is a DDIC chip of a display screen in a mobile terminal.
  • the embodiment of the present application also provides an AP, the AP is electrically connected to the DDIC chip of the display screen, and the AP is used for:
  • the DDIC chip is configured to perform image scanning and frame compensation according to the first image frame data
  • Delivering second image frame data to the DDIC chip where the DDIC chip is configured to perform image scanning according to the second image frame data and restore frame compensation.
  • the AP is used for:
  • the stop compensation instruction is issued to the DDIC chip.
  • an embodiment of the present application also provides a display screen module, the display screen module includes a display screen and a DDIC chip, the DDIC chip is used to drive the display screen, and the DDIC chip is used to realize the images provided by the above method embodiments. Display method.
  • FIG. 11 shows a structural block diagram of a terminal 1100 provided by an exemplary embodiment of the present application.
  • the terminal 1100 may be a smart phone, a tablet computer, a notebook computer, or the like.
  • the terminal 1100 in this application may include one or more of the following components: a processor 1110, a memory 1120, and a display screen module 1130.
  • the processor 1110 may include one or more processing cores.
  • the processor 1110 uses various interfaces and lines to connect various parts of the entire terminal 1100, and executes the terminal by running or executing the instructions, programs, code sets or instruction sets stored in the memory 1120, and calling the data stored in the memory 1120. 1100's various functions and processing data.
  • the processor 1110 may adopt at least one of digital signal processing (Digital Signal Processing, DSP), field-programmable gate array (Field-Programmable Gate Array, FPGA), and programmable logic array (Programmable Logic Array, PLA). A hardware form is implemented.
  • DSP Digital Signal Processing
  • FPGA Field-Programmable Gate Array
  • PLA programmable logic array
  • the processor 1110 may integrate one or more of a central processing unit (Central Processing Unit, CPU), a graphics processor (Graphics Processing Unit, GPU), a neural network processor (Neural-network Processing Unit, NPU), and a modem, etc.
  • a central processing unit Central Processing Unit, CPU
  • a graphics processor Graphics Processing Unit, GPU
  • a neural network processor Neural-network Processing Unit, NPU
  • a modem etc.
  • the CPU mainly handles the operating system, user interface, and application programs
  • the GPU is used for rendering and drawing the content that the touch display module 1130 needs to display
  • the NPU is used to implement artificial intelligence (AI) functions
  • AI artificial intelligence
  • the modem Used to handle wireless communications. It can be understood that, the above-mentioned modem may not be integrated into the processor 1110, but is implemented by a single chip.
  • the memory 1120 may include random access memory (Random Access Memory, RAM), or may include read-only memory (Read-Only Memory, ROM).
  • the memory 1120 includes a non-transitory computer-readable storage medium.
  • Memory 1120 may be used to store instructions, programs, codes, sets of codes, or sets of instructions.
  • the memory 1120 may include a stored program area and a stored data area, wherein the stored program area may store instructions for implementing an operating system, instructions for at least one function (such as a touch function, a sound playback function, an image playback function, etc.), Instructions and the like used to implement various method embodiments of the present application; the storage data area may store data (such as audio data, phone book) and the like created according to the use of the terminal 1100 .
  • the display screen module 1130 is a display component for displaying images, and is usually disposed on the front panel of the terminal 1100 .
  • the display screen module 1130 can be designed as a full screen, a curved screen, a special-shaped screen, a double-sided screen or a folding screen.
  • the display screen module 1130 can also be designed to be a combination of a full screen and a curved screen, or a combination of a special-shaped screen and a curved screen, which is not limited in this embodiment.
  • the display screen module 1130 includes a DDIC chip 1131 and a display screen 1132 (display panel).
  • the display screen 1132 is an OLED display screen, which may be a low temperature polysilicon (LTPS) AMOLED display screen or a low temperature polycrystalline oxide (Low Temperature Polycrystalline Oxide, LTPO) AMOLED display screen.
  • LTPS low temperature polysilicon
  • LTPO low temperature polycrystalline oxide
  • the DDIC chip 1131 is used to drive the display screen 1132 to perform image display, and the DDIC chip 1131 is used to implement the image display methods provided by the above embodiments.
  • the DDIC chip 1131 is connected with the processor 1110 through a MIPI interface, and is used for receiving image data and instructions issued by the processor 1110 .
  • the display screen module 1130 also has a touch function, and through the touch function, a user can use any suitable object such as a finger, a touch pen and the like to perform a touch operation on the display screen module 1130 .
  • the structure of the terminal 1100 shown in the above drawings does not constitute a limitation on the terminal 1100, and the terminal may include more or less components than those shown in the drawings, or combine some components, or a different arrangement of components.
  • the terminal 1100 further includes components such as a microphone, a speaker, a radio frequency circuit, an input unit, a sensor, an audio circuit, a Wireless Fidelity (WiFi) module, a power supply, and a Bluetooth module, which will not be repeated here.
  • Computer-readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another.
  • a storage medium can be any available medium that can be accessed by a general purpose or special purpose computer.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

一种图像显示方法、DDIC芯片、AP、显示屏模组及终端。该方法用于显示屏的DDIC芯片，该方法包括：根据AP下发的第一图像帧数据进行图像扫描，并进行帧补偿(401)；响应于AP下发的停止补偿指令，停止帧补偿并等待AP下发图像帧数据，停止补偿指令用于指示AP准备下发新的图像帧数据(402)；当接收到AP下发的第二图像帧数据时，根据第二图像帧数据进行图像扫描，并恢复帧补偿(403)。本申请实施例能够在避免因大范围变频导致画面闪烁的情况下，降低显示延迟，提高了变频过程中的图像显示质量。

Description

图像显示方法、DDIC芯片、AP、显示屏模组及终端
本申请要求于2020年11月17日提交的申请号为202011284905.8、发明名称为“图像显示方法、DDIC芯片、AP、显示屏模组及终端”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请实施例涉及显示技术领域，特别涉及一种图像显示方法、显示驱动电路(Display Driver Integrated Circuit，DDIC)芯片、应用处理器(Application Processor，AP)、显示屏模组及终端。
背景技术
随着显示屏技术的不断发展，高刷新率显示屏应运而生，且为了兼顾显示流畅性和功耗，越来越多的高刷新率显示屏开始支持动态变频。
动态变频过程中，DDIC芯片能够根据AP的图像绘制速度，动态调整显示屏的刷新率，在运行高帧率需求应用时，通过上调显示屏的刷新率，提高画面流畅度；在运行低帧率需求应用时，通过下调显示屏的刷新率，降低终端的功耗。并且，为了避免大范围变频过程中画面闪烁，DDIC芯片完成图像扫描后，会以帧为单位进行光学补偿。
发明内容
本申请实施例提供了一种图像显示方法、DDIC芯片、AP、显示屏模组及终端，能够在避免因大范围变频导致画面闪烁的情况下，降低显示延迟。所述技术方案如下：
一方面，本申请实施例提供了一种图像显示方法，所述方法用于有显示屏的DDIC芯片，所述方法包括：
根据AP下发的第一图像帧数据进行图像扫描，并进行帧补偿；
响应于AP下发的停止补偿指令，停止帧补偿并等待所述AP下发图像帧数据，所述停止补偿指令用于指示所述AP准备下发新的图像帧数据；
当接收到所述AP下发的第二图像帧数据时，根据所述第二图像帧数据进行图像扫描，并恢复帧补偿。
另一方面，本申请实施例提供了一种图像显示方法，所述方法用于AP，所述AP与显示屏的DDIC芯片电性相连，所述方法包括：
向所述DDIC芯片下发第一图像帧数据，所述DDIC芯片用于根据所述第一图像帧数据进行图像扫描和帧补偿；
向所述DDIC芯片下发停止补偿指令，所述停止补偿指令用于指示所述AP准备下发新的图像帧数据，所述DDIC芯片用于根据所述停止补偿指令停止帧 补偿并等待所述AP下发图像帧数据；
向所述DDIC芯片下发第二图像帧数据，所述DDIC芯片用于根据所述第二图像帧数据进行图像扫描，并恢复帧补偿。
另一方面，本申请实施例提供了一种DDIC芯片，所述DDIC芯片应用于显示屏，所述DDIC芯片用于：
根据AP下发的第一图像帧数据进行图像扫描，并进行帧补偿；
响应于AP下发的停止补偿指令，停止帧补偿并等待所述AP下发图像帧数据，所述停止补偿指令用于指示所述AP准备下发新的图像帧数据；
当接收到所述AP下发的第二图像帧数据时，根据所述第二图像帧数据进行图像扫描，并恢复帧补偿。
另一方面，本申请实施例提供了一种AP，所述AP与显示屏的DDIC芯片电性相连，所述AP用于：
向所述DDIC芯片下发第一图像帧数据，所述DDIC芯片用于根据所述第一图像帧数据进行图像扫描和帧补偿；
向所述DDIC芯片下发停止补偿指令，所述停止补偿指令用于指示所述AP准备下发新的图像帧数据，所述DDIC芯片用于根据所述停止补偿指令停止帧补偿并等待所述AP下发图像帧数据；
向所述DDIC芯片下发第二图像帧数据，所述DDIC芯片用于根据所述第二图像帧数据进行图像扫描，并恢复帧补偿。
另一方面，本申请实施例提供了一种显示屏模组，所述显示屏模组包括显示屏和DDIC芯片，所述DDIC芯片用于驱动所述显示屏，所述DDIC芯片用于实现如上述方面所述的图像显示方法。
另一方面，本申请实施例提供了一种终端，所述终端包括AP、显示屏和DDIC芯片，所述AP与所述DDIC芯片之间通过移动产业处理器接口(Mobile Industry Processor Interface，MIPI)相连，所述DDIC芯片用于实现如上述方面DDIC芯片侧的图像显示方法，所述AP用于实现如上述方面AP侧的图像显示方法。
附图说明
图1是AP-DDCI-Panel架构下图像显示过程的示意图；
图2是本申请一个示例性实施例示出的低精度ADFR方案的实施示意图；
图3是本申请一个示例性实施例示出的高精度ADFR方案的实施示意图；
图4示出了本申请一个示例性实施例示出的图像显示方法的流程图；
图5示出了本申请一个示例性实施例示出的图像显示方法实施过程的实施示意图；
图6是本申请一个示例性实施例示出的AP与DDIC芯片交互过程的流程图；
图7示出了本申请另一个示例性实施例示出的图像显示方法的流程图；
图8是本申请另一个示例性实施例示出的高精度ADFR方案的实施示意图；
图9示出了本申请另一个示例性实施例示出的图像显示方法的流程图；
图10示出了本申请另一个示例性实施例示出的图像显示方法实施过程的实施示意图；
图11示出了本申请一个示例性实施例提供的终端的结构方框图。
具体实施方式
为使本申请的目的、技术方案和优点更加清楚，下面将结合附图对本申请实施方式作进一步地详细描述。
在本文中提及的“多个”是指两个或两个以上。“和/或”，描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B这三种情况。字符“/”一般表示前后关联对象是一种“或”的关系。
如图1所示，在AP-DDIC-Panel(显示面板)架构下，AP侧首先通过应用程序(Application，App)进行图层绘制渲染，然后通过SurfaceFlinger(图层合成者)对绘制得到的图层进行图层合成得到图像数据，进而通过MIPI将图像数据送显(写入)DDIC。DDIC将AP送显的图像数据存储在缓存器(Buffer)中，并通过扫描(读取)Buffer中的图像数据，控制Panel进行图像刷新显示(Display)。而在实现自适应变频时，DDIC会根据AP的输出帧率(即，AP在单位时间内向DDIC输送图像数据的数量，或者，AP向DDIC输送图像数据的速度)，自适应地调节刷新频率。比如，当AP的输出帧率降低时，DDIC下调刷新频率，而当AP的输出帧率提高时，DDIC则上调刷新频率。
撕裂效应(Tearing Effect，TE)信号是一种由DDIC芯片产生的信号，用于防止图像显示过程中画面刷新时的撕裂问题。当准备好刷新下一帧图像时，DDIC芯片即产生TE信号，可选的，AP在监听到TE信号上升沿，或，检测到TE信号处于高电平状态后，向DDIC芯片发送下一帧图像数据。
发光(Emission，EM)频率：EM信号是一种面板行开关信号，用于控制当前行像素是否发光。相应的，EM频率即为产生EM信号的上报频率。通常情况下，EM频率为Gate频率的整数倍，即在Gate一帧内进行多次EM开关。比如，Gate频率为60Hz时，EM频率为240Hz。
相关技术中，由DDIC芯片在变频范围内自动实现的显示变频技术被称为自适应动态变频(Adaptive Dynamic Frame Rate，ADFR)。在一些实施例中，DDIC芯片以帧为单位在实现ADFR，DDIC芯片产生的TE信号与显示屏的基础刷新率(Base Frame Rate)保持一致，相应的，AP根据TE信号的频率进行图像绘制，并将绘制完成的图像帧数据传输至DDIC芯片，由DDIC芯片根据图像帧数据进行图像扫描(或称为图像更新(updating))，并且，DDIC芯片在相邻两次图像扫描之间，还会进行帧补偿(compensating)，其中，帧补偿是一种根据伽马(Gamma)参数对显示画面进行光学补偿的过程，用于避免非图像扫描期间画面亮度发生突变。
按照变频精度进行划分，ADFR可以被划分为低精度ADFR和高精度ADFR。其中，低精度ADFR以帧为单位进行，DDIC芯片按照基础刷新率(比如120Hz) 向AP上报TE信号，AP在检测到TE信号上升沿时，将准备好的图像帧数据下发至DDIC芯片，由DDIC芯片进行图像扫描和帧补偿；高精度ADFR则以显示屏的发光(Emission)周期为单位(一帧内可以包含多个Emission)进行，DDIC芯片可以按照发光(EM)频率(为基础刷新率的整数倍)向AP上报TE信号，AP在检测到TE信号上升沿时，将准备好的图像帧数据下发至DDIC芯片，由DDIC芯片进行图像扫描。由高精度ADFR相较于低精度ADFR上报TE信号的频率更高，因此可以提高变频过程的灵活度，降低画面延迟和卡顿。
示意性的，以显示屏的基础刷新率为120Hz，且每一帧包含三个发光脉冲(Emission Pulse)为例，如图2所示，当采用低精度ADFR方案时(120Hz)，DDIC芯片以每隔8.3ms向AP上报TE信号，AP则在图像帧数据准备完毕，且检测到TE信号上升沿时，将图像帧数据下发至DDIC芯片，由DDIC芯片进行图像扫描，并在完成图像扫描后，以帧为单位进行帧补偿。
相应的，低精度ADFR方案下，DDIC芯片需要以帧为单位进行变频。图2中，当AP在B帧的第一次帧补偿过程中未完成C帧数据准备，而在B帧的第二次帧补偿开始后完成C帧数据准备时，需要在第二次帧补偿结束后，才能向DDIC芯片下发C帧的图像帧数据，导致C帧的图像显示存在较大的延迟。
而采用高精度ADFR方案时(360Hz)，如图3所示，DDIC芯片每隔2.77ms(即EM频率)向AP上报TE信号，AP则在图像帧数据准备完毕，且检测到TE信号上升沿时，将图像帧数据下发至DDIC芯片，由DDIC芯片进行图像扫描(在图像扫描过程中保持TE信号低电平)，但无法在完成图像扫描后以帧为单位进行帧补偿。
相应的，高精度ADFR方案下，DDIC芯片以Emission Pulse为单位进行变频。图3中，当AP完成C帧数据准备后，由于DDIC芯片向AP上报TE信号的频率较高，因此AP可以及时检测到TE信号上升沿，从而将C帧的图像帧数据下发至DDIC芯片，由DDIC芯片进行图像扫描(在图像扫描过程中保持TE信号低电平)从而缩短C帧的图像显示延迟。
从上述示例性的说明可以看出，低精度ADFR能够在图像扫描后进行帧补偿，从而避免大范围变频过程中画面闪烁问题，而高精度ADFR则无法进行帧补偿，导致大范围变频过程中会出现画面闪烁的问题。但是高精度ADFR的变频精度高于低精度ADFR的变频精度，因此能够降低画面显示延迟和卡顿。
显然，上述低精度和高精度ADFR方案均无法兼顾画面闪烁和显示延迟问题。为了解决上述变频方案存在的问题，本申请实施例提出了一种兼容低精度帧补偿以及高精度变频的方案。该方案中，AP通过监测图像帧数据的准备进度，在图像帧数据即将准备完毕时(即准备下发图像帧数据前)，向DDIC芯片下发停止补偿指令，指示DDIC芯片停止帧补偿，并等待AP下发新的图像帧数据，避免帧补偿导致AP延迟下发图像帧数据的问题，降低了画面显示延迟；并且，当DDIC芯片接收到AP下发的图像帧数据时，在进行图像扫描后再次恢复帧补偿，并等待后续AP下发的停止补偿指令，避免出现因大范围变频导致画面闪烁的问题。
采用本申请实施例提供的方案，DDIC芯片在未接收到新图像帧数据时进行低精度ADFR和帧补偿，在接收到新图像帧数据时进行高精度ADFR，实现了帧补偿与高精度变频的兼容，兼顾大范围变频过程中的图像闪烁以及显示延迟，在降低显示屏功耗的情况下，提高了显示屏的显示效果。下面采用示意性的实施例进行说明。
请参考图4，其示出了本申请一个示例性实施例示出的图像显示方法的流程图。本实施例以该方法应用于显示屏的DDIC芯片来举例说明。该方法包括：
步骤401，根据AP下发的第一图像帧数据进行图像扫描，并进行帧补偿。
在一种可能的实施方式中，DDIC芯片接收到AP下发的第一图像帧数据后，即处于低精度ADFR模式，基于第一图像帧数据进行图像扫描，并在图像扫描完成后进行帧补偿。其中，DDIC芯片以低精度ADFR模式对应的频率对第一图像帧数据进行图像扫描和帧补偿。
可选的，DDIC芯片以帧为单位进行光学补偿，以此避免大范围变频过程中的画面闪烁的问题。本申请实施例并不对帧补偿的具体实施方式进行限定。
可选的，DDIC芯片进行图像扫描和帧补偿的过程中，按照低精度ADFR对应的TE频率，向AP上报TE信号。
示意性的，以显示屏的基础刷新率为120Hz，且每一帧包含三个Emission Pulse为例，如图5所示，DDIC芯片接收到AP下发的A帧的图像帧数据后，对A帧进行图像扫描，并在图像扫描后且未接收到新的图像帧数据时，对A帧进行帧补偿，且DDIC芯片以120Hz的频率，每隔8.3ms向AP上报TE信号。
步骤402，响应于AP下发的停止补偿指令，停止帧补偿并等待AP下发图像帧数据，停止补偿指令用于指示AP准备下发新的图像帧数据。
在一种可能的实施方式中，AP在进行图像绘制的过程中，对绘制进度进行监测，当监测到达到指定绘制阶段时，AP确定即将下发新的图像帧数据。为了避免因继续进行帧补偿，导致AP下发图像帧数据产生较大延迟，本实施例中，AP在准备下发新的图像帧数据时前，向DDIC芯片下发停止补偿指令。
相应的，DDIC芯片接收到停止补偿指令后，即停止帧补偿，并在停止帧补偿过程中等待AP下发图像帧数据。
可选的，DDIC芯片接收到停止补偿指令后，即停止帧补偿并进入高精度ADFR模式，从而采用高精度ADFR对应的TE信号上报方式，向AP上报TE信号。其中，采用高精度ADFR对应的TE信号上报方式上报TE信号时，AP根据TE信号下发图像帧数据的延迟降低(相较于低精度ADFR模式)。
示意性的，如图5所示，AP在准备B帧的图像帧数据时，DDIC芯片对A帧进行帧补偿。当接收到AP下发的停止补偿指令时，DDIC芯片即在完成当前帧补偿后，停止帧补偿，并等待AP下发B帧的图像帧数据。由于在当前帧补偿过程中个，AP即完成了B帧的图像帧数据准备，因此AP在检测到TE信号上升沿时，向DDIC芯片下发B帧的图像数据，由DDIC芯片进行B帧图像扫描。
而在对B帧进行帧补偿过程中，DDIC芯片再次接收到AP下发的停止补偿指令，DDIC芯片即在完成当前帧补偿后，停止帧补偿。停止帧补偿过程中，DDIC芯片调整TE信号的上报频率，使得AP在完成C帧的图像帧数据准备后，能够及时根据TE信号的上升沿位置，向DDIC芯片下发C帧的图像帧数据。
通过比较图2和图5可以明显看出，DDIC芯片根据AP下发的停止补偿指令停止帧扫描后，能够降低后续AP下发图像帧数据的延迟，降低图像绘制到显示之间的时间间隔，从而降低了画面显示延迟。
步骤403，当接收到AP下发的第二图像帧数据时，根据第二图像帧数据进行图像扫描，并恢复帧补偿。
为了避免因无法进行帧补偿，导致大范围变频过程中出现画面闪烁的问题，本申请实施例中，AP下发的停止补偿指令仅在DDIC芯片接收到图像帧数据前有效。
DDIC芯片在接收到AP下发的新的图像帧数据后恢复帧补偿，即由不带帧补偿机制的高精度ADFR模式恢复为带帧补偿机制的低精度ADFR模式。
示意性的，如图5所示，DDIC芯片接收到AP下发的B帧的图像帧数据后，即在完成B帧的图像扫描后，继续在低精度ADFR模式下对B帧进行帧补偿；DDIC芯片接收到AP下发的C帧的图像帧数据后，即在完成C帧的图像扫描后，继续在低精度ADFR模式下对C帧进行帧补偿。
从上述实施例可以看出，采用本申请实施例提供的方案，由AP根据自身的图像帧数据准备进度，在准备下发图像帧数据前，向DDIC芯片下发停止补偿指令，以便DDIC芯片根据该指令停止帧补偿，并做好接收图像帧数据的准备，能够显著降低因帧补偿造成的图像显示延迟；并且，在降低图像显示延迟的同时，仍旧保持了低精度ADFR模式下的帧补偿机制，保证大范围变频过程中画面亮度的稳定性，避免出现画面闪烁的问题，提高了变频过程中的画面显示质量。
综上所述，本申请实施例中，当AP准备下发新的图像帧数据时，通过向DDIC芯片下发停止补偿指令，指示DDIC芯片停止帧补偿并等待AP下发图像帧数据，避免因DDIC芯片进行帧补偿造成AP需要延迟下发图像帧数据，导致显示延迟的问题；同时，当DDIC芯片接收到AP下发的图像帧数据时，在进行图像扫描后恢复帧补偿，避免出现因大范围变频导致画面闪烁的问题。
可选的，响应于AP下发的停止补偿指令，停止帧补偿并等待AP下发图像帧数据，包括：
响应于在帧补偿过程中接收到AP下发的停止补偿指令，在TE信号低电平结束后，停止下一次帧补偿，其中，帧补偿在TE信号低电平期间进行；
在等待AP下发图像帧数据过程中，通过预设方式向AP上报TE信号，预设方式用于降低AP下发图像帧数据的延迟。
可选的，DDIC芯片在图像扫描和帧补偿过程中以第一频率向AP上报TE信号；
在等待所述AP下发图像帧数据过程中，通过预设方式向AP上报TE信号， 包括：
在等待AP下发图像帧数据过程中，以第二频率向所述AP上报TE信号，第二频率高于第一频率，AP用于在检测到TE信号的上升沿时下发图像帧数据。
可选的，DDIC芯片的EM频率为第二频率的整数倍。
可选的，DDIC芯片在图像扫描和帧补偿过程中以第一频率向AP上报TE信号；
在等待AP下发图像帧数据过程中，通过预设方式向AP上报TE信号，包括：
在等待AP下发图像帧数据过程中，向AP上报持续高电平TE信号，AP用于在检测到TE信号高电平时下发图像帧数据。
可选的，当接收到AP下发的第二图像帧数据时，根据第二图像帧数据进行图像扫描，并恢复帧补偿，包括：
当在持续高电平TE信号的最大持续时长内接收到AP下发的第二图像帧数据时，根据第二图像帧数据进行图像扫描，并恢复帧补偿；
该方法还包括：
若在持续高电平TE信号的最大持续时长内未接收到AP下发的第二图像帧数据，则恢复帧补偿。
可选的，最大持续时长为第一频率对应的单帧时长。
可选的，显示屏为有机发光二极管OLED显示屏。
可选的，显示屏为低温多晶氧化物LTPO显示屏。
可选的，该方法用于移动终端中显示屏的DDIC芯片。
结合图4所示的实施例，图像显示过程中DDIC芯片与AP的交互过程如图6所示。
步骤601，AP向DDIC芯片下发第一图像帧数据。
步骤602，DDIC芯片根据应用处理器AP下发的第一图像帧数据进行图像扫描，并进行帧补偿。
步骤603，AP向DDIC芯片下发停止补偿指令，停止补偿指令用于指示AP准备下发新的图像帧数据。
步骤604，响应于AP下发的停止补偿指令，DDIC芯片停止帧补偿并等待AP下发图像帧数据。
步骤605，AP向DDIC芯片下发第二图像帧数据。
步骤606，当接收到AP下发的第二图像帧数据时，DDIC芯片根据第二图像帧数据进行图像扫描，并恢复帧补偿。
关于AP向DDIC芯片下发停止补偿指令的时机，在一种可能的实施方式中，上述步骤603可以包括如下子步骤。
一、通过图层合成者(Surface Flinger)进行图像合成时，生成停止补偿指令。
SurfaceFlinger作为图层合成者，用于对上层(应用程序)传递的多个图层 (surface)进行合成，其中，每个surface对应上层的一个窗口(window)，比如对话框、状态栏、活动(Activity)。当AP通过SurfaceFlinger进行图像合成时，表明AP即将完成图像帧数据准备，因此为了提前通知DDIC芯片停止帧补偿，AP在通过SurfaceFlinger进行图像合成时，生成停止补偿指令。
二、在下一个TE信号低电平时，向DDIC芯片下发停止补偿指令。
由于下发停止补偿指令到下发图像帧数据之间存在一定的时间间隔(即AP仍旧需要经过一段时间才能下发图像帧数据)，因此，在一些实施例中，AP在下一个TE信号低电平时，向DDIC下发停止补偿指令，即DDIC芯片在帧补偿过程接收到停止补偿指令，AP则在DDIC芯片进行帧补偿过程中进行准备图像帧数据。
示意性的，如图5所示，AP通过SurfaceFlinger对B帧图像进行图像合成时，即生成停止补偿指令，并在下一个TE信号低电平时(即在A帧的帧补偿过程中)，向DDIC芯片下发该停止补偿指令；AP通过SurfaceFlinger对C帧图像进行图像合成时，即生成停止补偿指令，并在下一个TE信号低电平时(即在B帧的帧补偿过程中)，向DDIC芯片下发该停止补偿指令。
需要说明的是，上述实施例仅以AP在进行图像合成时生成并下发停止补偿指令为例进行说明，在其他可能的实施方式中，AP也可以在图像帧数据准备过程中的其他阶段下发停止补偿指令(确保在图像帧数据之前下发即可)，本申请实施例并不对停止补偿指令的具体下发时机进行限定。
为了降低AP完成图像帧数据准备到下发图像帧数据之间的延迟，在等待AP下发图像帧数据帧过程中，DDIC芯片通过预设方式向AP上报TE信号(改变低精度ADFR模式下上报TE信号的方式)，以此降低AP下发图像帧数据的延迟。其中，DDIC芯片在停止补偿期间内可以通过多TE(multiple TE)或单TE(single TE)方式向AP上报TE信号。下面分别采用示例性的实施例进行说明。
请参考图7，其示出了本申请另一个示例性实施例示出的图像显示方法的流程图。本实施例以该方法应用于机发光二极体(OrganicLight-Emitting Diode，OLED)显示屏的DDIC芯片来举例说明。该方法包括：
步骤701，根据AP下发的第一图像帧数据进行图像扫描，并进行帧补偿，其中，DDIC芯片在图像扫描和帧补偿过程中以第一频率向AP上报TE信号。
在一种可能的实施方式中，DDIC芯片在低精度ADFR模式下进行图像扫描和帧补偿过程中，按照第一频率向AP上报TE信号，AP即根据该TE信号进行图像帧数据准备和下发。
示意性的，如图5所示，以第一频率为120Hz为例，DDIC芯片在进行图像扫描和帧补偿过程中，以120Hz的频率向AP上报TE信号。
步骤702，响应于在帧补偿过程中接收到AP下发的停止补偿指令，在TE信号低电平结束后，停止下一次帧补偿，其中，帧补偿在TE信号低电平期间进行。
在一种可能的实施方式中，AP在TE信号低电平时下发停止补偿指令时，由于DDIC芯片在TE信号低电平期间正在进行帧补偿，因此，为了不影响正在进行中的帧补偿，DDIC芯片完成当前帧补偿后，在TE信号低电平结束后停止下一次帧补偿。
示意性的，如图5所示，若在对A帧进行帧补偿的过程中接收到AP下发的停止补偿指令，DDIC芯片继续完成对A帧的本次帧补偿，并在当前TE信号低电平结束后，停止对A帧的下一次帧补偿；若在对B帧进行帧补偿的过程中接收到AP下发的停止补偿指令，DDIC芯片继续完成对B帧的本次帧补偿，并在当前TE信号低电平结束后，停止对B帧的下一次帧补偿。
步骤703，在等待AP下发图像帧数据过程中，以第二频率向AP上报TE信号，第二频率高于第一频率，AP用于在检测到TE信号的上升沿时下发图像帧数据。
等待AP下发图像帧数据过程中，若仍旧按照低精度ADFR模式下的第一频率向AP上报TE信号，由于TE信号的上报频率较低，因此容易出现AP错过一个TE信号后，需要等待较长时间才能接收到下一个TE信号，导致已准备好的图像帧数据需要经过较高延迟才能被下发至DDIC芯片。
因此为了提高AP下发图像帧数据的及时性，在等待AP下发图像帧数据时，DDIC芯片以高于第一频率的第二频率向AP上报TE信号，即在停止帧补偿期间进行高频TE信号翻转。由于TE信号的上报频率提高，因此即便AP错过了了一个TE信号，也可以在较短时间内接收到下一个TE信号，从而尽快将图像帧数据下发至DDIC芯片，降低图像帧数据准备完成至下发之间的时间间隔。
在一种可能的实施方式中，为了便于后续对发光时序以及图像扫描时序进行时序匹配，DDIC芯片的EM频率(即发光扫描频率)为第二频率的整数倍。比如，当DDIC芯片的EM频率为360Hz时，DDIC芯片即在停止帧补偿期间以360Hz的频率进行TE信号上报，相应的，AP最多经过2.77ms的延迟即可将准备好的图像帧数据下发至DDIC芯片。
示意性的，如图5所示，在停止对A帧补偿过程中，DDIC芯片以360Hz的频率上报TE信号，在接收到B帧图像帧数据前，共上报一个TE信号；而在停止对B帧补偿过程中，DDIC芯片以360Hz的频率上报TE信号，在接收到C帧图像帧数据前，共上报两个TE信号。
当然，在其他可能的实施方式中，DDIC芯片还可以按照其他频率上报TE信号(比如EM频率的整数倍)，本实施例对此并不构成限定。
步骤704，当接收到AP下发的第二图像帧数据时，根据第二图像帧数据进行图像扫描，并恢复帧补偿。
可选的，当接收到AP下发的第二图像帧数据时，DDIC芯片根据第二图像帧数据进行图像扫描，并在图像扫描后恢复帧补偿，同时，DDIC芯片重新按照第一频率向AP上报TE信号。
示意性的，如图5所示，DDIC芯片接收到C帧的图像帧数据后，对C帧进行图像扫描，并在图像扫描后重新以帧为单位进行帧补偿，恢复120Hz的TE 信号上报频率。
可选的，为了避免因AP过早下发停止补偿指令，导致DDIC芯片长时间等待，当DDIC芯片以第二频率向AP上报TE信号的时长达到时长阈值时，DDIC芯片恢复帧补偿，从而避免因长时间未进行帧补偿导致画面亮度发生变化，提高显示质量。其中，该时长阈值可以为第一频率对应的单帧时长，本实施例对此不作限定。
本实施例中，DDIC芯片通过在停止帧补偿期间提高TE信号的上报频率，使AP能够根据高频TE信号及时下发准备好的图像帧数据，从而降低画面显示延迟，实现高精度ADFR。
在另一种可能的实施方式中，DDIC芯片可以通过single TE实现高精度ADFR。示意性的，如图8所示，DDIC芯片在进行图像扫描后(图中以B帧和C帧为例进行说明)，通过向AP上报持续高电平的TE信号，使AP能够通过检测TE信号高电平及时下发图像帧数据，从而降低图像显示延迟(但是同样无法实现帧补偿)。
基于上述高精度ADFR的实现原理，请参考图9，其示出了本申请另一个示例性实施例示出的图像显示方法的流程图。本实施例以该方法应用于显示屏的DDIC芯片来举例说明。该方法包括：
步骤901，根据AP下发的第一图像帧数据进行图像扫描，并进行帧补偿，其中，DDIC芯片在图像扫描和帧补偿过程中以第一频率向AP上报TE信号。
步骤902，响应于在帧补偿过程中接收到AP下发的停止补偿指令，在TE信号低电平结束后，停止下一次帧补偿，其中，帧补偿在TE信号低电平期间进行。
上述步骤901至902的实施方式可以参考步骤701至702，本实施例在此不再赘述。
步骤903，在等待AP下发图像帧数据过程中，向AP上报持续高电平TE信号，AP用于在检测到TE信号高电平时下发图像帧数据。
不同于上述实施例中，在等待图像帧数据期间产生多个高频TE信号(multiple TE)，本实施例中，DDIC芯片在等待图像帧数据期间向AP上报持续高电平TE信号，相应的，AP通过检测TE信号高电平的方式，向DDIC芯片下发图像帧数据。
可选的，为了避免因AP原因导致图像帧数据长时间未准备完毕，或者，因AP过早下发停止补偿指令，进而导致DDIC芯片长时间等待，持续高电平TE信号设置有最大持续时长。当在最大持续时长内接收到AP下发的图像帧数据，DDIC芯片则执行步骤904，步骤904：当在持续高电平TE信号的最大持续时长内接收到AP下发的第二图像帧数据时，根据第二图像帧数据进行图像扫描，并恢复帧补偿；若在最大持续时长内未接收到AP下发的图像帧数据，DDIC芯片则执行步骤905，步骤905：若在持续高电平TE信号的最大持续时长内未接收到AP下发的第二图像帧数据，则恢复帧补偿。
在一种可能的实施方式中，该最大持续时长为第一频率对应的单帧时长。比如，当DDIC芯片以120Hz进行图像扫描和帧补偿时，DDIC芯片在等待图像帧数据期间上报最长8.3ms的持续高电平TE信号。
当然，除了持续高电平TE信号的持续时长还可以根据实际需求由开发人员进行设置，本实施例对此并不构成限定。
示意性的，如图10所示，当在对A帧进行帧补偿的过程中接收到AP下发的停止补偿指令，DDIC芯片继续完成对A帧的本次帧补偿，并在本次帧补偿结束后，停止对A帧的下一次帧补偿，并向AP上报持续高电平TE信号。由于AP在A帧的帧补偿过程中即完成了图像帧数据准备，因此，DDIC芯片上报持续高电平TE信号初期即接收到B帧的图像帧数据，从而进行B帧扫描，并按照120Hz的频率进行帧补偿。
当在对B帧进行帧补偿的过程中接收到AP下发的停止补偿指令，DDIC芯片继续完成对B帧的本次帧补偿后，停止对B帧的下一次帧补偿，并向AP上报持续高电平TE信号。由于AP在B帧的帧补偿过程中尚未完成图像帧数据准备，因此DDIC芯片在上报持续高电平TE信号一段时间后，接收到AP下发的C帧的图像帧数据。
步骤904，当在持续高电平TE信号的最大持续时长内接收到AP下发的第二图像帧数据时，根据第二图像帧数据进行图像扫描，并恢复帧补偿。
当在持续高电平TE信号的最大持续时长内接收到AP下发的第二图像帧数据时，DDIC芯片即停止上报持续高电平TE信号，并重新按照第一频率向AP上报TE信号，从而进行图像扫描并恢复帧补偿。其中，DDIC芯片在进行图像扫描时需要保证Gate时序与EM时序相匹配。
示意性的，如图10所示，当在8.3ms内接收到AP下发的C帧的图像帧数据，DDIC芯片即在下一个EM下降沿时停止上报高电平TE信号，并进行C帧扫描，并在C帧扫描后，按照120Hz的频率进行帧补偿。
步骤905，若在持续高电平TE信号的最大持续时长内未接收到AP下发的第二图像帧数据，则恢复帧补偿。
若在持续高电平TE信号的最大持续时长内仍未接收到AP下发的第二图像帧数据，为了避免帧补偿停止时间过长导致画面亮度变化，DDIC芯片重新恢复帧补偿，并重新按照第一频率上报TE信号，等待AP下发新的图像帧数据。
示意性的，当DDIC芯片在8.3ms内未接收到AP下发的第二图像帧数据，DDIC芯片则恢复帧补偿，并重新按照120Hz的频率上报TE信号。
本实施例中，DDIC芯片通过在停止帧补偿期间向AP上报持续高电平TE，使AP能够根据TE信号高电平及时下发准备好的图像帧数据，从而降低画面显示延迟，实现高精度ADFR。此外，DDIC芯片通过设置持续高电平TE信号的最大持续时长，并在最大持续时长内未接收到图像帧数据时，恢复帧补偿，避免因AP绘制过慢造成的画面亮度大幅度变化，提高了变频过程中画面显示的稳定性。
总的来说，如表一所示，本申请实施例相较于相关技术提供的方案存在如下区别点和优点。
表一
Figure PCTCN2021123585-appb-000001
在一些实施例中，本申请实施例提供的方法应用于移动终端，即由移动终端中显示屏的DDIC芯片执行上述图像显示方法。由于移动终端通常由电池进行供电，且电池的电量有限(对功耗较为敏感)，因此将本申请实施例提供的方法用于移动终端后，能够兼容低精度ADFR的帧补偿和高精度ADFR的低显示延迟，并降低移动终端的功耗(动态变频可以降低显示屏功耗)。其中，该移动终端可以包括智能手机、平板电脑、可穿戴式设备(比如智能手表)、便携式个人计算机等等，本申请实施例并不对移动终端的具体类型进行限定。
当然，本申请实施例提供的方法还可以用于其他非电池供电的终端，比如电视、显示器或个人计算机等等，本申请实施例对此不作限定。
此外，本申请实施例中，显示屏为低温多晶氧化物(Low Temperature Polycrystalline Oxide，LTPO)显示屏，由于LTPO显示屏设计的特殊性，其在大范围变频时会发生闪烁，因此可以应用本申请实施例提供的方案，提高大范围变频对LTPO显示屏的显示效果。
本申请实施例还提供了一种DDIC芯片，所述DDIC芯片应用于显示屏，所述DDIC芯片用于：
根据AP下发的第一图像帧数据进行图像扫描，并进行帧补偿；
响应于AP下发的停止补偿指令，停止帧补偿并等待所述AP下发图像帧数据，所述停止补偿指令用于指示所述AP准备下发新的图像帧数据；
当接收到所述AP下发的第二图像帧数据时，根据所述第二图像帧数据进行图像扫描，并恢复帧补偿。
可选的，所述DDIC芯片，用于：
响应于在帧补偿过程中接收到所述AP下发的所述停止补偿指令，在撕裂效应TE信号低电平结束后，停止下一次帧补偿，其中，帧补偿在TE信号低电平期间进行；
在等待所述AP下发图像帧数据过程中，通过预设方式向所述AP上报TE信号，所述预设方式用于降低所述AP下发图像帧数据的延迟。
可选的，所述DDIC芯片用于在图像扫描和帧补偿过程中以第一频率向所述AP上报TE信号；
所述DDIC芯片，还用于：
在等待所述AP下发图像帧数据过程中，以第二频率向所述AP上报TE信 号，所述第二频率高于所述第一频率，所述AP用于在检测到TE信号的上升沿时下发图像帧数据。
可选的，所述DDIC芯片的发光EM频率为所述第二频率的整数倍。
可选的，所述DDIC芯片用于在图像扫描和帧补偿过程中以第一频率向所述AP上报TE信号；
所述DDIC芯片，还用于：
在等待所述AP下发图像帧数据过程中，向所述AP上报持续高电平TE信号，所述AP用于在检测到TE信号高电平时下发图像帧数据。
可选的，所述DDIC芯片，用于：
当在所述持续高电平TE信号的最大持续时长内接收到所述AP下发的所述第二图像帧数据时，根据所述第二图像帧数据进行图像扫描，并恢复帧补偿；
若在所述持续高电平TE信号的最大持续时长内未接收到所述AP下发的所述第二图像帧数据，恢复帧补偿。
可选的，所述最大持续时长为所述第一频率对应的单帧时长。
可选的，所述DDIC芯片为OLED显示屏中的DDIC芯片。
可选的，所述DDIC芯片为低温多晶氧化物LTPO显示屏中的DDIC芯片。
可选的，所述DDIC芯片为移动终端中显示屏的DDIC芯片。
本申请实施例还提供了一种AP，所述AP与显示屏的DDIC芯片电性相连，所述AP用于：
向所述DDIC芯片下发第一图像帧数据，所述DDIC芯片用于根据所述第一图像帧数据进行图像扫描和帧补偿；
向所述DDIC芯片下发停止补偿指令，所述停止补偿指令用于指示所述AP准备下发新的图像帧数据，所述DDIC芯片用于根据所述停止补偿指令停止帧补偿并等待所述AP下发图像帧数据；
向所述DDIC芯片下发第二图像帧数据，所述DDIC芯片用于根据所述第二图像帧数据进行图像扫描，并恢复帧补偿。
可选的，所述AP，用于：
通过SurfaceFlinger进行图像合成时，生成所述停止补偿指令；
在下一个TE信号低电平时，向所述DDIC芯片下发所述停止补偿指令。
上述DDIC芯片和AP在实现图像显示方法的详细过程可以参考上述各个方法实施例，本实施例在此不再赘述。
此外，本申请实施例还提供了一种显示屏模组，该显示屏模组包括显示屏和DDIC芯片，DDIC芯片用于驱动显示屏，DDIC芯片用于实现如上述各个方法实施例提供的图像显示方法。
请参考图11，其示出了本申请一个示例性实施例提供的终端1100的结构方框图。该终端1100可以是智能手机、平板电脑、笔记本电脑等。本申请中的终 端1100可以包括一个或多个如下部件：处理器1110、存储器1120、显示屏模组1130。
处理器1110可以包括一个或者多个处理核心。处理器1110利用各种接口和线路连接整个终端1100内的各个部分，通过运行或执行存储在存储器1120内的指令、程序、代码集或指令集，以及调用存储在存储器1120内的数据，执行终端1100的各种功能和处理数据。可选地，处理器1110可以采用数字信号处理(Digital Signal Processing，DSP)、现场可编程门阵列(Field－Programmable Gate Array，FPGA)、可编程逻辑阵列(Programmable Logic Array，PLA)中的至少一种硬件形式来实现。处理器1110可集成中央处理器(Central Processing Unit，CPU)、图像处理器(Graphics Processing Unit，GPU)、神经网络处理器(Neural-network Processing Unit，NPU)和调制解调器等中的一种或几种的组合。其中，CPU主要处理操作系统、用户界面和应用程序等；GPU用于负责触摸显示屏模组1130所需要显示的内容的渲染和绘制；NPU用于实现人工智能(Artificial Intelligence，AI)功能；调制解调器用于处理无线通信。可以理解的是，上述调制解调器也可以不集成到处理器1110中，单独通过一块芯片进行实现。
存储器1120可以包括随机存储器(Random Access Memory，RAM)，也可以包括只读存储器(Read-Only Memory，ROM)。可选地，该存储器1120包括非瞬时性计算机可读介质(non-transitory computer-readable storage medium)。存储器1120可用于存储指令、程序、代码、代码集或指令集。存储器1120可包括存储程序区和存储数据区，其中，存储程序区可存储用于实现操作系统的指令、用于至少一个功能的指令(比如触控功能、声音播放功能、图像播放功能等)、用于实现本申请各个方法实施例的指令等；存储数据区可存储根据终端1100的使用所创建的数据(比如音频数据、电话本)等。
显示屏模组1130是用于进行图像显示的显示组件，通常设置在终端1100的前面板。显示屏模组1130可被设计成为全面屏、曲面屏、异型屏、双面屏或折叠屏。显示屏模组1130还可被设计成为全面屏与曲面屏的结合，异型屏与曲面屏的结合，本实施例对此不加以限定。
本申请实施例中，显示屏模组1130包括DDIC芯片1131和显示屏1132(显示面板)。其中，显示屏1132为OLED显示屏，其可以是低温多晶硅(Low Temperature Poly-Silicon，LTPS)AMOLED显示屏或低温多晶氧化物(Low Temperature Polycrystalline Oxide，LTPO)AMOLED显示屏。
DDIC芯片1131用于驱动显示屏1132进行图像显示，且DDIC芯片1131用于实现上述各个实施例提供的图像显示方法。此外，DDIC芯片1131与处理器1110之间通过MIPI接口相连，用于接收处理器1110下发的图像数据以及指令。
在一种可能的实现方式中，该显示屏模组1130还具有触控功能，通过触控功能，用户可以使用手指、触摸笔等任何适合的物体在显示屏模组1130上进行触控操作。
除此之外，本领域技术人员可以理解，上述附图所示出的终端1100的结构并不构成对终端1100的限定，终端可以包括比图示更多或更少的部件，或者组合某些部件，或者不同的部件布置。比如，终端1100中还包括麦克风、扬声器、射频电路、输入单元、传感器、音频电路、无线保真(Wireless Fidelity，WiFi)模块、电源、蓝牙模块等部件，在此不再赘述。
本领域技术人员应该可以意识到，在上述一个或多个示例中，本申请实施例所描述的功能可以用硬件、软件、固件或它们的任意组合来实现。当使用软件实现时，可以将这些功能存储在计算机可读介质中或者作为计算机可读介质上的一个或多个指令或代码进行传输。计算机可读介质包括计算机存储介质和通信介质，其中通信介质包括便于从一个地方向另一个地方传送计算机程序的任何介质。存储介质可以是通用或专用计算机能够存取的任何可用介质。
以上所述仅为本申请的可选实施例，并不用以限制本申请，凡在本申请的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本申请的保护范围之内。

Claims (26)

  1. 一种图像显示方法，所述方法用于显示屏的显示驱动电路DDIC芯片，所述方法包括：
    根据应用处理器AP下发的第一图像帧数据进行图像扫描，并进行帧补偿；
    响应于AP下发的停止补偿指令，停止帧补偿并等待所述AP下发图像帧数据，所述停止补偿指令用于指示所述AP准备下发新的图像帧数据；
    当接收到所述AP下发的第二图像帧数据时，根据所述第二图像帧数据进行图像扫描，并恢复帧补偿。
  2. 根据权利要求1所述的方法，其中，所述响应于AP下发的停止补偿指令，停止帧补偿并等待所述AP下发图像帧数据，包括：
    响应于在帧补偿过程中接收到所述AP下发的所述停止补偿指令，在撕裂效应TE信号低电平结束后，停止下一次帧补偿，其中，帧补偿在TE信号低电平期间进行；
    在等待所述AP下发图像帧数据过程中，通过预设方式向所述AP上报TE信号，所述预设方式用于降低所述AP下发图像帧数据的延迟。
  3. 根据权利要求2所述的方法，其中，所述DDIC芯片在图像扫描和帧补偿过程中以第一频率向所述AP上报TE信号；
    所述在等待所述AP下发图像帧数据过程中，通过预设方式向所述AP上报TE信号，包括：
    在等待所述AP下发图像帧数据过程中，以第二频率向所述AP上报TE信号，所述第二频率高于所述第一频率，所述AP用于在检测到TE信号的上升沿时下发图像帧数据。
  4. 根据权利要求3所述的方法，其中，所述DDIC芯片的发光EM频率为所述第二频率的整数倍。
  5. 根据权利要求2所述的方法，其中，所述DDIC芯片在图像扫描和帧补偿过程中以第一频率向所述AP上报TE信号；
    所述在等待所述AP下发图像帧数据过程中，通过预设方式向所述AP上报TE信号，包括：
    在等待所述AP下发图像帧数据过程中，向所述AP上报持续高电平TE信号，所述AP用于在检测到TE信号高电平时下发图像帧数据。
  6. 根据权利要求5所述的方法，其中，所述当接收到所述AP下发的第二图像帧数据时，根据所述第二图像帧数据进行图像扫描，并恢复帧补偿，包括：
    当在所述持续高电平TE信号的最大持续时长内接收到所述AP下发的所述 第二图像帧数据时，根据所述第二图像帧数据进行图像扫描，并恢复帧补偿；
    所述方法还包括：
    若在所述持续高电平TE信号的最大持续时长内未接收到所述AP下发的所述第二图像帧数据，则恢复帧补偿。
  7. 根据权利要求6所述的方法，其中，所述最大持续时长为所述第一频率对应的单帧时长。
  8. 根据权利要求1至7任一所述的方法，其中，所述显示屏为有机发光二极管OLED显示屏。
  9. 根据权利要求1至7任一所述的方法，其中，所述显示屏为低温多晶氧化物LTPO显示屏。
  10. 根据权利要求1至7任一所述的方法，其中，所述方法用于移动终端中显示屏的DDIC芯片。
  11. 一种图像显示方法，所述方法用于AP，所述AP与显示屏的DDIC芯片电性相连，所述方法包括：
    向所述DDIC芯片下发第一图像帧数据，所述DDIC芯片用于根据所述第一图像帧数据进行图像扫描和帧补偿；
    向所述DDIC芯片下发停止补偿指令，所述停止补偿指令用于指示所述AP准备下发新的图像帧数据，所述DDIC芯片用于根据所述停止补偿指令停止帧补偿并等待所述AP下发图像帧数据；
    向所述DDIC芯片下发第二图像帧数据，所述DDIC芯片用于根据所述第二图像帧数据进行图像扫描，并恢复帧补偿。
  12. 根据权利要求11所述的方法，其中，所述向所述DDIC芯片下发的停止补偿指令，包括：
    通过SurfaceFlinger进行图像合成时，生成所述停止补偿指令；
    在下一个TE信号低电平时，向所述DDIC芯片下发所述停止补偿指令。
  13. 一种显示驱动电路DDIC芯片，其中，所述DDIC芯片应用于显示屏，所述DDIC芯片用于：
    根据应用处理器AP下发的第一图像帧数据进行图像扫描，并进行帧补偿；
    响应于AP下发的停止补偿指令，停止帧补偿并等待所述AP下发图像帧数据，所述停止补偿指令用于指示所述AP准备下发新的图像帧数据；
    当接收到所述AP下发的第二图像帧数据时，根据所述第二图像帧数据进行图像扫描，并恢复帧补偿。
  14. 根据权利要求13所述的DDIC芯片，其中，所述DDIC芯片，用于：
    响应于在帧补偿过程中接收到所述AP下发的所述停止补偿指令，在撕裂效应TE信号低电平结束后，停止下一次帧补偿，其中，帧补偿在TE信号低电平期间进行；
    在等待所述AP下发图像帧数据过程中，通过预设方式向所述AP上报TE信号，所述预设方式用于降低所述AP下发图像帧数据的延迟。
  15. 根据权利要求14所述的DDIC芯片，其中，所述DDIC芯片用于在图像扫描和帧补偿过程中以第一频率向所述AP上报TE信号；
    所述DDIC芯片，还用于：
    在等待所述AP下发图像帧数据过程中，以第二频率向所述AP上报TE信号，所述第二频率高于所述第一频率，所述AP用于在检测到TE信号的上升沿时下发图像帧数据。
  16. 根据权利要求15所述的DDIC芯片，其中，所述DDIC芯片的发光EM频率为所述第二频率的整数倍。
  17. 根据权利要求14所述的DDIC芯片，其中，所述DDIC芯片用于在图像扫描和帧补偿过程中以第一频率向所述AP上报TE信号；
    所述DDIC芯片，还用于：
    在等待所述AP下发图像帧数据过程中，向所述AP上报持续高电平TE信号，所述AP用于在检测到TE信号高电平时下发图像帧数据。
  18. 根据权利要求17所述的DDIC芯片，其中，所述DDIC芯片，用于：
    当在所述持续高电平TE信号的最大持续时长内接收到所述AP下发的所述第二图像帧数据时，根据所述第二图像帧数据进行图像扫描，并恢复帧补偿；
    若在所述持续高电平TE信号的最大持续时长内未接收到所述AP下发的所述第二图像帧数据，恢复帧补偿。
  19. 根据权利要求18所述的DDIC芯片，其中，所述最大持续时长为所述第一频率对应的单帧时长。
  20. 根据权利要求13至19任一所述的DDIC芯片，其中，所述DDIC芯片为有机发光二极管OLED显示屏中的DDIC芯片。
  21. 根据权利要求13至19任一所述的DDIC芯片，其中，所述DDIC芯片为低温多晶氧化物LTPO显示屏中的DDIC芯片。
  22. 根据权利要求13至19任一所述的DDIC芯片，其中，所述DDIC芯片为移动终端中显示屏的DDIC芯片。
  23. 一种应用处理器AP，所述AP与显示屏的DDIC芯片电性相连，所述AP用于：
    向所述DDIC芯片下发第一图像帧数据，所述DDIC芯片用于根据所述第一图像帧数据进行图像扫描和帧补偿；
    向所述DDIC芯片下发停止补偿指令，所述停止补偿指令用于指示所述AP准备下发新的图像帧数据，所述DDIC芯片用于根据所述停止补偿指令停止帧补偿并等待所述AP下发图像帧数据；
    向所述DDIC芯片下发第二图像帧数据，所述DDIC芯片用于根据所述第二图像帧数据进行图像扫描，并恢复帧补偿。
  24. 根据权利要求22所述的AP，其中，所述AP，用于：
    通过SurfaceFlinger进行图像合成时，生成所述停止补偿指令；
    在下一个TE信号低电平时，向所述DDIC芯片下发所述停止补偿指令。
  25. 一种显示屏模组，所述显示屏模组包括显示屏和显示驱动电路DDIC芯片，所述DDIC芯片用于驱动所述显示屏，所述DDIC芯片用于实现如权利要求1至10任一所述的图像显示方法。
  26. 一种终端，所述终端包括应用处理器AP、显示屏和显示驱动电路DDIC芯片，所述AP与所述DDIC芯片之间通过移动产业处理器接口MIPI相连，所述DDIC芯片用于实现如权利要求1至10任一所述的图像显示方法，所述AP用于实现如权利要求11至12任一所述的图像显示方法。
PCT/CN2021/123585 2020-11-17 2021-10-13 图像显示方法、ddic芯片、ap、显示屏模组及终端 WO2022105485A1 (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
EP21893634.2A EP4246950A4 (en) 2020-11-17 2021-10-13 IMAGE DISPLAY METHOD, DDIC CHIP, AP, DISPLAY SCREEN MODULE AND TERMINAL
US18/198,517 US20230290298A1 (en) 2020-11-17 2023-05-17 Image display method, ddic chip, ap, display screen module, and terminal

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202011284905.8A CN112511716B (zh) 2020-11-17 2020-11-17 图像显示方法、ddic芯片、ap、显示屏模组及终端
CN202011284905.8 2020-11-17

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US18/198,517 Continuation US20230290298A1 (en) 2020-11-17 2023-05-17 Image display method, ddic chip, ap, display screen module, and terminal

Publications (1)

Publication Number Publication Date
WO2022105485A1 true WO2022105485A1 (zh) 2022-05-27

Family

ID=74956456

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2021/123585 WO2022105485A1 (zh) 2020-11-17 2021-10-13 图像显示方法、ddic芯片、ap、显示屏模组及终端

Country Status (4)

Country Link
US (1) US20230290298A1 (zh)
EP (1) EP4246950A4 (zh)
CN (1) CN112511716B (zh)
WO (1) WO2022105485A1 (zh)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112511716B (zh) * 2020-11-17 2023-06-30 Oppo广东移动通信有限公司 图像显示方法、ddic芯片、ap、显示屏模组及终端
CN113741848B (zh) * 2021-09-15 2024-02-23 Oppo广东移动通信有限公司 图像显示方法、ddic、显示屏模组及终端
CN113805831B (zh) * 2021-09-15 2024-01-30 Oppo广东移动通信有限公司 图像数据传输方法、装置、终端及介质
CN114648951B (zh) * 2022-02-28 2023-05-12 荣耀终端有限公司 控制屏幕刷新率动态变化的方法及电子设备
CN116092452B (zh) * 2023-01-05 2023-10-20 荣耀终端有限公司 一种刷新率切换方法及电子设备
CN117133232A (zh) * 2023-04-12 2023-11-28 荣耀终端有限公司 一种显示方法、芯片及电子设备

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20170171450A1 (en) * 2015-12-15 2017-06-15 Samsung Electronics Co., Ltd. Image sensor circuit removing flicker and camera device including the same
CN108519807A (zh) * 2018-03-23 2018-09-11 维沃移动通信有限公司 一种应用处理器及移动终端
CN109817181A (zh) * 2019-03-29 2019-05-28 维沃移动通信有限公司 一种显示驱动方法及移动终端
CN111798781A (zh) * 2019-04-08 2020-10-20 三星电子株式会社 显示驱动集成电路及其操作方法
CN112511716A (zh) * 2020-11-17 2021-03-16 Oppo广东移动通信有限公司 图像显示方法、ddic芯片、ap、显示屏模组及终端

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101546537B (zh) * 2008-03-28 2011-02-16 北京京东方光电科技有限公司 液晶显示装置的驱动方法、补偿处理器及驱动装置
KR102135877B1 (ko) * 2013-11-22 2020-08-27 삼성디스플레이 주식회사 표시 패널의 구동 방법 및 이를 수행하기 위한 표시 장치
KR102219520B1 (ko) * 2014-07-04 2021-02-25 삼성디스플레이 주식회사 표시 장치 및 이의 구동 방법
CN109767738B (zh) * 2014-08-11 2021-04-30 麦克赛尔株式会社 显示装置
CN106648239B (zh) * 2016-12-23 2020-01-03 武汉华星光电技术有限公司 一种补偿显示中断的显示装置及显示面板
CN109785803B (zh) * 2017-11-13 2021-04-09 咸阳彩虹光电科技有限公司 一种显示方法、显示单元及显示器
CN108648704B (zh) * 2018-03-29 2019-10-08 京东方科技集团股份有限公司 电压补偿方法及装置、显示面板、显示装置
KR102482335B1 (ko) * 2018-10-04 2022-12-29 삼성디스플레이 주식회사 표시 장치 및 이를 이용한 표시 패널의 구동 방법
CN109545143B (zh) * 2019-01-24 2020-08-07 京东方科技集团股份有限公司 显示面板及其补偿方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20170171450A1 (en) * 2015-12-15 2017-06-15 Samsung Electronics Co., Ltd. Image sensor circuit removing flicker and camera device including the same
CN108519807A (zh) * 2018-03-23 2018-09-11 维沃移动通信有限公司 一种应用处理器及移动终端
CN109817181A (zh) * 2019-03-29 2019-05-28 维沃移动通信有限公司 一种显示驱动方法及移动终端
CN111798781A (zh) * 2019-04-08 2020-10-20 三星电子株式会社 显示驱动集成电路及其操作方法
CN112511716A (zh) * 2020-11-17 2021-03-16 Oppo广东移动通信有限公司 图像显示方法、ddic芯片、ap、显示屏模组及终端

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP4246950A4

Also Published As

Publication number Publication date
CN112511716A (zh) 2021-03-16
US20230290298A1 (en) 2023-09-14
EP4246950A4 (en) 2024-04-17
EP4246950A1 (en) 2023-09-20
CN112511716B (zh) 2023-06-30

Similar Documents

Publication Publication Date Title
WO2022105485A1 (zh) 图像显示方法、ddic芯片、ap、显示屏模组及终端
WO2022105484A1 (zh) 显示屏变频方法、ddic芯片、显示屏模组及终端
WO2021143676A1 (zh) 显示屏变频方法、ddic芯片、显示屏模组及终端
CN113160748B (zh) 显示屏变频方法、显示驱动集成电路芯片及应用处理器
WO2022111098A1 (zh) 触控扫描方法、tpic芯片、ddic芯片及模组
JP6069354B2 (ja) 受信装置、ビデオリフレッシュ周波数の制御方法、装置及びシステム
WO2023046164A1 (zh) 图像显示方法、ddic、显示屏模组及终端
WO2023040591A1 (zh) 图像显示方法、ddic、显示屏模组及终端
WO2023005558A1 (zh) 变频显示方法、ddic、显示屏模组及终端
CN115019732A (zh) 显示屏变频方法、显示驱动集成电路芯片及应用处理器
KR20130040251A (ko) 디스플레이 활동을 제어하기 위한 기법들
CN1428762A (zh) 显示驱动控制电路
JP6038475B2 (ja) 表示装置、情報処理装置、表示駆動方法、表示駆動プログラムおよびコンピュータ読取可能な記録媒体
CN115424599A (zh) 变化显示刷新率
WO2023040592A1 (zh) 图像数据传输方法、装置、终端及介质
WO2023061096A1 (zh) 显示屏刷新帧率的调整方法、装置、处理器、芯片和终端
WO2023040593A1 (zh) 图像数据传输方法、装置、终端及介质
JP2010049206A (ja) 表示システムおよび電子機器
WO2023010983A9 (zh) 刷新率的切换方法、电子设备和系统
JP2010032623A (ja) 表示コントローラ、表示装置、および携帯型電子機器
US20240211198A1 (en) Frame rate switching method and related apparatus
WO2024131274A1 (zh) 触控显示方法、装置、设备、系统和可读存储介质
WO2019019431A1 (zh) 低功耗智能显示装置及其显示方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 21893634

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

ENP Entry into the national phase

Ref document number: 2021893634

Country of ref document: EP

Effective date: 20230616