WO2021138873A1 - 半导体结构及其衬底、半导体结构及其衬底的制作方法 - Google Patents

半导体结构及其衬底、半导体结构及其衬底的制作方法 Download PDF

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WO2021138873A1
WO2021138873A1 PCT/CN2020/071185 CN2020071185W WO2021138873A1 WO 2021138873 A1 WO2021138873 A1 WO 2021138873A1 CN 2020071185 W CN2020071185 W CN 2020071185W WO 2021138873 A1 WO2021138873 A1 WO 2021138873A1
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sub
groove
substrate
thermally conductive
unit
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PCT/CN2020/071185
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English (en)
French (fr)
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程凯
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苏州晶湛半导体有限公司
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Priority to PCT/CN2020/071185 priority Critical patent/WO2021138873A1/zh
Priority to CN202080081003.6A priority patent/CN114902429A/zh
Priority to US17/617,737 priority patent/US20220254975A1/en
Publication of WO2021138873A1 publication Critical patent/WO2021138873A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/64—Heat extraction or cooling elements
    • H01L33/641—Heat extraction or cooling elements characterized by the materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components with at least one potential-jump barrier or surface barrier specially adapted for light emission
    • H01L27/153—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components with at least one potential-jump barrier or surface barrier specially adapted for light emission in a repetitive configuration, e.g. LED bars
    • H01L27/156—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components with at least one potential-jump barrier or surface barrier specially adapted for light emission in a repetitive configuration, e.g. LED bars two-dimensional arrays
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
    • H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0033—Processes relating to semiconductor body packages
    • H01L2933/0075—Processes relating to semiconductor body packages relating to heat extraction or cooling elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/04—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
    • H01L33/06—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction within the light emitting region, e.g. quantum confinement structure or tunnel barrier

Definitions

  • This application relates to the field of semiconductor technology, in particular to a semiconductor structure and its substrate, and a method for manufacturing the semiconductor structure and its substrate.
  • Light-emitting diodes use the recombination of electrons and holes to radiate visible light.
  • the two main application areas of LEDs include: lighting and display.
  • future development trends include: higher picture quality and higher definition (more pixels and smaller size pixels).
  • the key technology to realize high-definition display is to realize ultra-small light-emitting pixels, which requires a smaller-sized full-color LED light-emitting unit.
  • the size of the current full-color LED packaging unit is 1mm*1mm, and three formal LED chips, red, green, and blue, are packaged on the PCB through die bonding and wire bonding processes.
  • the PCB is then electrically conductive.
  • the through-hole process leads the electrodes of the three types of chips from the back to form a full-color LED package unit.
  • the full-color LED packaging unit is pressure-welded to the COB panel through the COB (chip on board) packaging process, and a dot matrix LED display is formed through the row and column wiring on the COB panel.
  • the purpose of the invention is to provide a semiconductor structure and its substrate, and a method for manufacturing the semiconductor structure and its substrate, which can be used for full-color LEDs and can reduce the size and cost of full-color LEDs.
  • the first aspect of the present invention provides a substrate, the substrate includes a plurality of unit regions, each unit region includes at least two sub-unit regions, each of the sub-unit regions has a groove, the There is a thermally conductive material in the groove; in one of the unit areas, the thermal conductivity of each sub-unit area is different.
  • the preset aperture ratios of the sub-unit areas are different.
  • the preset opening ratio of the sub-unit area refers to the percentage of the total volume of the grooves in a sub-unit area to the volume of the substrate block of the sub-unit area.
  • the grooves of the sub-unit regions have different preset depths, and/or different preset widths, and/or different preset opening densities.
  • the groove is opened from the front and/or back of the substrate.
  • each of the unit regions a part of the number of the grooves of the sub-unit area is opened from the front or back of the substrate; a part of the number of the grooves of the sub-unit area is opened from the substrate The front and back are opened.
  • the preset depths of the grooves of each of the subunit areas are different; or the preset aperture ratios of each of the subunit areas are the same; or a partial number of the subunit areas
  • the preset aperture ratios of the unit areas are different, and the preset aperture ratios of a partial number of the sub-unit areas are the same.
  • the thermally conductive materials in the grooves of each of the sub-unit areas are different; or the thermally conductive materials in the grooves of each of the sub-unit areas are the same; Or, the heat-conducting materials in the grooves of a part of the sub-unit areas are different, and the heat-conducting materials in the grooves of the part of the sub-unit areas are the same.
  • the porosity of the thermally conductive material in the groove of each sub-unit area is different; or the heat conduction material in the groove of each sub-unit area
  • the porosity of the material is the same; or the porosity of the thermally conductive material in the grooves of the partial number of the sub-unit regions is different, and the thermally conductive material in the grooves of the partial number of the sub-unit regions is different
  • the porosity is the same.
  • the thermal conductivity of the thermally conductive material in the groove of each sub-unit area is different; or the heat conduction in the groove of each sub-unit area
  • the thermal conductivity of the material is the same; or the thermal conductivity of the thermally conductive material in the grooves of a part of the sub-unit areas is different, and the thermally conductive material in the grooves of the partial number of the sub-unit areas The thermal conductivity is the same.
  • the thermally conductive material fills the groove, or an air gap is formed in the groove.
  • the material of the substrate is at least one of sapphire, silicon, silicon carbide, and GaN-based materials.
  • the second aspect of the present invention provides a semiconductor structure, including:
  • the light-emitting layer includes an N-type semiconductor layer, a P-type semiconductor layer, and a multiple quantum well material layer located between the N-type semiconductor layer and the P-type semiconductor layer.
  • the light-emitting layer includes a plurality of overlapping N-type semiconductor layers and P-type semiconductor layers, and a multiple quantum well material layer is arranged between adjacent N-type semiconductor layers and P-type semiconductor layers.
  • the semiconductor structure is used for display; the unit regions are arranged in an array, and the light-emitting layer of each unit region forms a light-emitting unit.
  • a third aspect of the present invention provides a method for manufacturing a substrate, including:
  • a prefabricated substrate is provided, the prefabricated substrate includes a plurality of unit regions, and each of the unit regions includes at least two subunit regions; a recess is formed in each of the subunit regions from the surface of the prefabricated substrate Groove; Filling the groove with a thermally conductive material to form a substrate; In one of the unit areas, the thermal conductivity of each of the sub-unit areas is different.
  • the preset opening ratios of the sub-unit areas are different.
  • the grooves of the sub-unit regions have different preset depths, and/or different preset widths, and/or different preset opening densities.
  • the groove is opened from the front and/or back of the prefabricated substrate.
  • each of the unit areas a part of the number of the grooves of the sub-unit area is opened from the front or back of the substrate; the part of the number of the grooves (101) of the sub-unit area is opened from the front or back of the substrate.
  • the front and back sides of the substrate are opened.
  • the preset aperture ratios of each of the subunit areas are different; or the preset aperture ratios of each of the subunit areas are the same; or a part of the number of the subunit areas is The preset aperture ratios are different, and the preset aperture ratios of a partial number of the sub-unit areas are the same.
  • the heat-conducting material filled in the grooves of each sub-unit area is different; or the heat-conducting material filled in the grooves of each sub-unit area The same; or the heat-conducting material filled in the grooves of a partial number of the sub-unit areas is different, and the heat-conducting material filled in the grooves of a partial number of the sub-unit areas is the same.
  • the porosity of the thermally conductive material filled in the grooves of each of the subunit areas is different; or all the porosity of the heat conductive material filled in the grooves of each of the subunit areas is different.
  • the porosity of the thermally conductive material is the same; or the porosity of the thermally conductive material filled in the grooves of a part of the subunit areas is different, and the porosity of the thermally conductive material is different for a part of the subunit areas.
  • the porosity of the thermally conductive materials is the same.
  • the thermal conductivity of the thermally conductive material filled in the grooves of each of the sub-unit areas is different; or all the heat-conducting materials filled in the grooves of each of the sub-unit areas
  • the thermal conductivity of the thermally conductive material is the same; or the thermal conductivity of the thermally conductive material filled in the grooves of a part of the subunit regions is different, and the thermal conductivity of the thermally conductive material filled in the grooves of a part of the subunit regions is different.
  • the thermal conductivity of the thermally conductive materials is the same.
  • the larger the predetermined opening rate of the sub-unit area the smaller the thermal conductivity of the thermally conductive material filled in the groove; the smaller the predetermined opening rate of the sub-unit area, so The thermal conductivity of the thermally conductive material filled in the groove is greater.
  • the thermally conductive material fills the groove, or an air gap is formed in the groove.
  • a fourth aspect of the present invention provides a method for manufacturing a semiconductor structure, including:
  • the substrate is manufactured according to the manufacturing method described in the above item;
  • a light-emitting layer is grown on the front surface of the substrate; in one of the unit regions, the light-emitting layers of the sub-unit regions have different light-emitting wavelengths.
  • the light-emitting layer includes an N-type semiconductor layer, a P-type semiconductor layer, and a multiple quantum well material layer located between the N-type semiconductor layer and the P-type semiconductor layer.
  • the light-emitting layer includes a plurality of overlapping N-type semiconductor layers and P-type semiconductor layers, and a multiple quantum well material layer is arranged between adjacent N-type semiconductor layers and P-type semiconductor layers.
  • the forbidden band width of the multi-quantum well material layer becomes wider as the growth temperature becomes higher; the larger the preset aperture ratio of the sub-unit region, the greater the thermal conductivity of the thermally conductive material in the groove The greater the porosity, the longer the emission wavelength of the corresponding light-emitting layer; the smaller the preset aperture ratio of the subunit area, the smaller the porosity of the thermally conductive material in the groove, and the corresponding light-emitting layer The shorter the emission wavelength.
  • the forbidden band width of the multi-quantum well material layer becomes wider as the growth temperature becomes higher; the larger the preset aperture ratio of the sub-unit region, the greater the thermal conductivity of the thermally conductive material in the groove The smaller the thermal conductivity, the longer the emission wavelength of the corresponding luminescent layer; the smaller the preset aperture ratio of the sub-unit area, the greater the thermal conductivity of the thermally conductive material in the groove, and the corresponding luminescent layer The shorter the emission wavelength.
  • the method for growing the light-emitting layer includes: atomic layer deposition, or chemical vapor deposition, or molecular beam epitaxial growth, or plasma enhanced chemical vapor deposition, or low pressure chemical vapor deposition, or metal organic At least one of compound chemical vapor deposition methods.
  • the semiconductor structure is used for display; the light-emitting layer grown in each of the unit regions forms a light-emitting unit.
  • the present invention has the following beneficial effects:
  • a groove is formed in each sub-unit area from the surface of the pre-fabricated substrate, the pre-fabricated substrate includes a plurality of unit areas, and each unit area includes at least two sub-unit areas;
  • the groove is filled with a thermally conductive material to form a substrate; in a unit area, the thermal conductivity of each sub-unit area is different.
  • the heat transfer efficiency of each sub-unit area is different.
  • the influence of the growth temperature on the light-emitting characteristics of the multiple quantum well material layer is used to realize different sub-unit areas when the light-emitting layer is grown on the front surface of the substrate.
  • the emission wavelength of the light-emitting layer is different.
  • the heat-conducting material is a porous material, and the porosity of the heat-conducting material filled in the grooves of each sub-unit area is different. The porosity controls the heat transfer efficiency of the thermally conductive material.
  • the preset aperture ratio of each sub-unit area is the same.
  • the greater the porosity of the thermally conductive material the longer the emission wavelength of the corresponding light-emitting layer; the smaller the porosity of the thermally conductive material, the smaller the corresponding The light-emitting layer has a shorter emission wavelength.
  • the greater the porosity of the thermally conductive material the worse the heat transfer efficiency, the lower the temperature of the thermally conductive material, the narrower the band gap of the grown multi-quantum well material layer, the smaller the frequency of photons produced by electronic transitions, and the longer the wavelength. On the contrary, the wavelength becomes shorter.
  • the preset aperture ratio of each sub-unit area is different.
  • the temperature at different positions of the substrate is controlled by the preset porosity of each subunit area and the porosity of the thermally conductive material.
  • the larger the preset porosity of a sub-unit region the greater the porosity of the thermally conductive material in the groove of the sub-unit region.
  • the forbidden band width of the layer becomes narrower, the frequency of the photon generated by the electronic transition becomes smaller, and the wavelength becomes longer. On the contrary, the wavelength becomes shorter.
  • the thermal conductivity of the thermally conductive material filled in the groove of each sub-unit area is different.
  • the heat transfer efficiency of the thermally conductive material is controlled by the thermal conductivity.
  • the preset opening rate of each sub-unit area is the same.
  • the larger the thermal conductivity of the thermally conductive material the shorter the emission wavelength of the corresponding light-emitting layer; the smaller the thermal conductivity of the thermally conductive material, the smaller the corresponding The longer the emission wavelength of the light-emitting layer.
  • the greater the thermal conductivity of the thermally conductive material the higher the heat transfer efficiency, the higher the temperature at the thermally conductive material, the wider the forbidden band width of the grown multi-quantum well material layer, the greater the frequency and the shorter the wavelength of photons produced by electronic transitions. On the contrary, the wavelength becomes longer.
  • the preset aperture ratio of each sub-unit area is different.
  • the temperature at different positions of the substrate is controlled by the preset opening rate of each sub-unit area and the thermal conductivity of the thermally conductive material.
  • the smaller the predetermined opening rate of a sub-unit area the greater the thermal conductivity of the thermally conductive material in the groove of the sub-unit area.
  • the band gap of the multi-quantum well material layer becomes wider, the frequency of photons generated by the electronic transition becomes larger, and the wavelength becomes shorter. On the contrary, the wavelength becomes longer.
  • a) the groove is filled with a thermally conductive material, or b) an air gap is formed in the groove. b) In the scheme, the size of the air gap is combined with the amount of heat-conducting material to adjust the heat transfer efficiency.
  • the light-emitting layer includes an N-type semiconductor layer, a P-type semiconductor layer, and a multiple quantum well material layer located between the N-type semiconductor layer and the P-type semiconductor layer; or b) the light-emitting layer includes multiple layers The N-type semiconductor layer and the P-type semiconductor layer are overlapped, and a multiple quantum well material layer is arranged between the adjacent N-type semiconductor layer and the P-type semiconductor layer.
  • the b) scheme can improve the luminous efficiency of the light-emitting layer compared with the a) scheme.
  • the semiconductor structure is used for display; the unit areas are arranged in an array, and the light-emitting layer of each unit area forms a light-emitting unit.
  • FIG. 1 is a top view of a semiconductor structure according to a first embodiment of the present invention
  • Figure 2 is a cross-sectional view taken along line AA in Figure 1;
  • FIG. 3 is a flowchart of the manufacturing method of the semiconductor structure in FIG. 1 and FIG. 2;
  • FIG. 4 is a top view of the prefabricated substrate in the process of FIG. 3;
  • Figure 5 is a cross-sectional view taken along line BB in Figure 4;
  • Fig. 6 is a top view of a substrate according to a second embodiment of the present invention.
  • Figure 7 is a cross-sectional view taken along line CC in Figure 6;
  • FIG. 8 is a flowchart of a method of manufacturing the substrate in FIG. 6 and FIG. 7;
  • FIG. 9 is a schematic diagram of a cross-sectional structure of a semiconductor structure according to a third embodiment of the present invention.
  • FIG. 10 is a flowchart of a manufacturing method of the semiconductor structure in FIG. 9;
  • FIG. 11 is a schematic diagram of a cross-sectional structure of a substrate according to a fourth embodiment of the present invention.
  • FIG. 12 is a flowchart of a method of manufacturing the substrate in FIG. 11;
  • FIG. 13 is a schematic diagram of a cross-sectional structure of a semiconductor structure according to a fifth embodiment of the present invention.
  • FIG. 14 is a schematic diagram of a cross-sectional structure of a substrate according to a sixth embodiment of the present invention.
  • FIG. 15 is a schematic diagram of a cross-sectional structure of a semiconductor structure according to a seventh embodiment of the present invention.
  • FIG. 16 is a schematic diagram of a cross-sectional structure of a substrate according to an eighth embodiment of the present invention.
  • FIG. 17 is a schematic diagram of a cross-sectional structure of a semiconductor structure according to a ninth embodiment of the present invention.
  • FIG. 18 is a schematic diagram of a cross-sectional structure of a substrate according to a tenth embodiment of the present invention.
  • FIG. 19 is a schematic diagram of a cross-sectional structure of a semiconductor structure according to an eleventh embodiment of the present invention.
  • FIG. 20 is a schematic diagram of a cross-sectional structure of a substrate according to a twelfth embodiment of the present invention.
  • FIG. 21 is a schematic cross-sectional structure diagram of a semiconductor structure according to a thirteenth embodiment of the present invention.
  • Sub-unit area 100a Pre-fabricated substrate front side, substrate front side 10a
  • Air gap 101a Pre-fabricated backside of substrate, backside of substrate 10b
  • FIG. 1 is a top view of a semiconductor structure according to a first embodiment of the present invention
  • FIG. 2 is a cross-sectional view taken along line AA in FIG. 1.
  • FIG. 3 is a flowchart of a manufacturing method of the semiconductor structure in FIG. 1 and FIG. 2.
  • 4 is a plan view of the prefabricated substrate in the process of FIG. 3
  • FIG. 5 is a cross-sectional view taken along line BB in FIG. 4.
  • a prefabricated substrate 10' is provided.
  • the prefabricated substrate 10' includes a plurality of unit regions 100, and each unit region 100 includes At least two sub-unit areas 100a; a groove 101 is opened in each sub-unit area 100a from the front surface 10a of the prefabricated substrate 10'; a thermally conductive material 102 is filled in the groove 101 to form the substrate 10; in one unit area 100 , The thermal conductivity of each sub-unit area 100a is different.
  • the prefabricated substrate 10' may be sapphire, silicon carbide, silicon or GaN-based material.
  • the semiconductor structure is used for display, and a plurality of unit areas 100 are arranged in an array, and each unit area 100 corresponds to a pixel unit area; each sub-unit area 100a corresponds to a sub-pixel area.
  • this step S1 at least two grooves 101 are opened in each pixel unit area.
  • the semiconductor structure can also be used for lighting.
  • a number of unit areas 100 are arranged in an array, and each unit area 100 corresponds to a lighting unit area; each sub-unit area 100a corresponds to a primary color light-emitting structure area.
  • this step S1 at least two grooves 101 are opened in each lighting unit area.
  • the number of grooves 101 is preferably three, corresponding to the formation of red, green, and blue LED light-emitting structures.
  • the groove 101 may adopt methods such as dry etching, laser groove cutting, mechanical groove cutting, and the like.
  • the predetermined depth, the predetermined width, and the predetermined opening density of the grooves 101 of each sub-unit area 100a are the same. Therefore, the predetermined opening of each sub-unit area 100a is the same.
  • the porosity is the same.
  • the predetermined opening rate of the sub-unit area 100a refers to the percentage of the total volume of the groove 101 in a sub-unit area 100a to the volume of the substrate block of the sub-unit area 100a.
  • the preset opening density refers to the number of grooves 101 per unit volume of the sub-unit area 100a.
  • the thermally conductive material 102 may be a porous material, such as a low-K dielectric layer (SiO 2 ), magnesium oxide (MgO), aluminum oxide (Al 2 O 3 ), and the like.
  • the porosity of the thermally conductive material 102 filled in the groove 101 of each sub-unit area 100a is different.
  • the thermal conductive material 102 fills the groove 101.
  • the light-emitting layer 20 is grown on the front surface 10 a of the substrate; in a unit area 100, the light-emitting layer 20 of each sub-unit area 100 a has different emission wavelengths.
  • the back surface 10b of the substrate is placed on the base in the reaction chamber.
  • a heating device is provided in the base, and the base transfers heat to the substrate 10 to heat the substrate 10 to the growth temperature.
  • the light emitting layer 20 may include an N-type semiconductor layer 20a, a P-type semiconductor layer 20b, and a multiple quantum well material layer 20c between the N-type semiconductor layer 20a and the P-type semiconductor layer 20b.
  • the material of the N-type semiconductor layer 20a, the multiple quantum well material layer 20c, and the P-type semiconductor layer 20b may be at least one of GaN, AlN, InN, InAlGaN, InAlN, GaAs, and AlGaAs, and the formation process may include: atomic layer deposition. (ALD, Atomic layer deposition), or Chemical Vapor Deposition (CVD, Chemical Vapor Deposition), or Molecular Beam Epitaxy (MBE, Molecular Beam Epitaxy), or Plasma Enhanced Chemical Vapor Deposition (PECVD, Plasma Enhanced Chemical Vapor) Deposition), or Low Pressure Chemical Vapor Deposition (LPCVD), or Metal-Organic Chemical Vapor Deposition (MOCVD), or a combination thereof.
  • ALD Atomic layer deposition
  • CVD Chemical Vapor Deposition
  • MBE Molecular Beam Epitaxy
  • PECVD Plasma Enhanced Chemical Vapor Deposition
  • LPCVD Low Pressure Chemical Vapor Deposition
  • a nucleation layer and a buffer layer may be formed in sequence.
  • the material of the nucleation layer may be, for example, AlN, AlGaN, etc.
  • the material of the buffer layer may include AlN.
  • the method of forming the buffer layer may be the same as the method of forming the N-type semiconductor layer 20a.
  • the nucleation layer can alleviate the epitaxially grown semiconductor layer, such as the lattice mismatch and thermal mismatch between the N-type semiconductor layer 20a and the multiple quantum well material layer 20c, and between the multiple quantum well material layer 20c and the P-type semiconductor layer 20b
  • the buffer layer can reduce the dislocation density and defect density of the epitaxially grown semiconductor layer and improve the crystal quality.
  • the preset porosity of each sub-unit area 100a is the same.
  • the emission wavelength of the grown multiple quantum well material layer 10c varies with temperature. Specifically, first, in direct band gap materials, the wavelength is inversely proportional to the band gap; second, the band gap of some semiconductor materials has a positive temperature coefficient, that is, when the growth temperature increases, the band gap increases. Large, so the wavelength is inversely proportional to the temperature; some semiconductor materials have a negative temperature coefficient, that is, when the growth temperature increases, the band gap decreases, so the wavelength is directly proportional to the temperature.
  • the common InGaN is a semiconductor material with a positive temperature coefficient.
  • the P-type semiconductor layer 20b may be close to the substrate 10, and the N-type semiconductor layer 20a may be far away from the substrate 10.
  • the thermal conductivity of the thermally conductive material 102 filled in the groove 101 of each sub-unit area 100a may be different.
  • the composition of the thermally conductive material 102 may be different, for example, different metals or dielectric materials, such as copper, aluminum, silicon dioxide, silicon nitride, and the like.
  • the multi-quantum well material layer 20c whose forbidden band width becomes wider as the growth temperature becomes higher, grow The forbidden band width of the multiple quantum well material layer 20c becomes wider, the frequency of photons generated by the electronic transition becomes larger, and the wavelength becomes shorter.
  • electrical connection structures that electrically connect the N-type semiconductor layer 20a and the P-type semiconductor layer 20b can be continuously fabricated on the semiconductor structure to form a full-color LED.
  • the light-emitting layer 20 grown in each pixel unit area 100 forms a light-emitting unit.
  • the semiconductor structure used for lighting it is also possible to cut along the cutting path between adjacent lighting unit regions 100 to form multiple lighting units.
  • a predetermined depth, a predetermined width, and a predetermined opening density are the same in each sub-unit area 100a from the front surface 10a of the prefabricated substrate 10'
  • Different grooves 101 are filled with different heat-conducting materials 102 to form the substrate 10.
  • the heat transfer efficiency of each sub-unit area 100a is different, and the influence of the growth temperature on the light-emitting characteristics of the multiple quantum well material layer 20c is used, so that when the light-emitting layer 20 is grown on the front surface 10a of the substrate,
  • the emission wavelengths of the light-emitting layers 20 that implement different sub-unit regions 100a are different.
  • the above process is simple, and a semiconductor structure for a full-color LED can be fabricated on one substrate 10, which reduces the size of the full-color LED and reduces the cost.
  • FIG. 6 is a top view of the substrate of the second embodiment of the present invention
  • FIG. 7 is a cross-sectional view taken along line CC in FIG. 6.
  • FIG. 8 is a flowchart of a method of manufacturing the substrate in FIG. 6 and FIG. 7.
  • the substrate and its manufacturing method of the second embodiment are exactly the same as the substrate and its manufacturing method in the semiconductor structure of the first embodiment, that is, the substrate and its manufacturing method in the semiconductor structure of the first embodiment
  • the manufacturing methods are all introduced in the second embodiment.
  • the substrate 10 in the semiconductor structure of the first embodiment can be produced and sold separately.
  • FIG. 9 is a schematic cross-sectional structure diagram of a semiconductor structure according to a third embodiment of the present invention.
  • FIG. 10 is a flowchart of a manufacturing method of the semiconductor structure in FIG. 9.
  • the semiconductor structure of the third embodiment is substantially the same as the semiconductor structure of the first embodiment, except that the groove 101 is opened from the back surface 10b of the substrate 10.
  • the manufacturing method of the semiconductor structure of the third embodiment is substantially the same as the manufacturing method of the semiconductor structure of the first embodiment, except that in step S1', a groove 101 is formed from the back surface 10b of the prefabricated substrate 10'.
  • a part of the grooves 101 of the sub-unit area 100a may be opened from the front surface 10a of the prefabricated substrate 10', and a part of the grooves 101 of the sub-unit area 100a may be self-prefabricated.
  • the back surface 10b of the substrate 10' is opened, and the predetermined depth and width of the groove 101 of each sub-unit area 100a are the same, and the predetermined opening density is the same, so as to control the predetermined opening rate of each sub-unit area 100a the same.
  • the preset aperture ratios of each sub-unit area 100a are the same ,
  • the thermal conductive material 102 filled in the groove 101 of the different sub-unit regions 100a is different. Therefore, in the process of heat transfer from the base to the substrate 10, the heat transfer efficiency of using different thermally conductive materials 102 is different, and the growth temperature has an influence on the light-emitting characteristics of the multiple quantum well material layer 20c, so that the light-emitting layer grown on the front side 10a of the substrate The emission wavelength of 20 is different.
  • FIG. 11 is a schematic diagram of a cross-sectional structure of a substrate according to a fourth embodiment of the present invention.
  • Fig. 12 is a flowchart of a method of manufacturing the substrate in Fig. 11.
  • the substrate and its manufacturing method of the fourth embodiment are exactly the same as the substrate and its manufacturing method in the semiconductor structure of the third embodiment, that is, the substrate and its manufacturing method in the semiconductor structure of the third embodiment
  • the production methods are all introduced in the fourth embodiment.
  • the substrate 10 in the semiconductor structure of the third embodiment can be produced and sold separately.
  • FIG. 13 is a schematic cross-sectional structure diagram of a semiconductor structure according to a fifth embodiment of the present invention.
  • the semiconductor structure of the fifth embodiment is substantially the same as the semiconductor structures of the first and third embodiments, except that the groove 101 of each sub-unit area 100a is opened from the front surface 10a and the back surface 10b of the substrate 10;
  • the grooves 101 of each subunit area 100a have the same preset depth, the same preset width, and the same preset opening density, so as to control the preset opening rate of each subunit area 100a to be the same.
  • the fabrication method of the semiconductor structure of the fifth embodiment is substantially the same as the fabrication methods of the semiconductor structure of the first and third embodiments, except that: in step S1, the front surface 10a and the back surface 10b of the prefabricated substrate 10' are respectively
  • Each sub-unit area 100a has a groove 101; the two grooves 101 of each sub-unit area 100a have the same preset depth, the same preset width, and the same preset opening density, so as to control each sub-unit area 100a
  • the default opening rate is the same.
  • the porosity of the thermally conductive material 102 filled in the two grooves 101 of each sub-unit area 100a is the same; the porosity of the thermally conductive material 102 filled in the grooves 101 of each sub-unit area 100a is different. In some embodiments, the porosity of the thermally conductive material 102 filled in the two grooves 101 of each sub-unit area 100a may be different.
  • the thermal conductivity of the thermally conductive material 102 filled in the two grooves 101 of each sub-unit area 100a is the same; the thermally conductive material 102 filled in the grooves 101 of each sub-unit area 100a has different thermal conductivity. In some embodiments, the thermal conductivity of the thermally conductive material 102 filled in the two grooves 101 of each sub-unit area 100a may be different.
  • a part of the grooves 101 of the sub-unit area 100a may be opened from the front side 10a or the back side 10b of the substrate 10; and the grooves 101 of a part of the sub-unit area 100a may be opened from the substrate 10
  • the front side 10a and the back side 10b of 10 are opened.
  • the preset depth of the groove 101 opened from the front side 10a or the back side 10b of the substrate 10 is equal to the sum of the preset depth of the groove 101 opened from the front side 10a and the back side 10b of the substrate 10.
  • the predetermined depth of each groove 101 It is assumed that the width is the same and the preset opening density is the same to control the preset opening rate of each subunit area 100a to be the same.
  • FIG. 14 is a schematic diagram of a cross-sectional structure of a substrate according to a sixth embodiment of the present invention.
  • the substrate and its manufacturing method of the sixth embodiment are exactly the same as the substrate and its manufacturing method in the semiconductor structure of the fifth embodiment, that is, the substrate and its manufacturing method in the semiconductor structure of the fifth embodiment All are introduced in this sixth embodiment.
  • the substrate 10 in the semiconductor structure of the fifth embodiment can be produced and sold separately.
  • FIG. 15 is a schematic diagram of a cross-sectional structure of a semiconductor structure according to a seventh embodiment of the present invention.
  • the semiconductor structure of the seventh embodiment is substantially the same as the semiconductor structures of the first and third embodiments. The only difference is that in one unit area 100, the predetermined depth of the groove 101 of each sub-unit area 100a is different.
  • the fabrication method of the semiconductor structure of the seventh embodiment is substantially the same as the fabrication methods of the semiconductor structure of the first and third embodiments, except that: in step S1, in one unit area 100, the front surface of the prefabricated substrate 10' In each sub-unit area 10a, grooves 101 with the same preset width and the same preset opening density but different preset depths are opened in each sub-unit area 100a.
  • the preset depth difference between the grooves 101 of each sub-unit area 100a may be a fixed value or a variable value.
  • the preset width of the groove 101 of each sub-unit area 100a may be different, or the preset opening density may be different, so as to adjust the preset opening rate of each sub-unit area 100a to be different.
  • the preset depths, and/or preset widths, and/or preset opening densities of the grooves 101 of each sub-unit area 100a are different, so as to adjust each sub-unit area 100a.
  • the preset opening rate is different.
  • the predetermined depth of the groove 101 of the two sub-unit areas 100a is different, and the predetermined width of the groove 101 of the other sub-unit area 100a is different (or the predetermined opening density is different).
  • the larger the preset porosity of a sub-unit area 100a is, the larger the porosity of the thermally conductive material 102 filled in the groove 101 of the sub-unit area 100a can be, so as to further reduce the porosity of the sub-unit area 100a.
  • Heat transfer efficiency the smaller the preset porosity of a sub-unit area 100a, the smaller the porosity of the thermally conductive material 102 filled in the groove 101 of the sub-unit area 100a to further improve the sub-unit area 100a Heat transfer efficiency.
  • the larger the preset porosity of a sub-unit area 100a the smaller the porosity of the thermally conductive material 102 filled in the groove 101 of the sub-unit area 100a; the preset of a sub-unit area 100a
  • the smaller the porosity the greater the porosity of the thermally conductive material 102 filled in the groove 101 of the subunit area 100a, so as to fine-tune the heat transfer efficiency of the subunit areas 100a with different preset porosity.
  • the porosity of the thermally conductive material 102 filled in the groove 101 of each sub-unit area 100a is the same.
  • the composition of the thermally conductive material 102 filled in the groove 101 of the sub-unit area 100a with different preset aperture ratios is different.
  • the thermal conductive material 102 filled in the groove 101 of the sub-unit region 100a with different preset aperture ratios has the same composition or the same thermal conductivity.
  • the groove 101 may also be opened from the back surface 10b of the prefabricated substrate 10'.
  • a part of the grooves 101 of the sub-unit area 100a may be opened from the front surface 10a of the prefabricated substrate 10', and a part of the grooves 101 of the sub-unit area 100a may be self-prefabricated.
  • the back side 10b of the substrate 10' is opened, and the preset depth and/or preset width of the groove 101 of each sub-unit area 100a are different, and/or the preset opening density is different, so as to control the size of each sub-unit area 100a.
  • the preset opening rate is different.
  • the scheme of this embodiment can be combined with the schemes of implementing one, three, and five. That is, in a unit area 100, the predetermined depth or sum of the preset depths of the grooves 101 of a part number of the subunit areas 100a are the same, the preset width is the same, and the preset opening density is the same, so as to control the size of each subunit area 100a.
  • the predetermined porosity is the same, and the porosity or thermal conductivity of the thermal conductive material 102 therein is different; the predetermined depth and/or the predetermined width of the groove 101 of the partial number of sub-unit regions 100a are different, and/or the predetermined The opening density is different to control the preset opening rate of each sub-unit area 100a to be different.
  • FIG. 16 is a schematic diagram of a cross-sectional structure of a substrate according to an eighth embodiment of the present invention.
  • the substrate and its manufacturing method of the eighth embodiment are exactly the same as the substrate and its manufacturing method in the semiconductor structure of the seventh embodiment, that is, the substrate and its manufacturing method in the semiconductor structure of the seventh embodiment All are introduced in the eighth embodiment.
  • the substrate 10 in the semiconductor structure of the seventh embodiment can be produced and sold separately.
  • FIG. 17 is a schematic diagram of a cross-sectional structure of a semiconductor structure according to a ninth embodiment of the present invention.
  • the semiconductor structure of the ninth embodiment is substantially the same as the semiconductor structure of the eighth embodiment, except that the groove 101 of each sub-unit area 100a is opened from the front surface 10a and the back surface 10b of the substrate 10;
  • the preset widths of the two grooves 101 in the unit area 100a are the same, and the preset opening density is the same, but the sum of the preset depths is different, so as to control the preset opening rates of each sub-unit area 100a to be different.
  • the manufacturing method of the semiconductor structure of the ninth embodiment is roughly the same as the manufacturing method of the semiconductor structure of the eighth embodiment.
  • the preset widths of the two grooves 101 of each sub-unit area 100a are the same, and the preset opening density is the same, but the sum of the preset depths is different, so as to control the preset depth of each sub-unit area 100a. Let the opening rate be different.
  • the preset width of the groove 101 of each sub-unit area 100a may be different, or the preset opening density may be different, so as to adjust the preset opening rate of each sub-unit area 100a to be different.
  • the preset depths, and/or preset widths, and/or preset opening densities of the grooves 101 of each sub-unit area 100a are different, so as to adjust each sub-unit area 100a.
  • the preset opening rate is different.
  • the predetermined depth of the groove 101 of the two sub-unit areas 100a is different, and the predetermined width of the groove 101 of the other sub-unit area 100a is different (or the predetermined opening density is different).
  • the porosity of the thermally conductive material 102 filled in the two grooves 101 of each sub-unit area 100a is the same; the porosity of the thermally conductive material 102 filled in the grooves 101 of each sub-unit area 100a is different.
  • the greater the porosity of a subunit area 100a (the greater the sum of the preset depths of the two grooves 101), the greater the porosity of the thermally conductive material 102 filled in the grooves 101; the porosity of a subunit area 100a
  • the smaller the sum of the preset depths of the two grooves 101 is smaller), the smaller the porosity of the thermally conductive material 102 filled in the grooves 101 is.
  • the porosity of the thermal conductive material 102 filled in the groove 101 of each sub-unit area 100a may also be the same.
  • the porosity of the thermally conductive material 102 filled in the two grooves 101 of each sub-unit area 100a may be different.
  • the thermal conductivity of the thermally conductive material 102 filled in the two grooves 101 of each sub-unit area 100a is the same; the thermally conductive material 102 filled in the grooves 101 of each sub-unit area 100a has different thermal conductivity.
  • the greater the porosity of a subunit area 100a (the greater the sum of the preset depths of the two grooves 101), the smaller the thermal conductivity of the thermally conductive material 102 filled in the groove 101; the porosity of a subunit area 100a
  • the smaller the sum of the preset depths of the two grooves 101 is smaller), the greater the thermal conductivity of the thermally conductive material 102 filled in the grooves 101.
  • the thermal conductivity of the thermally conductive material 102 filled in the groove 101 of each sub-unit area 100a may also be the same.
  • the thermal conductivity of the thermally conductive material 102 filled in the two grooves 101 of each sub-unit area 100a may be different.
  • a part of the grooves 101 of the sub-unit area 100a may be opened from the front side 10a or the back side 10b of the substrate 10; and the grooves 101 of a part of the sub-unit area 100a may be opened from the substrate 10
  • the front side 10a and the back side 10b of 10 are opened.
  • the predetermined depth of the groove 101 opened from the front side 10a or the back side 10b of the substrate 10 is not equal to the sum of the predetermined depth of the groove 101 opened from the front side 10a and the back side 10b of the substrate 10, or the predetermined depth of the groove 101
  • the width is different, and/or the preset hole density is different, so as to control the preset hole rate of each sub-unit area 100a to be different.
  • the scheme of this embodiment can be combined with the schemes of implementing one, three, and five. That is, in a unit area 100, the predetermined depth or sum of the preset depths of the grooves 101 of a part number of the subunit areas 100a are the same, the preset width is the same, and the preset opening density is the same, so as to control the size of each subunit area 100a.
  • the preset porosity is the same, and the porosity or thermal conductivity of the thermally conductive material 102 therein is different; the sum of the preset depths of the grooves 101 of the partial number of sub-unit regions 100a are different, and/or the preset widths are different, and/or The preset hole density is different to control the preset hole rate of each sub-unit area 100a to be different.
  • FIG. 18 is a schematic diagram of a cross-sectional structure of a substrate according to a tenth embodiment of the present invention.
  • the substrate and its manufacturing method of the tenth embodiment are exactly the same as the substrate and its manufacturing method in the semiconductor structure of the ninth embodiment, that is, the substrate and its manufacturing method in the semiconductor structure of the ninth embodiment All are introduced in the tenth embodiment.
  • the substrate 10 in the semiconductor structure of the ninth embodiment can be produced and sold separately.
  • FIG. 19 is a schematic diagram of a cross-sectional structure of a semiconductor structure according to an eleventh embodiment of the present invention.
  • the semiconductor structure of the eleventh embodiment is substantially the same as the semiconductor structures of the first, third, fifth, seventh, and ninth embodiments. The only difference is that an air gap 101a is formed in the groove 101.
  • the manufacturing method of the semiconductor structure of the eleventh embodiment is substantially the same as the manufacturing methods of the semiconductor structure of the first, third, fifth, seventh, and ninth embodiments, except that: in step S1, the groove 101 is filled When the thermally conductive material 102 is used, an air gap 101a is formed in the groove 101.
  • the size of the air gap 101a combined with the amount of the heat conducting material 102 is used to adjust the heat transfer efficiency.
  • the air gap 101a can be achieved by reducing the bias voltage between the plasma source and the base during the deposition process, or not applying the bias voltage, and/or reducing the pumping rate of the chamber.
  • FIG. 20 is a schematic diagram of a cross-sectional structure of a substrate according to a twelfth embodiment of the present invention.
  • the substrate and the manufacturing method thereof in the twelfth embodiment are exactly the same as the substrate and the manufacturing method in the semiconductor structure of the eleventh embodiment, that is, the substrate and the manufacturing method thereof in the semiconductor structure of the eleventh embodiment
  • the production methods are all introduced in the twelfth embodiment.
  • the substrate 10 in the semiconductor structure of the eleventh embodiment can be produced and sold separately.
  • FIG. 21 is a schematic cross-sectional structure diagram of a semiconductor structure according to a thirteenth embodiment of the present invention.
  • the semiconductor structure of the ninth embodiment is substantially the same as the semiconductor structures of the first, third, fifth, seventh, ninth, and eleventh embodiments.
  • the light-emitting layer 20 includes a multi-layer overlapping N-type
  • a multiple quantum well material layer 20c is provided between the semiconductor layer 20a and the P-type semiconductor layer 20b, and between the adjacent N-type semiconductor layer 20a and the P-type semiconductor layer 20b.
  • the manufacturing method of the semiconductor structure of the ninth embodiment is substantially the same as the manufacturing methods of the semiconductor structure of the first, third, fifth, seventh, ninth, and eleventh embodiments.
  • step S2 the grown light-emitting layer 20 It includes multiple overlapping N-type semiconductor layers 20a and P-type semiconductor layers 20b, and a multiple quantum well material layer 20c is arranged between adjacent N-type semiconductor layers 20a and P-type semiconductor layers 20b.
  • the semiconductor structure of the thirteenth embodiment can improve the luminous efficiency of the light-emitting layer 20.
  • the term “several” refers to one, two or more than two, unless specifically defined otherwise.

Abstract

本申请提供了一种半导体结构及其衬底、半导体结构及其衬底的制作方法，衬底的制作方法中，自预制作衬底的表面在每一子单元区内开设凹槽，预制作衬底包括若干单元区，每一单元区包括至少两个子单元区；在凹槽内填入导热材料形成衬底；一个单元区中，各个子单元区的导热系数不同。基台向衬底传热过程中，各个子单元区的传热效率不同，利用生长温度对多量子阱材料层的发光特性的影响，从而在衬底正面生长发光层时，实现不同子单元区的发光层的发光波长不同。上述工艺简单，且能在一个衬底上制作可用于全彩LED的半导体结构，减小了全彩LED的尺寸，降低了成本。

Description

半导体结构及其衬底、半导体结构及其衬底的制作方法 技术领域
本申请涉及半导体技术领域，尤其涉及一种半导体结构及其衬底、半导体结构及其衬底的制作方法。
背景技术
发光二极管，简称LED，是利用电子与空穴之间的复合辐射出可见光。LED的两个主要应用领域包括：照明与显示。尤其在显示领域，未来发展趋势包括：更高画质和更高清(更多数量的像素和更小尺寸的像素)。实现高清显示的关键技术是实现超小发光像素，需要更小尺寸的全彩LED发光单元。
而现有技术中，目前全彩LED封装单元的尺寸为1mm*1mm，采用的是红、绿、蓝三颗正装LED芯片通过固晶和打线工艺封装到PCB板上，PCB板再通过导电通孔工艺将三种芯片的电极从背面引出，形成一个全彩LED封装单元。全彩LED封装单元再通过COB(chip on board)封装工艺压焊到COB平板上，通过COB平板上的行列布线形成点阵LED显示屏。
发明内容
本发明的发明目的是提供一种半导体结构及其衬底、半导体结构及其衬底的制作方法，可用于全彩LED且能减小全彩LED的尺寸、降低成本。
为实现上述目的，本发明的第一方面提供一种衬底，所述衬底包括若干单元区，每一单元区包括至少两个子单元区，每一所述子单元区具有凹槽，所述凹槽内具有导热材料；一个所述单元区中，各个子单元区的导热系数不 同。
可选地，一个所述单元区中，各个所述子单元区的预设开孔率不同。
本发明中，子单元区的预设开孔率是指：一个子单元区中凹槽的总体积与该子单元区衬底块材料体积的百分比。
可选地，一个所述单元区中，各个所述子单元区的所述凹槽的预设深度不同，和/或预设宽度不同，和/或预设开孔密度不同。
可选地，每个所述单元区中，所述凹槽自所述衬底的正面和/或背面开设；或
每个所述单元区中，部分数目的所述子单元区的所述凹槽自所述衬底的正面或背面开设；部分数目的所述子单元区的所述凹槽自所述衬底的正面与背面开设。
可选地，一个所述单元区中：各个所述子单元区的所述凹槽的预设深度不同；或各个所述子单元区的预设开孔率相同；或部分数目的所述子单元区的预设开孔率不同，部分数目的所述子单元区的预设开孔率相同。
可选地，一个所述单元区中：各个所述子单元区的所述凹槽内的所述导热材料不同；或各个所述子单元区的所述凹槽内的所述导热材料相同；或部分数目的所述子单元区的所述凹槽内的所述导热材料不同，部分数目的所述子单元区的所述凹槽内的所述导热材料相同。
可选地，一个所述单元区中：各个所述子单元区的所述凹槽内的所述导热材料的孔隙率不同；或各个所述子单元区的所述凹槽内的所述导热材料的孔隙率相同；或部分数目的所述子单元区的所述凹槽内的所述导热材料的孔隙率不同，部分数目的所述子单元区的所述凹槽内的所述导热材料的孔隙率相同。
可选地，所述子单元区的预设开孔率越大，所述凹槽内的所述导热材料的孔隙率越大；所述子单元区的预设开孔率越小，所述凹槽内的所述导热 材料的孔隙率越小。
可选地，一个所述单元区中：各个所述子单元区的所述凹槽内的所述导热材料的导热系数不同；或各个所述子单元区的所述凹槽内的所述导热材料的导热系数相同；或部分数目的所述子单元区的所述凹槽内的所述导热材料的导热系数不同，部分数目的所述子单元区的所述凹槽内的所述导热材料的导热系数相同。
可选地，所述子单元区的预设开孔率越大，所述凹槽内的所述导热材料的导热系数越小；所述子单元区的预设开孔率越小，所述凹槽内的所述导热材料的导热系数越大。
可选地，所述导热材料填满所述凹槽，或所述凹槽内形成有空气隙。
可选地，所述衬底的材料为蓝宝石、硅、碳化硅、GaN基材料中的至少一种。
本发明的第二方面提供一种半导体结构，包括：
上述任一项所述的衬底；
位于所述衬底正面的发光层；一个所述单元区中，各子单元区的所述发光层的发光波长不同。
可选地，所述发光层包括N型半导体层，P型半导体层，以及位于所述N型半导体层与所述P型半导体层之间的多量子阱材料层。
可选地，所述发光层包括多层交叠设置的N型半导体层与P型半导体层，相邻所述N型半导体层与所述P型半导体层之间设置有多量子阱材料层。
可选地，所述半导体结构用于显示；所述单元区呈阵列式排布，每一所述单元区的所述发光层形成一个发光单元。
本发明的第三方面提供一种衬底的制作方法，包括：
提供预制作衬底，所述预制作衬底包括若干单元区，每一所述单元区 包括至少两个子单元区；自所述预制作衬底的表面在每一所述子单元区内开设凹槽；在所述凹槽内填充导热材料以形成衬底；一个所述单元区中，各个所述子单元区的导热系数不同。
可选地，在所述凹槽内填充导热材料前，一个所述单元区中，各个所述子单元区的预设开孔率不同。
可选地，一个所述单元区中，各个所述子单元区的所述凹槽的预设深度不同，和/或预设宽度不同，和/或预设开孔密度不同。
可选地，每个所述单元区中，所述凹槽自所述预制作衬底的正面和/或背面开设；或
每个所述单元区中，部分数目的所述子单元区的所述凹槽自所述衬底的正面或背面开设；部分数目的所述子单元区的所述凹槽(101)自所述衬底的正面与背面开设。
可选地，一个所述单元区中：各个所述子单元区的预设开孔率不同；或各个所述子单元区的预设开孔率相同；或部分数目的所述子单元区的预设开孔率不同，部分数目的所述子单元区的预设开孔率相同。
可选地，一个所述单元区中：各个所述子单元区的所述凹槽内填充的所述导热材料不同；或各个所述子单元区的所述凹槽内填充的所述导热材料相同；或部分数目的所述子单元区的所述凹槽内填充的所述导热材料不同，部分数目的所述子单元区的所述凹槽内填充的所述导热材料相同。
可选地，一个所述单元区中：各个所述子单元区的所述凹槽内填充的所述导热材料的孔隙率不同；或各个所述子单元区的所述凹槽内填充的所述导热材料的孔隙率相同；或部分数目的所述子单元区的所述凹槽内填充的所述导热材料的孔隙率不同，部分数目的所述子单元区的所述凹槽内填充的所述导热材料的孔隙率相同。
可选地，所述子单元区的预设开孔率越大，所述凹槽内填充的所述导 热材料的孔隙率越大；所述子单元区的预设开孔率越小，所述凹槽内填充的所述导热材料的孔隙率越小。
可选地，一个所述单元区中：各个所述子单元区的所述凹槽内填充的所述导热材料的导热系数不同；或各个所述子单元区的所述凹槽内填充的所述导热材料的导热系数相同；或部分数目的所述子单元区的所述凹槽内填充的所述导热材料的导热系数不同，部分数目的所述子单元区的所述凹槽内填充的所述导热材料的导热系数相同。
可选地，所述子单元区的预设开孔率越大，所述凹槽内填充的所述导热材料的导热系数越小；所述子单元区的预设开孔率越小，所述凹槽内填充的所述导热材料的导热系数越大。
可选地，在所述凹槽内填充导热材料步骤中，所述导热材料填满所述凹槽，或所述凹槽内形成有空气隙。
本发明的第四方面提供一种半导体结构的制作方法，包括：
根据上述一项所述的制作方法制作衬底；
在所述衬底正面生长发光层；一个所述单元区中，各子单元区的所述发光层的发光波长不同。
可选地，所述发光层包括N型半导体层，P型半导体层，以及位于所述N型半导体层与所述P型半导体层之间的多量子阱材料层。
可选地，所述发光层包括多层交叠设置的N型半导体层与P型半导体层，相邻所述N型半导体层与所述P型半导体层之间设置有多量子阱材料层。
可选地，所述多量子阱材料层的禁带宽度随生长温度的变高而变宽；所述子单元区的预设开孔率越大，所述凹槽内的所述导热材料的孔隙率越大，对应的发光层的发光波长越长；所述子单元区的预设开孔率越小，所述凹槽内的所述导热材料的孔隙率越小，对应的发光层的发光波长越短。
可选地，所述多量子阱材料层的禁带宽度随生长温度的变高而变宽；所述子单元区的预设开孔率越大，所述凹槽内的所述导热材料的导热系数越小，对应的发光层的发光波长越长；所述子单元区的预设开孔率越小，所述凹槽内的所述导热材料的导热系数越大，对应的发光层的发光波长越短。
可选地，所述发光层的生长方法包括：原子层沉积法、或化学气相沉积法、或分子束外延生长法、或等离子体增强化学气相沉积法、或低压化学蒸发沉积法，或金属有机化合物化学气相沉积法中的至少一种。
可选地，所述半导体结构用于显示；在每一所述单元区生长的所述发光层形成一个发光单元。
与现有技术相比，本发明的有益效果在于：
1)本发明的半导体结构的制作方法中，自预制作衬底的表面在每一子单元区内开设凹槽，预制作衬底包括若干单元区，每一单元区包括至少两个子单元区；在凹槽内填入导热材料形成衬底；一个单元区中，各个子单元区的导热系数不同。基台向衬底传热过程中，各个子单元区的传热效率不同，利用生长温度对多量子阱材料层的发光特性的影响，从而在衬底正面生长发光层时，实现不同子单元区的发光层的发光波长不同。上述工艺简单，且能在一个衬底上制作可用于全彩LED的半导体结构，减小了全彩LED的尺寸，降低了成本。
2)可选方案中，导热材料为多孔材料，各个子单元区的凹槽内填入的导热材料的孔隙率不同。通过孔隙率控制导热材料的传热效率。
3)可选方案中，各个子单元区的预设开孔率相同。对于禁带宽度随生长温度的变高而变宽的多量子阱材料层，导热材料的孔隙率越大，对应处的发光层的发光波长越长；导热材料的孔隙率越小，对应处的发光层的发光波长越短。导热材料的孔隙率越大，传热效率越差，导热材料处的温度越低，生长的多量子阱材料层的禁带宽度变窄，电子跃迁产生的光子的频率变小， 波长变长。反之波长变短。
4)可选方案中，各个子单元区的预设开孔率不同。通过各个子单元区的预设开孔率结合导热材料的孔隙率控制衬底不同位置处的温度高低。对于禁带宽度随生长温度的变高而变宽的多量子阱材料层，一个子单元区的预设开孔率越大，该子单元区的凹槽内的导热材料的孔隙率越大，对应处的发光层的发光波长越长；一个子单元区的预设开孔率越小，该子单元区的凹槽内的导热材料的孔隙率越小，对应处的发光层的发光波长越短。子单元区的预设开孔率越大，凹槽内的导热材料的孔隙率越大，子单元区的传热效率越差，子单元区的正面的温度越低，生长的多量子阱材料层的禁带宽度变窄，电子跃迁产生的光子的频率变小，波长变长。反之波长变短。
5)可选方案中，各个子单元区的凹槽内填入的导热材料的导热系数不同。通过导热系数控制导热材料的传热效率。
6)可选方案中，各个子单元区的预设开孔率相同。对于禁带宽度随生长温度的变高而变宽的多量子阱材料层，导热材料的导热系数越大，对应处的发光层的发光波长越短；导热材料的导热系数越小，对应处的发光层的发光波长越长。导热材料的导热系数越大，传热效率越高，导热材料处的温度越高，生长的多量子阱材料层的禁带宽度变宽，电子跃迁产生的光子的频率变大，波长变短。反之波长变长。
7)可选方案中，各个子单元区的预设开孔率不同。通过各个子单元区的预设开孔率结合导热材料的导热系数控制衬底不同位置处的温度高低。对于禁带宽度随生长温度的变高而变宽的多量子阱材料层，一个子单元区的预设开孔率越小，该子单元区的凹槽内的导热材料的导热系数越大，对应处的发光层的发光波长越短；一个子单元区的预设开孔率越大，该子单元区的凹槽内的导热材料的导热系数越小，对应处的发光层的发光波长越长。子单元区的预设开孔率越小，该子单元区的凹槽内的导热材料的导热系数越大，子单元区的传热效率越高，子单元区正面的温度越高，生长的多量子阱材料层 的禁带宽度变宽，电子跃迁产生的光子的频率变大，波长变短。反之波长变长。
8)可选方案中，a)导热材料填满凹槽，或b)凹槽内形成有空气隙(air gap)。b)方案中，空气隙的大小结合导热材料的多少调整传热效率。
9)可选方案中，a)发光层包括N型半导体层，P型半导体层，以及位于N型半导体层与P型半导体层之间的多量子阱材料层；或b)发光层包括多层交叠设置的N型半导体层与P型半导体层，相邻N型半导体层与P型半导体层之间设置有多量子阱材料层。b)方案相对于a)方案，能提高发光层的发光效率。
10)可选方案中，半导体结构用于显示；单元区呈阵列式排布，每一单元区的发光层形成一个发光单元。通过上述方法，可以实现阵列式排布的若干像素单元的同时制作。其它可选方案中，还可以同时制作多个用于照明的半导体结构。
附图说明
图1是本发明第一实施例的半导体结构的俯视图；
图2是沿着图1中的AA线的剖视图；
图3是图1与图2中的半导体结构的制作方法的流程图；
图4是图3的流程中的预制作衬底的俯视图；
图5是沿着图4中的BB线的剖视图；
图6是本发明第二实施例的衬底的俯视图；
图7是沿着图6中的CC线的剖视图；
图8是图6与图7中的衬底的制作方法的流程图；
图9是本发明第三实施例的半导体结构的截面结构示意图；
图10是图9中的半导体结构的制作方法的流程图；
图11是本发明第四实施例的衬底的截面结构示意图；
图12是图11中的衬底的制作方法的流程图；
图13是本发明第五实施例的半导体结构的截面结构示意图；
图14是本发明第六实施例的衬底的截面结构示意图；
图15是本发明第七实施例的半导体结构的截面结构示意图；
图16是本发明第八实施例的衬底的截面结构示意图；
图17是本发明第九实施例的半导体结构的截面结构示意图；
图18是本发明第十实施例的衬底的截面结构示意图；
图19是本发明第十一实施例的半导体结构的截面结构示意图；
图20是本发明第十二实施例的衬底的截面结构示意图；
图21是本发明第十三实施例的半导体结构的截面结构示意图。
为方便理解本发明，以下列出本发明中出现的所有附图标记：
预制作衬底10'              单元区100
子单元区100a               预制作衬底正面、衬底正面10a
凹槽101                    导热材料102
发光层20                   N型半导体层20a
P型半导体层20b             多量子阱材料层20c
空气隙101a                 预制作衬底背面、衬底背面10b
衬底10
具体实施方式
为使本发明的上述目的、特征和优点能够更为明显易懂，下面结合附图对本发明的具体实施例做详细的说明。
图1是本发明第一实施例的半导体结构的俯视图，图2是沿着图1中的AA线的剖视图。图3是图1与图2中的半导体结构的制作方法的流程图。图4是图3的流程中的预制作衬底的俯视图，图5是沿着图4中的BB线的剖视图。
首先，参照图3中的步骤S1、图1、图2、图4与图5所示，提供预制作衬底10'，预制作衬底10'包括若干单元区100，每一单元区100包括至少两个子单元区100a；自预制作衬底10'的正面10a在每一子单元区100a内开设凹槽101；在凹槽101内填充导热材料102以形成衬底10；一个单元区100中，各个子单元区100a的导热系数不同。
预制作衬底10'可以为蓝宝石、碳化硅、硅或GaN基材料。
本实施例中，半导体结构用于显示，若干单元区100呈阵列式排布，每一单元区100对应于一像素单元区；每一子单元区100a对应于一子像素区。本步骤S1中，在每一像素单元区开设至少两个凹槽101。
其它实施例中，半导体结构也可以用于照明。若干单元区100呈阵列式排布，每一单元区100对应于一照明单元区；每一子单元区100a对应于一基色发光结构区。本步骤S1中，在每一照明单元区开设至少两个凹槽101。
图2所示实施例中，凹槽101优选为三个，对应形成红、绿、蓝三基色的LED发光结构。
凹槽101可以采用干法刻蚀、激光刻槽、机械刻槽等方法。
参照图2所示，一个单元区100中，各个子单元区100a的凹槽101的预设深度相同、预设宽度相同，以及预设开孔密度相同，因而各个子单元区 100a的预设开孔率相同。
子单元区100a的预设开孔率是指：一个子单元区100a中凹槽101的总体积与该子单元区100a衬底块材料体积的百分比。
预设开孔密度是指：子单元区100a单位体积内凹槽101的数目。
导热材料102可以为多孔材料，例如低K介质层(SiO 2)、氧化镁(MgO)、三氧化二铝(Al 2O 3)等。
一个单元区100中，各个子单元区100a的凹槽101内填入的导热材料102的孔隙率不同。
参照图2所示，本实施例中，导热材料102填满了凹槽101。
接着，参照图3中的步骤S2、图4与图5所示，在衬底正面10a生长发光层20；一个单元区100中，各子单元区100a的发光层20的发光波长不同。
生长发光层20时，衬底的背面10b置于反应腔室内的基台上。基台内设置有加热装置，基台向衬底10传热，以将衬底10加热至生长温度。
发光层20可以包括N型半导体层20a，P型半导体层20b，以及位于N型半导体层20a与P型半导体层20b之间的多量子阱材料层20c。
N型半导体层20a、多量子阱材料层20c与P型半导体层20b的材料可以为GaN、AlN、InN、InAlGaN、InAlN、GaAs、AlGaAs中的至少一种，形成工艺可以包括：原子层沉积法(ALD，Atomic layer deposition)、或化学气相沉积法(CVD，Chemical Vapor Deposition)、或分子束外延生长法(MBE，Molecular Beam Epitaxy)、或等离子体增强化学气相沉积法(PECVD，Plasma Enhanced Chemical Vapor Deposition)、或低压化学蒸发沉积法(LPCVD，Low Pressure Chemical Vapor Deposition)，或金属有机化合物化学气相沉积法(MOCVD，Metal-Organic Chemical Vapor Deposition)、或其组合方式。
在衬底10上形成N型半导体层20a之前，还可以先依次形成成核层及缓冲层(未图示)，成核层的材质可以例如为AlN、AlGaN等，缓冲层的材质可以包括AlN、GaN、AlGaN、AlInGaN中的至少一种。缓冲层的形成方法可以与N型半导体层20a的形成方法相同。成核层可以缓解外延生长的半导体层，例如N型半导体层20a与多量子阱材料层20c之间、多量子阱材料层20c与P型半导体层20b之间的晶格失配和热失配的问题，缓冲层可以降低外延生长的半导体层的位错密度和缺陷密度，提升晶体质量。
本步骤S2中，各个子单元区100a的预设开孔率相同，凹槽101内的导热材料102的孔隙率越大，对应处的发光层20的发光波长可以越长；导热材料102的孔隙率越小，对应处的发光层20的发光波长可以越短。导热材料102的孔隙率越大，传热效率越差，子单元区100a正面的温度越低，导热材料102的孔隙率越小，传热效率越好，子单元区100a正面的温度越高。生长的多量子阱材料层10c的发光波长是会随着温度变化的。具体的，首先，在直接带隙材料中，波长是与禁带宽度成反比的；其次，某些半导体材料的禁带宽度具有正的温度系数，即当生长温度升高时，禁带宽度增大，因此波长与温度之间成反比；某些半导体材料具有负的温度系数，即当生长温度升高时，禁带宽度减小，因此波长与温度之间成正比。例如常见的InGaN为正温度系数的半导体材料。
一些实施例中，也可以P型半导体层20b靠近衬底10，N型半导体层20a远离衬底10。
一些实施例中，一个单元区100中，各个子单元区100a的凹槽101内填入的导热材料102的导热系数可以不同。导热材料102的成分可以不同，例如为不同的金属或介电材料，例如铜、铝、二氧化硅、氮化硅等。
具体地，导热材料102的导热系数越大，对应处的发光层20的发光波长可以越短，导热材料102的导热系数越小，对应处的发光层20的发光波长可以越长。这是因为：导热材料102的导热系数越大，传热效率越好，导热 材料102处的温度越高，对于禁带宽度随生长温度的变高而变宽的多量子阱材料层20c，生长的多量子阱材料层20c的禁带宽度变宽，电子跃迁产生的光子的频率变大，波长变短。相反地，导热材料102的导热系数越小，传热效率越差，导热材料102处的温度越低，生长的多量子阱材料层20c的禁带宽度变窄，电子跃迁产生的光子的频率变小，波长变长。
一些实施例中，还可以继续在半导体结构上制作分别电连接N型半导体层20a与P型半导体层20b的电连接结构，以形成全彩LED。
对于用于显示的半导体结构，每一像素单元区100生长的发光层20形成一个发光单元。对于用于照明的半导体结构，还可以沿着相邻照明单元区100之间的切割道切割，形成多个照明单元。
本实施例的半导体结构的制作方法中，一个单元区100中，自预制作衬底10'的正面10a在每一子单元区100a内开设预设深度、预设宽度以及预设开孔密度相同的凹槽101，在不同凹槽101内填入不同导热材料102形成衬底10。基台向衬底10传热过程中，各个子单元区100a的传热效率不同，利用生长温度对多量子阱材料层20c的发光特性的影响，从而在衬底正面10a生长发光层20时，实现不同子单元区100a的发光层20的发光波长不同。上述工艺简单，且能在一个衬底10上制作用于全彩LED的半导体结构，减小了全彩LED的尺寸，降低了成本。
图6是本发明第二实施例的衬底的俯视图，图7是沿着图6中的CC线的剖视图。图8是图6与图7中的衬底的制作方法的流程图。
参照图6至图8所示，本实施例二的衬底及其制作方法与实施例一的半导体结构中的衬底及其制作方法完全相同，即实施例一的半导体结构中的衬底及其制作方法全部引入本实施例二中。实施例一的半导体结构中的衬底10可单独生产与销售。
图9是本发明第三实施例的半导体结构的截面结构示意图。图10是图 9中的半导体结构的制作方法的流程图。
参照图9与图10所示，本实施例三的半导体结构与实施例一的半导体结构大致相同，区别仅在于：凹槽101自衬底10的背面10b开设。对应地，本实施例三的半导体结构的制作方法与实例一的半导体结构的制作方法大致相同，区别仅在于：步骤S1'中，自预制作衬底10'的背面10b开设凹槽101。
一些实施例中，一个单元区100中，还可以部分数目的子单元区100a的凹槽101自预制作衬底10'的正面10a开设，部分数目的子单元区100a的凹槽101自预制作衬底10'的背面10b开设，各个子单元区100a的凹槽101的预设深度相同、预设宽度相同，以及预设开孔密度相同，以控制各个子单元区100a的预设开孔率相同。
不论自预制作衬底10'的背面10b开设凹槽101，还是自预制作衬底10'的正面10a开设凹槽101，一个单元区100中，各个子单元区100a的预设开孔率相同，不同子单元区100a的凹槽101内填入的导热材料102不同。因而，使得基台向衬底10传热过程中，利用不同导热材料102的传热效率不同，生长温度对多量子阱材料层20c的发光特性具有影响，从而在衬底正面10a生长的发光层20的发光波长不同。
图11是本发明第四实施例的衬底的截面结构示意图。图12是图11中的衬底的制作方法的流程图。
参照图11与图12所示，本实施例四的衬底及其制作方法与实施例三的半导体结构中的衬底及其制作方法完全相同，即实施例三的半导体结构中的衬底及其制作方法全部引入本实施例四中。实施例三的半导体结构中的衬底10可单独生产与销售。
图13是本发明第五实施例的半导体结构的截面结构示意图。
参照图13所示，本实施例五的半导体结构与实施例一、三的半导体结构大致相同，区别仅在于：每个子单元区100a的凹槽101自衬底10的正面 10a与背面10b开设；各个子单元区100a的凹槽101的预设深度之和相同、预设宽度相同，以及预设开孔密度相同，以控制各个子单元区100a的预设开孔率相同。对应地，本实施例五的半导体结构的制作方法与实例一、三的半导体结构的制作方法大致相同，区别仅在于：步骤S1中，自预制作衬底10'的正面10a与背面10b分别在每个子单元区100a内开设凹槽101；各个子单元区100a的两个凹槽101的预设深度之和相同、预设宽度相同，以及预设开孔密度相同，以控制各个子单元区100a的预设开孔率相同。
一个单元区100中，每个子单元区100a的两个凹槽101内填入的导热材料102的孔隙率相同；各子单元区100a的凹槽101内填入的导热材料102的孔隙率不同。一些实施例中，每个子单元区100a的两个凹槽101内填入的导热材料102的孔隙率可以不同。
一个单元区100中，每个子单元区100a的两个凹槽101内填入的导热材料102的导热系数相同；各子单元区100a的凹槽101内填入的导热材料102的导热系数不同。一些实施例中，每个子单元区100a的两个凹槽101内填入的导热材料102的导热系数可以不同。
一些实施例中，一个单元区100中，也可以部分数目的子单元区100a的凹槽101自衬底10的正面10a或背面10b开设；部分数目的子单元区100a的凹槽101自衬底10的正面10a与背面10b开设。自衬底10的正面10a或背面10b开设的凹槽101的预设深度等于自衬底10的正面10a与背面10b开设的凹槽101的预设深度之和，此外，各凹槽101的预设宽度相同，以及预设开孔密度相同，以控制各个子单元区100a的预设开孔率相同。
图14是本发明第六实施例的衬底的截面结构示意图。
参照图14所示，本实施例六的衬底及其制作方法与实施例五的半导体结构中的衬底及其制作方法完全相同，即实施例五的半导体结构中的衬底及其制作方法全部引入本实施例六中。实施例五的半导体结构中的衬底10可单 独生产与销售。
图15是本发明第七实施例的半导体结构的截面结构示意图。
参照图15所示，本实施例七的半导体结构与实施例一、三的半导体结构大致相同，区别仅在于：一个单元区100中，各个子单元区100a的凹槽101的预设深度不同。对应地，本实施例七的半导体结构的制作方法与实例一、三的半导体结构的制作方法大致相同，区别仅在于：步骤S1中，一个单元区100中，自预制作衬底10'的正面10a在各个子单元区100a内开设预设宽度相同，以及预设开孔密度相同，但预设深度不同的凹槽101。
一个单元区100中，各个子单元区100a的凹槽101之间的预设深度差可以为固定值，也可以为可变值。
一些实施例中，一个单元区100中，各个子单元区100a的凹槽101的预设宽度可以不同，或预设开孔密度不同，以调节各个子单元区100a的预设开孔率不同。
一些实施例中，一个单元区100中，各个子单元区100a的凹槽101的预设深度不同，和/预设宽度不同，和/或预设开孔密度不同，以调节各个子单元区100a的预设开孔率不同。例如，两个子单元区100a的凹槽101的预设深度不同，与另一个子单元区100a的凹槽101的预设宽度不同(或预设开孔密度不同)。
一些实施例中，一个子单元区100a的预设开孔率越大，该子单元区100a的凹槽101内填充的导热材料102的孔隙率可以越大，以进一步降低该子单元区100a的传热效率；一个子单元区100a的预设开孔率越小，该子单元区100a的凹槽101内填充的导热材料102的孔隙率可以越小，以进一步提高该子单元区100a的的传热效率。
一些实施例中，一个子单元区100a的预设开孔率越大，该子单元区100a的凹槽101内填充的导热材料102的孔隙率也可以越小；一个子单元区100a 的预设开孔率越小，该子单元区100a的凹槽101内填充的导热材料102的孔隙率越大，以对不同预设开孔率的子单元区100a的传热效率进行微调。
一些实施例中，各个子单元区100a的凹槽101内填充的导热材料102的孔隙率相同。
一些实施例中，不同预设开孔率的子单元区100a的凹槽101内填充的导热材料102的成分不同。一个子单元区100a的预设开孔率越大，该子单元区100a的凹槽101内填充的导热材料102的导热系数越小，以进一步降低该子单元区100a的传热效率；一个子单元区100a的预设开孔率越小，该子单元区100a的凹槽101内填充的导热材料102的导热系数越大，以进一步提高该子单元区100a的传热效率。
一些实施例中，一个子单元区100a的预设开孔率越大，该子单元区100a的凹槽101内填充的导热材料102的导热系数越大；一个子单元区100a的预设开孔率越小，该子单元区100a的凹槽101内填充的导热材料102的导热系数越小，以对不同预设开孔率子单元区100a的传热效率进行微调。
一些实施例中，不同预设开孔率的子单元区100a的凹槽101内填充的导热材料102的成分相同或导热系数相同。
一些实施例中，凹槽101还可以自预制作衬底10'的背面10b开设。
一些实施例中，一个单元区100中，还可以部分数目的子单元区100a的凹槽101自预制作衬底10'的正面10a开设，部分数目的子单元区100a的凹槽101自预制作衬底10'的背面10b开设，各个子单元区100a的凹槽101的预设深度不同、和/或预设宽度不同，和/或预设开孔密度不同，以控制各个子单元区100a的预设开孔率不同。
本实施例的方案可以与实施一、三、五的方案结合。即一个单元区100中，部分数目的子单元区100a的凹槽101预设深度或预设深度之和相同、预设宽度相同，以及预设开孔密度相同，以控制各个子单元区100a的预设开孔 率相同，其内的导热材料102的孔隙率或导热系数不同；部分数目的子单元区100a的凹槽101预设深度不同、和/或预设宽度不同，和/或预设开孔密度不同，以控制各个子单元区100a的预设开孔率不同。
图16是本发明第八实施例的衬底的截面结构示意图。
参照图16所示，本实施例八的衬底及其制作方法与实施例七的半导体结构中的衬底及其制作方法完全相同，即实施例七的半导体结构中的衬底及其制作方法全部引入本实施例八中。实施例七的半导体结构中的衬底10可单独生产与销售。
图17是本发明第九实施例的半导体结构的截面结构示意图。
参照图17所示，本实施例九的半导体结构与实施例八的半导体结构大致相同，区别仅在于：每个子单元区100a的凹槽101自衬底10的正面10a与背面10b开设；各个子单元区100a的两个凹槽101的预设宽度相同，以及预设开孔密度相同，但预设深度之和不同，以控制各个子单元区100a的预设开孔率不同。对应地，本实施例九的半导体结构的制作方法与实例八的半导体结构的制作方法大致相同，区别仅在于：步骤S1中，自预制作衬底10'的正面10a与背面10b在每个子单元区100a内开设凹槽101；各个子单元区100a的两个凹槽101的预设宽度相同，以及预设开孔密度相同，但预设深度之和不同，以控制各个子单元区100a的预设开孔率不同。
一些实施例中，一个单元区100中，各个子单元区100a的凹槽101的预设宽度可以不同，或预设开孔密度不同，以调节各个子单元区100a的预设开孔率不同。
一些实施例中，一个单元区100中，各个子单元区100a的凹槽101的预设深度不同，和/预设宽度不同，和/或预设开孔密度不同，以调节各个子单元区100a的预设开孔率不同。例如，两个子单元区100a的凹槽101的预设深度不同，与另一个子单元区100a的凹槽101的预设宽度不同(或预设开孔密 度不同)。
一个单元区100中，每个子单元区100a的两个凹槽101内填入的导热材料102的孔隙率相同；各子单元区100a的凹槽101内填入的导热材料102的孔隙率不同。一个子单元区100a的孔隙率越大(两个凹槽101的预设深度之和越大)，其凹槽101内填充的导热材料102的孔隙率越大；一个子单元区100a的孔隙率越小(两个凹槽101的预设深度之和越小)，其凹槽101内填充的导热材料102的孔隙率越小。
一些实施例中，各子单元区100a的凹槽101内填入的导热材料102的孔隙率也可以相同。
一些实施例中，每个子单元区100a的两个凹槽101内填入的导热材料102的孔隙率可以不同。
一个单元区100中，每个子单元区100a的两个凹槽101内填入的导热材料102的导热系数相同；各子单元区100a的凹槽101内填入的导热材料102的导热系数不同。一个子单元区100a的孔隙率越大(两个凹槽101的预设深度之和越大)，其凹槽101内填充的导热材料102的导热系数越小；一个子单元区100a的孔隙率越小(两个凹槽101的预设深度之和越小)，其凹槽101内填充的导热材料102的导热系数越大。
一些实施例中，各子单元区100a的凹槽101内填入的导热材料102的导热系数也可以相同。
一些实施例中，每个子单元区100a的两个凹槽101内填入的导热材料102的导热系数可以不同。
一些实施例中，一个单元区100中，也可以部分数目的子单元区100a的凹槽101自衬底10的正面10a或背面10b开设；部分数目的子单元区100a的凹槽101自衬底10的正面10a与背面10b开设。自衬底10的正面10a或背面10b开设的凹槽101的预设深度不等于自衬底10的正面10a与背面10b开 设的凹槽101的预设深度之和，或凹槽101的预设宽度不同，和/或预设开孔密度不同，以控制各个子单元区100a的预设开孔率不同。
本实施例的方案可以与实施一、三、五的方案结合。即一个单元区100中，部分数目的子单元区100a的凹槽101预设深度或预设深度之和相同、预设宽度相同，以及预设开孔密度相同，以控制各个子单元区100a的预设开孔率相同，其内的导热材料102的孔隙率或导热系数不同；部分数目的子单元区100a的凹槽101预设深度之和不同、和/或预设宽度不同，和/或预设开孔密度不同，以控制各个子单元区100a的预设开孔率不同。
图18是本发明第十实施例的衬底的截面结构示意图。
参照图18所示，本实施例十的衬底及其制作方法与实施例九的半导体结构中的衬底及其制作方法完全相同，即实施例九的半导体结构中的衬底及其制作方法全部引入本实施例十中。实施例九的半导体结构中的衬底10可单独生产与销售。
图19是本发明第十一实施例的半导体结构的截面结构示意图。
参照图19所示，本实施例十一的半导体结构与实施例一、三、五、七、九的半导体结构大致相同，区别仅在于：凹槽101内形成有空气隙101a。对应地，本实施例十一的半导体结构的制作方法与实施例一、三、五、七、九的半导体结构的制作方法大致相同，区别仅在于：步骤S1中，在凹槽101内填入导热材料102时，凹槽101内形成有空气隙101a。
本实施例十一中，利用空气隙101a的大小结合导热材料102的多少调整传热效率。
空气隙101a可通过减小沉积工艺中等离子源与基台之间的偏置电压，或不施加偏置电压，和/或减少腔室的抽气速率实现。
图20是本发明第十二实施例的衬底的截面结构示意图。
参照图20所示，本实施例十二的衬底及其制作方法与实施例十一的半 导体结构中的衬底及其制作方法完全相同，即实施例十一的半导体结构中的衬底及其制作方法全部引入本实施例十二中。实施例十一的半导体结构中的衬底10可单独生产与销售。
图21是本发明第十三实施例的半导体结构的截面结构示意图。
参照图21所示，本实施例九的半导体结构与实施例一、三、五、七、九、十一的半导体结构大致相同，区别仅在于：发光层20包括多层交叠设置的N型半导体层20a与P型半导体层20b，相邻N型半导体层20a与P型半导体层20b之间设置有多量子阱材料层20c。对应地，本实施例九的半导体结构的制作方法与实施例一、三、五、七、九、十一的半导体结构的制作方法大致相同，区别仅在于：步骤S2中，生长的发光层20包括多层交叠设置的N型半导体层20a与P型半导体层20b，相邻N型半导体层20a与P型半导体层20b之间设置有多量子阱材料层20c。
本实施例十三的半导体结构相对于实施例一、三、五、七、九、十一的半导体结构，能提高发光层20的发光效率。
在本发明中，术语“若干”指一个、两个或两个以上，除非另有明确的限定。
虽然本发明披露如上，但本发明并非限定于此。任何本领域技术人员，在不脱离本发明的精神和范围内，均可作各种更动与修改，因此本发明的保护范围应当以权利要求所限定的范围为准。

Claims (34)

  1. 一种衬底，其特征在于，所述衬底(10)包括若干单元区(100)，每一单元区(100)包括至少两个子单元区(100a)，每一所述子单元区(100a)具有凹槽(101)，所述凹槽(101)内具有导热材料(102)；一个所述单元区(100)中，各个子单元区(100a)的导热系数不同。
  2. 根据权利要求1所述的衬底，其特征在于，一个所述单元区(100)中，各个所述子单元区(100a)的预设开孔率不同。
  3. 根据权利要求2所述的衬底，其特征在于，一个所述单元区(100)中，各个所述子单元区(100a)的所述凹槽(101)的预设深度不同，和/或预设宽度不同，和/或预设开孔密度不同。
  4. 根据权利要求1至3任一项所述的衬底，其特征在于，每个所述单元区(100)中，所述凹槽(101)自所述衬底(10)的正面(10a)和/或背面(10b)开设；或
    每个所述单元区(100)中，部分数目的所述子单元区(100a)的所述凹槽(101)自所述衬底(10)的正面(10a)或背面(10b)开设；部分数目的所述子单元区(100a)的所述凹槽(101)自所述衬底(10)的正面(10a)与背面(10b)开设。
  5. 根据权利要求4所述的衬底，其特征在于，一个所述单元区(100)中：各个所述子单元区(100a)的预设开孔率不同；或各个所述子单元区(100a)的预设开孔率相同；或部分数目的所述子单元区(100a)的预设开孔率不同，部分数目的所述子单元区(100a)的预设开孔率相同。
  6. 根据权利要求4或5所述的衬底，其特征在于，一个所述单元区(100)中：各个所述子单元区(100a)的所述凹槽(101)内的所述导热材料(102)不同；或各个所述子单元区(100a)的所述凹槽(101)内的所述导热材料(102)相同；或部分数目的所述子单元区(100a)的所述凹槽(101)内的所述导热材料(102)不同，部分数目的所述子单元区(100a)的所述凹槽(101)内的 所述导热材料(102)相同。
  7. 根据权利要求6所述的衬底，其特征在于，一个所述单元区(100)中：各个所述子单元区(100a)的所述凹槽(101)内的所述导热材料(102)的孔隙率不同；或各个所述子单元区(100a)的所述凹槽(101)内的所述导热材料(102)的孔隙率相同；或部分数目的所述子单元区(100a)的所述凹槽(101)内的所述导热材料(102)的孔隙率不同，部分数目的所述子单元区(100a)的所述凹槽(101)内的所述导热材料(102)的孔隙率相同。
  8. 根据权利要求7所述的衬底，其特征在于，所述子单元区(100a)的预设开孔率越大，所述凹槽(101)内的所述导热材料(102)的孔隙率越大；所述子单元区(100a)的预设开孔率越小，所述凹槽(101)内的所述导热材料(102)的孔隙率越小。
  9. 根据权利要求6所述的衬底，其特征在于，一个所述单元区(100)中：各个所述子单元区(100a)的所述凹槽(101)内的所述导热材料(102)的导热系数不同；或各个所述子单元区(100a)的所述凹槽(101)内的所述导热材料(102)的导热系数相同；或部分数目的所述子单元区(100a)的所述凹槽(101)内的所述导热材料(102)的导热系数不同，部分数目的所述子单元区(100a)的所述凹槽(101)内的所述导热材料(102)的导热系数相同。
  10. 根据权利要求9所述的衬底，其特征在于，所述子单元区(100a)的预设开孔率越大，所述凹槽(101)内的所述导热材料(102)的导热系数越小；所述子单元区(100a)的预设开孔率越小，所述凹槽(101)内的所述导热材料(102)的导热系数越大。
  11. 根据权利要求1所述的衬底，其特征在于，所述导热材料(102)填满所述凹槽(101)，或所述凹槽(101)内形成有空气隙(101a)。
  12. 根据权利要求1所述的衬底，其特征在于，所述衬底(10)的材料为蓝宝石、硅、碳化硅、GaN基材料中的至少一种。
  13. 一种半导体结构，其特征在于，包括：
    权利要求1至12任一项所述的衬底(10)；
    位于所述衬底正面(10a)的发光层(20)；一个所述单元区(100)中，各子单元区(100a)的所述发光层(20)的发光波长不同。
  14. 根据权利要求13所述的半导体结构，其特征在于，所述发光层(20)包括N型半导体层(20a)，P型半导体层(20b)，以及位于所述N型半导体层(20a)与所述P型半导体层(20b)之间的多量子阱材料层(20c)。
  15. 根据权利要求13所述的半导体结构，其特征在于，所述发光层(20)包括多层交叠设置的N型半导体层(20a)与P型半导体层(20b)，相邻所述N型半导体层(20a)与所述P型半导体层(20b)之间设置有多量子阱材料层(20c)。
  16. 根据权利要求13所述的半导体结构，其特征在于，所述半导体结构用于显示；每一所述单元区(100)的所述发光层(20)形成一个发光单元。
  17. 一种衬底的制作方法，其特征在于，包括：
    提供预制作衬底(10')，所述预制作衬底(10')包括若干单元区(100)，每一所述单元区(100)包括至少两个子单元区(100a)；自所述预制作衬底(10')的表面在每一所述子单元区(100a)内开设凹槽(101)；在所述凹槽(101)内填充导热材料(102)以形成衬底(10)；一个所述单元区(100)中，各个子单元区(100a)的导热系数不同。
  18. 根据权利要求17所述的衬底的制作方法，其特征在于，在所述凹槽(101)内填充导热材料(102)前，一个所述单元区(100)中，各个所述子单元区(100a)的预设开孔率不同。
  19. 根据权利要求18所述的衬底的制作方法，其特征在于，一个所述单元区(100)中，各个所述子单元区(100a)的所述凹槽(101)的预设深度不同，和/或预设宽度不同，和/或预设开孔密度不同。
  20. 根据权利要求17至19任一项所述的衬底的制作方法，其特征在于，每个所述单元区(100)中，所述凹槽(101)自所述预制作衬底(10')的正面(10a)或背面(10b)开设；或
    每个所述单元区(100)中，部分数目的所述子单元区(100a)的所述凹 槽(101)自所述衬底(10)的正面(10a)或背面(10b)开设；部分数目的所述子单元区(100a)的所述凹槽(101)自所述衬底(10)的正面(10a)与背面(10b)开设。
  21. 根据权利要求20所述的衬底的制作方法，其特征在于，一个所述单元区(100)中：各个所述子单元区(100a)的预设开孔率不同；或各个所述子单元区(100a)的预设开孔率相同；或部分数目的所述子单元区(100a)的预设开孔率不同，部分数目的所述子单元区(100a)的预设开孔率相同。
  22. 根据权利要求20或21所述的衬底的制作方法，其特征在于，一个所述单元区(100)中：各个所述子单元区(100a)的所述凹槽(101)内填充的所述导热材料(102)不同；或各个所述子单元区(100a)的所述凹槽(101)内填充的所述导热材料(102)相同；或部分数目的所述子单元区(100a)的所述凹槽(101)内填充的所述导热材料(102)不同，部分数目的所述子单元区(100a)的所述凹槽(101)内填充的所述导热材料(102)相同。
  23. 根据权利要求22所述的衬底的制作方法，其特征在于，一个所述单元区(100)中：各个所述子单元区(100a)的所述凹槽(101)内填充的所述导热材料(102)的孔隙率不同；或各个所述子单元区(100a)的所述凹槽(101)内填充的所述导热材料(102)的孔隙率相同；或部分数目的所述子单元区(100a)的所述凹槽(101)内填充的所述导热材料(102)的孔隙率不同，部分数目的所述子单元区(100a)的所述凹槽(101)内填充的所述导热材料(102)的孔隙率相同。
  24. 根据权利要求23所述的衬底的制作方法，其特征在于，所述子单元区(100a)的预设开孔率越大，所述凹槽(101)内填充的所述导热材料(102)的孔隙率越大；所述子单元区(100a)的预设开孔率越小，所述凹槽(101)内填充的所述导热材料(102)的孔隙率越小。
  25. 根据权利要求22所述的衬底的制作方法，其特征在于，一个所述单元区(100)中：各个所述子单元区(100a)的所述凹槽(101)内填充的所述导热材料(102)的导热系数不同；或各个所述子单元区(100a)的所述凹槽 (101)内填充的所述导热材料(102)的导热系数相同；或部分数目的所述子单元区(100a)的所述凹槽(101)内填充的所述导热材料(102)的导热系数不同，部分数目的所述子单元区(100a)的所述凹槽(101)内填充的所述导热材料(102)的导热系数相同。
  26. 根据权利要求25所述的衬底的制作方法，其特征在于，所述子单元区(100a)的预设开孔率越大，所述凹槽(101)内填充的所述导热材料(102)的导热系数越小；所述子单元区(100a)的预设开孔率越小，所述凹槽(101)内填充的所述导热材料(102)的导热系数越大。
  27. 根据权利要求17所述的衬底的制作方法，其特征在于，在所述凹槽(101)内填充导热材料(102)步骤中，所述导热材料(102)填满所述凹槽(101)，或所述凹槽(101)内形成有空气隙(101a)。
  28. 一种半导体结构的制作方法，其特征在于，包括：
    根据权利要求17至27任一项所述的制作方法制作衬底(10)；
    在所述衬底正面(10a)生长发光层(20)；一个所述单元区(100)中，各子单元区(100a)的所述发光层(20)的发光波长不同。
  29. 根据权利要求28所述的半导体结构的制作方法，其特征在于，所述发光层(20)包括N型半导体层(20a)，P型半导体层(20b)，以及位于所述N型半导体层(20a)与所述P型半导体层(20b)之间的多量子阱材料层(20c)。
  30. 根据权利要求28所述的半导体结构的制作方法，其特征在于，所述发光层(20)包括多层交叠设置的N型半导体层(20a)与P型半导体层(20b)，相邻所述N型半导体层(20a)与所述P型半导体层(20b)之间设置有多量子阱材料层(20c)。
  31. 根据权利要求29或30所述的半导体结构的制作方法，其特征在于，所述多量子阱材料层(20c)的禁带宽度随生长温度的变高而变宽；所述子单元区(100a)的预设开孔率越大，所述凹槽(101)内的所述导热材料(102)的孔隙率越大，对应的发光层(20)的发光波长越长；所述子单元区(100a)的预设开孔率越小，所述凹槽(101)内的所述导热材料(102)的孔隙率越小， 对应的发光层(20)的发光波长越短。
  32. 根据权利要求29或30所述的半导体结构的制作方法，其特征在于，所述多量子阱材料层(20c)的禁带宽度随生长温度的变高而变宽；所述子单元区(100a)的预设开孔率越大，所述凹槽(101)内的所述导热材料(102)的导热系数越小，对应的发光层(20)的发光波长越长；所述子单元区(100a)的预设开孔率越小，所述凹槽(101)内的所述导热材料(102)的导热系数越大，对应的发光层(20)的发光波长越短。
  33. 根据权利要求28所述的半导体结构的制作方法，其特征在于，所述发光层(20)的生长方法包括：原子层沉积法、或化学气相沉积法、或分子束外延生长法、或等离子体增强化学气相沉积法、或低压化学蒸发沉积法，或金属有机化合物化学气相沉积法中的至少一种。
  34. 根据权利要求28所述的半导体结构的制作方法，其特征在于，所述半导体结构用于显示；在每一所述单元区(100)生长的所述发光层(20)形成一个发光单元。
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