WO2021138838A1 - 一种图像读取电路、图像传感器以及终端设备 - Google Patents

一种图像读取电路、图像传感器以及终端设备 Download PDF

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Publication number
WO2021138838A1
WO2021138838A1 PCT/CN2020/070926 CN2020070926W WO2021138838A1 WO 2021138838 A1 WO2021138838 A1 WO 2021138838A1 CN 2020070926 W CN2020070926 W CN 2020070926W WO 2021138838 A1 WO2021138838 A1 WO 2021138838A1
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Prior art keywords
voltage
circuit
sampling
pixel
electrically connected
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PCT/CN2020/070926
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English (en)
French (fr)
Inventor
郑胜群
叶天翔
潘撼
唐样洋
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华为技术有限公司
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Priority to PCT/CN2020/070926 priority Critical patent/WO2021138838A1/zh
Priority to CN202080090751.0A priority patent/CN114982222A/zh
Publication of WO2021138838A1 publication Critical patent/WO2021138838A1/zh

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/71—Charge-coupled device [CCD] sensors; Charge-transfer registers specially adapted for CCD sensors
    • H04N25/75—Circuitry for providing, modifying or processing image signals from the pixel array

Definitions

  • This application relates to the technical field of electronic circuits, and in particular to an image reading circuit, an image sensor and a terminal device.
  • An image sensor is a sensor that converts optical images into electrical signals, and is widely used in terminal devices such as digital cameras and smart phones.
  • image sensors are mainly a type of CMOS image sensor (complementary metal oxide semiconductor image sensor, CIS) manufactured using a complementary metal oxide semiconductor (CMOS) process.
  • CMOS complementary metal oxide semiconductor
  • the circuit included in the image sensor (CIS) is called an image reading circuit.
  • the image reading circuit mainly includes two parts: a photosensitive part and a non-photosensitive part (the non-photosensitive part is also called a data reading part).
  • the photosensitive part is composed of a pixel array, and the basic unit included in the pixel array is called a pixel (or a photoelectric conversion circuit (photovoltaic conversion circuit)), and each pixel includes a photosensor and other circuits.
  • the photoelectric sensor in the pixel uses the photoelectric effect to convert the received photons into photoelectrons.
  • Other circuits in the pixel except the photoelectric sensor) convert and store the photoelectron to obtain the corresponding electrical signal.
  • the data readout part (including the column readout circuit) quantizes and processes the electrical signal.
  • the process of receiving photons by the photoelectric sensor is called exposure.
  • the image reading circuit performs a reset operation.
  • CMS correlated multiple sampling
  • the photoelectric conversion circuit includes a reset circuit, and the voltage applied to the photoelectric conversion circuit when the reset circuit performs a reset operation is called a reset voltage. Since the photoelectric conversion circuit needs to undergo a reset operation before receiving photoelectrons, the voltage collected by the image reading circuit according to the received photoelectrons includes the reset voltage and the voltage generated by the photoelectrons. The collected voltage is called the pixel Voltage.
  • the specific operation of the related multi-sampling is: sampling the pixel voltage and the reset voltage multiple times. Therefore, by subtracting the multi-sampled pixel voltage from the multi-sampled reset voltage and dividing by the number of samplings, the voltage value actually generated by the received photoelectron can be obtained.
  • the number of samplings is also called M, where M is Positive integer.
  • the effective voltage the reset voltage and the voltage generated by the photoelectron
  • the result of multiple sampling is equivalent to multiplying the effective voltage by M times.
  • random noise since it is random in the time domain, with positive and negative, the random noise accumulated by multiple sampling is equivalent to a result of mean filtering in the time domain, so the noise is effectively suppressed after multiple sampling.
  • the reset noise can be effectively eliminated.
  • an analog-to-digital converter needs to be used to convert analog signals such as voltage into digital signals (such as digital codes) for subsequent component processing.
  • M value the number of sampling
  • the pixel voltage collected by the image reading circuit has a higher voltage value.
  • the pixel voltage is multiplied by The result of M often exceeds the quantization range of the ADC. New errors are generated in the ADC's analog-to-digital conversion process, which in turn affects the quality of the output image.
  • the first aspect of the embodiments of the present application provides an image reading circuit, an image sensor, and a terminal device, which improve the quality of output images and improve the dynamic range of pixels.
  • an embodiment of the present application proposes an image reading circuit, which includes: a photoelectric conversion circuit, a decision circuit (decision circuit), and a correlated multiple sampling circuit (CMS circuit).
  • the photoelectric conversion circuit includes a photoelectric sensor and a reset circuit.
  • the photoelectric sensor uses the photoelectric effect to convert the received photons into photoelectrons.
  • the reset circuit is used to output a reset voltage.
  • the reset circuit can be composed of one or more components.
  • the reset circuit (reset circuit) can also be implemented by one or more reset transistors or reset transistors, which is not limited here; the photoelectric conversion circuit is used to collect the pixel voltage and output the pixel voltage to the judgment circuit.
  • the photoelectric conversion circuit further collects the photoelectrons output by the photoelectric sensor on the basis of the electrons corresponding to the reset voltage to complete the collection of the pixel voltage; the judgment circuit is used to determine the first sampling according to the pixel voltage The number of times, where the first number of sampling times is negatively correlated with the pixel voltage. Specifically, when the pixel voltage collected by the photoelectric conversion circuit is larger, the first sampling number determined by the judging circuit according to the pixel voltage is smaller.
  • the correlated multi-sampling circuit is used for performing the pixel voltage and the reset voltage according to the first sampling number Correlated multi-sampling to determine the first voltage, the first voltage is a voltage generated by photoelectrons, and the first voltage is positively correlated with the light intensity.
  • the image reading circuit determines the sampling times of correlated multi-sampling according to the pixel voltage. Secondly, the image reading circuit performs correlated multi-sampling on the pixel voltage and the reset voltage according to the determined sampling times to determine the first voltage.
  • the first voltage is the voltage generated by photoelectrons. Since the photoelectric conversion circuit further collects the photoelectrons output by the photoelectric sensor on the basis of the electrons corresponding to the reset voltage to complete the collection of the pixel voltage, the pixel voltage is positively correlated with the light intensity, that is, the greater the light intensity, the greater the pixel voltage; the greater the light intensity The smaller the pixel voltage is.
  • the image reading circuit determines the lower sampling times according to the higher pixel voltages collected, avoiding the pixel voltage multiplied by the sampling times, exceeding the quantization range of the ADC, and improving the output image the quality of.
  • the image reading circuit determines a higher sampling frequency according to the smaller pixel voltage, which reduces the noise of the output image in the dark light environment and improves the quality of the output image , Improve the dynamic range of pixels.
  • the photoelectric conversion circuit may further include: a first transistor, a second transistor, a first capacitor, and a second capacitor, wherein the first transistor and the photoelectric sensor Electrically connected, the first transistor is electrically connected to the second capacitor, the first transistor is electrically connected to the reset circuit, and the first transistor is used to turn on or turn off the photoelectric sensor and the second capacitor.
  • the first transistor is also used to control the on or off of the connection path between the reset circuit and the second capacitor, the second capacitor is used to collect the pixel voltage; the second transistor and the first transistor Electrically connected, the second transistor is electrically connected to the first capacitor, wherein the second transistor and the first transistor are used together to control the on or off of the connection path between the reset circuit and the first capacitor, the The first capacitor is used to collect the reset voltage; the correlated multi-sampling circuit is electrically connected to the second transistor, and the second transistor is used to control the on or off of the connection path between the correlated multi-sampling circuit and the first capacitor ; The correlated multi-sampling circuit is electrically connected to the second capacitor.
  • the first capacitor collects the reset voltage under the common control of the first transistor and the second transistor, and the second capacitor collects the pixel voltage under the control of the first transistor, so that the photoelectric conversion circuit
  • the pixel voltage can be output to the judgment circuit (and the correlated multi-sampling circuit) first, so that the judgment circuit determines the first sampling times according to the pixel voltage, where the pixel voltage is positively correlated with the light intensity, and the first sampling times is negatively correlated with the pixel voltage.
  • the judgment circuit specifically includes a first voltage comparator (voltage comparator), a threshold voltage generator circuit (threshold voltage generator), and a multi-sampling frequency selection circuit (multi-sampling circuit).
  • the first voltage comparator is electrically connected to the threshold voltage generating circuit, and the threshold voltage generating circuit is used to generate a first threshold voltage; the first voltage comparator is electrically connected to the second capacitor, and the first voltage The comparator is used to compare the first threshold voltage with the pixel voltage to generate a first voltage comparison result; the first voltage comparator is electrically connected to the multi-sampling number selection circuit, and the multi-sampling number selection circuit compares according to the first voltage As a result, the first sampling number is determined.
  • the first voltage comparator compares the first threshold voltage with the pixel voltage from the photoelectric conversion circuit to determine the first voltage comparison result.
  • the first threshold voltage generated by the threshold voltage generating circuit includes 0.25 volt (V), 0.5V, and 0.8V.
  • the pixel voltage from the photoelectric conversion circuit 101 is 0.45V.
  • the first voltage comparator first compares 0.25V (first threshold voltage) and 0.45V (pixel voltage), and the output voltage comparison result is 1 (that is, the pixel voltage is greater than the first threshold voltage). Then, 0.5V (first threshold voltage) and 0.45V (pixel voltage) are compared, and the output voltage comparison result is 0 (that is, the pixel voltage is less than the first threshold voltage).
  • the above voltage comparison results are collectively referred to as the first voltage comparison results.
  • a plurality of voltage intervals are preset in the first voltage comparator to determine the voltage interval corresponding to the pixel voltage, and each voltage interval is preset with a corresponding sampling number.
  • the first voltage comparator determines the voltage interval in which the pixel voltage is located according to the first voltage comparison result.
  • the preset voltage intervals in the first voltage comparator are: the first voltage interval 0V-0.25V; the second voltage interval 0.25V-0.5V; the third voltage interval 0.5V-0.8V; the fourth voltage interval 0.8V- 1.5V. Therefore, the first voltage comparator determines that the pixel voltage is in the second voltage interval.
  • the first voltage comparator outputs the first voltage comparison result to the multi-sampling number selection circuit.
  • the judgment circuit uses the first voltage comparator, the threshold voltage generation circuit, and the multi-sampling selection circuit to determine the voltage interval of the pixel voltage output by the photoelectric conversion circuit, and then determine the pixel voltage. Corresponding first sampling times. Improved the flexibility of the solution.
  • the judgment circuit may further include a second voltage comparator, the second voltage comparator is electrically connected to the threshold voltage generating circuit, and the second voltage comparator is connected to The multi-sampling frequency selection circuit is electrically connected; the second voltage comparator is configured to determine a second voltage comparison result according to the second threshold voltage and the pixel voltage, the second threshold voltage is generated by the threshold voltage generating circuit; the multi-sampling The frequency selection circuit is specifically configured to: determine the voltage interval where the pixel voltage is located according to the first voltage comparison result and the second voltage comparison result; and determine the first sampling frequency according to the voltage interval. Specifically, the number of the first voltage comparator and the second voltage comparator is not limited here.
  • the judgment circuit can compare the pixel voltage domain with multiple threshold voltages (the first threshold voltage and the second threshold voltage) at the same time , so the speed of determining the voltage comparison result of the pixel voltage (the first voltage comparison result and the second voltage comparison result) is greatly increased, so the speed of reading the pixel image can be effectively improved.
  • the image reading circuit may also include a first analog-to-digital converter and a pixel processor.
  • the analog-to-digital converter is usually Refers to an electronic component that converts an analog signal (voltage) into a digital signal (digital code).
  • An analog-to-digital converter is used to convert an electrical signal (voltage) into a digital code (digital encoding).
  • Digital code is a binary code used by computers, such as "0101001", which is used to indicate the size of the signal.
  • the correlated multiple sampling circuit is electrically connected to the judgment circuit, the correlated multiple sampling circuit is electrically connected to the first analog-to-digital converter, the correlated multiple sampling circuit is electrically connected to the photoelectric conversion circuit, and the first analog-to-digital converter is electrically connected to the
  • the pixel processor is electrically connected to the judgment circuit; the correlated multi-sampling circuit is used to perform correlated multi-sampling of the pixel voltage and the reset voltage to obtain a second voltage, where the second voltage is the The pixel voltage and the reset voltage are the cumulative sum of the voltage values after the correlation multi-sampling, the second voltage is the product of the first voltage and the first sampling times; the first analog-to-digital converter is used to convert the second voltage Is a second digital code; the pixel processor is configured to determine a first digital code according to the second digital code and the first sampling times, and the first digital code is a digital code of the first voltage.
  • the correlated multi-sampling circuit performs correlated multi-sampling of the pixel voltage and the reset voltage according to the control timing to obtain the second voltage, where the second voltage is the cumulative sum of the pixel voltage and the reset voltage after correlated multi-sampling.
  • the timing is determined by the judgment circuit according to the first sampling times, the second voltage is the product of the first voltage and the first sampling times; secondly, the first analog-to-digital converter converts the second voltage into a second digital code; again, because the pixel processor It is electrically connected to the multi-sampling number selection circuit, so the pixel processor determines the first digital code according to the first sampling number from the multi-sampling number selection circuit and the second digital code from the first analog-to-digital converter, and the first digital code is the first digital code.
  • a digital code for a voltage may also perform post-processing such as filtering on the first digital code (digital signal).
  • the voltage output by the correlated multi-sampling circuit is processed by the first analog-to-digital converter for further processing by the pixel processor and other components.
  • the image reading circuit further includes a first analog-to-digital converter and a pixel processor, the correlated multi-sampling circuit is electrically connected to the judgment circuit, and the correlated multi-sampling circuit Electrically connected to the photoelectric conversion circuit, the correlated multi-sampling circuit is electrically connected to the first analog-to-digital converter, the first analog-to-digital converter is electrically connected to the pixel processor, and the pixel processor is electrically connected to the judgment circuit;
  • the correlated multi-sampling circuit is also used to collect the first pixel voltage after the pixel voltage undergoes correlated multi-sampling of the first number of sampling times; the first analog-to-digital converter is used to convert the first pixel voltage to a third Digital code; the correlated multi-sampling circuit is also used to collect the first reset voltage after the reset voltage has undergone correlation multi-sampling of the first sampling times; the first analog-to-digital converter is also used to convert the first
  • the correlated multi-sampling circuit outputs the first pixel voltage to the first analog-to-digital converter after correlated multi-sampling of the pixel voltage for the first number of times.
  • the first analog-to-digital converter converts the first pixel voltage into a third digital code;
  • the correlated multi-sampling circuit performs a reset operation to eliminate the electrons remaining in the previous correlated multi-sampling of the pixel voltage.
  • the correlated multi-sampling circuit outputs the first reset voltage to the first analog-to-digital converter after correlated multi-sampling of the reset voltage for the first number of sampling times.
  • the cumulative sum of the reset voltage after the correlated multi-sampling The first analog-to-digital converter converts the first reset voltage into a fourth digital code; again, the pixel processor determines the second digital code according to the third digital code and the fourth digital code, and the second digital code is corresponding to the second voltage Digital code, the second voltage is the cumulative sum of the voltage values of the pixel voltage and the reset voltage after correlated multi-sampling; the pixel processor determines the first digital code according to the second digital code and the first sampling times, and the first digital code is the first The digital code of the voltage.
  • the first analog-to-digital converter separately converts the accumulation and quantization of the pixel voltage and the reset voltage into digital codes, and then performs a subtraction operation. Through the operation in the digital domain, the system error generated by the analog-to-digital converter is eliminated, thereby improving the fixed pattern noise (FPN) of the image reading circuit.
  • FPN fixed pattern noise
  • the photoelectric conversion circuit may further include a first source follower; the first source follower is electrically connected to the photoelectric sensor, and the first source follower is connected to the photoelectric sensor.
  • the reset circuit is electrically connected, the first source follower is electrically connected with the first transistor, and the first source follower is used to isolate currents between the photo sensor and the first transistor, and the reset circuit and the first transistor.
  • the first source follower is used to isolate the current between the photoelectric sensor and the first transistor, the reset circuit and the first transistor, thereby increasing the conversion gain (CG), thereby improving the application of the The signal-to-noise ratio (signal noise rotio, SNR) of the image sensor of the image reading circuit.
  • CG conversion gain
  • SNR signal-to-noise ratio
  • the judgment circuit may further include: S6 switch, AZ1 switch, C3 capacitor, and C4 capacitor, wherein both ends of the C3 capacitor are compared with the S5 switch and the first voltage.
  • the other end of the S5 switch is electrically connected to the photoelectric conversion circuit, one end of the S6 switch is electrically connected to the threshold voltage generating circuit, the other end is electrically connected to one end of the C4 capacitor, and the other end of the C4 capacitor is electrically connected to the first voltage comparator. connection.
  • the non-inverting input terminal and the inverting input terminal of the first voltage comparator are respectively electrically connected to the AZ1 switch, and the other end of the AZ1 switch is used to connect the reference voltage Vcom2.
  • the first voltage comparator uses the voltage difference measured during automatic zero adjustment to eliminate errors, so as to improve the accuracy of the first voltage comparator.
  • a capacitor is provided between the first voltage comparator and the threshold voltage generating circuit and the photoelectric conversion circuit. While protecting the first voltage comparator, the first voltage comparator uses a lower first threshold voltage and power supply voltage. Next, the voltage value interval where the pixel voltage is located can also be determined, which reduces the power consumption of the image reading circuit.
  • the photoelectric conversion circuit may further include a second source follower; the second source follower is electrically connected to the second transistor, and the second source follower is connected to The second capacitor is electrically connected, the second source follower is electrically connected with the judgment circuit and the correlated multi-sampling circuit, and the second source follower is used to amplify the pixel voltage and the reset voltage output by the photoelectric conversion circuit.
  • an embodiment of the present application proposes an image reading method, which can be applied to any possible image reading circuit of the first aspect or the first aspect, and the image reading method include:
  • the reset circuit outputs a reset voltage
  • the first transistor and the second transistor are in a conducting state
  • the first capacitor and the second capacitor collect the reset voltage
  • the photoelectric sensor outputs photoelectrons.
  • the first transistor is in the on state and the second transistor is in the off state. Therefore, the reset voltage is maintained on the first capacitor, and the second capacitor is further based on the electrons corresponding to the reset voltage. Collect the photoelectron output from the photoelectric sensor to complete the collection of the pixel voltage;
  • the first sampling frequency is determined according to the pixel voltage, wherein the first sampling frequency is negatively correlated with the pixel voltage.
  • the first sampling times are determined according to the pixel voltage.
  • the threshold voltage generating circuit is used to generate one or more first threshold voltages, and the first threshold voltages are output to the first voltage comparator.
  • the first voltage comparator compares the first threshold voltage with the pixel voltage from the photoelectric conversion circuit to determine the first voltage comparison result.
  • the multi-sampling times selection circuit is preset with sampling times corresponding to each voltage interval.
  • the multi-sampling times selection circuit can determine the first sampling times according to the first voltage comparison result, and determine the correlated multi-sampling circuit corresponding to the first sampling times
  • the control sequence control sequences
  • Correlated multi-sampling is performed on the pixel voltage and the reset voltage according to the first sampling times to determine the first voltage.
  • the correlated multi-sampling circuit is specifically configured to perform correlated multi-sampling on the pixel voltage and the reset voltage output by the photoelectric conversion circuit according to the first sampling times output by the judgment circuit, and output the second voltage to the first analog-to-digital converter,
  • the second voltage is a cumulative sum of the first voltage
  • the first voltage is a voltage generated by photoelectrons.
  • the correlated multi-sampling circuit is electrically connected with the first analog-to-digital converter.
  • the correlated multi-sampling circuit includes one or more switches and one or more capacitor circuits.
  • the correlated multi-sampling circuit is used for correlated multi-sampling of the pixel voltage and the reset voltage according to the control timing configured by the multi-sampling number selection circuit. Specifically, when the first sampling number is 1, the correlated multi-sampling circuit 10 performs one sampling operation on the pixel voltage and the reset voltage; when the first sampling number is 2, the correlated multi-sampling circuit performs each sampling operation on the pixel voltage and the reset voltage. After one sampling operation, repeat the previous sampling operation, and so on.
  • the collected pixel voltage is also higher.
  • the higher pixel voltage Determine the lower first sampling times to avoid the output voltage exceeding the quantization range of the analog-to-digital converter and improve the output image quality.
  • the output pixel voltage is also lower.
  • a higher first sampling number is determined, which reduces the noise of the output image in a dark light environment and improves the output image Quality improves the dynamic range of pixels.
  • determining the first sampling times according to the pixel voltage may include: generating a first threshold voltage; and determining the first voltage according to the first threshold voltage and the pixel voltage Comparison result; determining the first sampling times according to the first voltage comparison result.
  • the first voltage comparison result is determined according to the comparison between the first threshold voltage and the pixel voltage.
  • the first threshold voltage includes 0.25 volts (V), 0.5V and 0.8V.
  • the pixel voltage is 0.45V.
  • 0.5V (first threshold voltage) and 0.45V (pixel voltage) are compared, and the output voltage comparison result is 0 (that is, the pixel voltage is less than the first threshold voltage).
  • the above voltage comparison results are collectively referred to as the first voltage comparison results.
  • a plurality of voltage intervals are preset in the first voltage comparator to determine the voltage interval corresponding to the pixel voltage, and each voltage interval is preset with a corresponding sampling number.
  • the voltage interval in which the pixel voltage is located is determined according to the first voltage comparison result.
  • the preset voltage intervals are: the first voltage interval 0V-0.25V; the second voltage interval 0.25V-0.5V; the third voltage interval 0.5V-0.8V; the fourth voltage interval 0.8V-1.5V. Therefore, it is determined that the pixel voltage is in the second voltage interval. And determine the first sampling times according to the voltage interval.
  • the first sampling times corresponding to the pixel voltage are determined by determining the voltage interval in which the pixel voltage is located. Improved the flexibility of the solution.
  • it may further include: performing correlated multi-sampling on the pixel voltage and the reset voltage to obtain a second voltage, where the second voltage is the pixel voltage and the reset voltage.
  • the voltage is the accumulated sum of voltage values after correlated multi-sampling, the second voltage is the product of the first voltage and the first sampling times; converted into a second digital code according to the second voltage; according to the second digital code and the first A sampling number determines the first digital code, and the first digital code is the digital code of the first voltage.
  • first perform correlated multi-sampling of the pixel voltage and the reset voltage to obtain the second voltage, where the second voltage is the cumulative sum of the pixel voltage and the reset voltage after the correlated multi-sampling, and the second voltage is the first voltage and the reset voltage.
  • the voltage is converted into a digital code for the subsequent further processing of the pixel processor and other components.
  • it may further include: converting the first pixel voltage into a third digital code, where the first pixel voltage is the correlation value of the pixel voltage after the first sampling times.
  • the accumulated sum of the pixel voltage after sampling is converted into a fourth digital code according to the first reset voltage, and the first reset voltage is the accumulated sum of the reset voltage after the reset voltage undergoes correlated multi-sampling of the first sampling times; according to the The third digital code and the fourth digital code determine the second digital code, the second digital code is the digital code corresponding to the second voltage, and the second voltage is the voltage value of the pixel voltage and the reset voltage after correlated multi-sampling Cumulative sum; a first digital code is determined according to the second digital code and the first sampling times, and the first digital code is a digital code of the first voltage.
  • the first pixel voltage is output, and the first pixel voltage is the cumulative sum of the pixel voltage after the pixel voltage has undergone correlated multi-sampling for the first number of sampling times. Convert the first pixel voltage into a third digital code; secondly, after the reset voltage has undergone the first sampling times of correlated multi-sampling, the first reset voltage is output, and the first reset voltage is the correlation multi-sampling of the reset voltage after the first sampling times. The cumulative sum of the reset voltage after sampling.
  • the first reset voltage is converted into a fourth digital code; again, the second digital code is determined according to the third digital code and the fourth digital code, the second digital code is the digital code corresponding to the second voltage, and the second voltage is the pixel voltage and
  • the reset voltage is the cumulative sum of the voltage values after the correlation multi-sampling; the first digital code is determined according to the second digital code and the first sampling times, and the first digital code is the digital code of the first voltage.
  • the accumulation and quantization of the pixel voltage and the accumulation and quantization of the reset voltage are respectively converted into digital codes, and then the subtraction operation is performed.
  • the systematic error generated in the process of quantizing the voltage into the digital code is eliminated, thereby improving the fixed pattern noise (FPN).
  • an embodiment of the present application further provides an image sensor, including a pixel control circuit and an image reading circuit, wherein the image reading circuit includes the above-mentioned first aspect and the possible implementation of any one of the first aspects.
  • An image reading circuit, and the pixel control circuit is used to control the exposure of the image reading circuit.
  • an embodiment of the present application further provides an image capturing optical system, including a lens group, a driving device, an image sensor, and an image stabilization module, wherein the image sensor includes the image sensor according to the third aspect.
  • the lens group is used to converge light; the image sensor is used to process the light converged by the lens group and output an image.
  • an embodiment of the present application also provides a terminal device, including an image capturing optical system, a flash module, a focus assist module, an image signal processor, a user interface, and an image software processor, wherein the image capturing optical system
  • the system includes the image capturing optical system as described in the foregoing fourth aspect, the image capturing optical system includes an image sensor, the image sensor includes an image reading circuit, and the image reading circuit includes the foregoing first aspect and the first aspect. Any one of the aspects may be realized by the image reading circuit.
  • FIG. 1 is a schematic diagram of a system structure of an image reading circuit provided by an embodiment of the application
  • FIG. 2 is a schematic diagram of a composition structure of an image reading circuit proposed in an embodiment of the application.
  • FIG. 3 is a schematic diagram of the composition structure of a photoelectric conversion circuit proposed by an embodiment of the application.
  • FIG. 4 is a schematic diagram of a control sequence of the photoelectric conversion circuit according to an embodiment of the application.
  • FIG. 6 is a schematic diagram of a control sequence of the image reading circuit according to an embodiment of the application.
  • FIG. 7 is a schematic diagram of a simulation experiment involved in an embodiment of this application.
  • FIG. 8 is a schematic diagram of another composition structure of an image reading circuit in an embodiment of the application.
  • FIG. 9 is a schematic diagram of another control sequence of the image reading circuit according to an embodiment of the application.
  • FIG. 10 is a schematic diagram of another composition structure of an image reading circuit in an embodiment of the application.
  • FIG. 11 is a schematic diagram of another composition structure of an image reading circuit in an embodiment of the application.
  • FIG. 12 is a schematic diagram of another control sequence of the image reading circuit according to an embodiment of the application.
  • FIG. 13 is a schematic structural diagram of a time-of-flight sensor proposed by an embodiment of this application.
  • FIG. 14 is a schematic structural diagram of an image capturing optical system in an embodiment of the application.
  • FIG. 15 is a schematic diagram of a terminal device in an embodiment of this application.
  • FIG. 16 is a schematic diagram of another terminal device in an embodiment of this application.
  • FIG. 17 is a schematic flowchart of an embodiment of an image reading method in an embodiment of the application.
  • the embodiments of the present application provide an image reading circuit, an image sensor, and a terminal device, which improve the quality of output images and improve the dynamic range of pixels.
  • FIG. 1 is a schematic diagram of a system structure of an image reading circuit provided by an embodiment of the application.
  • the circuit included in the image sensor is called the image reading circuit 100.
  • the image reading circuit 100 mainly includes two parts: a photosensitive part and a non-photosensitive part (the non-photosensitive part is also called a data readout part). ).
  • the photosensitive part is composed of a pixel array, and the basic unit included in the pixel array is called a pixel (or called a photoelectric conversion circuit 101 (photovoltaic conversion circuit)), and each pixel includes a photoelectric sensor and other circuits.
  • the photoelectric sensor in the pixel uses the photoelectric effect to convert the received photons into photoelectrons.
  • the image sensor also includes a pixel control circuit, which is used to control the exposure of the photosensor in the image reading circuit, for example, to control the photosensor to perform 1/100 second exposure.
  • the pixel includes a photosensor and a reset circuit.
  • the photosensor is used to receive photons and output photoelectrons, and the reset circuit is used to output a reset voltage.
  • Other circuits (except the photo sensor) included in the photoelectric conversion circuit 101 are used to collect the pixel voltage and the reset voltage.
  • the column readout circuit electrically connected to the photoelectric conversion circuit 101 includes a decision circuit 102 (decision circuit) and a first circuit 103, wherein the decision circuit 102 is electrically connected to the first circuit 103.
  • the judgment circuit 102 is used for determining the first sampling times according to the pixel voltage, and the first sampling times is negatively correlated with the pixel voltage.
  • the judgment circuit 102 is also used to determine the control timing of the correlated multiple sampling circuit (CMS circuit) in the first circuit 103 according to the first sampling times, so that the first circuit 103 resets and resets the pixel voltage according to the control timing.
  • the voltage is subjected to correlated multi-sampling to determine the first voltage, the first voltage is a voltage generated by photoelectrons, and the voltage value of the first voltage is positively correlated with the illumination.
  • FIG. 2 is a schematic diagram of a composition structure of the image reading circuit proposed in an embodiment of the application.
  • the image reading circuit 100 proposed in the embodiment of the present application includes a photoelectric conversion circuit 101, a judgment circuit 102, and a first circuit 103.
  • a photoelectric conversion circuit 101 for converting photoelectric signals to digital signals.
  • a judgment circuit 102 for determining whether the image reading circuit 100 will be introduced separately.
  • the photoelectric conversion circuit 101 is specifically used to output the pixel voltage and the reset voltage to other parts of the image reading circuit 100.
  • the photoelectric conversion circuit 101 includes a photo sensor 1011, a reset circuit 1012, a first transistor 1013, a second transistor 1014, a first capacitor 1015, a second capacitor 1016, a first source follower 1017 and a second source follower 1018, and a photo sensor 1011 It is electrically connected to the first source follower 1017, the reset circuit 1012 is electrically connected to the first source follower 1017, the first source follower 1017 is electrically connected to the first transistor 1013, and the first transistor 1013 is electrically connected to the second capacitor 1016.
  • a transistor 1013 is electrically connected to the second transistor 1014, the second transistor 1014 is electrically connected to the first capacitor 1015, the second capacitor 1016 is electrically connected to the second source follower 1018, and the second transistor 1014 is electrically connected to the second source follower 1018 .
  • the photoelectric sensor 1011 uses the photoelectric effect to convert the received photons into photoelectrons.
  • the implementation of the photoelectric sensor 1011 can be a photodiode, or a phototriode, or other photons that can be converted into
  • the optoelectronic components are not limited here.
  • the photosensor 1011 includes a photodiode D and an M5 transistor.
  • the photodiode D is used to receive photons and convert the photons into photoelectrons
  • the drain (or source) of the M5 transistor is electrically connected to the photodiode D
  • the source (or drain) of the M5 transistor follows the first source
  • the device 1017 is electrically connected, and the gate of the M5 transistor is used to receive a control signal (TX), and the control signal (TX) is used to control the on or off of the connection path between the photodiode D and the first source follower 1017.
  • TX control signal
  • the control signal (TX) controls the M5 transistor to be turned on
  • the photodiode D outputs photoelectrons to the first source follower 1017 through the M5 transistor.
  • the reset circuit 1012 is used to apply a reset voltage (VRST) to the photoelectric conversion circuit 101 before the end of each exposure, so that the first source follower 1017 electrically connected to the reset circuit 1012 is reset to a fixed
  • the voltage value (the voltage value of the reset voltage) eliminates the photoelectrons received in the previous exposure and prevents the previous image from affecting the next image.
  • the reset circuit 1012 may be implemented by a reset circuit composed of one or more components, or may be implemented by one or more reset transistors or reset transistors, which is not limited here.
  • the reset circuit 1012 is an M6 transistor, the gate of the M6 transistor is used to receive a control signal (RST), the control signal (RST) is used to control the M6 transistor to output a reset voltage, and the source or drain of the M6 transistor It is electrically connected to the first source follower 1017.
  • the reset voltage output by the source or drain of the M6 transistor is VRST.
  • the first source follower 1017 the source follower (source follower) has an impedance transform (impedance transformer) function.
  • the first source follower 1017 is used to isolate the current between the photo sensor 1011 and the first transistor 1013, and the first source follower is used to isolate the current between the reset circuit 1012 and the first transistor 1013.
  • the gate of the first source follower 1017 is electrically connected to the photosensor 1011, and the gate of the first source follower 1017 is electrically connected to the drain or source of the reset circuit 1012.
  • the first source follower 1017 is composed of two transistors, namely an M3 transistor and an M4 transistor, wherein the M3 transistor is used as a source follower tube, the M4 transistor is used as a tail current tube, and the drain (or source) of the M3 transistor is It is electrically connected to the drain (or source) of the M4 transistor so that the M3 transistor and the M4 transistor form a first source follower 1017.
  • the gate of the M3 transistor is electrically connected to the photosensor 1011 and the reset circuit 1012, and this connection point is also called a floating diffusion (FD) point.
  • the first source follower 1017 buffers the voltage at point FD.
  • the gate of the M4 transistor is used to receive a control signal.
  • the control signal (VBIAS) is used to control the first source follower 1017 to turn on or off.
  • VBIAS controls the first source follower 1017 to turn off
  • the first source follower 1017 is turned off.
  • 1017 isolates the current between the photoelectric sensor 1011 and the reset circuit 1012, and the first transistor 1013.
  • the VBIAS controls the first source follower 1017 to turn on
  • the first source follower 1017 buffers the voltage output by the photo sensor 1011 and the reset circuit 1012, and outputs the buffered voltage to the first transistor 1013.
  • the first transistor 1013 is electrically connected to the first source follower 1017, the first transistor 1013 is electrically connected to the second capacitor 1016, and the first transistor 1013 is electrically connected to the second transistor 1014.
  • the first transistor 1013 is used to control the on and off of the circuit between the first source follower 1017 (that is, the photo sensor 1011 and the reset circuit 1012) and the second capacitor 1016 and the second transistor 1014.
  • the first transistor 1013 may be composed of an M1 transistor, the source (or drain) of the M1 transistor is electrically connected to the first source follower 1017, and the drain (or source) of the M1 transistor is electrically connected to the second transistor. 1014 and the second capacitor 1016 are electrically connected.
  • the gate of the M1 transistor is used to receive a control signal (SS), and the control signal (SS) is used to control the M1 transistor to be turned on or off.
  • the second transistor 1014 is electrically connected to the first transistor 1013, the second transistor 1014 is electrically connected to the first capacitor 1015, and the second transistor 1014 is electrically connected to the second source follower 1018.
  • the second transistor 1014 is used to control the on or off of the connection path between the first transistor 1013 and the first capacitor 1015. Therefore, the first transistor 1013 and the second transistor 1014 jointly control the on or off of the connection path between the first source follower 1017 (that is, the photosensor 1011 and the reset circuit 1012) and the first capacitor 1015.
  • the second transistor 1014 may be composed of an M2 transistor, the source (or drain) of the M2 transistor is electrically connected to the first transistor 1013, and the drain (or source) of the M2 transistor is electrically connected to the first capacitor 1015. connection.
  • the gate of the M2 transistor is used to receive a control signal (SR), and the control signal (SR) is used to control the on or off of the M2 transistor.
  • the reset circuit 1012 outputs a reset voltage
  • the first transistor 1013 and the second transistor 1014 are in the conducting state
  • the first capacitor 1015 and the second capacitor 1016 collect the reset voltage
  • the photoelectric sensor 1011 outputs photoelectrons.
  • the first The transistor 1013 is in the on state and the second transistor 1014 is in the off state. Therefore, the reset voltage is maintained on the first capacitor 1015, and the second capacitor 1016 further collects the photoelectrons output by the photoelectric sensor 1011 on the basis of the electrons corresponding to the reset voltage to complete the alignment. Pixel voltage collection.
  • the judging circuit 102 is specifically configured to determine the sampling times of the pixel voltage and the reset voltage by the correlated multi-sampling circuit 1031 according to the pixel voltage output by the photoelectric conversion circuit 101, and the sampling times are called the first sampling times.
  • the judgment circuit 102 includes a threshold voltage generating circuit 1021 (threshold voltage generator), a first voltage comparator 1022 (voltage comparator), and a multi-sampling time selection circuit 1023 (multi-sampling time selection).
  • the first voltage comparator 1022 and the photoelectric The second source follower 1018 in the conversion circuit 101 is electrically connected, the first voltage comparator 1022 is electrically connected with the threshold voltage generating circuit 1021, the first voltage comparator 1022 is electrically connected with the multi-sampling frequency selection circuit 1023, the multi-sampling frequency selection circuit 1023 is electrically connected to the correlated multi-sampling circuit 1031.
  • the threshold voltage generating circuit 1021 is used to generate one or more first threshold voltages, and the first threshold voltages are output to the first voltage comparator 1022.
  • the first voltage comparator 1022 compares the first threshold voltage with the pixel voltage from the photoelectric conversion circuit 101 to determine the first voltage comparison result.
  • the first threshold voltage generated by the threshold voltage generating circuit 1021 includes 0.25 volt (V), 0.5V, and 0.8V.
  • the pixel voltage from the photoelectric conversion circuit 101 is 0.45V.
  • the first voltage comparator 1022 first compares 0.25V (first threshold voltage) and 0.45V (pixel voltage), and the output voltage comparison result is 1 (that is, the pixel voltage is greater than the first threshold voltage). Then, 0.5V (first threshold voltage) and 0.45V (pixel voltage) are compared, and the output voltage comparison result is 0 (that is, the pixel voltage is less than the first threshold voltage).
  • the above voltage comparison results are collectively referred to as the first voltage comparison results.
  • a plurality of voltage intervals are preset in the first voltage comparator 1022 to determine the voltage interval corresponding to the pixel voltage, and each voltage interval is preset with a corresponding sampling number.
  • the first voltage comparator 1022 determines the voltage interval in which the pixel voltage is located according to the first voltage comparison result.
  • the preset voltage intervals in the first voltage comparator 1022 are: the first voltage interval 0V-0.25V; the second voltage interval 0.25V-0.5V; the third voltage interval 0.5V-0.8V; the fourth voltage interval 0.8V -1.5V. Therefore, the first voltage comparator 1022 determines that the pixel voltage is in the second voltage interval.
  • the first voltage comparator 1022 outputs the first voltage comparison result to the multi-sampling number selection circuit 1023.
  • the multi-sampling frequency selection circuit 1023 is preset with sampling times corresponding to each voltage interval.
  • the multi-sampling frequency selection circuit 1023 can determine the first sampling frequency according to the first voltage comparison result, and determine the correlation multiplier corresponding to the first sampling frequency.
  • the multi-sampling frequency selection circuit 1023 is electrically connected to the correlated multi-sampling circuit 1031. After the multi-sampling frequency selection circuit 1023 determines the control sequence, the control sequence is configured to the correlated multi-sampling circuit 1031.
  • the first voltage interval 0V-0.25V, the corresponding first sampling number is 6; the second voltage interval 0.25V-0.5V, the corresponding first sampling number is 3; the third voltage interval 0.5V-0.8V, corresponding The first sampling number of is 2; the fourth voltage interval is 0.8V-1.5V, and the corresponding first sampling number is 1.
  • the first voltage comparator 1022 determines that the first voltage comparison result is: the voltage interval where the pixel voltage is 0.25V is the second voltage interval.
  • the multi-sampling number selection circuit determines that the first sampling number corresponding to the pixel voltage is 3, and determines the control timing of the correlated multi-sampling circuit 1031 corresponding to the first sampling number, and configures the control timing to the correlated multi-sampling circuit 1031 .
  • the first circuit 103 includes a correlated multi-sampling circuit 1031, a first analog-to-digital converter 1032 (ADC), and a pixel processor 1033 (pixel processor).
  • the correlated multi-sampling circuit 1031 and the judgment circuit 102 are electrically connected to each other.
  • the correlated multi-sampling circuit 1031 is electrically connected to the first analog-to-digital converter 1032
  • the correlated multi-sampling circuit 1031 is electrically connected to the photoelectric conversion circuit 101
  • the first analog-to-digital converter 1032 is electrically connected to the pixel processor 1033
  • the pixel processor 1033 It is electrically connected to the judgment circuit 102.
  • the correlated multi-sampling circuit 1031 is specifically configured to perform correlated multi-sampling on the pixel voltage and the reset voltage output by the photoelectric conversion circuit 101 according to the first sampling times output by the judgment circuit 102, and output the second voltage to the first analog-to-digital converter 1032,
  • the second voltage is a cumulative sum of the first voltage
  • the first voltage is a voltage generated by photoelectrons.
  • the correlated multi-sampling circuit 1031 is electrically connected to the first analog-to-digital converter 1032.
  • the correlated multi-sampling circuit 1031 includes one or more switches and one or more capacitor circuits.
  • the correlated multi-sampling circuit 1031 is used to correlate the pixel voltage and the reset voltage according to the control timing configured by the multi-sampling number selection circuit 1023. sampling. Specifically, when the first sampling number is 1, the correlated multi-sampling circuit 1031 performs one sampling operation on the pixel voltage and the reset voltage; when the first sampling number is 2, the correlated multi-sampling circuit 1031 performs a sampling operation on the pixel voltage and the reset voltage. After each sampling operation is performed once, the previous sampling operation is repeated, and so on.
  • the first analog-to-digital converter 1032 is electrically connected to the pixel processor 1033, and the first analog-to-digital converter 1032 is electrically connected to the correlated multi-sampling circuit 1031.
  • An analog-to-digital converter (ADC) usually refers to an electronic component that converts an analog signal (voltage) into a digital signal (digital code).
  • the first analog-to-digital converter 1032 is electrically connected to the correlated multi-sampling circuit 1031, and the first analog-to-digital converter 1032 is used to convert the electrical signal (voltage) output by the correlated multi-sampling circuit 1031 into a digital code (digital encoding). ).
  • Digital code is a binary code used by computers, such as "0101001", which is used to indicate the size of the signal.
  • the first analog-to-digital converter 1032 converts analog signals such as voltage into digital codes for subsequent processing by the pixel processor 1033.
  • the correlated multi-sampling circuit 1031 can perform correlated multi-sampling operation on the pixel voltage and then perform correlated multi-sampling operation on the reset voltage on the basis of the pixel voltage; second, it can also perform correlated multi-sampling operation on the pixel voltage After that, the accumulated sum of the pixel voltage is output to the first analog-to-digital converter, and the correlated multi-sampling circuit 1031 performs a reset operation, and then the reset voltage output by the photoelectric conversion circuit 101 is subjected to a correlated multi-sampling operation. Expand the description below.
  • the correlated multi-sampling circuit 1031 performs correlated multi-sampling of the pixel voltage and the reset voltage according to the control timing to obtain the second voltage, where the second voltage is the accumulated sum of the pixel voltage and the reset voltage after correlated multi-sampling, and controls
  • the timing is determined by the judging circuit 102 according to the first sampling times, and the second voltage is the product of the first voltage and the first sampling times; secondly, the first analog-to-digital converter 1032 converts the second voltage into the second digital code; again, because the pixel
  • the processor 1033 is electrically connected to the multi-sampling frequency selection circuit 1023, so the pixel processor 1033 determines the first digital code according to the first sampling frequency from the multi-sampling frequency selection circuit 1023 and the second digital code from the first analog-to-digital converter 1032 ,
  • the first digital code is the digital code of the first voltage.
  • the correlated multi-sampling circuit 1031 outputs the first pixel voltage to the first analog-to-digital converter 1032 after correlated multi-sampling of the pixel voltage for the first number of times.
  • the first pixel voltage is the pixel voltage of the correlated multi-sampling circuit 1031 The cumulative sum of pixel voltages after the first sampling times of correlated multi-sampling.
  • the first analog-to-digital converter 1032 converts the first pixel voltage into a third digital code; secondly, the correlated multi-sampling circuit 1031 performs a reset operation to eliminate the electrons remaining in the previous correlated multi-sampling of the pixel voltage.
  • the correlated multi-sampling circuit 1031 outputs the first reset voltage to the first analog-to-digital converter 1032 after correlated multi-sampling of the reset voltage by the first number of sampling times.
  • the first analog-to-digital converter 1032 converts the first reset voltage into a fourth digital code; again, the pixel processor 1033 determines the second digital code according to the third digital code and the fourth digital code, and the second digital code is the second voltage Corresponding digital code, the second voltage is the cumulative sum of the pixel voltage and the reset voltage after correlated multi-sampling; the pixel processor 1033 determines the first digital code according to the second digital code and the first sampling times, the first digital code Is the digital code of the first voltage.
  • the pixel processor 1033 is specifically configured to process the digital code output by the first analog-to-digital converter 1032 to determine a first digital code, where the first digital code is a digital code of a first voltage, and the first voltage is a voltage generated by optoelectronics .
  • the pixel processor 1033 may also perform post-processing such as filtering on the first digital code (digital signal).
  • the image reading circuit includes a photoelectric conversion circuit, a judgment circuit, and a first circuit.
  • the photoelectric conversion circuit is specifically used to output pixel voltages and reset voltages to other parts of the image reading circuit;
  • the judgment circuit is specifically used to According to the pixel voltage output by the photoelectric conversion circuit, determine the number of sampling times of the pixel voltage and the reset voltage by the first circuit. This sampling number is called the first sampling number;
  • the first circuit is specifically used to determine the number of samples output by the judgment circuit according to the first sampling number.
  • the pixel voltage output by the photoelectric conversion circuit and the reset voltage are subjected to correlated multi-sampling to determine the first voltage.
  • the first transistor is electrically connected to the second capacitor
  • the first transistor is electrically connected to the second transistor
  • the second transistor is electrically connected to the first capacitor
  • the first transistor is used to control the connection path between the photo sensor and the second capacitor
  • the first transistor is used to control the turn-on or turn-off of the connection path between the reset circuit and the second capacitor
  • the first transistor is used to control the turn-on or turn-off of the connection path between the reset circuit and the second transistor.
  • the second transistor controls the on or off of the connection path between the first capacitor and the first transistor.
  • the first capacitor collects the reset voltage under the common control of the first transistor and the second transistor, and the second capacitor collects the pixel voltage under the control of the first transistor, so that the photoelectric conversion circuit can report to the judgment circuit (and The first circuit) outputs the pixel voltage first, so that the judgment circuit determines the first sampling times according to the pixel voltage, wherein the pixel voltage is positively correlated with the light intensity, and the first sampling times is negatively correlated with the pixel voltage.
  • the first circuit includes a correlated multi-sampling circuit, a first analog-to-digital converter, and a pixel processor.
  • the correlated multi-sampling circuit performs correlated multi-sampling operations on the pixel voltage and the reset voltage output by the photoelectric conversion circuit according to the first sampling times.
  • the analog-to-digital converter converts the voltage output by the correlated multi-sampling circuit and determines the corresponding digital code
  • the pixel processor processes the digital code output by the first analog-to-digital converter according to the first sampling times to determine the first voltage corresponding to the first voltage.
  • a digital code the first voltage generated by the photoelectron.
  • the pixel voltage output by the photoelectric conversion circuit is also higher, and the judgment circuit is based on the higher
  • the pixel voltage determines the lower number of first sampling times, which prevents the voltage output by the correlated multi-sampling circuit from exceeding the quantization range of the first analog-to-digital converter, and improves the image quality output by the image reading circuit.
  • the pixel voltage output by the photoelectric conversion circuit is also lower.
  • the judgment circuit determines the higher first sampling times according to the lower pixel voltage, which reduces the noise of the output image in a dark light environment. Improve the quality of the output image and improve the dynamic range of pixels.
  • FIG. 3 is a schematic diagram of the composition structure of a photoelectric conversion circuit proposed in an embodiment of the application.
  • the photoelectric conversion circuit 101 proposed in the embodiment of the present application includes an M1 transistor, an M2 transistor, an M3 transistor, an M4 transistor, an M5 transistor, an M6 transistor, an M7 transistor, an M8 transistor, a C1 capacitor, a C2 capacitor, and a photodiode D.
  • FIG. 4 is a schematic diagram of a control sequence of the photoelectric conversion circuit according to an embodiment of the application.
  • the control timing shown in FIG. 4 is the control timing of the photoelectric conversion circuit 101 shown in FIG. 3.
  • the photodiode D is used to receive photons and convert the photons into optoelectronic output.
  • the photodiode D constitutes the photoelectric sensor 1011; the source and drain of the M5 transistor are connected to the M3 transistor and the photoelectric respectively.
  • the diode D is electrically connected, and the gate of the M5 transistor is used to receive the control signal (TX).
  • the control signal (TX) is used to control the turn-on or turn-off of the connection path between the M5 transistors, thereby controlling the photoelectrons output by the photodiode D.
  • the M5 transistor When the control signal (TX) is at a high level, the M5 transistor is turned on, and the photoelectrons output by the photodiode D can flow through the M5 transistor and transfer to the FD point, indicating the start of exposure; when the control signal (TX) is at low level, the M5 transistor Turn off, cut off the photoelectron transfer path, the photoelectron generated by the photodiode D is no longer collected by the FD point, indicating the end of exposure.
  • the photoelectrons generated by the photodiode D are transferred to the FD point, a voltage is accumulated at the FD point.
  • C FD in Fig. 3 represents the parasitic capacitance at point FD , and the capacitance of C FD determines the conversion gain (CG) from photoelectrons to voltage.
  • the M6 transistor constitutes the reset circuit 1012.
  • the source (or drain) of the M6 transistor is electrically connected to the input of the FD point and the reset voltage (VRST).
  • the voltage output from the M6 transistor to the FD point is the reset voltage (VRST).
  • the gate is used to receive the control signal (RST).
  • the control signal (RST) is used to control the turn-on or turn-off of the connection path between the M6 transistors, thereby controlling the reset voltage (VRST).
  • the M3 transistor is a source follower tube
  • the M4 transistor is a tail current tube
  • the M3 transistor and the M4 transistor form the first source follower 1017, where the gate of the M3 transistor is electrically connected to the FD point, and the source and drain of the M3 transistor are respectively connected to
  • the power supply voltage (VDD) is electrically connected to the source (or drain) of the M4 transistor, the other end of the drain (or source) of the M4 transistor is grounded, and the gate of the M4 transistor is connected to the bias current (IBIAS) .
  • the first source follower 1017 composed of M3 transistor and M4 transistor is used to separate the FD point from the subsequent capacitors (C1 capacitor and C2 capacitor), so that the FD point and the subsequent capacitors (C1 capacitor and C2 capacitor) do not interfere with each other
  • capacitors with larger capacitance can be used to reduce the switching thermal noise (KT/C noise) of the capacitor, and the parasitic capacitance of C FD at the FD point can be minimized. Capacitance value, thereby increasing the conversion gain.
  • the M1 transistor constitutes the first transistor 1013, the source (or drain) of the M1 transistor is electrically connected to the first source follower 1017 (M3 transistor and the M4 transistor), and the drain (or source) of the M1 transistor is connected to the M2 transistor and the C2 capacitor It is electrically connected to the M7 transistor, and the gate of the M1 transistor is used to receive the control signal (SS).
  • the control signal (SS) is used to control the on or off of the connection path between the M1 transistors.
  • the M1 transistor When the control signal (SS) is at a high level, the M1 transistor is turned on, and the voltage from the first source follower 1017 is input to other subsequent components (M2 transistor, C2 capacitor and M7 transistor) through the M1 transistor; when the control signal (SS) At low level, the M1 transistor is turned off.
  • the M2 transistor constitutes the second transistor 1014, the source or gate of the M2 transistor is electrically connected to the M1 transistor, the drain (or source) of the M2 transistor is electrically connected to the C1 capacitor, and the gate of the M2 transistor is used to receive the control signal (SR ), the control signal (SR) is used to control the on or off of the connection path between the M2 transistors.
  • the control signal (SR) is at a high level, the M2 transistor is turned on, and the voltage from the M1 transistor is input to the C1 capacitor through the M2 transistor; when the control signal (SR) is at a low level, the M2 transistor is turned off.
  • One end of the C1 capacitor is electrically connected to the source (or drain) of the M2 transistor, and the other end is grounded.
  • the C1 capacitor forms the first capacitor 1015, and the C1 capacitor is used to collect the reset voltage.
  • One end of the C2 capacitor is electrically connected to the gate of the M7 transistor, and the other end is grounded.
  • the C2 capacitor forms the second capacitor 1016, and the C2 capacitor is used to collect the pixel voltage.
  • the M7 transistor cooperates with the tail current (not shown in the figure) to form the second source follower 1018.
  • the M7 transistor is similar to the M3 transistor.
  • the source (or drain) of the M7 transistor receives the power supply voltage (VDD), and the drain of the M7 transistor ( Or source) is electrically connected to the M8 transistor.
  • the M7 transistor is used to amplify the reset voltage output by the C1 capacitor and the pixel voltage output by the C2 capacitor.
  • the source (or drain) of the M8 transistor is electrically connected to the M7 transistor, the drain of the M8 transistor is electrically connected to other circuits following the source (such as the judgment circuit 102 and the correlated multi-sampling circuit 1031), and the gate of the M8 transistor is used for Receive a control signal (SEL), the control signal (SEL) is used to control the on or off of the connection path between the M8 transistors, when the control signal (SEL) is at a high level, the M8 transistor is turned on, the pixel voltage or the reset voltage Output to other circuits via M7 transistor and M8 transistor; when the control signal (SEL) is at low level, the M8 transistor is turned off.
  • SEL control signal
  • control timing shown in FIG. 4 is the control timing of the photoelectric conversion circuit 101 when the image sensor proposed in the present application (in which the photoelectric conversion circuit 101 shown in FIG. 3 is applied) uses the global shutter mode for exposure. It should be noted that the control sequence shown in FIG. 4 is only an exemplary description. According to the actual composition of the components of the photoelectric conversion circuit 101, there are different control sequences, which are not limited here.
  • the working time of the pixel is mainly divided into a global shutter (Global shutter) time period and a column readout (Column Readout) time period.
  • Global shutter Global shutter
  • Column Readout Column Readout
  • the RST signal is controlled from low to high, and then the M6 transistor is controlled to turn on, and the FD point is reset.
  • the photodiode D can be reset.
  • the M6 transistor is equivalent to a resistor during reset, and the voltage at point FD will rise slowly and will eventually be reset to VRST.
  • the RST signal and TX signal are controlled from high level to low level. At this time, the M6 transistor will be turned off, and the FD point will remain at the VRST voltage.
  • the thermal noise current generated by the M6 transistor forms a thermal noise voltage at the FD point, which is also called KT/C noise.
  • the thermal noise voltage also remains on the FD point, which is also called reset noise. Due to the randomness of the noise, the noise on the FD point is different each time it is reset, that is, after each reset, the voltage at the FD point has a slight difference, which is manifested as noise on the image.
  • the KT/C noise formula the smaller the capacitance at the FD point, the greater the thermal noise voltage. As the pixel size shrinks, the FD point capacitance also becomes smaller, so the reset noise becomes larger.
  • the specific implementation method is to store the reset voltage along with the reset noise, read it out at a later point in time, and subtract it from the pixel voltage, thereby eliminating the noise.
  • the reset voltage at the FD point is transmitted to one end of the M1 transistor through the first source follower 1017 formed by the M3 transistor and the M4 transistor.
  • the SR signal and the SS signal are controlled from low level to high level, and the M1 and M2 transistors are both turned on.
  • the voltage on the upper plate of the capacitor C1 follows the voltage change at the FD point.
  • the SR signal is controlled from high level to low level.
  • the reset voltage and reset noise will remain on the capacitor C1, that is, the storage of the reset voltage is completed, which is represented by VRST.
  • control the TX signal from low to high.
  • the M5 transistor is turned on, and the electrons generated by the photodiode D flow to the FD point through the M5 transistor. Because the electrons are negatively charged, the voltage at the FD point will drop.
  • the amount of voltage drop at point FD is equal to the number of electrons produced by the photodiode D multiplied by the conversion gain, and is linearly related to the light intensity received by the photodiode D.
  • the TX signal is controlled from high level to low level, the M5 transistor is turned off, and the voltage at the FD point no longer changes at this time.
  • the SS signal is controlled from a high level to a low level.
  • the pixel voltage will remain on the capacitor C2, that is, the storage of the pixel voltage is completed, which is represented by VSIG.
  • the voltage value actually generated by the photoelectron is the difference between the reset voltage and the pixel voltage, which is VRST-VSIG.
  • the column readout circuit (including the judgment circuit 102 and the first circuit 103 proposed in this application) completes the readout and quantization of the electrical signal in the pixel.
  • control the SEL signal from low level to high level.
  • the second source follower 1018 formed by the M7 transistor and the tail current the voltage output by the photoelectric conversion circuit 101 follows the change of the gate voltage of the M7 transistor. Since the upper plate of the capacitor C2 is directly connected to the gate of the M7 transistor, and the voltage of the upper plate is the sampled pixel voltage at this time, the pixel voltage VSIG is read out.
  • the SR signal is controlled from low level to high level.
  • the M2 transistor is turned on, and the C1 capacitor and the C2 capacitor form charge sharing. Since the upper plate voltage of the C2 capacitor is the pixel voltage, the upper plate voltage of the C1 capacitor is the reset voltage.
  • the pixel voltage collected on the C1 capacitor is the cumulative sum of the voltage generated by the photoelectron based on the reset voltage. Therefore, the final pixel voltage minus the reset voltage and the first voltage (the voltage corresponding to the photoelectron) can successfully eliminate the reset noise.
  • FIG. 5 is a schematic diagram of the composition and structure of an image reading circuit according to an embodiment of the application.
  • the image reading circuit 100 proposed in the embodiment of the present application includes a photoelectric conversion circuit 101 (other parts of the photoelectric conversion circuit 101 in FIG. 5 are not shown), a judgment circuit 102, and a first circuit 103.
  • the judgment circuit 102 includes a threshold voltage A generating circuit 1021, a first voltage comparator 1022, a multi-sampling number selection circuit 1023, and an S5 switch.
  • the first circuit 103 includes a correlated multi-sampling circuit 1031, a first analog-to-digital converter 1032, and a pixel processor 1033 (not shown in FIG. 5).
  • the correlated multi-sampling circuit 1031 includes S1 switch, S2 switch, S3 switch, S4 switch, Cin capacitor, Cf capacitor, switch AZ, operational amplifier (AMP) and SH switch.
  • one end of the S1 switch in the correlated multi-sampling circuit 1031 is electrically connected to the source (or drain) of the M8 transistor, and the other end of the S1 switch is electrically connected to the Cin capacitor.
  • the S3 switch and the S4 switch are connected in parallel to both ends of the Cin capacitor, and the other ends of the S3 switch and the S4 switch are connected to the reference voltage (Vcom) and are electrically connected to the input end of the operational amplifier.
  • One end of the Cin capacitor that is electrically connected to the S4 switch is electrically connected to the S2 switch, and the other end of the S2 switch is electrically connected to the input end of the operational amplifier.
  • the output of the S2 switch can be electrically connected to the non-inverting input terminal of the operational amplifier (at this time, the outputs of the S3 switch and S4 switch are electrically connected to the inverting input terminal of the operational amplifier), or it can be connected to the inverting input terminal of the operational amplifier.
  • the input terminal is electrically connected (the output of the S3 switch and the S4 switch are electrically connected to the non-inverting input terminal of the operational amplifier at this time), which is not limited here.
  • the operational amplifier may specifically be: a general operational amplifier, a programmable control operational amplifier, a high-impedance operational amplifier or a low-power operational amplifier, etc., which are not limited here.
  • a Cf capacitor is connected in parallel at both ends of the input and output ends of the operational amplifier, and an AZ switch is connected in parallel at both ends of the Cf capacitor.
  • One end of the SH switch is electrically connected to the output end of the operational amplifier, the other end of the SH switch is electrically connected to the first analog-to-digital converter 1032, and the output end of the first analog-to-digital converter 1032 is connected to the pixel processor 1033 (not shown in FIG. 5). Out) Electrical connection.
  • the output terminal of the threshold voltage generating circuit 1021 in the judgment circuit 102 is electrically connected to the input terminal of the first voltage comparator 1022, and the other input terminal of the first voltage comparator 1022 is electrically connected to the S5 switch.
  • the threshold voltage generating circuit 1021 is electrically connected to the non-inverting input terminal of the first voltage comparator 1022, and at this time, the S5 switch is electrically connected to the inverting input terminal of the first voltage comparator 1022; or, the threshold voltage generating circuit 1021 is opposite to the first voltage comparator 1022.
  • the phase input terminal is electrically connected. At this time, the S5 switch is electrically connected to the non-inverting input terminal of the first voltage comparator 1022.
  • the other end of the S5 switch is electrically connected to the output end of the photoelectric conversion circuit 101 (ie, the source or drain of the M8 transistor).
  • the output terminal of the first voltage comparator 1022 is electrically connected to the multi-sampling frequency selection circuit 1023, and the output terminal of the multi-sampling frequency selection circuit 1023 is electrically connected to the correlated multi-sampling circuit 1031, and outputs control timing to the correlated multi-sampling circuit 1031.
  • FIG. 6 is a schematic diagram of a control sequence of the image reading circuit proposed in an embodiment of the application.
  • control the SEL signal from low to high, indicating that the pixel is strobed.
  • automatic zero adjustment is performed.
  • the AZ signal is controlled from low level to high level, the AZ switch is closed, and the output of the operational amplifier is connected to the inverting input terminal to form a negative feedback of the unit gain.
  • the two ends of the Cf capacitor are connected to clear the stored charge in the previous reading to ensure that the next reading is not affected.
  • the inverting input terminal of the operational amplifier stores a compensation value (offset), and the compensation value is used to compensate for errors that exist due to device mismatch during the production of the operational amplifier.
  • the AZ signal is controlled from high level to low level, and the AZ switch is turned off. Then, the S5 switch of the judgment circuit 102 is turned on, the first voltage comparator 1022 and the photoelectric conversion circuit 101 are turned on, and the first voltage comparator 1022 samples the pixel voltage output by the M8 transistor.
  • the threshold voltage generating circuit 1021 generates one or more first threshold voltages in a time-division manner. The first voltage comparator 1022 uses the first threshold voltage to compare with the pixel voltage multiple times to determine the first voltage comparison result, and compare it according to the first voltage The result determines the voltage range to which the pixel voltage belongs.
  • the multi-sampling time selection circuit 1023 determines the first sampling number corresponding to the pixel voltage according to the first voltage comparison result.
  • the multi-sampling frequency selection circuit 1023 determines the control timing of the correlated multi-sampling circuit 1031 according to the first sampling frequency.
  • the control timing is used to control the correlated multi-sampling circuit 1031 to perform correlated multi-sampling on the output (pixel voltage and reset voltage) of the photoelectric conversion circuit 101
  • the operation operation optionally, the correlated multiple sampling operation includes an adaptive correlated multiple sampling operation (adaptive correlated multiple sampling, Adaptive-CMS).
  • the correlated multi-sampling circuit 1031 performs one pixel voltage sampling and accumulation.
  • the specific accumulation process is as follows: First, the S1 switch and S4 switch are turned on to sample the pixel voltage. At this time, the charge on the C in capacitor is equal to:
  • Q in 0 is the charge on the C in capacitor
  • V com is the reference voltage (also called common mode voltage)
  • V SIG is the pixel voltage
  • C in is the capacitance value of the C in capacitor.
  • switch S1 and The S4 switch is turned off, and then the S2 switch and S3 switch are turned on. At this time:
  • Q total is the total charge of the correlated multi-sampling circuit 1031
  • Q in 1 is the charge of the Cin capacitor at t2
  • Q f1 is the charge of the Cf capacitor at t2
  • V - is the voltage value of the inverting input terminal of the operational amplifier.
  • V com is the reference voltage
  • V o is the voltage value of the output terminal of the operational amplifier (ie, the voltage value of the bottom plate of the Cf capacitor)
  • C in is the capacitance value of the C in capacitor
  • C f is the capacitance value of the C f capacitor.
  • the output voltage of the operational amplifier is equal to:
  • V o,t2 V com -C in /C f (V com -V SIG );
  • the C in capacitor represents the input sampling capacitor
  • the C f capacitor represents the feedback capacitor.
  • V o,t2 V com +(V SIG -V com );
  • the time period t2-t3 indicates that the correlated multi-sampling circuit 1031 repeats the t1-t2 process, repeatedly sampling and accumulating the pixel voltage.
  • the number of repetitions is equal to the first sampling number (M). For example, if the first sampling number is 2, then on the basis of t1-t2, another sampling is required.
  • the S1 switch and the S4 switch are turned on to sample the pixel voltage.
  • Q f2 C f (V com -V SIG ). Therefore, the total charge of the correlated multi-sampling circuit 1031 is:
  • the output voltage of the operational amplifier is equal to:
  • V o,t3 V com +2(V SIG -V com );
  • V o,t3 M(V SIG -V com )+V com ;
  • the SR signal is controlled from low to high, indicating that the photoelectric conversion circuit 101 will output the stored reset voltage.
  • the output voltage of the M8 transistor changes from VSIG to VRST.
  • the correlated multi-sampling circuit 1031 performs a reset voltage sampling and subtraction operation. First, the S1 switch is turned on. At this time , the upper plate voltage of the C in capacitor is equal to VRST, and the total charge can be expressed as:
  • V o,t5 V o,t3 -(V RST -V com ).
  • both the S1 switch and the S2 switch are turned off, while the S3 switch and the S4 switch are turned on, and the charge on the C in capacitor is cleared.
  • the correlated multi-sampling circuit 1031 repeats the t4-t5 process, repeating sampling and accumulating the reset voltage. The number of repetitions is the first sampling number (M). Similarly, assuming that the first sampling frequency is 2, then on the basis of t4–t5, another sampling is required. First, the S1 switch and S2 switch are turned on, so that the voltage of the upper plate of the C in capacitor is equal to VRST. At this time, the total charge can be expressed as:
  • V o,t6 V o,t3 -M(V RST -V com );
  • V o,t6 V com -M(V RST -V SIG );
  • the time period t6-t7 indicates that the first analog-to-digital converter 1032 (ADC) samples the output voltage of the operational amplifier in the correlated multi-sampling circuit 1031, and the SH switch is turned on. After t7, the first analog-to-digital converter 1032 quantizes the voltage value after multiple samples to obtain the corresponding digital code. It can be seen from the expression of V o, t6 that since the reference voltage V com is a fixed quantity and has nothing to do with the intensity of light, the voltage value output by the operational amplifier minus the reference voltage is equal to the difference between the reset voltage and the pixel voltage multiplied by With the first sampling times, random noise can be effectively reduced.
  • the correlated multi-sampling circuit 1031 performs correlated multi-sampling on the voltage output by the photoelectric conversion circuit 101.
  • FIG. 7 is a schematic diagram of a simulation experiment involved in an embodiment of the application.
  • Vo_amp is the output voltage of the operational amplifier in the correlated multi-sampling circuit 1031. It can be seen from Fig. 7 that the number of sampling times (the first sampling times) of the pixel voltage (and reset voltage) by the correlated multi-sampling circuit is determined by the voltage of the pixel voltage. Therefore, in the scene of higher light intensity, the pixel voltage output by the photoelectric conversion circuit is also higher.
  • the judgment circuit determines the lower first sampling times according to the higher pixel voltage, so as to prevent the voltage output by the correlated multi-sampling circuit from exceeding the first A quantization range of the analog-to-digital converter; and in the scene of lower light intensity, the pixel voltage output by the photoelectric conversion circuit is also lower, and the judgment circuit determines the higher first sampling times according to the lower pixel voltage. Not limited by pixel full hydrazine capacity. Whether it is a scene with high light intensity or low light intensity, Vo_amp will not exceed the quantization range of the analog-to-digital converter (ADC). Therefore, it can effectively reduce the noise of the output image in the dark environment, improve the quality of the output image, and increase the pixels. Dynamic range.
  • the judgment circuit 102 further includes: S6 switch, AZ1 switch, C3 capacitor, and C4 capacitor, wherein both ends of the C3 capacitor are connected to the S5 switch and the first voltage comparator respectively.
  • one end of the S6 switch is electrically connected to the threshold voltage generating circuit
  • the other end is electrically connected to one end of the C4 capacitor
  • the other end of the C4 capacitor is electrically connected to the first voltage comparator.
  • the non-inverting input terminal and the inverting input terminal of the first voltage comparator are respectively electrically connected to the AZ1 switch, and the other end of the AZ1 switch is used to connect to the reference voltage Vcom2.
  • FIG. 9 is a schematic diagram of another control sequence of the image reading circuit according to an embodiment of the application.
  • the determination circuit 102 detects the pixel voltage (t0-t1 time period)
  • the AZ1 signal is controlled from a low level to a high level, and the AZ1 switch is turned on.
  • the S5 switch and the S6 switch are turned off, so that the first voltage comparator 1022 performs automatic zero adjustment, specifically: the first voltage comparator 1022 is input from the non-inverting input terminal and the inverting input terminal
  • Vcom2 reference voltage
  • the first voltage comparator 1022 uses the voltage difference to eliminate errors, so as to improve the accuracy of the first voltage comparator.
  • the S5 signal and the S6 signal are controlled from low level to high level, the S5 switch and S6 switch are turned on, the C3 capacitor collects the pixel voltage, and the C4 capacitor collects the first Threshold voltage. Since the capacitor has the function of isolating direct current, the C3 capacitor and the C4 capacitor can be used to protect the first voltage comparator 1022, and the first voltage comparator 1022 also uses a lower first threshold voltage and power supply voltage. The voltage value interval where the pixel voltage is located can be determined to reduce the power consumption of the image reading circuit.
  • the first voltage comparator uses the voltage difference measured during automatic zero adjustment to eliminate errors, so as to improve the accuracy of the first voltage comparator.
  • a capacitor is provided between the first voltage comparator and the threshold voltage generating circuit and the photoelectric conversion circuit. While protecting the first voltage comparator, the first voltage comparator uses a lower first threshold voltage and power supply voltage. Next, the voltage value interval where the pixel voltage is located can also be determined, which reduces the power consumption of the image reading circuit.
  • the judgment circuit 102 may also include a second voltage comparator, the number of the second voltage comparator is one or more, and the purpose of the second voltage comparator is different from that of the second voltage comparator.
  • the first voltage comparator 1022 is similar.
  • the judgment circuit 102 further includes: an S7 switch, an S8 switch, a C5 capacitor, and a C6 capacitor, wherein both ends of the C5 capacitor are electrically connected to the S7 switch and the second voltage comparator, and one end of the S8 switch generates a threshold voltage.
  • the circuit is electrically connected, the other end is electrically connected to one end of the C6 capacitor, and the other end of the C6 capacitor is electrically connected to the second voltage comparator.
  • the non-inverting input terminal and the inverting input terminal of the second voltage comparator are respectively electrically connected to the AZ1 switch, and the other end of the AZ1 switch is used to connect to the reference voltage Vcom2.
  • the second voltage comparator is used to determine the second voltage comparison result based on the second threshold voltage and the pixel voltage, the second threshold voltage is generated by the threshold voltage generating circuit; the multiple sampling times selection circuit is also used to determine the second voltage comparison result based on the first voltage The comparison result and the second voltage comparison result determine the first sampling times.
  • the judgment circuit can compare the pixel voltage domain with multiple threshold voltages (second threshold voltages) at the same time to determine the voltage comparison of the pixel voltage As a result, the speed of the result (the second voltage comparison result) is greatly increased, so that the speed of pixel image reading can be effectively increased.
  • the first circuit 103 can also use multiple analog-to-digital converters to process the voltage.
  • the first circuit 103 further includes an SHR switch, a CSHR capacitor, an SHS switch, a CSHS capacitor, and a second analog-to-digital converter.
  • the output terminal of the operational amplifier (AMP) is electrically connected to one end of the SHR switch and one end of the SHS switch, respectively.
  • the other end of the SHR switch is electrically connected with the CSHR capacitor and the first analog-to-digital converter
  • the other end of the SHS switch is electrically connected with the CSHS capacitor and the second analog-to-digital converter.
  • FIG. 12 is a schematic diagram of another control sequence of the image reading circuit according to an embodiment of the application.
  • the judgment circuit 102 in the image reading circuit 100 collects the pixel voltage, and determines the first sampling number according to the pixel voltage. Then, in the time period t1–t3, the correlated multi-sampling circuit 1031 in the first circuit 103 performs correlated multi-sampling of the pixel voltage by controlling the S1 switch, the S2 switch, the S3 switch, and the S4 switch to obtain the first pixel voltage. Specifically, The description of the foregoing embodiment is similar to the description here and will not be repeated.
  • the SHS switch is turned on, and the first pixel voltage (the cumulative sum of the pixel voltage) is sampled on the CSHS capacitor and output to the second analog-to-digital converter at the back end for quantization.
  • the resulting digital code is called The third number code.
  • the SR switch (not shown in the figure) in the photoelectric conversion circuit 101 is turned on, and the photoelectric conversion circuit 101 outputs the reset voltage to the correlated multi-sampling circuit 1031.
  • the correlated multi-sampling circuit 1031 completes the correlated multi-sampling of the reset voltage to obtain the first A reset voltage.
  • the SHR switch is turned on, and the first reset voltage (the cumulative sum of the reset voltage) is sampled on the CSHR capacitor and output to the first analog-to-digital converter at the back end for quantization.
  • the resulting digital code is called The fourth digital code.
  • the pixel processor processes the digital codes output by the first analog-to-digital converter and the second analog-to-digital converter, specifically, subtracting the third digital code from the fourth digital code
  • the second digital code is obtained, the second digital code is the digital code corresponding to the second voltage, and the second voltage is the accumulated sum of the pixel voltage after correlated multi-sampling, and the difference between the accumulated sum of the reset voltage after correlated multi-sampling.
  • the pixel processor determines the first digital code according to the second digital code and the first sampling times, where the first digital code is a digital code corresponding to the first voltage. Specifically, the second digital code is divided by the first sampling times to obtain the first digital code.
  • first analog-to-digital converter and the second analog-to-digital converter in the embodiment of the present application can be different analog-to-digital converters or the same analog-to-digital converter.
  • the analog-to-digital converter separately executes the steps performed by the first analog-to-digital converter and the second analog-to-digital converter in this embodiment, which are not limited here.
  • the analog-to-digital converter in the first circuit respectively performs the subtraction operation after the accumulation and quantization of the pixel voltage and the accumulation and quantization of the reset voltage are respectively converted into digital codes.
  • the system error generated by the analog-to-digital converter is eliminated, thereby improving the fixed pattern noise (FPN) of the image reading circuit (and the image sensor to which the image reading circuit is applied).
  • FPN fixed pattern noise
  • the judgment circuit shown in FIG. 10 the first circuit shown in FIG. 11, and the photoelectric conversion circuit shown in FIG. 3 can form another image reading circuit.
  • the specific connection structure and work of the image reading circuit The manner is similar to the content described in the foregoing embodiment, and will not be repeated here.
  • the image reading circuit described in the foregoing embodiments can be applied to an image sensor, which is a type of CMOS image sensor (complementary metal oxide semiconductor) manufactured by a complementary metal oxide semiconductor (CMOS) process.
  • CMOS complementary metal oxide semiconductor
  • metal oxide semiconductor image sensor, CIS metal oxide semiconductor image sensor
  • the following takes the image sensor as a time-of-flight sensor as an example for introduction.
  • FIG. 13 is a schematic structural diagram of a time-of-flight sensor according to an embodiment of the application.
  • a time-of-flight sensor (ToF) is an image sensor that detects the time of flight from the camera head and reflects the object to be measured until it is received by the camera, and combines the speed of light to calculate the depth of the object.
  • the time-of-flight sensor includes a pixel array (pixels array), a column readout circuit (column readout), a post-processing circuit (post-processing), a timing controller (sequencer), a modulation driver (modulation driver), etc.
  • the time-of-flight sensor first uses the timing controller to generate specific modulation pulses, and controls the pixel array through the modulation driver.
  • another signal is driven by the board-level laser drive chip to drive an external laser to send out a modulated light signal. After the modulated light signal is reflected by the measured object, it is focused on the pixel array of the time-of-flight sensor through the lens.
  • the pixels convert the received light signals into electrical signals, and after the column readout circuit and post-processing unit quantize and process the electrical signals of each pixel, the flight time of the light path received by each pixel can be obtained. Finally, through other post-processing algorithms, the complete depth information of the object can be obtained.
  • the time-of-flight sensor needs to actively emit light pulse signals, according to the principle of time-of-flight detection, all pixels need to receive photons at the same time to ensure the consistency of the pixel array, so the time-of-flight sensor often adopts the global shutter exposure mode.
  • the global shutter mode can avoid serious motion artifacts.
  • the chip is required to accurately quantify the received light energy and reduce noise. Therefore, low noise is also an important design requirement.
  • the pixel voltage output by the photoelectric conversion circuit is determined by the voltage value of the pixel voltage. It is also higher.
  • the judgment circuit determines the lower first sampling times according to the higher pixel voltage, so as to prevent the voltage output by the correlated multi-sampling circuit from exceeding the quantization range of the first analog-to-digital converter, and improve the image output by the image reading circuit. quality. In a scene with lower light intensity, the pixel voltage output by the photoelectric conversion circuit is also lower.
  • the judgment circuit determines the higher first sampling times according to the lower pixel voltage, which reduces the noise of the output image in a dark light environment. Improve the quality of the output image and improve the dynamic range of pixels.
  • the image reading circuit proposed in this application is applied to the time-of-flight sensor, the design requirements of the time-of-flight sensor can be fully satisfied, and the output image quality of the time-of-flight sensor is improved.
  • FIG. 14 is a schematic structural diagram of an image capturing optical system in an embodiment of the application.
  • the image capturing optical system 1400 includes an imaging lens group 1401, a driving device 1402, an image sensor 1403, and an image stabilization module 1404.
  • the image sensor 1403 includes the image reading circuit in any of the above embodiments.
  • the image capturing optical system 1400 utilizes the lens group 1401 to collect light to generate an image, and cooperates with the driving device 1402 to perform image focusing, and finally the image is formed on the image sensor 1403 and can be output as image data.
  • the driving device 1402 may have an auto-focus function, and its driving method may use such as voice coil motor (VCM), micro electro-mechanical systems (MEMS), piezoelectric system (piezoelectric) , And drive systems such as shape memory alloy.
  • VCM voice coil motor
  • MEMS micro electro-mechanical systems
  • piezoelectric piezoelectric
  • shape memory alloy a shape memory alloy
  • the driving device 1402 can allow the lens group 1401 to obtain a better imaging position, and can provide a clear image of the subject under different object distances.
  • the image capturing optical system 1400 is equipped with an image sensor 1403 with good sensitivity and low noise, such as a complementary metal-oxide-semiconductor (CMOS) photosensitive device.
  • CMOS complementary metal-oxide-semiconductor
  • the image sensor 1403 is arranged on the image surface of the lens group, which can truly present the good imaging quality of the lens group.
  • the image stabilization module 1404 is, for example, an accelerometer, a gyroscope, or a Hall Effect Sensor (Hall Effect Sensor).
  • the driving device 1402 can be combined with the image stabilization module 1404 to act as an optical image stabilization (OIS), which adjusts the change of the lens group 1401 in different axial directions to compensate for the blurred image caused by shaking at the moment of shooting, or use image software
  • OIS optical image stabilization
  • the image compensation technology in China provides electronic image stabilization (EIS) to further improve the imaging quality of dynamic and low-light scenes.
  • FIG. 15 is a schematic diagram of a terminal device in an embodiment of this application
  • FIG. 16 is a schematic diagram of another terminal device in an embodiment of this application.
  • the terminal device 20 is a smart phone.
  • the terminal device 20 includes an image capturing optical system 1400, a flash module 21, a focus assist module 22, an image signal processor 23 (image signal processor), a user interface 24, and an image software processor 25.
  • the aforementioned terminal device 20 includes an image capturing optical system 1400 as an example, but this embodiment is not limited to this.
  • the terminal device 20 may include a plurality of image capturing optical systems 1400, or may further include other image capturing optical systems in addition to the image capturing optical system 1400.
  • the terminal device 20 uses the image capturing optical system 1400 to condense and capture the image, activates the flash module 21 to fill light, and uses the subject provided by the focus assist module 22
  • the object distance information of the object is quickly focused, and the image signal processor 23 performs image optimization processing to further improve the image quality produced by the lens group of the camera system.
  • the focus assist module 22 can use an infrared or laser focus assist system to achieve rapid focus.
  • the user interface 24 may adopt a touch screen or a physical shooting button, and cooperate with the diversified functions of the image software processor 25 to perform image shooting and image processing.
  • the image capturing optical system 1400 of the present application is not limited to being applied to smart phones.
  • the image capturing optical system 1400 can be applied to a mobile focusing system as required, and has the characteristics of excellent aberration correction and good imaging quality.
  • the image capturing optical system 1400 can be applied to three-dimensional (3D) image capturing, digital cameras, mobile devices, tablet computers, smart TVs, network monitoring equipment, driving recorders, reversing development devices, and multi-lens devices. , Identification systems, somatosensory game consoles and wearable devices and other terminal equipment.
  • the terminal device disclosed in this embodiment only exemplarily illustrates the practical application example of the present application, and does not limit the application scope of the image capturing optical system of the present application.
  • this application also proposes an image reading method of the image reading circuit, which is applied to the image reading circuit 1400.
  • an image reading method of the image reading circuit which is applied to the image reading circuit 1400.
  • Figure 17 is a schematic flowchart of an embodiment of an image reading method in an embodiment of the application.
  • Step 1701 Collect the reset voltage.
  • the reset circuit 1012 outputs a reset voltage
  • the first transistor 1013 and the second transistor 1014 are in a conducting state
  • the first capacitor 1015 and the second capacitor 1016 collect the reset voltage.
  • Step 1702 Collect pixel voltages.
  • the photoelectric sensor 1011 outputs photoelectrons.
  • the first transistor 1013 is in the on state and the second transistor 1014 is in the off state. Therefore, the first capacitor 1015 maintains the reset voltage, and the second capacitor 1016 is based on the electrons corresponding to the reset voltage.
  • the photoelectron output from the photoelectric sensor 1011 is further collected to complete the collection of the pixel voltage.
  • Step 1703 Determine the first sampling times according to the pixel voltage.
  • the threshold voltage generating circuit 1021 is used to generate one or more first threshold voltages, and the first threshold voltages are output to the first voltage comparator 1022.
  • the first voltage comparator 1022 compares the first threshold voltage with the pixel voltage from the photoelectric conversion circuit 101 to determine the first voltage comparison result.
  • the multi-sampling frequency selection circuit 1023 is preset with sampling times corresponding to each voltage interval. The multi-sampling frequency selection circuit 1023 can determine the first sampling frequency according to the first voltage comparison result, and determine the correlation multiplier corresponding to the first sampling frequency. Control sequences of the sampling circuit 1003.
  • Step 1704 Perform correlated multi-sampling on the pixel voltage and the reset voltage according to the first sampling times to determine the first voltage.
  • the correlated multi-sampling circuit 1031 is specifically configured to perform correlated multi-sampling on the pixel voltage and the reset voltage output by the photoelectric conversion circuit 101 according to the first sampling times output by the judgment circuit 102, and output the second voltage to the first analog-to-digital converter 1032,
  • the second voltage is a cumulative sum of the first voltage
  • the first voltage is a voltage generated by photoelectrons.
  • the correlated multi-sampling circuit 1031 is electrically connected to the first analog-to-digital converter 1032.
  • the correlated multi-sampling circuit 1031 includes one or more switches and one or more capacitor circuits.
  • the correlated multi-sampling circuit 1031 is used to correlate the pixel voltage and the reset voltage according to the control timing configured by the multi-sampling number selection circuit 1023. sampling. Specifically, when the first sampling number is 1, the correlated multi-sampling circuit 1031 performs one sampling operation on the pixel voltage and the reset voltage; when the first sampling number is 2, the correlated multi-sampling circuit 1031 performs a sampling operation on the pixel voltage and the reset voltage. After each sampling operation is performed once, the previous sampling operation is repeated, and so on.
  • the correlated multi-sampling circuit 1031 performs correlated multi-sampling on the pixel voltage and the reset voltage according to the control timing to obtain the second voltage, where the second voltage is the cumulative sum of the pixel voltage and the reset voltage after correlated multi-sampling, and controls
  • the timing is determined by the judging circuit 102 according to the first sampling times, and the second voltage is the product of the first voltage and the first sampling times; secondly, the first analog-to-digital converter 1032 converts the second voltage into the second digital code; again, because the pixel
  • the processor 1033 is electrically connected to the multi-sampling frequency selection circuit 1023, so the pixel processor 1033 determines the first digital code according to the first sampling frequency from the multi-sampling frequency selection circuit 1023 and the second digital code from the first analog-to-digital converter 1032 ,
  • the first digital code is the digital code of the first voltage.
  • the correlated multi-sampling circuit 1031 outputs the first pixel voltage to the first analog-to-digital converter 1032 after correlated multi-sampling of the pixel voltage for the first number of times.
  • the first pixel voltage is the pixel voltage of the correlated multi-sampling circuit 1031.
  • the first analog-to-digital converter 1032 converts the first pixel voltage into a third digital code; secondly, the correlated multi-sampling circuit 1031 performs a reset operation to eliminate the electrons remaining in the previous correlated multi-sampling of the pixel voltage.
  • the correlated multi-sampling circuit 1031 outputs the first reset voltage to the first analog-to-digital converter 1032 after correlated multi-sampling of the reset voltage by the first number of sampling times.
  • the first analog-to-digital converter 1032 converts the first reset voltage into a fourth digital code; again, the pixel processor 1033 determines the second digital code according to the third digital code and the fourth digital code, and the second digital code is the second voltage Corresponding digital code, the second voltage is the difference between the accumulated sum of the pixel voltage after correlated multi-sampling and the reset voltage after correlated multi-sampling; the pixel processor 1033 determines it according to the second digital code and the first sampling times
  • the first digital code the first digital code is a digital code of the first voltage.
  • the pixel voltage output by the photoelectric conversion circuit is also higher in a scene with higher light intensity.
  • the judgment circuit determines the lower first sampling times according to the higher pixel voltage, so as to prevent the voltage output by the correlated multi-sampling circuit from exceeding the quantization range of the first analog-to-digital converter, and improve the image quality output by the image reading circuit.
  • the pixel voltage output by the photoelectric conversion circuit is also lower.
  • the judgment circuit determines the higher first sampling times according to the lower pixel voltage, which reduces the noise of the output image in a dark light environment. Improve the quality of the output image and improve the dynamic range of pixels.
  • determining the first sampling times according to the pixel voltage may include: generating a first threshold voltage; determining a first voltage comparison result according to the first threshold voltage and the pixel voltage; The first voltage comparison result determines the first sampling times.
  • the first voltage comparison result is determined according to the comparison between the first threshold voltage and the pixel voltage.
  • the first threshold voltage of includes 0.25 volts (V), 0.5V and 0.8V.
  • the pixel voltage is 0.45V.
  • 0.5V (first threshold voltage) and 0.45V (pixel voltage) are compared, and the output voltage comparison result is 0 (that is, the pixel voltage is less than the first threshold voltage).
  • the above voltage comparison results are collectively referred to as the first voltage comparison results.
  • a plurality of voltage intervals are preset in the first voltage comparator to determine the voltage interval corresponding to the pixel voltage, and each voltage interval is preset with a corresponding sampling number.
  • the voltage interval in which the pixel voltage is located is determined according to the first voltage comparison result.
  • the preset voltage intervals are: the first voltage interval 0V-0.25V; the second voltage interval 0.25V-0.5V; the third voltage interval 0.5V-0.8V; the fourth voltage interval 0.8V-1.5V. Therefore, it is determined that the pixel voltage is in the second voltage interval. And determine the first sampling times according to the voltage interval.
  • the first sampling times corresponding to the pixel voltage are determined by determining the voltage interval in which the pixel voltage is located. Improved the flexibility of the solution.
  • the second voltage is the product of the first voltage and the first sampling times; the second voltage is converted into a second digital code; the second digital code is determined according to the second digital code and the first sampling times.
  • a digital code, and the first digital code is a digital code of the first voltage.
  • first perform correlated multi-sampling of the pixel voltage and the reset voltage to obtain the second voltage, where the second voltage is the cumulative sum of the pixel voltage and the reset voltage after the correlated multi-sampling, and the second voltage is the first voltage and the reset voltage.
  • the voltage is converted into a digital code for the subsequent further processing of the pixel processor and other components.
  • the first reset voltage converted into a fourth digital code the first reset voltage is the reset voltage after the first sampling times of correlated multi-sampling of the reset voltage; according to the third digital code and The fourth digital code determines the second digital code, the second digital code is the digital code corresponding to the second voltage, and the second voltage is the cumulative sum of the pixel voltage and the reset voltage after correlated multi-sampling; according to the The second digital code and the first sampling frequency determine a first digital code, and the first digital code is a digital code of the first voltage.
  • the first pixel voltage is output, and the first pixel voltage is the cumulative sum of the pixel voltage after the pixel voltage has undergone correlated multi-sampling for the first number of sampling times. Convert the first pixel voltage into a third digital code; secondly, after the reset voltage has undergone the first sampling times of correlated multi-sampling, the first reset voltage is output, and the first reset voltage is the correlation multi-sampling of the reset voltage after the first sampling times. The cumulative sum of the reset voltage after sampling.
  • the first reset voltage is converted into a fourth digital code; again, the second digital code is determined according to the third digital code and the fourth digital code, the second digital code is the digital code corresponding to the second voltage, and the second voltage is the pixel voltage and
  • the reset voltage is the cumulative sum of the voltage values after the correlation multi-sampling; the first digital code is determined according to the second digital code and the first sampling times, and the first digital code is the digital code of the first voltage.
  • the accumulation and quantization of the pixel voltage and the accumulation and quantization of the reset voltage are respectively converted into digital codes, and then the subtraction operation is performed.
  • the systematic error generated in the process of quantizing the voltage into the digital code is eliminated, thereby improving the fixed pattern noise (FPN).
  • one embodiment or “an embodiment” mentioned throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of the present application. Therefore, the appearances of "in one embodiment” or “in an embodiment” in various places throughout the specification do not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in the various embodiments of the present application, the size of the sequence number of the above-mentioned processes does not mean the order of execution, and the execution order of each process should be determined by its function and internal logic, and should not correspond to the embodiments of the present application. The implementation process constitutes any limitation.

Abstract

本申请实施例提出一种图像读取电路、图像传感器以及终端设备。其中，图像读取电路包括：光电转换电路包括光电传感器和复位电路，光电传感器用于接收光子并输出光电子，复位电路用于输出复位电压；光电转换电路，还用于采集像素电压，像素电压为第一电压和复位电压的累加和，第一电压为光电子产生的电压，第一电压与光照强度正相关；判断电路，用于根据像素电压确定第一采样次数，其中，第一采样次数与像素电压负相关；相关多采样电路，用于根据第一采样次数对像素电压和复位电压进行相关多采样以确定第一电压。提升了输出图像的质量，提高了像素的动态范围。

Description

一种图像读取电路、图像传感器以及终端设备 技术领域
本申请涉及电子电路技术领域，尤其涉及一种图像读取电路、图像传感器以及终端设备。
背景技术
图像传感器是一种将光学影像转换成电信号的传感器，广泛应用在数码相机、智能手机等终端设备中。目前，常用的图像传感器主要是一类利用互补式金属氧化物半导体(complementary metal oxide semiconductor，CMOS)工艺制造的CMOS图像传感器(complementary metal oxide semiconductor image sensor，CIS)。图像传感器(CIS)包括的电路称为图像读取电路，图像读取电路主要包括两个部分：感光部分与非感光部分(非感光部分也称为数据读出部分)。其中，感光部分由像素阵列组成，像素阵列中包括的基本单元称为像素(或称为光电转换电路(photovoltaic conversion circuit))，每个像素中包括光电传感器和其它电路。像素中光电传感器利用光电效应将接收的光子(photon)转换为光电子(photoelectron)。像素中其它电路(除光电传感器以外部分)对该光电子进行转换和存储，得到相应的电信号。数据读出部分(包括列读出电路)对该电信号进行量化和处理。
光电传感器接收光子的过程称为曝光(exposure)，为了消除每次曝光所生成的光电子对下次曝光的结果产生影响，在每次曝光结束后，图像读取电路进行复位操作。目前，通常采用相关多采样(correlated multiple sampling，CMS)消除复位操作所产生的复位噪声和电路本身产生的随机噪声。
在光电转换电路中包括复位电路，该复位电路执行复位操作时对光电转换电路所施加的电压称为复位电压。由于，光电转换电路需要经过复位操作后，才会接收光电子，因此，图像读取电路根据所接收的光电子采集得到的电压，包括复位电压和光电子所产生的电压，该采集得到的电压称为像素电压。相关多采样的具体操作为：多次采样像素电压和复位电压。因此，将多次采样的像素电压与多次采样的复位电压相减，再除以采样的次数，即可得到真正由接收的光电子所产生的电压值，该采样次数也称为M，M为正整数。对于有效电压(复位电压以及光电子所产生的电压)，其在时域是稳定的，多次采样的结果等效为将有效电压乘以M倍。而对于随机噪声，由于其在时域是随机的，有正有负，多次采样累加的随机噪声等效为一个在时域上均值滤波的结果，因此噪声经过多采样后被有效抑制。通过像素电压与复位电压的相减操作，可有效消除复位噪声。
在图像读取电路的末端，需要通过模数转换器(analog-to-digital converter，ADC)将电压等模拟信号转换为数字信号(例如数字码)，以便后续元器件的处理。然而，目前的相关多采样技术中，采样次数(M值)是固定的。由于光强与像素电压成正比，在光强特别大的场景下，图像读取电路采集的像素电压的电压值也较高，采样次数较大时，经过相关多采样后，该像素电压乘以M的结果，往往会超过ADC的量化范围。在ADC的模数转换 过程中产生新的误差，进而影响输出图像的质量。
发明内容
本申请实施例第一方面提供了一种图像读取电路、图像传感器以及终端设备，提升了输出图像的质量，提高了像素的动态范围。
有鉴于此，本申请实施例提出如下技术方案：
第一方面，本申请实施例提出一种图像读取电路，该图像读取电路包括：光电转换电路、判断电路(decision circuit)和相关多采样电路(correlated multiple sampling circuit，CMS circuit)。该光电转换电路包括光电传感器和复位电路，该光电传感器利用光电效应将接收的光子转换为光电子，该复位电路用于输出复位电压，可选的，该复位电路可以通过一个或多个元器件组成的复位电路(reset circuit)实现，也可以通过一个或多个复位三极管或复位晶体管实现，此处不作限定；该光电转换电路，用于采集像素电压，并将该像素电压分别输出至该判断电路和该相关多采样电路，具体的，光电转换电路在复位电压对应的电子基础上进一步采集光电传感器输出的光电子，完成对像素电压的采集；该判断电路，用于根据该像素电压确定第一采样次数，其中，该第一采样次数与该像素电压负相关。具体的，当光电转换电路采集的像素电压越大，则判断电路根据该像素电压确定的第一采样次数越小。当光电转换电路采集的像素电压越小，则判断电路根据该像素电压确定的第一采样次数越大；该相关多采样电路，用于根据该第一采样次数对该像素电压和该复位电压进行相关多采样以确定第一电压，该第一电压为光电子产生的电压，第一电压与光照强度正相关。
本申请实施例中，图像读取电路根据像素电压确定相关多采样的采样次数，其次，图像读取电路根据确定的采样次数对像素电压和复位电压进行相关多采样，以确定第一电压，该第一电压为光电子产生的电压。由于光电转换电路在复位电压对应的电子基础上进一步采集光电传感器输出的光电子，完成对像素电压的采集，因此像素电压与光照强度正相关，即光照强度越大，像素电压越大；光照强度越小，像素电压越小。在光强特别大的场景下，图像读取电路根据所采集的较高的像素电压，确定较低的采样次数，避免了像素电压乘以采样次数后，超过ADC的量化范围，提升了输出图像的质量。而在光强特别小的场景(暗光环境)下，图像读取电路根据较小的像素电压，确定较高的采样次数，降低了暗光环境下输出图像的噪点，提升了输出图像的质量，提高了像素的动态范围。
结合第一方面，在第一方面的一种可能实现中，该光电转换电路还可能包括：第一晶体管、第二晶体管、第一电容和第二电容，其中，该第一晶体管与该光电传感器电连接，该第一晶体管与该第二电容电连接，该第一晶体管与该复位电路电连接，其中，该第一晶体管用于导通或关断该光电传感器与该第二电容之间的连接通路，该第一晶体管还用于控制该复位电路与该第二电容之间连接通路的导通或关断，该第二电容用于采集该像素电压；该第二晶体管与该第一晶体管电连接，该第二晶体管与该第一电容电连接，其中，该第二晶体管与该第一晶体管共同用于控制该复位电路与该第一电容之间连接通路的导通或关 断，该第一电容用于采集该复位电压；该相关多采样电路与该第二晶体管电连接，该第二晶体管用于控制该相关多采样电路与该第一电容之间连接通路的导通或关断；该相关多采样电路与该第二电容电连接。
本申请实施例中，通过上述的光电转换电路，第一电容在第一晶体管和第二晶体管的共同控制下采集复位电压，第二电容在第一晶体管的控制下采集像素电压，使得光电转换电路可以向判断电路(和相关多采样电路)先输出像素电压，以便判断电路根据该像素电压确定第一采样次数，其中，像素电压与光照强度正相关，第一采样次数与像素电压负相关。
结合第一方面，在第一方面的一种可能实现中，该判断电路具体包括第一电压比较器(voltage comparator)、阈值电压产生电路(threshold voltage generator)和多采样次数选择电路(multi-sampling time selection)，该第一电压比较器与该阈值电压产生电路电连接，该阈值电压产生电路用于产生第一阈值电压；该第一电压比较器与该第二电容电连接，该第一电压比较器用于比较该第一阈值电压与该像素电压，以产生第一电压比较结果；该第一电压比较器与该多采样次数选择电路电连接，该多采样次数选择电路根据该第一电压比较结果确定该第一采样次数。
具体的，第一电压比较器根据该第一阈值电压与来自光电转换电路的像素电压进行比较，确定第一电压比较结果。例如，阈值电压产生电路产生的第一阈值电压包括0.25伏(V)，0.5V和0.8V。来自光电转换电路101的像素电压为0.45V。第一电压比较器首先比较0.25V(第一阈值电压)与0.45V(像素电压)，输出电压比较结果为1(即像素电压大于该第一阈值电压)。然后，比较0.5V(第一阈值电压)与0.45V(像素电压)，输出电压比较结果为0(即像素电压小于该第一阈值电压)。上述电压比较结果统称为第一电压比较结果。第一电压比较器中预设多个电压区间，用以确定像素电压所对应的电压区间，每个电压区间预设有对应的采样次数。第一电压比较器根据该第一电压比较结果确定像素电压所在的电压区间。第一电压比较器中预设的电压区间分别为：第一电压区间0V-0.25V；第二电压区间0.25V-0.5V；第三电压区间0.5V-0.8V；第四电压区间0.8V-1.5V。因此，第一电压比较器确定该像素电压处于第二电压区间。第一电压比较器将该第一电压比较结果输出至多采样次数选择电路。
本申请实施例中，判断电路通过第一电压比较器、阈值电压产生电路和多采样次数选择电路之间的配合使用，确定光电转换电路输出的像素电压所在的电压区间，进而确定该像素电压所对应的第一采样次数。提升了方案的实现灵活性。
结合第一方面，在第一方面的一种可能实现中，该判断电路还可以包括第二电压比较器，该第二电压比较器与该阈值电压产生电路电连接，该第二电压比较器与该多采样次数选择电路电连接；该第二电压比较器，用于根据第二阈值电压与该像素电压确定第二电压比较结果，该第二阈值电压由该阈值电压产生电路产生；该多采样次数选择电路，具体用于：根据该第一电压比较结果和该第二电压比较结果确定该像素电压所在电压区间；根据 该电压区间确定该第一采样次数。具体的，该第一电压比较器和第二电压比较器的数量，此处不作限定。
本申请实施例中，通过在判断电路中设置第一电压比较器和第二电压比较器，判断电路可以同时将像素电压域与多个阈值电压(第一阈值电压和第二阈值电压)进行比较，确定像素电压的电压比较结果(第一电压比较结果和第二电压比较结果)的速度大大增快，因此能有效提高像素图像读取的速度。
结合第一方面，在第一方面的一种可能实现中，该图像读取电路还可以包括第一模数转换器和像素处理器，模数转换器(analog-to-digital converter，ADC)通常是指一个将模拟信号(电压)转变为数字信号(数字码)的电子元件，模数转换器用于将电信号(电压)转换为数字码(digital encoding)。数字码是一种计算机所用的二进制码，如“0101001”，用来表示信号的大小。该相关多采样电路与该判断电路电连接，该相关多采样电路与该第一模数转换器电连接，该相关多采样电路与该光电转换电路电连接，该第一模数转换器与该像素处理器电连接，该像素处理器与该判断电路电连接；该相关多采样电路，用于对该像素电压和该复位电压进行相关多采样得到第二电压，其中，该第二电压为该像素电压和该复位电压经过相关多采样后电压值的累加和，该第二电压为该第一电压与该第一采样次数乘积；该第一模数转换器，用于将该第二电压转换为第二数字码；该像素处理器，用于根据该第二数字码和该第一采样次数确定第一数字码，该第一数字码为该第一电压的数字码。
具体的，首先，相关多采样电路根据控制时序对像素电压和复位电压进行相关多采样得到第二电压，其中，第二电压为像素电压和复位电压经过相关多采样后电压值的累加和，控制时序由判断电路根据第一采样次数确定，第二电压为第一电压与第一采样次数乘积；其次，第一模数转换器将第二电压转换为第二数字码；再次，由于像素处理器与多采样次数选择电路电连接，因此像素处理器根据来自多采样次数选择电路的第一采样次数和来自第一模数转换器的第二数字码确定第一数字码，第一数字码为第一电压的数字码。可选的，像素处理器还可以对第一数字码(数字信号)进行滤波等后处理。
本申请实施例中，通过第一模数转换器对相关多采样电路输出的电压进行处理，以便后续像素处理器和其它元件的进一步处理。
结合第一方面，在第一方面的一种可能实现中，图像读取电路还包括第一模数转换器和像素处理器，该相关多采样电路与该判断电路电连接，该相关多采样电路与该光电转换电路电连接，该相关多采样电路与该第一模数转换器电连接，该第一模数转换器与该像素处理器电连接，该像素处理器与该判断电路电连接；该相关多采样电路，还用于对该像素电压经过该第一采样次数的相关多采样后采集得到第一像素电压；该第一模数转换器，用于将第一像素电压转换为第三数字码；该相关多采样电路，还用于对该复位电压经过该第一采样次数的相关多采样后采集得到第一复位电压；该第一模数转换器，还用于将第一复位电压转换为第四数字码，该第一复位电压为该相关多采样电路对该复位电压经过该第一 采样次数的相关多采样后该复位电压的累加和；该像素处理器，用于根据该第三数字码和该第四数字码确定第二数字码，该第二数字码为第二电压对应的数字码，该第二电压为该像素电压和该复位电压经过相关多采样后电压值的累加和；该像素处理器，还用于根据该第二数字码和该第一采样次数确定第一数字码，该第一数字码为该第一电压的数字码。
具体的，首先，相关多采样电路对像素电压经过第一采样次数的相关多采样后，向第一模数转换器输出第一像素电压，第一像素电压为相关多采样电路对像素电压经过第一采样次数的相关多采样后像素电压的累加和。第一模数转换器将第一像素电压转换为第三数字码；其次，相关多采样电路进行复位操作，以消除前次对像素电压进行相关多采样所残留的电子。然后，相关多采样电路对复位电压经过第一采样次数的相关多采样后，向第一模数转换器输出第一复位电压，第一复位电压为相关多采样电路对复位电压经过第一采样次数的相关多采样后复位电压的累加和。第一模数转换器，将第一复位电压转换为第四数字码；再次，像素处理器根据第三数字码和第四数字码确定第二数字码，第二数字码为第二电压对应的数字码，第二电压为像素电压和复位电压经过相关多采样后电压值的累加和；像素处理器，根据第二数字码和第一采样次数确定第一数字码，第一数字码为第一电压的数字码。
本申请实施例中，第一模数转换器分别将像素电压的累加和和复位电压的累加和量化为数字码后，再进行相减操作。通过数字域上的操作，将模数转换器所产生的系统误差进行消除，从而改善图像读取电路的固定模式误差(fixed pattern noise，FPN)。
结合第一方面，在第一方面的一种可能实现中，该光电转换电路还可以包括第一源跟随器；该第一源跟随器与该光电传感器电连接，该第一源跟随器与该复位电路电连接，该第一源跟随器与该第一晶体管电连接，该第一源跟随器用于隔绝该光电传感器和该第一晶体管、该复位电路和该第一晶体管之间的电流。
本申请实施例中，通过第一源跟随器隔绝该光电传感器和该第一晶体管、该复位电路和该第一晶体管之间的电流，进而提升转换增益(conversion gain，CG)，进而提升应用该图像读取电路的图像传感器的信噪比(signal noise rotio，SNR)。
结合第一方面，在第一方面的一种可能实现中，判断电路还可以包括：S6开关、AZ1开关、C3电容和C4电容，其中，C3电容的两端分别与S5开关和第一电压比较器电连接，S5开关的另一端与光电转换电路电连接，S6开关的一端与阈值电压产生电路电连接，另一端与C4电容的一端电连接，C4电容的另一端与第一电压比较器电连接。第一电压比较器的正相输入端和反相输入端分别与AZ1开关电连接，该AZ1开关的另一端用于接入参考电压Vcom2。
本申请实施例中，第一电压比较器使用自动调零时测量得到的电压差值消除误差，以提升第一电压比较器的准确性。在第一电压比较器与阈值电压产生电路和光电转换电路之间设置电容，在保护该第一电压比较器的同时，第一电压比较器在使用较低的第一阈值电压和电源电压的情况下，也可以确定像素电压所在的电压值区间，降低了图像读取电路的功耗。
结合第一方面，在第一方面的一种可能实现中，该光电转换电路还可以包括第二源跟随器；该第二源跟随器与该第二晶体管电连接，该第二源跟随器与该第二电容电连接，该第二源跟随器与该判断电路和该相关多采样电路电连接，该第二源跟随器用于放大该光电转换电路输出的该像素电压和该复位电压。
第二方面，本申请实施例提出了一种图像读取方法，该图像读取方法可以应用于如第一方面或第一方面的任一种可能实现的图像读取电路，该图像读取方法包括：
采集复位电压。可选的，复位电路输出复位电压，第一晶体管和第二晶体管处于导通状态，第一电容和第二电容采集该复位电压；
采集像素电压。可选的，光电传感器输出光电子，此时，第一晶体管处于导通状态，第二晶体管处于关断状态，因此，第一电容上维持复位电压，第二电容在复位电压对应的电子基础上进一步采集光电传感器输出的光电子，完成对像素电压的采集；
根据该像素电压确定第一采样次数，其中，该第一采样次数与该像素电压负相关。可选的，根据像素电压确定第一采样次数。阈值电压产生电路用于产生一个或多个第一阈值电压，该第一阈值电压输出至第一电压比较器。第一电压比较器根据该第一阈值电压与来自光电转换电路的像素电压进行比较，确定第一电压比较结果。多采样次数选择电路中预设有对应于各个电压区间的采样次数，多采样次数选择电路可根据第一电压比较结果确定第一采样次数，并确定该第一采样次数所对应的相关多采样电路的控制时序(control sequences)；
根据该第一采样次数对该像素电压和该复位电压进行相关多采样以确定该第一电压。可选的，相关多采样电路具体用于根据判断电路输出的第一采样次数，对光电转换电路输出的像素电压和复位电压进行相关多采样，并向第一模数转换器输出第二电压，该第二电压为第一电压的累加和，该第一电压为光电子产生的电压。相关多采样电路与第一模数转换器电连接。相关多采样电路中包括一个或多个开关以及一个或多个电容的电路，相关多采样电路用于根据多采样次数选择电路所配置的控制时序，对像素电压和复位电压进行相关多采样。具体的，当第一采样次数为1时，相关多采样电路10像素电压和复位电压各进行1次采样操作；当第一采样次数为2时，相关多采样电路对像素电压和复位电压各进行1次采样操作后，重复前次采样操作，以此类推。
本申请实施例中，由于对像素电压的采样次数(第一采样次数)由像素电压的电压值确定，因此在较高光强的场景下，采集的像素电压也较高，根据该较高的像素电压确定较低的第一采样次数，避免输出的电压超过模数转换器的量化范围，提升了输出的图像质量。而在较低光强的场景下，输出的像素电压也较低，根据该较低的像素电压确定较高的第一采样次数，降低了暗光环境下输出图像的噪点，提升了输出图像的质量，提高了像素的动态范围。
结合第二方面，在第二方面的一种可能实现中，根据该像素电压确定该第一采样次数，可能包括：产生第一阈值电压；根据该第一阈值电压与该像素电压确定第一电压比较结果； 根据该第一电压比较结果确定该第一采样次数。
具体的，根据该第一阈值电压与像素电压进行比较，确定第一电压比较结果。例如，的第一阈值电压包括0.25伏(V)，0.5V和0.8V。像素电压为0.45V。首先比较0.25V(第一阈值电压)与0.45V(像素电压)，输出电压比较结果为1(即像素电压大于该第一阈值电压)。然后，比较0.5V(第一阈值电压)与0.45V(像素电压)，输出电压比较结果为0(即像素电压小于该第一阈值电压)。上述电压比较结果统称为第一电压比较结果。第一电压比较器中预设多个电压区间，用以确定像素电压所对应的电压区间，每个电压区间预设有对应的采样次数。根据该第一电压比较结果确定像素电压所在的电压区间。中预设的电压区间分别为：第一电压区间0V-0.25V；第二电压区间0.25V-0.5V；第三电压区间0.5V-0.8V；第四电压区间0.8V-1.5V。因此，确定该像素电压处于第二电压区间。并根据该电压区间确定第一采样次数。
本申请实施例中，通过确定像素电压所在的电压区间，进而确定该像素电压所对应的第一采样次数。提升了方案的实现灵活性。
结合第二方面，在第二方面的一种可能实现中，还可能包括：对该像素电压和该复位电压进行相关多采样得到第二电压，其中，该第二电压为该像素电压和该复位电压经过相关多采样后电压值的累加和，该第二电压为该第一电压与该第一采样次数乘积；根据该第二电压转换为第二数字码；根据该第二数字码和该第一采样次数确定第一数字码，该第一数字码为该第一电压的数字码。
具体的，首先，对像素电压和复位电压进行相关多采样得到第二电压，其中，第二电压为像素电压和复位电压经过相关多采样后电压值的累加和，第二电压为第一电压与第一采样次数乘积；其次，将第二电压转换为第二数字码；再次，根据第一采样次数和第二数字码确定第一数字码，第一数字码为第一电压的数字码。
本申请实施例中，通过将电压转换为数字码，以便后续像素处理器和其它元件的进一步处理。
结合第二方面，在第二方面的一种可能实现中，还可能包括：根据第一像素电压转换为第三数字码，该第一像素电压为该像素电压经过该第一采样次数的相关多采样后该像素电压的累加和；根据第一复位电压转换为第四数字码，该第一复位电压为该复位电压经过该第一采样次数的相关多采样后该复位电压的累加和；根据该第三数字码和该第四数字码确定第二数字码，该第二数字码为第二电压对应的数字码，该第二电压为该像素电压和该复位电压经过相关多采样后电压值的累加和；根据该第二数字码和该第一采样次数确定第一数字码，该第一数字码为该第一电压的数字码。
具体的，首先，对像素电压经过第一采样次数的相关多采样后，输出第一像素电压，第一像素电压为像素电压经过第一采样次数的相关多采样后像素电压的累加和。将第一像素电压转换为第三数字码；其次，对复位电压经过第一采样次数的相关多采样后，输出第一复位电压，第一复位电压为对复位电压经过第一采样次数的相关多采样后复位电压的累加和。将第一复位电压转换为第四数字码；再次，根据第三数字码和第四数字码确定第二数字码，第二数字码为第二电压对应的数字码，第二电压为像素电压和复位电压经过相关 多采样后电压值的累加和；根据第二数字码和第一采样次数确定第一数字码，第一数字码为第一电压的数字码。
本申请实施例中，分别将像素电压的累加和和复位电压的累加和量化为数字码后，再进行相减操作。通过数字域上的操作，将电压量化为数字码过程中所产生的系统误差进行消除，从而改善固定模式误差(fixed pattern noise，FPN)。
第三方面，本申请实施例还提供一种图像传感器，包括像素控制电路和图像读取电路，其中，该图像读取电路包括如上述第一方面以及第一方面的任一项可能实现的该图像读取电路，该像素控制电路用于控制该图像读取电路的曝光。
第四方面，本申请实施例还提供一种图像擷取光学系统，包括镜头组、驱动装置、图像传感器以及图像稳定模块，其中，该图像传感器包括如上述第三方面的该图像传感器。该镜头组用于会聚光线；该图像传感器用于对该镜头组会聚的光线进行处理，并输出图像。
第五方面，本申请实施例还提供一种终端设备，包括图像撷取光学系统、闪光灯模块、对焦辅助模块、图像信号处理器、使用者界面以及图像软件处理器，其中，该图像撷取光学系统包括如上述第四方面的所述图像撷取光学系统，该图像撷取光学系统中包括图像传感器，该图像传感器包括图像读取电路，该图像读取电路包括如上述第一方面以及第一方面的任一项可能实现的该图像读取电路。
附图说明
图1为本申请实施例提供的图像读取电路的一种系统结构示意图；
图2为本申请实施例提出的图像读取电路的一种组成结构示意图；
图3为本申请实施例提出的一种光电转换电路的组成结构示意图；
图4为本申请实施例提出的光电转换电路的一种控制时序示意图；
图5为本申请实施例提出的一种图像读取电路的组成结构示意图；
图6为本申请实施例提出的图像读取电路的一种控制时序示意图；
图7为本申请实施例涉及的一种仿真实验示意图；
图8为本申请实施例中图像读取电路的另一种组成结构示意图；
图9为本申请实施例提出的图像读取电路的另一种控制时序示意图；
图10为本申请实施例中图像读取电路的另一种组成结构示意图；
图11为本申请实施例中图像读取电路的另一种组成结构示意图；
图12为本申请实施例提出的图像读取电路的另一种控制时序示意图；
图13为本申请实施例提出的一种飞行时间传感器的结构示意图；
图14为本申请实施例中一种图像撷取光学系统的结构示意图；
图15为本申请实施例中一种终端设备示意图；
图16为本申请实施例中另一种终端设备示意图；
图17为本申请实施例中一种图像读取方法的实施例流程示意图。
具体实施方式
本申请实施例提供了一种图像读取电路、图像传感器以及终端设备，提升了输出图像的质量，提高了像素的动态范围。
请参阅图1，图1为本申请实施例提供的图像读取电路的一种系统结构示意图。本申请实施例中，图像传感器(CIS)包括的电路称为图像读取电路100，图像读取电路100主要包括两个部分：感光部分与非感光部分(非感光部分也称为数据读出部分)。其中，感光部分由像素阵列组成，像素阵列中包括的基本单元称为像素(或称为光电转换电路101(photovoltaic conversion circuit))，每个像素中包括光电传感器和其它电路。像素中光电传感器利用光电效应将接收的光子(photon)转换为光电子(photoelectron)。像素中其它电路(除光电传感器以外部分)对该光电子进行转换和存储，得到相应的电信号。数据读出部分(包括列读出电路)对该电信号进行量化和处理。除此之外，图像传感器还包括像素控制电路，该像素控制电路用于控制图像读取电路中光电传感器的曝光，例如，控制光电传感器进行1/100秒的曝光。
以图1像素阵列中任意一个像素为例进行说明，该像素(光电转换电路101)中包括光电传感器和复位电路，该光电传感器用于接收光子并输出光电子，该复位电路用于输出复位电压。该光电转换电路101中包括的其它电路(除了光电传感器外)用于采集像素电压和复位电压。与该光电转换电路101电连接的列读出电路包括判断电路102(decision circuit)和第一电路103，其中，该判断电路102与该第一电路103电连接。该判断电路102，用于根据像素电压确定第一采样次数，第一采样次数与像素电压负相关。该判断电路102还用于根据第一采样次数确定第一电路103中相关多采样电路(correlated multiple sampling circuit，CMS circuit)的控制时序，使得该第一电路103根据该控制时序对像素电压和复位电压进行相关多采样以确定第一电压，该第一电压为光电子产生的电压，该第一电压的电压值与光照强度(illumination)正相关。
下面，结合附图对本申请实施例提出的图像读取电路进行详细介绍。
请参阅图2，图2为本申请实施例提出的图像读取电路的一种组成结构示意图。本申请实施例提出的图像读取电路100包括光电转换电路101、判断电路102、第一电路103。下面，分别介绍图像读取电路100的各个部分。
(1)、光电转换电路101。
光电转换电路101具体用于向图像读取电路100的其它部分输出像素电压和复位电压。光电转换电路101包括光电传感器1011、复位电路1012、第一晶体管1013、第二晶体管1014、第一电容1015、第二电容1016、第一源跟随器1017和第二源跟随器1018，光电传感器1011与第一源跟随器1017电连接，复位电路1012与第一源跟随器1017电连接，第一源跟随器1017与第一晶体管1013电连接，第一晶体管1013与第二电容1016电连接，第一晶体管1013与第二晶体管1014电连接，第二晶体管1014与第一电容1015电连接，第二电容1016与第二源跟随器1018电连接，第二晶体管1014与第二源跟随器1018电连接。
光电传感器1011利用光电效应将接收的光子转换为光电子，可选的，该光电传感器 1011中执行可以是光电二极管(photodiode)，也可以是光电三极管(phototriode)，还可以是其它可将光子转换为光电子的元器件，此处不作限定。可选的，光电传感器1011包括光电二极管D和M5晶体管。该光电二极管D用于接收光子并将光子转换为光电子，该M5晶体管的漏极(或源极)与该光电二极管D电连接，该M5晶体管的源极(或漏极)与第一源跟随器1017电连接，该M5晶体管的栅极用于接收控制信号(TX)，该控制信号(TX)用于控制光电二极管D与第一源跟随器1017之间连接通路的导通或关断。当该控制信号(TX)控制该M5晶体管导通时，光电二极管D通过该M5晶体管向第一源跟随器1017输出光电子。
复位电路1012用于每次曝光结束前，该复位电路1012对光电转换电路101施加复位电压(reset voltage，VRST)，使得与该复位电路1012电连接的第一源跟随器1017复位到一个固定的电压值(复位电压的电压值)，将上一次曝光接收到的光电子消除，避免上一帧图像对下一帧图像产生影响。可选的，该复位电路1012可以通过一个或多个元器件组成的复位电路(reset circuit)实现，也可以通过一个或多个复位三极管或复位晶体管实现，此处不作限定。例如，该复位电路1012为M6晶体管，该M6晶体管的栅极用于接收控制信号(RST)，该控制信号(RST)用于控制该M6晶体管输出复位电压，该M6晶体管的源极或漏极与第一源跟随器1017电连接。该M6晶体管的源极或漏极输出的复位电压为VRST。
第一源跟随器1017，源跟随器(source follower)具有阻抗变换(impedance transformer)的功能。本实施例中，第一源跟随器1017用于隔绝光电传感器1011与第一晶体管1013之间的电流，第一源跟随器用于隔绝复位电路1012与第一晶体管1013之间的电流。具体的，第一源跟随器1017的栅极与光电传感器1011电连接，第一源跟随器1017的栅极与复位电路1012的漏极或源极电连接。可选的，第一源跟随器1017由两个晶体管组成，分别是M3晶体管和M4晶体管，其中，M3晶体管作为源跟随管，M4晶体管作为尾电流管，M3晶体管的漏极(或源极)和M4晶体管的漏极(或源极)电连接使得M3晶体管与M4晶体管形成第一源跟随器1017。M3晶体管的栅极与光电传感器1011和复位电路1012电连接，该连接点也称为浮动扩散(floating diffusion，FD)点。第一源跟随器1017对FD点的电压起缓冲作用。M4晶体管的栅极用于接收控制信号，该控制信号(VBIAS)用于控制第一源跟随器1017导通或关断，当VBIAS控制第一源跟随器1017关断时，第一源跟随器1017隔绝光电传感器1011和复位电路1012，与第一晶体管1013之间的电流。当VBIAS控制第一源跟随器1017导通时，第一源跟随器1017对光电传感器1011和复位电路1012输出的电压起缓冲作用，并将缓冲后的电压输出至第一晶体管1013。
第一晶体管1013与第一源跟随器1017电连接，第一晶体管1013与第二电容1016电连接，第一晶体管1013与第二晶体管1014电连接。第一晶体管1013用于控制第一源跟随器1017(也就是光电传感器1011和复位电路1012)与第二电容1016和第二晶体管1014之间电路的导通与关断。可选地，第一晶体管1013可以由M1晶体管组成，该M1晶体管的源极(或漏极)与第一源跟随器1017电连接，该M1晶体管的漏极(或源极)与第二晶体管1014和第二电容1016电连接。该M1晶体管的栅极用于接收控制信号(SS)，该控制信号(SS)用于控制该M1晶体管导通或关断。
第二晶体管1014与第一晶体管1013电连接，第二晶体管1014与第一电容1015电连接，第二晶体管1014与第二源跟随器1018电连接。第二晶体管1014用于控制第一晶体管1013与第一电容1015之间电路之间连接通路的导通或关断。因此，第一晶体管1013和第二晶体管1014共同控制第一源跟随器1017(也就是光电传感器1011和复位电路1012)与第一电容1015之间之间连接通路的导通或关断。可选地，第二晶体管1014可以由M2晶体管组成，该M2晶体管的源极(或漏极)与第一晶体管1013电连接，该M2晶体管的漏极(或源极)与第一电容1015电连接。该M2晶体管的栅极用于接收控制信号(SR)，该控制信号(SR)用于控制该M2晶体管导通或关断。
具体的，下面描述第一晶体管1013、第二晶体管1014、第一电容1015和第二电容1016是如何采集像素电压和复位电压。首先，复位电路1012输出复位电压，第一晶体管1013和第二晶体管1014处于导通状态，第一电容1015和第二电容1016采集该复位电压；其次，光电传感器1011输出光电子，此时，第一晶体管1013处于导通状态，第二晶体管1014处于关断状态，因此，第一电容1015上维持复位电压，第二电容1016在复位电压对应的电子基础上进一步采集光电传感器1011输出的光电子，完成对像素电压的采集。
(2)、判断电路102。
判断电路102具体用于根据光电转换电路101输出的像素电压，确定相关多采样电路1031对像素电压和复位电压的采样次数，该采样次数称为第一采样次数。判断电路102包括阈值电压产生电路1021(threshold voltage generator)、第一电压比较器1022(voltage comparator)和多采样次数选择电路1023(multi-sampling time selection)，其中，第一电压比较器1022与光电转换电路101中的第二源跟随器1018电连接，第一电压比较器1022与阈值电压产生电路1021电连接，第一电压比较器1022与多采样次数选择电路1023电连接，多采样次数选择电路1023与相关多采样电路1031电连接。
阈值电压产生电路1021用于产生一个或多个第一阈值电压，该第一阈值电压输出至第一电压比较器1022。
第一电压比较器1022根据该第一阈值电压与来自光电转换电路101的像素电压进行比较，确定第一电压比较结果。例如，阈值电压产生电路1021产生的第一阈值电压包括0.25伏(V)，0.5V和0.8V。来自光电转换电路101的像素电压为0.45V。第一电压比较器1022首先比较0.25V(第一阈值电压)与0.45V(像素电压)，输出电压比较结果为1(即像素电压大于该第一阈值电压)。然后，比较0.5V(第一阈值电压)与0.45V(像素电压)，输出电压比较结果为0(即像素电压小于该第一阈值电压)。上述电压比较结果统称为第一电压比较结果。第一电压比较器1022中预设多个电压区间，用以确定像素电压所对应的电压区间，每个电压区间预设有对应的采样次数。第一电压比较器1022根据该第一电压比较结果确定像素电压所在的电压区间。第一电压比较器1022中预设的电压区间分别为：第一电压区间0V-0.25V；第二电压区间0.25V-0.5V；第三电压区间0.5V-0.8V；第四电压区间0.8V-1.5V。因此，第一电压比较器1022确定该像素电压处于第二电压区间。第一电压比较器1022将该第一电压比较结果输出至多采样次数选择电路1023。
多采样次数选择电路1023中预设有对应于各个电压区间的采样次数，多采样次数选择 电路1023可根据第一电压比较结果确定第一采样次数，并确定该第一采样次数所对应的相关多采样电路1003的控制时序(control sequences)。多采样次数选择电路1023与相关多采样电路1031电连接，多采样次数选择电路1023确定控制时序后，将该控制时序配置给相关多采样电路1031。例如：第一电压区间0V-0.25V，对应的第一采样次数为6；第二电压区间0.25V-0.5V，对应的第一采样次数为3；第三电压区间0.5V-0.8V，对应的第一采样次数为2；第四电压区间0.8V-1.5V，对应的第一采样次数为1。第一电压比较器1022确定第一电压比较结果为：像素电压0.25V所在的电压区间为第二电压区间。则多采样次数选择电路确定该像素电压对应的第一采样次数为3，并确定该第一采样次数所对应的相关多采样电路1031的控制时序，并将该控制时序配置给相关多采样电路1031。
(3)、第一电路103。
第一电路103包括相关多采样电路1031、第一模数转换器1032(analog-to-digital converter，ADC)和像素处理器1033(pixel processor)，其中，相关多采样电路1031与判断电路102电连接，相关多采样电路1031与第一模数转换器1032电连接，相关多采样电路1031与光电转换电路101电连接，第一模数转换器1032与像素处理器1033电连接，像素处理器1033与判断电路102电连接。
相关多采样电路1031具体用于根据判断电路102输出的第一采样次数，对光电转换电路101输出的像素电压和复位电压进行相关多采样，并向第一模数转换器1032输出第二电压，该第二电压为第一电压的累加和，该第一电压为光电子产生的电压。相关多采样电路1031与第一模数转换器1032电连接。相关多采样电路1031中包括一个或多个开关以及一个或多个电容的电路，相关多采样电路1031用于根据多采样次数选择电路1023所配置的控制时序，对像素电压和复位电压进行相关多采样。具体的，当第一采样次数为1时，相关多采样电路1031对像素电压和复位电压各进行1次采样操作；当第一采样次数为2时，相关多采样电路1031对像素电压和复位电压各进行1次采样操作后，重复前次采样操作，以此类推。
第一模数转换器1032与像素处理器1033电连接，第一模数转换器1032与相关多采样电路1031电连接。模数转换器(analog-to-digital converter，ADC)通常是指一个将模拟信号(电压)转变为数字信号(数字码)的电子元件。本实施例中，第一模数转换器1032与相关多采样电路1031电连接，第一模数转换器1032用于将相关多采样电路1031输出的电信号(电压)转换为数字码(digital encoding)。数字码是一种计算机所用的二进制码，如“0101001”，用来表示信号的大小。第一模数转换器1032通过将电压这类的模拟信号转换为数字码，以便后续像素处理器1033进行处理。
可选的，一、相关多采样电路1031既可以对像素电压进行相关多采样操作后，在像素电压的基础上对复位电压进行相关多采样操作；二、也可以对像素电压进行相关多采样操作后，向第一模数转换器输出该像素电压的累加和，并且相关多采样电路1031进行复位操作，然后再对光电转换电路101输出的复位电压进行相关多采样操作。下面展开说明。
一、首先，相关多采样电路1031根据控制时序对像素电压和复位电压进行相关多采样得到第二电压，其中，第二电压为像素电压和复位电压经过相关多采样后电压值的累加和， 控制时序由判断电路102根据第一采样次数确定，第二电压为第一电压与第一采样次数乘积；其次，第一模数转换器1032将第二电压转换为第二数字码；再次，由于像素处理器1033与多采样次数选择电路1023电连接，因此像素处理器1033根据来自多采样次数选择电路1023的第一采样次数和来自第一模数转换器1032的第二数字码确定第一数字码，第一数字码为第一电压的数字码。
二、首先，相关多采样电路1031对像素电压经过第一采样次数的相关多采样后，向第一模数转换器1032输出第一像素电压，第一像素电压为相关多采样电路1031对像素电压经过第一采样次数的相关多采样后像素电压的累加和。第一模数转换器1032将第一像素电压转换为第三数字码；其次，相关多采样电路1031进行复位操作，以消除前次对像素电压进行相关多采样所残留的电子。然后，相关多采样电路1031对复位电压经过第一采样次数的相关多采样后，向第一模数转换器1032输出第一复位电压，第一复位电压为相关多采样电路1031对复位电压经过第一采样次数的相关多采样后复位电压的累加和。第一模数转换器1032，将第一复位电压转换为第四数字码；再次，像素处理器1033根据第三数字码和第四数字码确定第二数字码，第二数字码为第二电压对应的数字码，第二电压为像素电压和复位电压经过相关多采样后电压值的累加和；像素处理器1033，根据第二数字码和第一采样次数确定第一数字码，第一数字码为第一电压的数字码。
像素处理器1033具体用于对第一模数转换器1032输出的数字码进行处理，确定第一数字码，该第一数字码为第一电压的数字码，该第一电压为光电子产生的电压。可选的，像素处理器1033还可以对第一数字码(数字信号)进行滤波等后处理。
本申请实施例中，图像读取电路包括光电转换电路、判断电路和第一电路，其中，光电转换电路具体用于向图像读取电路的其它部分输出像素电压和复位电压；判断电路具体用于根据光电转换电路输出的像素电压，确定第一电路对像素电压和复位电压的采样次数，该采样次数称为第一采样次数；第一电路具体用于根据判断电路输出的第一采样次数，对光电转换电路输出的像素电压和复位电压进行相关多采样，以确定第一电压。光电转换电路中第一晶体管与第二电容电连接，第一晶体管与第二晶体管电连接，第二晶体管与第一电容电连接，第一晶体管用于控制光电传感器与第二电容之间连接通路的导通或关断，第一晶体管用于控制复位电路与第二电容之间连接通路的导通或关断，第一晶体管用于控制复位电路与第二晶体管之间连接通路的导通或关断，第二晶体管控制第一电容与第一晶体管之间连接通路的导通或关断。通过上述的光电转换电路，第一电容在第一晶体管和第二晶体管的共同控制下采集复位电压，第二电容在第一晶体管的控制下采集像素电压，使得光电转换电路可以向判断电路(和第一电路)先输出像素电压，以便判断电路根据该像素电压确定第一采样次数，其中，像素电压与光照强度正相关，第一采样次数与像素电压负相关。第一电路包括相关多采样电路、第一模数转换器和像素处理器，其中，相关多采样电路根据第一采样次数对光电转换电路输出的像素电压和复位电压进行相关多采样操作，第一模数转换器对相关多采样电路输出的电压进行转换并确定对应的数字码，像素处理器根据第一采样次数对第一模数转换器输出的数字码进行处理以确定第一电压对应的第一数字码，该第一电压在光电子产生的电压。由于相关多采样电路对像素电压的采样次数(第 一采样次数)由像素电压的电压值确定，因此在较高光强的场景下，光电转换电路输出的像素电压也较高，判断电路根据该较高的像素电压确定较低的第一采样次数，避免相关多采样电路输出的电压超过第一模数转换器的量化范围，提升了图像读取电路输出的图像质量。而在较低光强的场景下，光电转换电路输出的像素电压也较低，判断电路根据该较低的像素电压确定较高的第一采样次数，降低了暗光环境下输出图像的噪点，提升了输出图像的质量，提高了像素的动态范围。
本申请实施例提出的光电转换电路101可以适用于多种拓扑结构的电路。例如，在图2对应的实施例的基础上，请参阅图3，图3为本申请实施例提出的一种光电转换电路的组成结构示意图。本申请实施例提出的光电转换电路101包括M1晶体管、M2晶体管、M3晶体管、M4晶体管、M5晶体管、M6晶体管、M7晶体管、M8晶体管、C1电容、C2电容和光电二极管D。为了便于理解，在图3的基础上请参阅图4，图4为本申请实施例提出的光电转换电路的一种控制时序示意图。图4所示的控制时序为图3所示的光电转换电路101的控制时序。
光电二极管D一端接地、另一端与M5晶体管电连接，光电二极管D用于接收光子并将光子转换为光电子输出，光电二极管D组成光电传感器1011；M5晶体管源极与漏极分别与M3晶体管和光电二极管D电连接，M5晶体管的栅极用于接收控制信号(TX)。该控制信号(TX)用于控制M5晶体管之间连接通路的导通或关断，进而控制光电二极管D输出的光电子。当控制信号(TX)处于高电平时，M5晶体管导通，光电二极管D输出的光电子可流过M5晶体管，转移到FD点，表示曝光开始；当控制信号(TX)处于低电平时，M5晶体管关断，切断光电子的转移路径，光电二极管D产生的光电子不再被FD点收集，表示曝光结束。当光电二极管D产生的光电子转移到FD点时，在FD点累计形成电压。图3中的C FD表示FD点的寄生电容，C FD的电容大小决定了光电子到电压的转换增益(conversion gain，CG)。
M6晶体管组成复位电路1012，M6晶体管的源极(或漏极)分别与FD点和复位电压(VRST)的输入电连接，M6晶体管向FD点输出的电压为复位电压(VRST)，M6晶体管的栅极用于接收控制信号(RST)。该控制信号(RST)用于控制M6晶体管之间连接通路的导通或关断，进而控制复位电压(VRST)。当控制信号(RST)处于高电平时，M6晶体管导通，复位电压(VRST)经由M6晶体管输出至FD点，使得FD点的电压复位至VRST，消除上一次曝光时收集的光电子；当控制信号(RST)处于低电平时，M6晶体管关断，复位电压(VRST)不再影响FD点。
M3晶体管为源跟随管，M4晶体管为尾电流管，M3晶体管与M4晶体管组成第一源跟随器1017，其中，M3晶体管的栅极与FD点电连接，M3晶体管的源极与漏极分别与电源电压(VDD)和M4晶体管的源极(或漏极)电连接，M4晶体管的漏极(或源极)的另一端接地，M4晶体管的栅极接入偏置电流(bias current，IBIAS)。M3晶体管与M4晶体管共同组成的第一源跟随器1017，用于隔开FD点与后续的电容(C1电容和C2电容)，使得FD点与后续的电容(C1电容和C2电容)互不干扰，光电转换电路101中可使用电容值较大的电容(C1电容和C2电容)以减小电容的开关热噪声(KT/C噪声)，并且，可尽量减小FD点的C FD寄生电容的电容值，进而提升转换增益。光电转换电路101中，光电二极管D在接收相同光 照强度的前提下，提升转换增益可以提升所产生的像素电压，进而提升应用该光电转换电路101的图像传感器的信噪比(signal noise rotio，SNR)。
M1晶体管组成第一晶体管1013，M1晶体管源极(或漏极)与第一源跟随器1017(M3晶体管和M4晶体管)电连接，M1晶体管的漏极(或源极)与M2晶体管、C2电容和M7晶体管电连接，M1晶体管的栅极用于接收控制信号(SS)。该控制信号(SS)用于控制M1晶体管之间连接通路的导通或关断。当控制信号(SS)处于高电平时，M1晶体管导通，来自第一源跟随器1017的电压经由M1晶体管输入后续其它元器件(M2晶体管、C2电容和M7晶体管)；当控制信号(SS)处于低电平时，M1晶体管关断。
M2晶体管组成第二晶体管1014，M2晶体管的源极或栅极与M1晶体管电连接，M2晶体管的漏极(或源极)与C1电容电连接，M2晶体管的栅极用于接收控制信号(SR)，该控制信号(SR)用于控制M2晶体管之间连接通路的导通或关断。当控制信号(SR)处于高电平时，M2晶体管导通，来自M1晶体管的电压经由M2晶体管输入C1电容；当控制信号(SR)处于低电平时，M2晶体管关断。
C1电容的一端与M2晶体管的源极(或漏极)电连接，另一端接地，C1电容组成第一电容1015，C1电容用于采集复位电压。
C2电容的一端与M7晶体管的栅极电连接，另一端接地，C2电容组成第二电容1016，C2电容用于采集像素电压。
M7晶体管配合尾电流(图中未示出)组成第二源跟随器1018，M7晶体管与M3晶体管类似，M7晶体管的源极(或漏极)接收电源电压(VDD)，M7晶体管的漏极(或源极)与M8晶体管电连接。M7晶体管用于放大C1电容输出的复位电压与C2电容输出的像素电压。
M8晶体管的源极(或漏极)与M7晶体管电连接，M8晶体管的漏极与源极后续的其它电路(如判断电路102和相关多采样电路1031)电连接，M8晶体管的栅极用于接收控制信号(SEL)，该控制信号(SEL)用于控制M8晶体管之间连接通路的导通或关断，当控制信号(SEL)处于高电平时，M8晶体管导通，像素电压或复位电压经由M7晶体管和M8晶体管输出至其它电路；当控制信号(SEL)处于低电平时，M8晶体管关断。
下面对图4所示的控制时序进行详细说明。具体的，图4所示的控制时序，是本申请提出的图像传感器(该图像传感器中应用图3所示的光电转换电路101)使用全局快门模式进行曝光时，光电转换电路101的控制时序。需要说明的是，图4所示的控制时序仅是一种示例性说明，根据实际光电转换电路101各个元件组成的不同，存在不同的控制时序，此处不作限定。
图像传感器进行曝光时，像素的工作时间主要分为全局快门(Global shutter)时间段和列读出(Column Readout)时间段。
在全局曝光时间段中，首先，在像素进行曝光前，控制RST信号从低电平至高电平，进而控制M6晶体管导通，将FD点进行复位。同时，控制TX信号从低电平至高电平，可对光电二极管D进行复位。复位时M6晶体管等效为一个电阻，FD点电压将缓慢上升并最终被复位到VRST。经过预设的复位时间后，例如100纳秒-5微秒，控制RST信号和TX信号从高电平至低电平，此时M6晶体管将断开，FD点维持在VRST电压。
由于工作在导通状态的晶体管存在热噪声电流，M6晶体管所产生的热噪声电流在FD点形成热噪声电压，也称为KT/C噪声。当M6晶体管拉低时，该热噪声电压也留存在FD点上，也称为复位噪声。由于噪声的随机性，每次复位时FD点上的噪声均不相同，即每次复位后，FD点电压均有微小的差异，表现为图像上的噪点。根据KT/C噪声的公式，FD点电容越小，热噪声电压越大。随着像素尺寸的缩小，FD点电容也随着变小，因此复位噪声随着变大，为了提高图像的质量需要将复位噪声进行消除。其具体实现方法是，将复位电压随复位噪声一起存储下来，并在后续某个时间点将其读出，与像素电压进行相减，从而将噪声消除。在本实施例中，FD点的复位电压通过M3晶体管和M4晶体管形成的第一源跟随器1017，传输到M1晶体管的一端。同时，控制SR信号和SS信号从低电平至高电平，M1和M2晶体管均导通，此时电容C1上极板电压跟随FD点电压变化。当像素复位完成后，控制SR信号从高电平至低电平，此时复位电压及其复位噪声将保留在电容C1上，即完成了复位电压的存储，用VRST表示。然后，控制TX信号从低电平至高电平，此时M5晶体管导通，光电二极管D产生的电子通过M5晶体管流向FD点，由于电子为负电荷，将导致FD点电压下降。FD点电压下降的量等于光电二极管D产生的电子数量乘以转换增益，与光电二极管D接收到的光强成线性关系。像素曝光结束后，将控制TX信号从高电平至低电平，M5晶体管关断，此时FD点的电压不再变化。待电压稳定后，控制SS信号从高电平至低电平，此时像素电压将保留在电容C2上，即完成像素电压的存储，用VSIG表示。光电子实际产生的电压值就是复位电压与像素电压相减的差值，即VRST-VSIG。
在列读出时间段中，列读出电路(包括本申请提出的判断电路102和第一电路103)完成像素内电信号的读出和量化。首先，控制SEL信号从低电平至高电平，此时M7晶体管与尾电流形成的第二源跟随器1018，光电转换电路101输出的电压跟随M7晶体管的栅极电压的变化。由于电容C2上极板与M7晶体管的栅极直接相连，且此时上极板电压为采样到的像素电压，因此像素电压VSIG被读出。在列读出电路完成像素电压VSIG的采样后，控制SR信号从低电平至高电平，此时M2晶体管导通，C1电容和C2电容形成电荷共享。由于C2电容的上极板电压为像素电压，C1电容的上极板电压为复位电压。而C1电容上采集的像素电压是复位电压的基础上光电子所产生电压的累加和，因此最终像素电压减去复位电压所得到的第一电压(光电子所对应的电压)可成功消除复位噪声。
本申请实施例提出的判断电路102和相关多采样电路1031可以适用于多种拓扑结构的电路。例如，在图2至图3对应的实施例的基础上，请参阅图5，图5为本申请实施例提出的一种图像读取电路的组成结构示意图。本申请实施例提出的图像读取电路100包括光电转换电路101(图5中光电转换电路101的其它部分未示出)、判断电路102和第一电路103，其中，判断电路102中包括阈值电压产生电路1021、第一电压比较器1022、多采样次数选择电路1023和S5开关，第一电路103包括相关多采样电路1031、第一模数转换器1032和像素处理器1033(图5中未示出)，相关多采样电路1031包括S1开关、S2开关、S3开关、S4开关、Cin电容、Cf电容、开关AZ、运算放大器(operational amplifier，AMP)和SH开关。
具体的，相关多采样电路1031中S1开关的一端与M8晶体管的源极(或漏极)电连接， S1开关的另一端与Cin电容电连接。S3开关与S4开关并联在Cin电容两端，S3开关和S4开关的另一端接入参考电压(Vcom)并与运算放大器的输入端电连接。Cin电容与S4开关电连接的一端与S2开关电连接，S2开关的另一端与运算放大器的输入端电连接。需要说明的是，S2开关的输出既可以与运算放大器的同相输入端电连接(此时S3开关和S4开关的输出与运算放大器的反相输入端电连接)，也可以与运算放大器的反相输入端电连接(此时S3开关和S4开关的输出与运算放大器的同相输入端电连接)，此处不作限定。运算放大器具体可以是：通用型运算放大器、可编程控制运算放大器、高阻型运算放大器或低功耗型运算放大器等，此处不作限定。在运算放大器的输入端和输出端两端并联Cf电容，在Cf电容的两端并联AZ开关。SH开关的一端与运算放大器的输出端电连接，SH开关的另一端与第一模数转换器1032电连接，第一模数转换器1032的输出端与像素处理器1033(图5中未示出)电连接。
判断电路102中阈值电压产生电路1021的输出端与第一电压比较器1022的输入端电连接，第一电压比较器1022的另一输入端与S5开关电连接，可选的，阈值电压产生电路1021与第一电压比较器1022的同相输入端电连接，此时S5开关与第一电压比较器1022的反相输入端电连接；或者，阈值电压产生电路1021与第一电压比较器1022的反相输入端电连接，此时S5开关与第一电压比较器1022的同相输入端电连接。S5开关的另一端与光电转换电路101的输出端(即M8晶体管的源极或漏极)电连接。第一电压比较器1022的输出端与多采样次数选择电路1023电连接，多采样次数选择电路1023的输出端与相关多采样电路1031电连接，并向相关多采样电路1031输出控制时序。
为了便于理解，下面结合图6说明图5中各个元器件之间的工作关系，图6为本申请实施例提出的图像读取电路的一种控制时序示意图。首先，控制SEL信号从低电平至高电平，表示该像素被选通。在t0-t1时间段，进行自动调零，具体的：控制AZ信号从低电平至高电平，使AZ开关闭合，运算放大器输出与反相输入端相连，形成单元增益负反馈。Cf电容两端相连，将上一次读出所存储的电荷进行清零，保证下一次读出不受影响。可选的，在自动调零过程中，运算放大器的反相输入端存储补偿值(offset)，该补偿值用于补偿运算放大器生产时因器件失配所存在的误差。
自动调零结束后，控制AZ信号从高电平至低电平，AZ开关断开。然后，判断电路102的S5开关导通，第一电压比较器1022与光电转换电路101之间导通，第一电压比较器1022对M8晶体管输出的像素电压进行采样。阈值电压产生电路1021分时产生一个或多个第一阈值电压，第一电压比较器1022使用该第一阈值电压与像素电压进行多次比较，确定第一电压比较结果，并根据第一电压比较结果确定像素电压所属的电压大小范围。
多采样次数选择电路1023(multi-sampling time selection)根据第一电压比较结果确定该像素电压所对应的第一采样次数。多采样次数选择电路1023根据第一采样次数确定相关多采样电路1031的控制时序，该控制时序用于控制相关多采样电路1031对光电转换电路101的输出(像素电压和复位电压)进行相关多采样操作操作，可选的，该相关多采样操作包括自适应相关多采样操作(adaptive correlated multiple sampling，Adaptive-CMS)。
在t1–t2时间段，相关多采样电路1031进行一次像素电压采样及累加。具体的累加过程如下：首先，S1开关和S4开关导通，对像素电压进行采样，此时C in电容上的电荷等于：
Q in  0＝C in(V com-V SIG)；
其中，Q in  0为C in电容上的电荷,V com为参考电压(也称共模电压)，V SIG为像素电压，C in为C in电容的电容值。
当C in电容的电压稳定(例如，10纳秒内C in电容的电压值变化小于0.1毫伏，此处仅做示例性说明，不对实际电压稳定的判断标准进行限定)后，将S1开关和S4开关断开，然后将S2开关和S3开关导通，此时：
Q total＝Q in  1+Q f1＝C in(V --V com)+C f(V --V o,t2)；
其中，Q total为相关多采样电路1031的总电荷量，Q in  1为t2时刻Cin电容的电荷量，Q f1为t2时刻Cf电容的电荷量，V -为运算放大器反相输入端电压值，V com为参考电压，V o,t2为运算放大器输出端的电压值(即Cf电容下极板的电压值)，C in为C in电容的电容值，C f为C f电容的电容值。
由于运算放大器的负反馈作用，其同相输入端和反相输入端的电压将趋于相等，即：V -＝V +＝V com。代入上式，有：
Q total＝C in(V com-V com)+C f(V com-V o,t2)＝C f(V com-V o,t2)；
根据电荷守恒原理，Q total＝Q in  0+Q f0＝Q in  0，可得到：
C in(V com-V SIG)＝C f(V com-V o,t2)；
因此，在t2时刻，运算放大器的输出电压等于：
V o,t2＝V com-C in/C f(V com-V SIG)；
注意到，C in电容表示输入采样电容，C f电容表示反馈电容，其比值C in/C f可确定相关多采样电路1031的增益。以增益为1(即C in/C f＝1)为例，即令C in＝C f，可得t2时刻运算放大器的输出电压为：
V o,t2＝V com+(V SIG-V com)；
t2–t3时间段表示相关多采样电路1031重复t1–t2过程，重复对像素电压进行采样及累积。该重复次数等于第一采样次数(M)，例如，第一采样次数为2，那么在t1–t2基础上，需要再进行一次采样。同样地，首先，S1开关和S4开关导通，对像素电压进行采样，此时C in电容上的电荷等于：Q in  2＝C in(V com-V SIG)。注意到，在t2时刻，C f电容上存在电荷：Q f2＝C f(V com-V SIG)。因此相关多采样电路1031总电荷为：
Q total＝Q in  2+Q f2＝C in(V com-V SIG)+C f(V com-V SIG)；
同样地，当C in电容的电压稳定后，将S1开关和S4开关断开，然后将S2开关和S3开关导通，此时：
Q total＝Q in  3+Q f3＝C in(V com-V com)+C f(V com-V o,t3)＝C f(V com-V o,t3)；
根据电荷守恒原理，可得到：
C in(V com-V SIG)+C f(V com-V SIG)＝C f(V com-V o,t3)；
因此，t3时刻，运算放大器的输出电压等于：
V o,t3＝V com+2(V SIG-V com)；
根据上式可知道，随着相关多采样电路1031每进行一次多采样，将在其输出叠加一个ΔV＝V SIG-V com的量，相当于将每次C in上采样到的电压差转移到运算放大器输出进行累加。由此可推导，当第一采样次数为M时，在t3时刻，运算放大器的输出电压为：
V o,t3＝M(V SIG-V com)+V com；
t3–t4时间段，控制SR信号从低电平至高电平，表示光电转换电路101将储存的复位电压输出，此时M8晶体管输出电压由VSIG变为VRST。t4–t5时间段内，相关多采样电路1031进行一次复位电压采样及减法操作。首先S1开关导通，此时C in电容的上极板电压等于VRST，此时总电荷可表示为：
Q total＝Q in+Q f＝C in(V com-V RST)+C f(V com-V o,t5)；
在t3时刻，电容上的总电荷等于Q f＝C f(V com-V o,t3)，根据电荷守恒原理，可得：
C f(V com-V o,t3)＝C in(V com-V RST)+C f(V com-V o,t5)；
即可推导出：V o,t5＝V o,t3-(V RST-V com)。
然后在t5时刻，S1开关和S2开关都断开，同时S3开关和S4开关导通，将C in电容上的电荷清空。在t5–t6时间，相关多采样电路1031重复t4–t5过程，重复对复位电压进行采样及累减。该重复次数为第一采样次数(M)。同样地，假设第一采样次数为2，那么在t4–t5基础上，需要再进行一次采样。首先S1开关和S2开关导通，使C in电容上极板电压等于VRST，此时总电荷可表示为：
Q total＝Q in+Q f＝C in(V com-V RST)+C f(V com-V o,t6)；
在t5时刻，电容上的总电荷等于Q f＝C f(V com-V o,t5)，根据电荷守恒原理，可得：
C f(V com-V o,t5)＝C in(V com-V RST)+C f(V com-V o,t6)；
即可推导出：V o,t6＝V o,t5-(V RST-V com)＝V o,t3-2(V RST-V com)。
根据上式可知道，随着相关多采样电路1031每进行一次多采样，将在其输出减去一个ΔV＝V RST-V com的量，相当于将每次C in上的电荷泄放到地端。由此可推导，当第一采样次数为M时，在t6时刻，运算放大器的输出电压为：
V o,t6＝V o,t3-M(V RST-V com)；
根据前面关于t1–t3的时间段的推导，可知在t3时刻运算放大器的输出电压等于V o,t3＝M(V SIG-V com)+V com，代入上式即可得：
V o,t6＝V com-M(V RST-V SIG)；
时间段t6–t7表示第一模数转换器1032(ADC)对相关多采样电路1031中运算放大器的输出电压进行采样，SH开关导通。t7时刻后第一模数转换器1032将对多次采样后的电压值进行量化，得到相应的数字码。由V o,t6的表达式可知，由于参考电压V com是一个固定量，与光强大小无关，因此运算放大器输出的电压值减去该参考电压后，等于复位电压与像素电压的差值乘以第一采样次数，可有效降低随机噪声。
本申请实施例中，相关多采样电路1031对光电转换电路101输出的电压进行相关多采样的仿真示意图，请参阅图7，图7为本申请实施例涉及的一种仿真实验示意图。图7中，Vo_amp为相关多采样电路1031中运算放大器的输出电压，由图7可知，由于相关多采样电路对像素电压(和复位电压)的采样次数(第一采样次数)由像素电压的电压值确定，因此在较高光强的场景下，光电转换电路输出的像素电压也较高，判断电路根据该较高的像素电压确定较低的第一采样次数，避免相关多采样电路输出的电压超过第一模数转换器的量化范围；而在较低光强的场景下，光电转换电路输出的像素电压也较低，判断电路根据该较低的像素电压确定较高的第一采样次数，采样次数不受像素满肼容量的限制。无论是高光强还是低光强的场景，Vo_amp都不会超过模数转换器(ADC)的量化范围，因此，可有效降低暗光环境下输出图像的噪点，提升了输出图像的质量，提高了像素的动态范围。
可选的，请参阅图8，图8为本申请实施例中图像读取电路的另一种组成结构示意图。在图5所示的图像读取电路的基础上，判断电路102还包括：S6开关、AZ1开关、C3电容和C4电容，其中，C3电容的两端分别与S5开关和第一电压比较器电连接，S6开关的一端与阈值电压产生电路电连接，另一端与C4电容的一端电连接，C4电容的另一端与第一电压比较器电连接。第一电压比较器的正相输入端和反相输入端分别与AZ1开关电连接，该AZ1开关的另一端用于接入参考电压Vcom2。
为了便于理解，与图8所示图像读取电路对应的，请参阅图9，图9为本申请实施例提出的图像读取电路的另一种控制时序示意图。在判断电路102对像素电压进行检测之前(t0-t1时间段)，控制AZ1信号从低电平至高电平，AZ1开关导通。控制S5信号与S6信号为低电平，S5开关和S6开关断开，使得第一电压比较器1022进行自动调零，具体的：第一电压比较器1022正相输入端与反相输入端输入参考电压(Vcom2)，若第一电压比较器1022确定的两端电压值不一致，则第一电压比较器1022出现误差，该误差至与电压值的差值一致。第一电压比较器1022使用该电压差值消除误差，以提升第一电压比较器的准确性。
当光电转换电路101输出像素电压时(t1-t2时间段)，控制S5信号与S6信号从低电平至高电平，S5开关和S6开关导通，C3电容采集像素电压，C4电容采集第一阈值电压。由于电容具有隔绝直流电的功能，因此，C3电容与C4电容可用于保护第一电压比较器1022，并且，第一电压比较器1022在使用较低的第一阈值电压和电源电压的情况下，也可以确定 像素电压所在的电压值区间，以降低图像读取电路的功耗。
本申请实施例中，第一电压比较器使用自动调零时测量得到的电压差值消除误差，以提升第一电压比较器的准确性。在第一电压比较器与阈值电压产生电路和光电转换电路之间设置电容，在保护该第一电压比较器的同时，第一电压比较器在使用较低的第一阈值电压和电源电压的情况下，也可以确定像素电压所在的电压值区间，降低了图像读取电路的功耗。
可选的，请参阅图10，图10为本申请实施例中图像读取电路的另一种组成结构示意图。在图8所示的图像读取电路的基础上，判断电路102中还可以包括第二电压比较器，该第二电压比较器的数量为一个或多个，该第二电压比较器的用途与第一电压比较器1022类似。具体的，该判断电路102还包括：S7开关、S8开关、C5电容和C6电容，其中，C5电容的两端分别与S7开关和第二电压比较器电连接，S8开关的一端与阈值电压产生电路电连接，另一端与C6电容的一端电连接，C6电容的另一端与第二电压比较器电连接。第二电压比较器的正相输入端和反相输入端分别与AZ1开关电连接，该AZ1开关的另一端用于接入参考电压Vcom2。
具体的，第二电压比较器，用于根据第二阈值电压与像素电压确定第二电压比较结果，第二阈值电压由阈值电压产生电路产生；多采样次数选择电路，还用于根据第一电压比较结果和第二电压比较结果确定第一采样次数。
本申请实施例中，通过在判断电路中设置一个或多个第二电压比较器，判断电路可以同时将像素电压域与多个阈值电压(第二阈值电压)进行比较，确定像素电压的电压比较结果(第二电压比较结果)的速度大大增快，因此能有效提高像素图像读取的速度。
可选的，请参阅图11，图11为本申请实施例中图像读取电路的另一种组成结构示意图。在图8所示的图像读取电路的基础上，第一电路103还可以使用多个模数转换器对电压进行处理。具体的，第一电路103还包括SHR开关、CSHR电容、SHS开关、CSHS电容和第二模数转换器，其中，运算放大器(AMP)的输出端分别与SHR开关的一端和SHS开关的一端电连接，SHR开关的另一端与CSHR电容和第一模数转换器电连接，SHS开关的另一端与CSHS电容和第二模数转换器电连接。
为了便于理解，与图11所示图像读取电路对应的，请参阅图12，图12为本申请实施例提出的图像读取电路的另一种控制时序示意图。
在t0–t1时间段，图像读取电路100中的判断电路102采集像素电压，并根据该像素电压确定第一采样次数。然后，在t1–t3时间段，第一电路103中的相关多采样电路1031通过控制S1开关、S2开关、S3开关和S4开关对像素电压进行相关多采样得到第一像素电压，具体的，与前述实施例的描述类似此处不再赘述。
在t3–t4时间段，SHS开关导通，将第一像素电压(像素电压的累加和)采样到CSHS电容上，并输出到后端的第二模数转换器进行量化，得到的数字码称为第三数字码。
在t3–t4时间段，光电转换电路101中的SR开关(图中未示出)导通，光电转换电 路101向相关多采样电路1031输出复位电压。
在t3–t4时间段，将像素电压的累加和采样到CSHS电容之后，断开SHS开关(此时SHR开关同样处于断开状态)，控制AZ信号从低电平至高电平，AZ开关导通，对运算放大器进行自动调零。
在t4–t6时间段，S1开关、S2开关、S3开关和S4开关的控制时序与t1–t3时间段中上述开关的控制时序类似，相关多采样电路1031完成复位电压的相关多采样，得到第一复位电压。
在t6–t7时间段，SHR开关导通，将第一复位电压(复位电压的累加和)采样到CSHR电容上，并输出到后端的第一模数转换器进行量化，得到的数字码称为第四数字码。
最后，像素处理器(图中未示出)对第一模数转换器和第二模数转换器输出的数字码进行处理，具体的，将第三数字码与第四数字码进行相减操作得到第二数字码，第二数字码为第二电压对应的数字码，第二电压为像素电压经过相关多采样后的累加和，与复位电压经过相关多采样后的累加和的差值。像素处理器，根据第二数字码与第一采样次数确定第一数字码，该第一数字码为第一电压对应的数字码。具体的，第二数字码除以第一采样次数得到第一数字码。
需要说明的是，本申请实施例中第一模数转换器与第二模数转换器既可以是不同的模数转换器，也可以是同一个模数转换器，当第一模数转换器与第二模数转换器属于同一个模数转换器时，该模数转换器分别执行本实施例中第一模数转换器与第二模数转换器执行的步骤，此处不作限定。
本申请实施例中，第一电路中的模数转换器，分别将像素电压的累加和和复位电压的累加和量化为数字码后，再进行相减操作。通过数字域上的操作，将模数转换器所产生的系统误差进行消除，从而改善图像读取电路(以及应用该图像读取电路的图像传感器)的固定模式误差(fixed pattern noise，FPN)。
可选的，图10所示的判断电路、图11所示的第一电路以及图3所示的光电转换电路可以组成另一种图像读取电路，该图像读取电路的具体连接结构与工作方式与前述实施例描述的内容类似，此处不再赘述。
另一方面，前述实施例描述的图像读取电路，可以应用于图像传感器中，该图像传感器是一类利用互补式金属氧化物半导体(complementary metal oxide semiconductor，CMOS)工艺制造的CMOS图像传感器(complementary metal oxide semiconductor image sensor，CIS)。具体的，下面以该图像传感器为飞行时间传感器为例进行介绍。请参阅图13，图13为本申请实施例提出的一种飞行时间传感器的结构示意图。飞行时间传感器(time-of-flight，ToF)是一种通过探测光从摄像头发出后经待测物体反射，直到被摄像头接收的飞行时间，并结合光速来计算物体深度的一种图像传感器。该飞行时间传感器包括像素阵列(pixels array)，列读出电路(column readout)、后处理电路(post-processing)、时序控制器(sequencer)和调制驱动器(modulation driver)等。飞行时间传感器首先利用时序控制器产生特定的调制脉冲，并通过调制驱动器对像素阵列 进行控制。同时，另一路信号通过板级的激光器驱动芯片驱动外部激光器发出调制光信号，调制光信号经被测物体反射后，经过镜头聚焦于飞行时间传感器的像素阵列。像素将接收到光信号转换为电信号，而列读出电路和后处理单元对各像素电信号进行量化和处理后，可得到每一个像素接受到的光路的飞行时间。最后，通过其他后处理算法，便可得到物体的完整深度信息。
由于飞行时间传感器需要主动发射光脉冲信号，根据飞行时间探测的原理，要求所有像素需要在同样的时间进行光子接收，以保证像素阵列的一致性，因此飞行时间传感器常采用全局快门的曝光模式。另外，对于高速运动的物体，全局快门模式可避免出现严重的运动伪影问题。另外，为了降低实际探测深度的误差，要求芯片能精确地量化接收的光能量，并降低噪声。因此，低噪声也是一个重要的设计要求。
而本申请提出的图像读取电路，由于相关多采样电路对像素电压的采样次数(第一采样次数)由像素电压的电压值确定，因此在较高光强的场景下，光电转换电路输出的像素电压也较高，判断电路根据该较高的像素电压确定较低的第一采样次数，避免相关多采样电路输出的电压超过第一模数转换器的量化范围，提升了图像读取电路输出的图像质量。而在较低光强的场景下，光电转换电路输出的像素电压也较低，判断电路根据该较低的像素电压确定较高的第一采样次数，降低了暗光环境下输出图像的噪点，提升了输出图像的质量，提高了像素的动态范围。当本申请提出的图像读取电路应用于该飞行时间传感器中，可以充分满足飞行时间传感器的设计要求，提升了飞行时间传感器的输出图像质量。
另一方面，请参阅图14，图14为本申请实施例中一种图像撷取光学系统的结构示意图。在本实施例中，图像撷取光学系统1400包含成像镜头组1401、驱动装置1402、图像传感器1403以及图像稳定模块1404。图像传感器1403包括上述任一实施例中的图像读取电路。图像撷取光学系统1400利用镜头组1401聚光产生图像，并配合驱动装置1402进行图像对焦，最后成像于图像传感器1403并且能作为图像资料输出。
驱动装置1402可具有自动对焦(auto-focus)功能，其驱动方式可使用如音圈马达(voice coil motor，VCM)、微机电系统(micro electro-mechanical systems，MEMS)、压电系统(piezoelectric)、以及记忆金属(shape memory alloy)等驱动系统。驱动装置1402可让镜头组1401取得较佳的成像位置，可提供被摄物于不同物距的状态下，皆能拍摄清晰图像。
此外，图像撷取光学系统1400搭载感光度佳及低杂讯的图像传感器1403，例如，互补式金属氧化物半导体(complementary metal-oxide-semiconductor，CMOS)感光器件等。图像传感器1403设置于镜头组的像面，可真实呈现镜头组的良好成像品质。
图像稳定模块1404例如为加速计、陀螺仪或霍尔元件(Hall Effect Sensor)。驱动装置1402可搭配图像稳定模块1404而共同作为光学防抖装置(optical image stabilization，OIS)，通过调整镜头组1401不同轴向的变化以补偿拍摄瞬间因晃动而产生的模糊图像，或利用图像软件中的图像补偿技术，来提供电子防抖功能(electronic image stabilization，EIS)，进一步提升动态以及低照度场景拍摄的成像品质。
请参照图15以及图16，图15为本申请实施例中一种终端设备示意图，图16为本申请实施例中另一种终端设备示意图。在本实施例中，终端设备20为智能手机。终端设备20包含图像撷取光学系统1400、闪光灯模块21、对焦辅助模块22、图像信号处理器23(image signal processor)、使用者界面24以及图像软件处理器25。上述终端设备20以包含一个图像撷取光学系统1400为例，但本实施例并不以此为限。终端设备20可包含多个图像撷取光学系统1400，或是除了图像撷取光学系统1400之外再进一步包含其他图像撷取光学系统。
当使用者经由使用者界面24拍摄物体(被摄物)时，终端设备20利用图像撷取光学系统1400聚光取像，启动闪光灯模块21进行补光，并使用对焦辅助模块22提供的被摄物的物距信息进行快速对焦，再加上图像信号处理器23进行图像优化处理，来进一步提升摄像系统镜头组所产生的图像品质。对焦辅助模块22可采用红外线或激光对焦辅助系统来达到快速对焦。
使用者界面24可采用触控屏幕或实体拍摄按钮，配合图像软件处理器25的多样化功能进行图像拍摄以及图像处理。
本申请的图像撷取光学系统1400并不以应用于智能手机为限。图像撷取光学系统1400更可视需求应用于移动对焦的系统，并兼具优良像差修正与良好成像品质的特色。举例来说，图像撷取光学系统1400可多方面应用于三维(3D)图像撷取、数码相机、移动装置、平板计算机、智能电视、网络监控设备、行车记录器、倒车显影装置、多镜头装置、辨识系统、体感游戏机与穿戴式装置等终端设备中。本实施例所公开的终端设备中仅是示范性地说明本申请的实际运用例子，并非限制本申请的图像撷取光学系统的运用范围。
基于前述图1-图11的图像读取电路，本申请还提出了一种图像读取电路的图像读取方法，该方法应用于图像读取电路1400中，具体的，请参阅图17，图17为本申请实施例中一种图像读取方法的实施例流程示意图。
步骤1701、采集复位电压。复位电路1012输出复位电压，第一晶体管1013和第二晶体管1014处于导通状态，第一电容1015和第二电容1016采集该复位电压。
步骤1702、采集像素电压。光电传感器1011输出光电子，此时，第一晶体管1013处于导通状态，第二晶体管1014处于关断状态，因此，第一电容1015上维持复位电压，第二电容1016在复位电压对应的电子基础上进一步采集光电传感器1011输出的光电子，完成对像素电压的采集。
步骤1703、根据像素电压确定第一采样次数。阈值电压产生电路1021用于产生一个或多个第一阈值电压，该第一阈值电压输出至第一电压比较器1022。第一电压比较器1022根据该第一阈值电压与来自光电转换电路101的像素电压进行比较，确定第一电压比较结果。多采样次数选择电路1023中预设有对应于各个电压区间的采样次数，多采样次数选择电路1023可根据第一电压比较结果确定第一采样次数，并确定该第一采样次数所对应的相关多采样电路1003的控制时序(control sequences)。
步骤1704、根据第一采样次数对像素电压和复位电压进行相关多采样以确定第一电压。
相关多采样电路1031具体用于根据判断电路102输出的第一采样次数，对光电转换电 路101输出的像素电压和复位电压进行相关多采样，并向第一模数转换器1032输出第二电压，该第二电压为第一电压的累加和，该第一电压为光电子产生的电压。相关多采样电路1031与第一模数转换器1032电连接。相关多采样电路1031中包括一个或多个开关以及一个或多个电容的电路，相关多采样电路1031用于根据多采样次数选择电路1023所配置的控制时序，对像素电压和复位电压进行相关多采样。具体的，当第一采样次数为1时，相关多采样电路1031对像素电压和复位电压各进行1次采样操作；当第一采样次数为2时，相关多采样电路1031对像素电压和复位电压各进行1次采样操作后，重复前次采样操作，以此类推。
可选的，相关多采样电路1031根据控制时序对像素电压和复位电压进行相关多采样得到第二电压，其中，第二电压为像素电压和复位电压经过相关多采样后电压值的累加和，控制时序由判断电路102根据第一采样次数确定，第二电压为第一电压与第一采样次数乘积；其次，第一模数转换器1032将第二电压转换为第二数字码；再次，由于像素处理器1033与多采样次数选择电路1023电连接，因此像素处理器1033根据来自多采样次数选择电路1023的第一采样次数和来自第一模数转换器1032的第二数字码确定第一数字码，第一数字码为第一电压的数字码。
可选的，相关多采样电路1031对像素电压经过第一采样次数的相关多采样后，向第一模数转换器1032输出第一像素电压，第一像素电压为相关多采样电路1031对像素电压经过第一采样次数的相关多采样后像素电压的累加和。第一模数转换器1032将第一像素电压转换为第三数字码；其次，相关多采样电路1031进行复位操作，以消除前次对像素电压进行相关多采样所残留的电子。然后，相关多采样电路1031对复位电压经过第一采样次数的相关多采样后，向第一模数转换器1032输出第一复位电压，第一复位电压为相关多采样电路1031对复位电压经过第一采样次数的相关多采样后复位电压的累加和。第一模数转换器1032，将第一复位电压转换为第四数字码；再次，像素处理器1033根据第三数字码和第四数字码确定第二数字码，第二数字码为第二电压对应的数字码，第二电压为像素电压经过相关多采样后的累加和与复位电压经过相关多采样后的累加和的差值；像素处理器1033，根据第二数字码和第一采样次数确定第一数字码，第一数字码为第一电压的数字码。
本申请实施例中，由于相关多采样电路对像素电压的采样次数(第一采样次数)由像素电压的电压值确定，因此在较高光强的场景下，光电转换电路输出的像素电压也较高，判断电路根据该较高的像素电压确定较低的第一采样次数，避免相关多采样电路输出的电压超过第一模数转换器的量化范围，提升了图像读取电路输出的图像质量。而在较低光强的场景下，光电转换电路输出的像素电压也较低，判断电路根据该较低的像素电压确定较高的第一采样次数，降低了暗光环境下输出图像的噪点，提升了输出图像的质量，提高了像素的动态范围。
在图17所示实施例的基础上，根据该像素电压确定该第一采样次数，可能包括：产生第一阈值电压；根据该第一阈值电压与该像素电压确定第一电压比较结果；根据该第一电压比较结果确定该第一采样次数。
具体的，根据该第一阈值电压与像素电压进行比较，确定第一电压比较结果。例如， 的第一阈值电压包括0.25伏(V)，0.5V和0.8V。像素电压为0.45V。首先比较0.25V(第一阈值电压)与0.45V(像素电压)，输出电压比较结果为1(即像素电压大于该第一阈值电压)。然后，比较0.5V(第一阈值电压)与0.45V(像素电压)，输出电压比较结果为0(即像素电压小于该第一阈值电压)。上述电压比较结果统称为第一电压比较结果。第一电压比较器中预设多个电压区间，用以确定像素电压所对应的电压区间，每个电压区间预设有对应的采样次数。根据该第一电压比较结果确定像素电压所在的电压区间。中预设的电压区间分别为：第一电压区间0V-0.25V；第二电压区间0.25V-0.5V；第三电压区间0.5V-0.8V；第四电压区间0.8V-1.5V。因此，确定该像素电压处于第二电压区间。并根据该电压区间确定第一采样次数。
本申请实施例中，通过确定像素电压所在的电压区间，进而确定该像素电压所对应的第一采样次数。提升了方案的实现灵活性。
在图17所示实施例的基础上，还可能包括：对该像素电压和该复位电压进行相关多采样得到第二电压，其中，该第二电压为该像素电压和该复位电压经过相关多采样后电压值的累加和，该第二电压为该第一电压与该第一采样次数乘积；根据该第二电压转换为第二数字码；根据该第二数字码和该第一采样次数确定第一数字码，该第一数字码为该第一电压的数字码。
具体的，首先，对像素电压和复位电压进行相关多采样得到第二电压，其中，第二电压为像素电压和复位电压经过相关多采样后电压值的累加和，第二电压为第一电压与第一采样次数乘积；其次，将第二电压转换为第二数字码；再次，根据第一采样次数和第二数字码确定第一数字码，第一数字码为第一电压的数字码。
本申请实施例中，通过将电压转换为数字码，以便后续像素处理器和其它元件的进一步处理。
在图17所示实施例的基础上，还可能包括：根据第一像素电压转换为第三数字码，该第一像素电压为该像素电压经过该第一采样次数的相关多采样后该像素电压的累加和；根据第一复位电压转换为第四数字码，该第一复位电压为该复位电压经过该第一采样次数的相关多采样后该复位电压的累加和；根据该第三数字码和该第四数字码确定第二数字码，该第二数字码为第二电压对应的数字码，该第二电压为该像素电压和该复位电压经过相关多采样后电压值的累加和；根据该第二数字码和该第一采样次数确定第一数字码，该第一数字码为该第一电压的数字码。
具体的，首先，对像素电压经过第一采样次数的相关多采样后，输出第一像素电压，第一像素电压为像素电压经过第一采样次数的相关多采样后像素电压的累加和。将第一像素电压转换为第三数字码；其次，对复位电压经过第一采样次数的相关多采样后，输出第一复位电压，第一复位电压为对复位电压经过第一采样次数的相关多采样后复位电压的累加和。将第一复位电压转换为第四数字码；再次，根据第三数字码和第四数字码确定第二数字码，第二数字码为第二电压对应的数字码，第二电压为像素电压和复位电压经过相关多采样后电压值的累加和；根据第二数字码和第一采样次数确定第一数字码，第一数字码为第一电压的数字码。
本申请实施例中，分别将像素电压的累加和和复位电压的累加和量化为数字码后，再进行相减操作。通过数字域上的操作，将电压量化为数字码过程中所产生的系统误差进行消除，从而改善固定模式误差(fixed pattern noise，FPN)。
应理解，说明书通篇中提到的“一个实施例”或“一实施例”意味着与实施例有关的特定特征、结构或特性包括在本申请的至少一个实施例中。因此，在整个说明书各处出现的“在一个实施例中”或“在一实施例中”未必一定指相同的实施例。此外，这些特定的特征、结构或特性可以任意适合的方式结合在一个或多个实施例中。应理解，在本申请的各种实施例中，上述各过程的序号的大小并不意味着执行顺序的先后，各过程的执行顺序应以其功能和内在逻辑确定，而不应对本申请实施例的实施过程构成任何限定。
所属领域的技术人员可以清楚地了解到，为了描述的方便和简洁，上述描述的系统、装置和单元的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。
总之，以上所述仅为本申请技术方案的较佳实施例而已，并非用于限定本申请的保护范围。凡在本申请的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本申请的保护范围之内。
以上对本申请所提供的图像读取电路以及部件进行了详细介绍，本文中应用了具体个例对本申请的具体实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的方法及其核心思想；同时，对于本领域的一般技术人员，依据本申请的思想，在具体实施方式及应用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本申请的限制。

Claims (11)

  1. 一种图像读取电路，其特征在于，包括：光电转换电路、判断电路和相关多采样电路；
    所述光电转换电路包括光电传感器和复位电路，所述光电传感器用于接收光子并输出光电子，所述复位电路用于输出复位电压；
    所述光电转换电路，用于采集像素电压，并将所述像素电压分别输出至所述判断电路和所述相关多采样电路；
    所述判断电路，用于根据所述像素电压确定第一采样次数，其中，所述第一采样次数与所述像素电压负相关；
    所述相关多采样电路，用于根据所述第一采样次数对所述像素电压和所述复位电压进行相关多采样以确定第一电压，所述第一电压为光电子产生的电压。
  2. 根据权利要求1所述的图像读取电路，其特征在于，所述光电转换电路还包括：第一晶体管、第二晶体管、第一电容和第二电容，其中，
    所述第一晶体管与所述光电传感器电连接，所述第一晶体管与所述第二电容电连接，所述第一晶体管与所述复位电路电连接，其中，所述第一晶体管用于导通或关断所述光电传感器与所述第二电容之间的连接通路，所述第一晶体管还用于控制所述复位电路与所述第二电容之间连接通路的导通或关断，所述第二电容用于采集所述像素电压；
    所述第二晶体管与所述第一晶体管电连接，所述第二晶体管与所述第一电容电连接，其中，所述第二晶体管与所述第一晶体管共同用于控制所述复位电路与所述第一电容之间连接通路的导通或关断，所述第一电容用于采集所述复位电压；
    所述相关多采样电路与所述第二晶体管电连接，所述第二晶体管用于控制所述相关多采样电路与所述第一电容之间之间连接通路的导通或关断；
    所述相关多采样电路与所述第二电容电连接。
  3. 根据权利要求2所述的图像读取电路，其特征在于，所述判断电路包括第一电压比较器、阈值电压产生电路和多采样次数选择电路，所述第一电压比较器与所述阈值电压产生电路电连接，所述阈值电压产生电路用于产生第一阈值电压；
    所述第一电压比较器与所述第二电容电连接，所述第一电压比较器用于比较所述第一阈值电压与所述像素电压，以产生第一电压比较结果；
    所述第一电压比较器与所述多采样次数选择电路电连接，所述多采样次数选择电路根据所述第一电压比较结果确定所述第一采样次数。
  4. 根据权利要求3所述的图像读取电路，其特征在于，所述判断电路还包括第二电压比较器，所述第二电压比较器与所述阈值电压产生电路电连接，所述第二电压比较器与所述多采样次数选择电路电连接；
    所述第二电压比较器，用于根据第二阈值电压与所述像素电压确定第二电压比较结果，所述第二阈值电压由所述阈值电压产生电路产生；
    所述多采样次数选择电路，具体用于：根据所述第一电压比较结果和所述第二电压比较结果确定所述像素电压所在电压区间；
    根据所述电压区间确定所述第一采样次数。
  5. 根据权利要求1-4中任一项所述的图像读取电路，其特征在于，所述图像读取电路还包括第一模数转换器和像素处理器，所述相关多采样电路与所述判断电路电连接，所述相关多采样电路与所述第一模数转换器电连接，所述相关多采样电路与所述光电转换电路电连接，所述第一模数转换器与所述像素处理器电连接，所述像素处理器与所述判断电路电连接；
    所述相关多采样电路，用于对所述像素电压和所述复位电压进行相关多采样得到第二电压，其中，所述第二电压为所述像素电压和所述复位电压经过相关多采样后电压值的累加和，所述第二电压为所述第一电压与所述第一采样次数乘积；
    所述第一模数转换器，用于将所述第二电压转换为第二数字码；
    所述像素处理器，用于根据所述第二数字码和所述第一采样次数确定第一数字码，所述第一数字码为所述第一电压的数字码。
  6. 根据权利要求1-4中任一项所述的图像读取电路，其特征在于，所述图像读取电路还包括第一模数转换器和像素处理器，所述相关多采样电路与所述判断电路电连接，所述相关多采样电路与所述光电转换电路电连接，所述相关多采样电路与所述第一模数转换器电连接，所述第一模数转换器与所述像素处理器电连接，所述像素处理器与所述判断电路电连接；
    所述相关多采样电路，还用于对所述像素电压经过所述第一采样次数的相关多采样后采集得到第一像素电压；
    所述第一模数转换器，用于将第一像素电压转换为第三数字码；
    所述相关多采样电路，还用于对所述复位电压经过所述第一采样次数的相关多采样后采集得到第一复位电压；
    所述第一模数转换器，还用于将第一复位电压转换为第四数字码，所述第一复位电压为所述相关多采样电路对所述复位电压经过所述第一采样次数的相关多采样后所述复位电压的累加和；
    所述像素处理器，用于根据所述第三数字码和所述第四数字码确定第二数字码，所述第二数字码为第二电压对应的数字码，所述第二电压为所述像素电压和所述复位电压经过相关多采样后电压值的累加和；
    所述像素处理器，还用于根据所述第二数字码和所述第一采样次数确定第一数字码，所述第一数字码为所述第一电压的数字码。
  7. 根据权利要求1-6中任一项所述的图像读取电路，其特征在于，所述光电转换电路还包括第一源跟随器；
    所述第一源跟随器与所述光电传感器电连接，所述第一源跟随器与所述复位电路电连接，所述第一源跟随器与所述第一晶体管电连接，所述第一源跟随器用于隔绝所述光电传感器和所述第一晶体管、所述复位电路和所述第一晶体管之间的电流。
  8. 根据权利要求7所述的图像读取电路，其特征在于，所述光电转换电路还包括第二源跟随器；
    所述第二源跟随器与所述第二晶体管电连接，所述第二源跟随器与所述第二电容电连接，所述第二源跟随器与所述判断电路和所述相关多采样电路电连接，所述第二源跟随器用于放大所述光电转换电路输出的所述像素电压和所述复位电压。
  9. 一种图像传感器，其特征在于，所述图像传感器包括像素控制电路和权利要求1-8中任一项所述的图像读取电路，
    所述像素控制电路用于控制所述图像读取电路的曝光。
  10. 一种图像擷取光学系统，其特征在于，所述图像撷取光学系统包括镜头组和权利要求9所述的图像传感器，其中，
    所述镜头组用于会聚光线；
    所述图像传感器用于对所述镜头组会聚的光线进行处理。
  11. 一种终端设备，其特征在于，所述终端设备包括图像信号处理器和权利要求10所述的图像擷取光学系统，其中，
    所述图像撷取光学系统用于输出图像；
    所述图像信号处理器用于对所述图像撷取光学系统输出的所述图像进行优化处理。
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