WO2021136282A1 - 一种滤波器、信号处理设备及制造所述滤波器的方法 - Google Patents

一种滤波器、信号处理设备及制造所述滤波器的方法 Download PDF

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WO2021136282A1
WO2021136282A1 PCT/CN2020/140935 CN2020140935W WO2021136282A1 WO 2021136282 A1 WO2021136282 A1 WO 2021136282A1 CN 2020140935 W CN2020140935 W CN 2020140935W WO 2021136282 A1 WO2021136282 A1 WO 2021136282A1
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resonator
resonators
series
parallel
designated
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PCT/CN2020/140935
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English (en)
French (fr)
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庞慰
郑云卓
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诺思(天津)微系统有限责任公司
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
    • H03H9/15—Constructional features of resonators consisting of piezoelectric or electrostrictive material
    • H03H9/205—Constructional features of resonators consisting of piezoelectric or electrostrictive material having multiple resonators
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
    • H03H9/46—Filters
    • H03H9/54—Filters comprising resonators of piezo-electric or electrostrictive material
    • H03H9/58—Multiple crystal filters

Definitions

  • the present invention relates to the field of filtering devices for communication, in particular to a filter, a signal processing device and a method of manufacturing the filter.
  • the downlink frequency band of Beidou Navigation uses S-band with a frequency of 2483.5MHz ⁇ 2500MHz. Its low frequency side is the ISM frequency band (2400MHz ⁇ 2483.5MHz), and the high frequency side is the transmission frequency band of LTE Band 7 (2500MHz ⁇ 2570MHz). , There is almost no gap between them.
  • the ISM band (2400MHz ⁇ 2483.5MHz), except for the high frequency side is the transmission frequency band of LTE Band 7 (2500MHz ⁇ 2570MHz), and its low frequency side is the LTE frequency band 40 (2300MHz ⁇ 2400MHz).
  • LTE Band 7 2500MHz ⁇ 2570MHz
  • LTE frequency band 40 2300MHz ⁇ 2400MHz
  • the elimination of interference between various communication frequency bands can be optimized in part by the allocation of communication resource blocks, and the other can be mainly filtered by radio frequency filters. This congestion of frequency resources puts forward higher requirements on the filter.
  • the small-size filters that can meet the use of communication terminals are mainly piezoelectric acoustic wave filters.
  • the resonators that constitute this type of acoustic wave filter mainly include: FBAR (Film Bulk Acoustic Resonator), SMR (Solidly Mounted) Resonator, solid-state assembly resonator) and SAW (Surface Acoustic Wave, surface acoustic wave resonator).
  • FBAR and SMR duplexers manufactured based on the principle of bulk acoustic wave have a higher Q value than the SAW duplexers manufactured based on the principle of surface acoustic wave.
  • Figure 11(a) is the electrical symbol of the piezoelectric acoustic wave resonator
  • Figure 11(b) is its equivalent electrical model diagram.
  • the electrical model is simplified to a resonant circuit composed of Lm, Cm and C0 .
  • the resonant circuit has two resonant frequency points: one is the fs when the impedance value of the resonant circuit reaches the minimum, and fs is defined as the string resonance frequency of the resonator; the other is when the impedance value of the resonant circuit reaches the maximum
  • fp is defined as the anti-resonant frequency of the resonator. among them,
  • fs is smaller than fp.
  • electromechanical coupling coefficient Kt 2 of the resonator is defined, which can be expressed by fs and fp:
  • Figure 12 shows the relationship between the resonator impedance and fs and fp.
  • Kt 2 the greater the frequency difference between fs and fp, that is, the farther the two resonance frequencies are
  • Kt 2 the smaller the frequency difference between fs and fp will be, that is, two The closer the resonance frequencies are.
  • the impedance of the resonator at Fs is defined as the resonant impedance Rs
  • the impedance of the resonator at Fp is defined as the anti-resonant impedance Rp.
  • Rs the impedance of the resonator at Fs
  • Rp the anti-resonant impedance
  • the bandwidth of an ordinary ladder-shaped filter mainly depends on the difference between the resonant frequency and the anti-resonant frequency of the resonator it contains, or in other words, depends on the Kt 2 of the resonator it contains.
  • Kt 2 is related to many factors and cannot be reduced indefinitely according to the needs of users.
  • AlN aluminum nitride
  • the loss performance of the resonator in this range is better, but the filter made by conventional
  • the bandwidth is wider, the roll-off is slower, and the size of the filter is relatively large.
  • Kt 2 drops below 4.5%, due to factors such as the area of the resonator and the stacking thickness ratio, the loss characteristics of the resonator will drop faster.
  • the bandwidth of the filter made with such a resonator is more suitable, the insertion loss is mostly Poor, there is still no way to meet the communication requirements.
  • the present application provides a filter, a method for improving the performance of the filter, and a signal processing device to improve the performance of the filter.
  • an embodiment of the present application provides a filter including: a plurality of resonators, the plurality of resonators include a plurality of series resonators and a plurality of parallel resonators, the series resonators are connected in series with each other One end of the parallel resonator is connected to the connection point of the two series resonators, and the other end is connected to an inductor, and the inductor is grounded.
  • the multiple series resonators include one or more designated series resonators, and the designated series resonator The device is connected in parallel with at least one first resonator;
  • the plurality of parallel resonators include one or more designated parallel resonators, and the designated parallel resonators are connected in series with at least one second resonator or a capacitor;
  • the multiple resonators are respectively arranged on different wafers according to different resonance frequencies.
  • the resonant frequency of the designated series resonator is greater than the resonant frequency of the first resonator
  • the designated series resonator and the other series resonators are arranged on a first wafer, and the first resonator and the parallel resonator are arranged on a second wafer.
  • the difference between the anti-resonant frequency of the designated series resonator and the resonant frequency of the first resonator is smaller than a preset value.
  • the resonant frequency of the designated parallel resonator is less than the resonant frequency of the second resonator;
  • the second resonator and the series resonator are arranged on a first wafer, and the designated parallel resonator and the other parallel resonators are arranged on a second wafer.
  • the difference between the anti-resonant frequency of the designated parallel resonator and the resonant frequency of the second resonator is smaller than a preset value.
  • the designated parallel resonator when the designated parallel resonator is connected in series with a capacitor, one end of the capacitor is connected to the node of two adjacent series resonators, and the other end of the capacitor is connected to one end of the designated parallel resonator, The other end of the designated parallel resonator is connected to a grounded inductor;
  • the series resonator is arranged on a first wafer, and the first resonator and the capacitor, the designated parallel resonator and the other parallel resonators are arranged on a second wafer.
  • an embodiment of the present application provides a signal processing device, including: a signal input circuit, a signal output circuit, and the filter according to the first aspect; the signal input circuit is connected to the filter, The filter is connected to the signal output circuit.
  • an embodiment of the present application provides a method for manufacturing a filter
  • the filter includes: a plurality of resonators, the plurality of resonators include a plurality of series resonators and a plurality of parallel resonators, so The series resonators are connected in series with each other, one end of the parallel resonator is connected to the connection point of the two series resonators, and the other end is connected to an inductor, and the inductor is grounded.
  • the method includes:
  • the plurality of parallel resonators include one or more designated parallel resonators, and the designated parallel resonators are connected in series with at least one second resonator or a capacitor;
  • the plurality of resonators are respectively arranged on different wafers according to different resonance frequencies.
  • the method further includes:
  • the arranging the multiple resonators on different wafers according to different resonance frequencies includes:
  • the designated series resonator and the other series resonators are arranged on a first wafer, and the first resonator and the parallel resonator are arranged on a second wafer.
  • the method further includes:
  • the difference between the anti-resonant frequency of the designated series resonator and the resonant frequency of the first resonator is set to be smaller than a preset value.
  • the method further includes:
  • the arranging the multiple resonators on different wafers according to different resonance frequencies includes:
  • the second resonator and the series resonator are arranged on a first wafer, and the designated parallel resonator and the other parallel resonators are arranged on a second wafer.
  • the method further includes:
  • the difference between the anti-resonant frequency of the designated parallel resonator and the resonant frequency of the second resonator is set to be smaller than a preset value.
  • the method further includes:
  • the designated parallel resonator When the designated parallel resonator is connected in series with a capacitor, one end of the capacitor is connected to the node of two adjacent series resonators, and the other end of the capacitor is connected to one end of the designated parallel resonator. The other end of the parallel resonator is connected to the ground inductance;
  • the series resonator is arranged on the first wafer, and the first resonator and the capacitor, the designated parallel resonator and the other parallel resonators are arranged on the second wafer
  • a plurality of series resonators are provided, including one or more designated series resonators, and the designated series resonators are connected to at least one first The resonators are connected in parallel; and/or, the multiple parallel resonators include one or more designated parallel resonators, and the designated parallel resonators are connected in series with at least one second resonator or a capacitor; and the multiple resonators are arranged in accordance with the resonance frequency
  • the difference is set on different wafers.
  • Fig. 1 is a schematic diagram of the structure of a filter in the prior art.
  • FIG. 2 is a schematic diagram of the circuit structure of the filter shown in Embodiment 1 of the present application;
  • Fig. 3 is a side view of the filtering shown in the above-mentioned embodiment 1;
  • 4a is a schematic diagram of the chip design of the upper wafer 202 in the embodiment 1 shown in FIG. 2;
  • 4b is a schematic diagram of the chip design of the lower wafer 201 in the embodiment 1 shown in FIG. 2;
  • FIG. 5 is a schematic diagram showing the comparison between the insertion loss and the frequency relationship curve of the filter of the embodiment 1 shown in FIG. 2 and the effect of the prior art;
  • FIG. 6 is a schematic diagram of the filter circuit structure of Embodiment 2 provided by the present application.
  • FIG. 7 is a side view of the filter of Embodiment 2 shown in FIG. 6;
  • FIG. 8a is a schematic diagram of the chip design of the wafer on the filter in the above-mentioned embodiment 2;
  • 8b is a schematic diagram of the chip design of the lower wafer of the filter in the above-mentioned embodiment 2;
  • FIG. 9 is a schematic diagram of the circuit structure of the filter in Embodiment 3 of the present invention.
  • FIG. 10 is a schematic diagram of the circuit structure of the filter in Embodiment 4 of the present invention.
  • Figure 11(a) is the electrical symbol of the piezoelectric acoustic resonator
  • Figure 11(b) is the equivalent electrical model diagram of the piezoelectric acoustic resonator
  • Figure 12 shows the relationship between the resonator impedance and fs and fp
  • FIG. 13 is a schematic diagram of a parallel combined resonator Res formed by connecting two resonators with different resonance frequencies in parallel;
  • FIG. 14 is a schematic diagram of the impedance and Kt relationships of the parallel combined resonator Res, the first resonator Res1 and the first resonator Res2 in FIG. 13;
  • FIG. 15 is a schematic structural diagram of a series combination resonator Res formed by connecting two resonators with different resonance frequencies in series;
  • FIG. 16 is a schematic diagram of the impedance and Kt relationships of the series combination resonator Res, the first resonator Res1 and the first resonator Res2 in FIG. 15.
  • Fig. 1 is a schematic structural diagram of a filter in the prior art.
  • the conventional ladder-shaped filter in the prior art includes a plurality of resonators, the plurality of resonators including a first number of series resonators and a second number of parallel resonators, the figure contains 4 Take three series resonators S1, S2, S3, S4 and three parallel resonators P1, P2, P3 as an example, and the input end of the filter is connected to the first inductor, and the output end of the filter is connected to the second inductor.
  • the ground terminals of the devices are respectively connected with third inductors, one end of each third inductor is connected to the parallel resonator, and the other end is grounded.
  • the first inductor and the second inductor connected to the input terminal and the output terminal are mainly located on the packaging substrate, and all the resonators in the prior art are arranged on a wafer, which is susceptible to the limitation of the wafer material. The performance of the resonator cannot be further optimized.
  • An embodiment of the present application provides a filter including: a plurality of resonators, the plurality of resonators include a plurality of series resonators and a plurality of parallel resonators, the series resonators are connected in series with each other, and one end of the parallel resonator is connected to At the connection point of the two series resonators, the other end is connected to an inductor, the inductor is grounded, wherein the plurality of series resonators include one or more designated series resonators, and the designated series resonators are connected in parallel with at least one first resonator.
  • the multiple parallel resonators include one or more designated parallel resonators, and the designated parallel resonators are connected in series with at least one second resonator or a capacitor;
  • the above-mentioned multiple resonators are respectively arranged on different wafers according to different resonance frequencies.
  • Figure 13 is a parallel combination resonator Res formed by connecting two resonators with different resonance frequencies in parallel.
  • the two resonators are the first resonator 1 and the second resonator 2, and the first resonator 1
  • the resonant frequency is greater than the resonant frequency of the second resonator 2, and the difference between these frequencies is mainly achieved by adding a mass load on the second resonator 2.
  • FIG. 14 is a schematic diagram of the impedance and Kt relationship of the parallel combined resonator Res, the first resonator Res1 and the first resonator Res2 in FIG. 13.
  • the parallel combination resonator Res1 has a resonant frequency Fs1 and an anti-resonant frequency Fp1
  • the second resonator Res2 has a resonant frequency Fs2 and an anti-resonant frequency Fp2, where Fs2 ⁇ Fs1, and Fp2 and Fs1 are relatively close. Due to the above-mentioned frequency relationship, the parallel combination resonator Res forms an impedance characteristic as shown by the thick solid line in Figure 14.
  • the anti-resonance frequency between Fp1 is Fp3, where Fp3>Fs3, and Fp3 ⁇ Fp1.
  • the impedance value of the parallel combination resonator Res at Fp3 is lower than the impedance of the resonator Res1 at its anti-resonant frequency Fp1, or the impedance of the resonator Res2 at its anti-resonant frequency Fp2.
  • the impedance value of the combined resonator Res at Fp4 is lower than its impedance value at Fp3.
  • the resonance at the combined resonator Fs3 and Fp3 is defined as the main resonance
  • the resonance at Fs4 and Fp4 is defined as the secondary resonance.
  • the main resonance of the parallel combined resonator Res occurs due to the position of Fp3 compared to Fp1. Shift left, so the Kt 2 of the main resonance is smaller than the resonator Res1.
  • the Rp of the main resonance is smaller than the resonator Res1
  • the secondary resonator Rp is smaller than the main resonance
  • the Rs of the main resonance and the secondary resonance are basically the same as the resonator Res1.
  • the parallel combination resonator Res can be regarded as a resonator that compares with the resonator Res1, Rs does not change, Rp becomes worse, but at the same time Kt 2 becomes smaller. If this parallel combination resonator is placed in the series position of the filter, the passband insertion loss of the filter will not become worse, and the roll-off on the right side will become better.
  • the designated series resonator is connected in parallel with the first resonator to form a parallel combination resonator as shown in FIG. 13, so that the filter can be inserted in the passband.
  • the loss will not get worse, so that the roll-off on the right side will get better.
  • FIG. 2 is a schematic diagram of the circuit structure of Embodiment 1 of the present invention.
  • the circuit includes series resonators S2, S3, and designated series resonators S1, S4.
  • the designated series resonator S1 is connected in parallel with the first resonator SP1
  • the designated series resonator S4 is in parallel with the first resonator.
  • SP4 is connected in parallel; and compared to the existing circuit structure in Fig.
  • the series resonator S1 in the series position is replaced with a parallel combination resonator formed by the parallel connection of the designated series resonator S1 and the first resonator SP1, in the series position
  • the series resonator S4 of is replaced by a parallel combination resonator formed by the parallel connection of the designated series resonator S4 and the first resonator SP4.
  • the resonance frequencies of the resonators SP1 and SP4 are the same as or similar to the resonance frequencies of the parallel resonators P1 to P3. Therefore, in this embodiment, the four resonators S1 to S4 are arranged on the lower wafer 201, and the resonators P1 to P3 , SP1 and SP4 are made on the upper wafer 202.
  • FIG. 3 is a side view of Embodiment 1 shown in FIG. 2 above.
  • the upper wafer 202 is provided with parallel resonators P1, P2, P3 and first resonators SP1, SP4
  • the lower wafer 201 is provided with series resonators S1, S2, S3, S4; the bottom of the resonator is the substrate.
  • FIG. 4a and 4b are schematic diagrams of the chip design of the upper wafer 202 and the lower wafer 201 in the embodiment 1 shown in FIG. 2 above.
  • the position where the series and parallel are broken (the upper wafer and the lower wafer are connected) New bonding areas J1, J2, and J3 have been added.
  • the new bonding areas J1, J2, and J3 are only used to connect the upper wafer with the lower wafer, and do not need to be connected to the outside of the chip through vias. Therefore, its shape is different from the bonding area of the connection via, and the area is only one-half of the original.
  • the dotted circle indicates the position of the chip solder ball connected to the nearby wafer via.
  • the inductors connected to the input and output terminals are mainly located on the package substrate.
  • Fig. 5 is a schematic diagram of the comparison between the insertion loss and frequency relationship curve of the filter of embodiment 1 shown in Fig. 2 and the effect of the prior art; as a narrowband filter applied to WLAN CH1 ⁇ CH11, the passband range is 2402MHz ⁇ 2472MHz as an example, it needs to achieve better roll-off characteristics on the left and right sides.
  • the solid line in the figure is the insertion loss versus frequency relationship curve of the filter of this embodiment
  • the dashed line is the insertion loss versus frequency relationship curve designed using the prior art.
  • the Kt 2 of the combined resonator can be even smaller. It is precisely because of this feature that the resonator in the embodiment has better loss characteristics, and the insertion loss of the filter is better, and the roll-off is faster. Take the left roll-off as an example, from the passband 2dB insertion loss to 40dB suppression. The roll-off distance has been reduced from 15.5MHz in the prior art to 12MHz and increased by 3.5MHz. Moreover, due to the folding of the series-parallel resonator, the miniaturization of the chip size is realized.
  • Figure 15 is a series combination resonator Res formed by connecting two resonators with different resonant frequencies in series.
  • the two resonators are the first resonator 1'and the second resonator 2', in which the first resonator
  • the resonant frequency of 1' is greater than the resonant frequency of the second resonator 2', and the difference between the frequencies is mainly achieved by adding a mass load on the second resonator 2'.
  • the anti-resonant frequency of the first resonator 1' is relatively close to the resonant frequency of the second resonator 2'.
  • FIG. 16 is a schematic diagram of the impedance and Kt relationship of the series combination resonator Res, the first resonator Res1 and the first resonator Res2 in FIG. 15.
  • the first resonator Res1 has a resonant frequency Fs1 and an anti-resonant frequency Fp1
  • the second resonator Res2 has a resonant frequency Fs2 and an anti-resonant frequency Fp2, where Fs2 ⁇ Fs1, and Fp2 is relatively close to Fs1. Due to the above-mentioned frequency relationship, the series combination resonator Res forms an impedance characteristic as shown by the thick solid line in Fig. 16.
  • the impedance characteristic includes 4 resonance frequencies: the same impedance as Fs1, the low-point resonance frequency Fs3, and The anti-resonant frequency Fp3 between Fs1 and Fp1, where Fp3>Fs3, the anti-resonant frequency Fp3 of the main resonance is the same as Fp1 of the resonator 1, and Fs3 is located between Fs1 and Fp3, which is equivalent to Fs1 shifting to the right.
  • the low-point resonance frequency Fs4 which is the same as Fs2, and the anti-resonance frequency Fp4 between Fs2 and Fp2, where Fp4>Fs3, and Fp4 ⁇ Fp2.
  • the impedance value of the series combination resonator Res at Fp3 is lower than the impedance of the resonator Res1 at its anti-resonant frequency Fp1, or the impedance of the resonator Res2 at its anti-resonant frequency Fp2.
  • the impedance value of the combined resonator Res at Fp4 is lower than its impedance value at Fp3.
  • the resonance at the combined resonator Fs3 and Fp3 is defined as the main resonance, and the resonance at Fs4 and Fp4 is defined as the secondary resonance.
  • the main resonance of the series combined resonator Res occurs due to the position of Fp3 compared to Fp1.
  • the Kt 2 of the main resonance is smaller than the resonator Res1.
  • the Rp of the primary resonance is smaller than the resonator Res1
  • the secondary resonator Rp is smaller than the primary resonance.
  • the Rs of the primary resonance is worse than that of the resonator Res1
  • the secondary resonance is worse than the primary resonance.
  • Res1 is basically the same. If this series combination resonator is placed in the parallel position of the filter, the passband insertion loss of the filter will not become worse, and the left side roll-off will become better.
  • the designated parallel resonator is connected in series with the second resonator to form a series combination resonator as shown in FIG. 15, so that the filter can be inserted in the passband.
  • the loss will not get worse, so that the roll-off on the right side will get better.
  • FIG. 6 is a schematic diagram of the circuit structure of Embodiment 2 provided by the present application. Referring to FIG. 6, the difference from the prior art is that in this embodiment, part of the resonators in the parallel position are replaced with combined resonators, and they are made in On two wafers.
  • the filter includes series resonators S1, S2, S3, S4, and parallel resonators P1, P2, P3, and the parallel resonators include designated parallel resonators P1, P3,
  • the designated parallel resonators P1 and P3 are respectively connected in series with the second resonators PS1 and PS3, one end of the second resonator PS1 is connected to the connection point of the series resonators S1, S2, and the other end of the second resonator PS1 is in parallel resonance with the designated P1 is connected, the designated parallel resonator is also connected to an inductor, and the inductor is grounded.
  • FIG. 7 is a side view of the filter of Embodiment 2 shown in FIG. 6. Referring to FIG.
  • the upper wafer 302 is provided with parallel resonators P1, P2, P3; the lower wafer 301
  • the series resonators S1, S2, S3, S4 are arranged on the upper part, and the bottom of the second resonators PS1, PS2 is the substrate.
  • FIGS. 8a and 8b are schematic diagrams of the chip design of the upper wafer 302 and the lower wafer 301 of the filter in the above-mentioned embodiment 2.
  • the position where the series and parallel breaks are broken is added
  • the new bonding areas J1, J2, and J3 are only used to connect the upper wafer and the lower wafer, and do not need to be connected to the outside of the chip through vias.
  • the shape is different from the bonding area of the connecting via, and the area is only one-half of the original.
  • the dotted circle indicates the position of the chip solder ball connected to the nearby wafer via.
  • FIG. 9 is a schematic diagram of the circuit structure of the filter in Embodiment 3 of the present invention.
  • a combination resonator is used in the series position and the parallel position, and the resonator is made on two wafers according to the frequency of the resonator.
  • the filter includes series resonators S1, S2, S3, S4, and parallel resonators P1, P2, P3, and the parallel resonator includes a designated parallel resonator P2.
  • the parallel resonator P2 is connected in series with the second resonator PS2, one end of the second resonator PS2 is connected to the connection point of the series resonators S2 and S3, and the other end of the second resonator PS2 is connected to the designated parallel resonator P2.
  • the parallel resonator P2 is also connected to an inductor, which is grounded.
  • the series resonators S1, S2, S3, S4, and the second resonator PS2 are provided on the lower wafer 401, and the parallel resonators P1, P2, P3, and the first resonators SP1, SP4 are provided On the upper wafer 402.
  • Fig. 10 is a schematic diagram of the circuit structure of the filter in embodiment 4 of the present invention.
  • the difference from embodiment 3 is that the auxiliary resonator of the combined resonator in the parallel position in the circuit structure is replaced by a resonator fabricated on a wafer
  • This kind of auxiliary resonator is replaced by a combined resonator of a capacitor.
  • the filter includes series resonators S1, S2, S3, S4, and parallel resonators P1, P2, and P3.
  • the parallel resonators include designated parallel resonators P1, P2, and the designated parallel resonator P1 , P2 are connected in series with the capacitors CP1 and CP2 respectively.
  • One end of the capacitor CP2 is connected to the connection point of the series resonators S2 and S3, and the other end of the capacitor CP2 is connected to the designated parallel resonator P2.
  • the designated parallel resonator P2 is also connected to the inductor.
  • the inductance is grounded; one end of the capacitor CP1 is connected to the connection point of the series resonator S1, S2 and the first resonator SP1, the other end of the capacitor CP1 is connected to the designated parallel resonator P1, and the designated parallel resonator P1 is also connected to The inductors are connected, and the inductors are grounded.
  • a narrowband filter generally requires a small electromechanical coupling coefficient.
  • a resonator with a small electromechanical coupling coefficient may have poor resonator performance or poor process manufacturing size tolerance characteristics.
  • the combination mode can be series or parallel, and the position of the combined resonator can be either in series or in parallel.
  • two structures are mainly proposed.
  • One is a combination resonator formed by connecting two resonators in parallel in a series position
  • the other is a combination resonator formed by connecting two resonators in series in a parallel position.
  • Combination resonator according to the different frequency of the resonator, these resonators are made separately on the upper and lower wafers.
  • the two resonators in the combined resonator are located on two wafers because of their different frequencies.
  • the size of the resonator is reduced and the performance is improved.
  • An embodiment of the present application also provides a signal processing device, including: a signal input circuit, a signal output circuit, and the filter according to any one of the above embodiments; the signal input circuit is connected to the filter, The filter is connected to the signal output circuit.
  • the filter is a combination resonator formed by connecting two frequency resonators in parallel in a series position, and/or a combination formed by connecting two frequency resonators in series in a parallel position Resonator. And, according to the different frequency of the resonator, these resonators are made separately on the upper and lower wafers. In particular, the two resonators in the combined resonator are located on two wafers because of different frequencies. This reduces the size of the device and improves performance.
  • a method for manufacturing a filter which is used to manufacture the filter described in any of the above embodiments.
  • the filter includes: a plurality of resonators, the plurality of resonators including A plurality of series resonators and a plurality of parallel resonators, the series resonators are connected in series with each other, one end of the parallel resonator is connected to the connection point of the two series resonators, the other end is connected to an inductor, and the inductor is grounded.
  • Methods include:
  • the plurality of parallel resonators include one or more designated parallel resonators, and the designated parallel resonators are connected in series with at least one second resonator or a capacitor;
  • the plurality of resonators are respectively arranged on different wafers according to different resonance frequencies.
  • the above method further includes:
  • the arranging the multiple resonators on different wafers according to different resonance frequencies includes:
  • the designated series resonator and the other series resonators are arranged on a first wafer, and the first resonator and the parallel resonator are arranged on a second wafer.
  • the above method further includes:
  • the difference between the anti-resonant frequency of the designated series resonator and the resonant frequency of the first resonator is set to be smaller than a preset value.
  • the above method further includes:
  • the arranging the multiple resonators on different wafers according to different resonance frequencies includes:
  • the second resonator and the series resonator are arranged on a first wafer, and the designated parallel resonator and the other parallel resonators are arranged on a second wafer.
  • the above method further includes:
  • the difference between the anti-resonant frequency of the designated parallel resonator and the resonant frequency of the second resonator is set to be smaller than a preset value.
  • the above method further includes:
  • the designated parallel resonator When the designated parallel resonator is connected in series with a capacitor, one end of the capacitor is connected to the node of two adjacent series resonators, and the other end of the capacitor is connected to one end of the designated parallel resonator. The other end of the parallel resonator is connected to the ground inductance;
  • the series resonator is arranged on a first wafer, and the first resonator and the capacitor, the designated parallel resonator and the other parallel resonators are arranged on a second wafer.
  • the resonator manufactured by applying the method has the advantages of reducing the size of the resonator and improving the performance of the resonator.

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Abstract

本申请提供一种滤波器及提高滤波器性能的方法和信号处理设备。其中，滤波器包括：多个谐振器，所述多个谐振器包括多个串联谐振器和多个并联谐振器，所述串联谐振器彼此串联连接，所述并联谐振器一端连接至两个串联谐振器的连接点，另一端连接电感，所述电感接地，所述多个串联谐振器包括一个或多个指定串联谐振器，所述指定串联谐振器与至少一个第一谐振器并联；和/或，所述多个并联谐振器中包括一个或多个指定并联谐振器，所述指定并联谐振器与至少一个第二谐振器或者电容串联；所述多个谐振器按照谐振频率的不同分别设置于不同的晶圆上。如此，可以改善滤波器的性能，并降低滤波器尺寸。

Description

一种滤波器、信号处理设备及制造所述滤波器的方法 技术领域
本发明涉及通信用滤波类器件领域，具体而言，涉及一种滤波器、信号处理设备及制造所述滤波器的方法。
背景技术
随着市场的迅猛发展，无线通讯终端和设备不断朝着小型化，多模-多频段的方向发展。近年来，一些窄带的通信频段逐渐兴起。这些频段的附近通常存在其它可能存在干扰的频段，因此对滤波器的滚降特性有较高的要求。例如，北斗导航的下行频段采用S波段，频率为2483.5MHz～2500MHz，它低频一侧是ISM频段(2400MHz～2483.5MHz),高频一侧则是LTE的频段7的发送频段(2500MHz～2570MHz)，它们之间几乎没有空隙。再如，ISM频段(2400MHz～2483.5MHz)，除了高频一侧是LTE的频段7的发送频段(2500MHz～2570MHz)之外，它的低频一侧是LTE的频段40(2300MHz～2400MHz)，之间同样没有空隙。各种通信频段之间干扰的消除，一部分可以通过通信资源块的分配来实现优化，另一种则主要通过射频滤波器进行滤波。这种频率资源的拥挤，对滤波器提出了更高的要求。
目前，能够满足通讯终端使用的小尺寸滤波器主要是压电声波滤波器，构成此类声波滤波器的谐振器主要包括：FBAR(Film Bulk Acoustic Resonator，薄膜体声波谐振器)，SMR(Solidly Mounted Resonator，固态装配谐振器)和SAW(Surface Acoustic Wave，表面声波谐振器)。其中基于体声波原理制造的FBAR和SMR双工器，相比基于表面声波原理制造的SAW双工器，具有更高的Q值。
图11(a)是压电声波谐振器的电学符号，图11(b)是其等效电学模型图，在不考虑损耗项的情况下，电学模型简化为Lm、Cm和C0组成的谐振电路。根据谐振条件可知，该谐振电路存在两个谐振频点：一个是谐振电路阻抗值达到最小值时的fs，将fs定义为该谐振器的串谐振频率；另一个是当谐振电路阻抗值达到最大值时的fp，将fp定义为该谐振器的反谐振频率。其中，
Figure PCTCN2020140935-appb-000001
并且，fs比fp要小。同时，定义了谐振器的机电耦合系数Kt 2，它可以用fs和fp来表示：
Figure PCTCN2020140935-appb-000002
图12示出了谐振器阻抗与fs和fp之间的关系。在某一特定的频率下，Kt 2越大，则fs和fp的频率差越大，即两个谐振频率离得越远，Kt 2越小，则fs和fp的频率差越小，即两个谐振频率离得越近。
谐振器在Fs处的阻抗定义为谐振阻抗Rs，谐振器在Fp处的阻抗定义为反谐振阻抗Rp，通常，Rs越小，或Rp越大，均代表谐振器的Q值越高，所制作的滤波器的损耗也越小。
普通梯形结构滤波器的带宽主要取决于其所包含的谐振器的谐振频率与反谐振频率的差值，或者说，取决于其所包含谐振器的Kt 2，为了实现较窄带宽的滤波器，或者实现较快的边沿滚降，就要想办法减少谐振器的Kt 2。但是，Kt 2与多种因素相关，并不可以按用户的需要而无限制的减少。以氮化铝(AlN)为压电材料制作的FBAR谐振器举例，其Kt 2一般可以做到5～6％左右，这个范围内的谐振器损耗性能较好，但是用常规制作出来的滤波器带宽较宽，滚降较慢，而且滤波器的尺寸也相对较大。而当Kt 2降到4.5％以下，因为谐振器面积，层叠厚度配比等因素，谐振器损耗特性会下降较快，用这样的谐振器做出来的滤波器虽然带宽比较合适，但是大多插入损耗较差，仍然没有办法满足通信要 求。
如何利用谐振器损耗较好的Kt 2区间，实现窄带高滚降的滤波器，同时缩小滤波器的尺寸，逐渐成为一个滤波器设计工程师亟待解决的问题。
发明内容
有鉴于此，本申请提供一种滤波器及提高滤波器性能的方法和信号处理设备，以改善滤波器的性能。
具体地，本申请是通过如下技术方案实现的：
第一方面，本申请实施例中提供了一种滤波器，包括：多个谐振器，所述多个谐振器包括多个串联谐振器和多个并联谐振器，所述串联谐振器彼此串联连接，所述并联谐振器一端连接至两个串联谐振器的连接点，另一端连接电感，所述电感接地，所述多个串联谐振器包括一个或多个指定串联谐振器，所述指定串联谐振器与至少一个第一谐振器并联；
和/或，
所述多个并联谐振器中包括一个或多个指定并联谐振器，所述指定并联谐振器与至少一个第二谐振器或者电容串联；
所述多个谐振器按照谐振频率的不同分别设置于不同的晶圆上。
可选地，所述指定串联谐振器的谐振频率大于所述第一谐振器的谐振频率；
所述指定串联谐振器与其他所述串联谐振器设置于第一晶圆上，所述第一谐振器与所述并联谐振器设置于第二晶圆上。
可选地，所述指定串联谐振器的反谐振频率与所述第一谐振器的谐振频率之差小于预设值。
可选地，所述指定并联谐振器的谐振频率小于所述第二谐振器的谐振频率；
所述第二谐振器与所述串联谐振器设置于第一晶圆上，所述指定并联谐振器与其他所述并联谐振器设置于第二晶圆上。
可选地，所述指定并联谐振器的反谐振频率与所述第二谐振器的谐振频率之差小于预设值。
可选地，所述指定并联谐振器与电容串联时，所述电容的一端与相邻两个串联谐 振器的节点相连，所述电容的另一端与所述指定并联谐振器的一端相连接，所述指定并联谐振器的另一端与接地电感相连接；
所述串联谐振器设置于第一晶圆上，所述第一谐振器和所述电容、所述指定并联谐振器和其他所述并联谐振器设置于第二晶圆上。
第二方面，本申请实施例中提供了一种信号处理设备，包括：信号输入电路、信号输出电路和如第一方面所述的滤波器；所述信号输入电路与所述滤波器相连接，所述滤波器与所述信号输出电路相连接。
第三方面，本申请实施例中提供了一种滤波器制造的方法，所述滤波器包括：多个谐振器，所述多个谐振器包括多个串联谐振器和多个并联谐振器，所述串联谐振器彼此串联连接，所述并联谐振器一端连接至两个串联谐振器的连接点，另一端连接电感，所述电感接地，所述方法包括：
设置所述多个串联谐振器包括一个或多个指定串联谐振器，所述指定串联谐振器与至少一个第一谐振器并联；
和/或，
所述多个并联谐振器中包括一个或多个指定并联谐振器，所述指定并联谐振器与至少一个第二谐振器或者电容串联；
将所述多个谐振器按照谐振频率的不同分别设置于不同的晶圆上。
可选地，所述方法还包括：
设置所述指定串联谐振器的谐振频率大于所述第一谐振器的谐振频率；
所述将所述多个谐振器按照谐振频率的不同分别设置于不同的晶圆上，包括：
设置所述指定串联谐振器与其他所述串联谐振器设置于第一晶圆上，所述第一谐振器与所述并联谐振器设置于第二晶圆上。
可选地，所述方法还包括：
设置所述指定串联谐振器的反谐振频率与所述第一谐振器的谐振频率之差小于预设值。
可选地，所述方法还包括：
设置所述指定并联谐振器的谐振频率小于所述第二谐振器的谐振频率；
所述将所述多个谐振器按照谐振频率的不同分别设置于不同的晶圆上，包括：
将所述第二谐振器与所述串联谐振器设置于第一晶圆上，所述指定并联谐振器与 其他所述并联谐振器设置于第二晶圆上。
可选地，所述方法还包括：
设置所述指定并联谐振器的反谐振频率与所述第二谐振器的谐振频率之差小于预设值。
可选地，所述方法还包括：
所述指定并联谐振器与电容串联时，将所述电容的一端与相邻两个串联谐振器的节点相连，所述电容的另一端与所述指定并联谐振器的一端相连接，所述指定并联谐振器的另一端与接地电感相连接；
将所述串联谐振器设置于第一晶圆上，所述第一谐振器和所述电容、所述指定并联谐振器和其他所述并联谐振器设置于第二晶圆上
本申请实施例所提供的一种滤波器及提高滤波器性能的方法和信号处理设备，通过设置多个串联谐振器包括一个或多个指定串联谐振器，该指定串联谐振器与至少一个第一谐振器并联；和/或，设置多个并联谐振器中包括一个或多个指定并联谐振器，该指定并联谐振器与至少一个第二谐振器或者电容串联；并将多个谐振器按照谐振频率的不同分别设置于不同的晶圆上。使得在保证滤波器的通带插损不变差的同时，使得滚降会变得更好，并且降低了滤波器的尺寸。
附图说明
图1是现有技术中的一种滤波器的结构示意图。
图2是本申请实施例1示出的滤波器的电路结构示意图；
图3是上述实施例1示出的滤波的侧视图；
图4a是上述图2所示的实施例1中上晶圆202的芯片设计示意图；
图4b是上述图2所示的实施例1中下晶圆201的芯片设计示意图；
图5是上述图2所示的实施例1的滤波器的插入损耗与频率关系曲线与现有技术的效果对比示意图；
图6是本申请提供的实施例2的滤波器电路结构示意图；
图7是上述图6所示的实施例2的滤波器的侧视图；
图8a是上述的实施例2中滤波器上晶圆的芯片设计示意；
图8b是上述的实施例2中滤波器下晶圆的芯片设计示意；
图9是本发明实施例3中滤波器的电路结构示意图；
图10是本发明实施例4中滤波器的电路结构示意图；
图11(a)是压电声波谐振器的电学符号；
图11(b)是压电声波谐振器等效电学模型图；
图12示出了谐振器阻抗与fs和fp之间的关系；
图13是一个由两个具有不同谐振频率的谐振器并联连接形成的一个并联组合谐振器Res的示意图；
图14是图13中并联组合谐振器Res、第一谐振器Res1和第一谐振器Res2的阻抗及Kt关系示意图；
图15是一个由两个具有不同谐振频率的谐振器串联连接形成的一个串联组合谐振器Res的结构示意图；
图16是图15中串联组合谐振器Res、第一谐振器Res1和第一谐振器Res2的阻抗及Kt关系示意图。
具体实施方式
这里将详细地对示例性实施例进行说明，其示例表示在附图中。下面的描述涉及附图时，除非另有表示，不同附图中的相同数字表示相同或相似的要素。以下示例性实施例中所描述的实施方式并不代表与本申请相一致的所有实施方式。相反，它们仅是与如所附权利要求书中所详述的、本申请的一些方面相一致的装置和方法的例子。
图1为现有技术中的一种滤波器的结构示意图。参照图1所示，现有技术中的普通梯形结构滤波器包括多个谐振器，该多个谐振器包括第一数量的串联谐振器和第二数量的并联谐振器，图中以包含有4个串联谐振器S1、S2、S3、S4和3个并联谐振器P1、P2、P3为例，并且该滤波器的输入端连接有第一电感，滤波器的输出端连接有第二电感，滤波器的接地端分别连接有第三电感，每个第三电感一端与并联谐振器连接，另一端接地。其中，连接到输入端、输出端的第一电感、第二电感，主要位于封装基板上，并且现有技术中所有的谐振器设置于一个晶圆上的，容易受到晶圆材料的限制，使得该谐振器的性能不能被继续优化。
本申请实施例中提供了一种滤波器，包括：多个谐振器，该多个谐振器包括多个 串联谐振器和多个并联谐振器，串联谐振器彼此串联连接，并联谐振器一端连接至两个串联谐振器的连接点，另一端连接电感，该电感接地，其中，多个串联谐振器包括一个或多个指定串联谐振器，该指定串联谐振器与至少一个第一谐振器并联。
和/或，
上述多个并联谐振器中包括一个或多个指定并联谐振器，该指定并联谐振器与至少一个第二谐振器或者电容串联；
并且上述多个谐振器按照谐振频率的不同分别设置于不同的晶圆上。
上述指定串联谐振器与第一谐振器并联后，可以等效为一个并联组合谐振器。
图13是一个由两个具有不同谐振频率的谐振器并联连接形成的一个并联组合谐振器Res，两个谐振器分别为第一谐振器1和第二谐振器2，其中第一谐振器1的谐振频率大于第二谐振器2的谐振频率，这个频率之间的差异，主要是通过在第二谐振器2上添加质量负载层(Mass load)来实现的。
图14是图13中并联组合谐振器Res、第一谐振器Res1和第一谐振器Res2的阻抗及Kt关系示意图。并联组合谐振器Res1具有谐振频率Fs1和反谐振频率Fp1，第二谐振器Res2具有谐振频率Fs2和反谐振频率Fp2，其中Fs2<Fs1，并且Fp2与Fs1相对比较接近。由于上述这种频率关系，并联组合谐振器Res形成了如图14中的粗实线所示的阻抗特性，它包含4个谐振频率：与Fs1相同的阻抗低点谐振频率Fs3，以及位于Fs1与Fp1之间的反谐振频率Fp3，其中Fp3>Fs3，且Fp3<Fp1。与Fs2相同的阻抗低点谐振频率Fs4，以及位于Fs2与Fp2之间的反谐振频率Fp4，其中Fp4>Fs3，且Fp4<Fp2。并且，并联组合谐振器Res在Fp3处的阻抗值低于谐振器Res1在其反谐振频率Fp1处的阻抗，或者谐振器Res2在其反谐振频率Fp2处的阻抗。组合谐振器Res在Fp4处的阻抗值，又低于其在Fp3处的阻抗值。将组合谐振器Fs3和Fp3处的谐振定义为主谐振，Fs4和Fp4处的谐振定义为次谐振，则相比谐振器Res1，并联组合谐振器Res的主谐振由于Fp3的位置相比Fp1发生了左移，因此主谐振的Kt 2小于谐振器Res1。并且，主谐振的Rp小于谐振器Res1，次谐振器Rp又小于主谐振，而主谐振与次谐振的Rs均与谐振器Res1基本相同。因此，可以将并联组合谐振器Res，看作是一个与谐振器Res1相比，Rs不变，Rp变差，但同时Kt 2变小的谐振器。如果将这个并联组合谐振器放在滤波器的串联位置，则滤波器的通带插损不会变差，同时右侧滚降会变得更好。
进而，本申请上述实施例中，通过设置指定串联谐振器，使该指定串联谐振器与第一谐振器并联，构成如图13所示的并联组合谐振器，可以使得滤波器在保持通带插损不会变差，使得右侧滚降会变得更好。
图2是本发明实施例1的电路结构示意图。参照图2所示，该电路中包含了串联谐振器S2、S3，和指定串联谐振器S1、S4，该指定串联谐振器S1与第一谐振器SP1并联，指定串联谐振器S4与第一谐振器SP4并联；进而相对于图1现有的电路结构，在串联位置的串联谐振器S1，替换成了由指定串联谐振器S1与第一谐振器SP1并联形成的并联组合谐振器，在串联位置的串联谐振器S4，替换成了由指定串联谐振器S4与第一谐振器SP4并联形成的并联组合谐振器。其中谐振器SP1、SP4的谐振频率与并联谐振器P1～P3的谐振频率相同或相近，因此，本实施例中将S1～S4四个谐振器设置在下晶圆201上，而谐振器P1～P3、SP1、SP4做在了上晶圆202上。
分成两个晶圆制作，则可以采用不同的层叠，甚至选择不同的压电材料，从而实现两片晶圆上的Kt 2自由度，即二者可以相同，也可以不同，设计灵活度大大提升。而在现有技术中，由于所有谐振器都是在一片晶圆上同时制作，只能通过质量负载来调节，因此谐振器S1～S4，P1～P3这些谐振器的Kt 2基本相同。
图3是上述图2所示的实施例1的侧视图，参照图3所示，该滤波器中，上晶圆202上设置有并联谐振器P1、P2、P3以及第一谐振器SP1、SP4，下晶圆201上设置有串联谐振器S1、S2、S3、S4；谐振器最下方为基板。
图4a和4b是上述图2所示的实施例1中上晶圆202和下晶圆201的芯片设计示意图，本实施例中在串并联折断的位置(上晶圆和下晶圆连接部位)添加了新的键合区J1、J2和J3，此新的键合区J1、J2和J3只是用来将上晶圆与下晶圆连接在一起，而不需要通过过孔向芯片外部连接，因此其形状都与连接过孔的键合区不同，面积则仅为原来的二分之一。虚线的圆圈则示意出了与就近的晶圆过孔相连的芯片焊球的位置。连接到输入、输出端子的电感，主要位于封装基板上。
图5是上述图2所示的实施例1的滤波器的插入损耗与频率关系曲线与现有技术的效果对比示意图；以作为一个应用于WLAN CH1～CH11的窄带滤波器，通带范围为2402MHz～2472MHz为例，其左右两侧均需要做到较好的滚降特性。
具体的，图中实线为本实施例的滤波器插入损耗与频率关系曲线，虚线为用现有技术设计的插入损耗与频率关系曲线，可见，由于带宽相对较窄，采用现有技术时， 所有的谐振器Kt 2基本一样，而且当Kt 2较小的谐振器的损耗也较差。而采用本发明的实施例1，串并联谐振器分开设计，包括组合谐振器，也分别做在两片晶圆上，因此两片晶圆上谐振器的Kt 2可以不同，且均大于现有技术的谐振器Kt 2，但组合谐振器的Kt 2可以达到更小。正是因为这个特点，实施例中的谐振器损耗特性较好，做成滤波器的插损更好，滚降更快，以左侧滚降为例，从通带2dB插损到40dB抑制的滚降距离，由现有技术的15.5MHz，减少到了12MHz，提高了3.5MHz。并且，由于串并联谐振器的折叠，实现了芯片尺寸的小型化。
图15是一个由两个具有不同谐振频率的谐振器串联连接形成的一个串联组合谐振器Res，两个谐振器分别为第一谐振器1’和第二谐振器2’，其中第一谐振器1’的谐振频率大于第二谐振器2’的谐振频率，该频率之间的差异，主要是通过在第二谐振器2’上添加质量负载层(Mass load)来实现的。一般情况下，第一谐振器1’的反谐振频率与第二谐振器2’的谐振频率比较接近。
图16是图15中串联组合谐振器Res、第一谐振器Res1和第一谐振器Res2的阻抗及Kt关系示意图。第一谐振器Res1具有谐振频率Fs1和反谐振频率Fp1，第二谐振器Res2具有谐振频率Fs2和反谐振频率Fp2，其中Fs2<Fs1，并且Fp2与Fs1相对比较接近。由于上述这种频率关系，串联组合谐振器Res形成了如图16中的粗实线所示的阻抗特性，该阻抗特性包含4个谐振频率：与Fs1相同的阻抗低点谐振频率Fs3，以及位于Fs1与Fp1之间的反谐振频率Fp3，其中Fp3>Fs3，主谐振的反谐振频率Fp3与谐振器1的Fp1相同，Fs3则位于Fs1与Fp3之间，相当于Fs1右移。与Fs2相同的阻抗低点谐振频率Fs4，以及位于Fs2与Fp2之间的反谐振频率Fp4，其中Fp4>Fs3，且Fp4<Fp2。并且，串联组合谐振器Res在Fp3处的阻抗值低于谐振器Res1在其反谐振频率Fp1处的阻抗，或者谐振器Res2在其反谐振频率Fp2处的阻抗。组合谐振器Res在Fp4处的阻抗值，又低于其在Fp3处的阻抗值。将组合谐振器Fs3和Fp3处的谐振定义为主谐振，Fs4和Fp4处的谐振定义为次谐振，则相比谐振器Res1，串联组合谐振器Res的主谐振由于Fp3的位置相比Fp1发生了左移，因此主谐振的Kt 2小于谐振器Res1。并且，主谐振的Rp小于谐振器Res1，次谐振器Rp又小于主谐振，同时，主谐振的Rs差于谐振器Res1，次谐振又差于主谐振，而两个反谐振阻抗则与谐振器Res1基本相同。如果将这个串联组合谐振器放在滤波器的并联位置，则滤波器的通带插损不会变差，同时左侧滚降会变得更好。
进而，本申请上述实施例中，通过设置指定并联谐振器，使该指定并联谐振器与第二谐振器串联，构成如图15所示的串联组合谐振器，可以使得滤波器在保持通带插损不会变差，使得右侧滚降会变得更好。
图6是本申请提供的实施例2的电路结构示意图，参照图6所示，与现有技术不同的是，本实施例中将并联位置的部分谐振器，替换为组合谐振器，并且做在两片晶圆上。
具体的，参照图6所示，该滤波器中包括串联谐振器S1、S2、S3、S4，和并联谐振器P1、P2、P3，其中并联谐振器中包含有指定并联谐振器P1、P3，该指定并联谐振器P1、P3分别与第二谐振器PS1、PS3串联，第二谐振器PS1的一端与串联谐振器S1、S2的连接点相连，第二谐振器PS1的另一端与指定并联谐振器P1相连接，该指定并联谐振器还与电感相连接，该电感接地。图7是上述图6所示的实施例2的滤波器的侧视图，参照图7所示，该滤波器中，上晶圆302上设置有并联谐振器P1、P2、P3；下晶圆301上设置有串联谐振器S1、S2、S3、S4以及第二谐振器PS1、PS2最下方为基板。
图8a和8b是上述的实施例2中滤波器上晶圆302和下晶圆301的芯片设计示意图，本实施例中在串并联折断的位置(上晶圆和下晶圆连接部位)添加了新的键合区J1、J2和J3，此新的键合区J1、J2和J3只是用来将上晶圆与下晶圆连接在一起，而不需要通过过孔向芯片外部连接，因此其形状都与连接过孔的键合区不同，面积则仅为原来的二分之一。虚线的圆圈则示意出了与就近的晶圆过孔相连的芯片焊球的位置。
图9是本发明实施例3中滤波器的电路结构示意图，本实施例中串联位置和并联位置均采用了组合谐振器，并且根据谐振器的频率，分别做在两片晶圆上。
具体的，参照图9所示，该滤波器中包括串联谐振器S1、S2、S3、S4，和并联谐振器P1、P2、P3，其中并联谐振器中包含有指定并联谐振器P2，该指定并联谐振器P2与第二谐振器PS2串联，第二谐振器PS2的一端与串联谐振器S2、S3的连接点相连，第二谐振器PS2的另一端与指定并联谐振器P2相连接，该指定并联谐振器P2还与电感相连接，该电感接地。
本实施例中，上述串联谐振器S1、S2、S3、S4，以及第二谐振器PS2设置于下晶圆401上，上述并联谐振器P1、P2、P3，以及第一谐振器SP1、SP4设置于上晶圆402上。
图10是本发明实施例4中滤波器的电路结构示意图，与实施例3不同的是，本电路结构中并联位置的组合谐振器中起辅助作用的谐振器，替换成了制作在晶圆上的电容，这种辅助谐振器替换为电容的组合谐振器，只有一个主谐振，原理与前述相同，但不存在次谐振。
具体的，该滤波器中包括串联谐振器S1、S2、S3、S4，和并联谐振器P1、P2、P3，其中并联谐振器中包含有指定并联谐振器P1、P2，该指定并联谐振器P1、P2分别与电容CP1、CP2串联，电容CP2的一端与串联谐振器S2、S3的连接点相连，电容CP2的另一端与指定并联谐振器P2相连接，该指定并联谐振器P2还与电感相连接，该电感接地；电容CP1的一端与串联谐振器S1、S2和第一谐振器SP1的连接点相连，电容CP1的另一端与指定并联谐振器P1相连接，该指定并联谐振器P1还与电感相连接，该电感接地。
需要说明的是，以上各例将滤波器中各谐振器的谐振频率简化为只有两种，对应附图图示，一种是空白的，一种是加阴影的谐振器。实际上，由于所有谐振器被单独做在两片晶圆上，因此如果在同一片晶圆上添加不同的厚度较薄的质量负载，则可以实现更多种频率的谐振器，提高设计的自由度，从而更好的改善滤波器的匹配、插损和滚降特性。
另外，如果只从缩小Kt 2的角度考虑，也可以在串联位置上使用串联连接的组合谐振器，或者在并联位置上使用并联连接的组合谐振器，但如前面对于谐振阻抗Rs和反谐振阻抗Rp的分析，这样的应用通常会导致滤波器插损变大，因此一般并不采用。
现有技术中，做窄带滤波器，一般需要小的机电耦合系数，但是如果用传统的设计方法，小机电耦合系数的谐振器，存在谐振器性能较差，或者工艺制作尺寸容差特性较差等缺点，因此利用具有不同谐振频率的谐振器组合，可以实现相对较小的机电耦合系数。组合方式可以为串联，或者并联，组合谐振器的位置可以是在串联位置，也可以并联位置。本发明实施例中主要提出了两种结构，一种是在串联位置，用两种频率谐振并联连接形成的组合谐振器，另一种是在并联位置，用两种频率谐振器串联连接形成的组合谐振器。并且，根据谐振器频率的不同，把这些谐振器分开做在上、下两片晶圆上。特别的，组合谐振器中的两个谐振器因为频率不同，分别位于两片晶圆上，一方面降低了谐振器的尺寸，并且提高了性能。
本申请一实施例中还提供了一种信号处理设备，包括：信号输入电路、信号输出电路和如上述任一实施例所述的滤波器；所述信号输入电路与所述滤波器相连接，所述滤波器与所述信号输出电路相连接。
本实施例提供的信号处理设备中，滤波器在在串联位置，用两种频率谐振器并联连接形成的组合谐振器，和/或，在并联位置，用两种频率谐振器串联连接形成的组合谐振器。并且，根据谐振器频率的不同，把这些谐振器分开做在上、下两片晶圆上。特别的，组合谐振器中的两个谐振器因为频率不同，分别位于两片晶圆上，如此一方面降低了设备的尺寸，并且提高了性能。
本申请又一实施例中还提供了一种滤波器制造的方法，用于制造上述任一实施例中所述的滤波器，该滤波器包括：多个谐振器，所述多个谐振器包括多个串联谐振器和多个并联谐振器，所述串联谐振器彼此串联连接，所述并联谐振器一端连接至两个串联谐振器的连接点，另一端连接电感，所述电感接地，所述方法包括：
设置所述多个串联谐振器包括一个或多个指定串联谐振器，所述指定串联谐振器与至少一个第一谐振器并联；
和/或，
所述多个并联谐振器中包括一个或多个指定并联谐振器，所述指定并联谐振器与至少一个第二谐振器或者电容串联；
将所述多个谐振器按照谐振频率的不同分别设置于不同的晶圆上。
可选地，上述方法还包括：
设置所述指定串联谐振器的谐振频率大于所述第一谐振器的谐振频率；
所述将所述多个谐振器按照谐振频率的不同分别设置于不同的晶圆上，包括：
设置所述指定串联谐振器与其他所述串联谐振器设置于第一晶圆上，所述第一谐振器与所述并联谐振器设置于第二晶圆上。
可选地，上述方法还包括：
设置所述指定串联谐振器的反谐振频率与所述第一谐振器的谐振频率之差小于预设值。
可选地，上述方法还包括：
设置所述指定并联谐振器的谐振频率小于所述第二谐振器的谐振频率；
所述将所述多个谐振器按照谐振频率的不同分别设置于不同的晶圆上，包括：
将所述第二谐振器与所述串联谐振器设置于第一晶圆上，所述指定并联谐振器与其他所述并联谐振器设置于第二晶圆上。
可选地，上述方法还包括：
设置所述指定并联谐振器的反谐振频率与所述第二谐振器的谐振频率之差小于预设值。
可选地，上述方法还包括：
所述指定并联谐振器与电容串联时，将所述电容的一端与相邻两个串联谐振器的节点相连，所述电容的另一端与所述指定并联谐振器的一端相连接，所述指定并联谐振器的另一端与接地电感相连接；
将所述串联谐振器设置于第一晶圆上，所述第一谐振器和所述电容、所述指定并联谐振器和其他所述并联谐振器设置于第二晶圆上。
应用本方法所制造的谐振器，具有降低了谐振器的尺寸，并且提高了谐振器性能等的优点。
以上所述仅为本申请的较佳实施例而已，并不用以限制本申请，凡在本申请的精神和原则之内，所做的任何修改、等同替换、改进等，均应包含在本申请保护的范围之内。

Claims (13)

  1. 一种滤波器，包括：多个谐振器，所述多个谐振器包括多个串联谐振器和多个并联谐振器，所述串联谐振器彼此串联连接，所述并联谐振器一端连接至两个串联谐振器的连接点，另一端连接电感，所述电感接地，其特征在于，所述多个串联谐振器包括一个或多个指定串联谐振器，所述指定串联谐振器与至少一个第一谐振器并联；
    和/或，
    所述多个并联谐振器中包括一个或多个指定并联谐振器，所述指定并联谐振器与至少一个第二谐振器或者电容串联；
    所述多个谐振器按照谐振频率的不同分别设置于不同的晶圆上。
  2. 根据权利要求1所述的滤波器，其特征在于，所述指定串联谐振器的谐振频率大于所述第一谐振器的谐振频率；
    所述指定串联谐振器与其他所述串联谐振器设置于第一晶圆上，所述第一谐振器与所述并联谐振器设置于第二晶圆上。
  3. 根据权利要求1或2所述的滤波器，其特征在于，所述指定串联谐振器的反谐振频率与所述第一谐振器的谐振频率之差小于预设值。
  4. 根据权利要求1所述的滤波器，其特征在于，所述指定并联谐振器的谐振频率小于所述第二谐振器的谐振频率；
    所述第二谐振器与所述串联谐振器设置于第一晶圆上，所述指定并联谐振器与其他所述并联谐振器设置于第二晶圆上。
  5. 根据权利要求4所述的滤波器，其特征在于，所述指定并联谐振器的反谐振频率与所述第二谐振器的谐振频率之差小于预设值。
  6. 根据权利要求1所述的滤波器，其特征在于，所述指定并联谐振器与电容串联时，所述电容的一端与相邻两个串联谐振器的节点相连，所述电容的另一端与所述指定并联谐振器的一端相连接，所述指定并联谐振器的另一端与接地电感相连接；
    所述串联谐振器设置于第一晶圆上，所述第一谐振器和所述电容、所述指定并联谐振器和其他所述并联谐振器设置于第二晶圆上。
  7. 一种信号处理设备，其特征在于，包括：信号输入电路、信号输出电路和如权利要求1-6中任一项所述的滤波器；所述信号输入电路与所述滤波器相连接，所述滤波器与所述信号输出电路相连接。
  8. 一种滤波器制造的方法，所述滤波器包括：多个谐振器，所述多个谐振器包括多个串联谐振器和多个并联谐振器，所述串联谐振器彼此串联连接，所述并联谐振器一端连接至两个串联谐振器的连接点，另一端连接电感，所述电感接地，其特征在于，所述方法包括：
    设置所述多个串联谐振器包括一个或多个指定串联谐振器，所述指定串联谐振器与至少一个第一谐振器并联；
    和/或，
    所述多个并联谐振器中包括一个或多个指定并联谐振器，所述指定并联谐振器与至少一个第二谐振器或者电容串联；
    将所述多个谐振器按照谐振频率的不同分别设置于不同的晶圆上。
  9. 根据权利要求8所述的方法，其特征在于，还包括：
    设置所述指定串联谐振器的谐振频率大于所述第一谐振器的谐振频率；
    所述将所述多个谐振器按照谐振频率的不同分别设置于不同的晶圆上，包括：
    设置所述指定串联谐振器与其他所述串联谐振器设置于第一晶圆上，所述第一谐振器与所述并联谐振器设置于第二晶圆上。
  10. 根据权利要求8或9所述的方法，其特征在于，还包括：
    设置所述指定串联谐振器的反谐振频率与所述第一谐振器的谐振频率之差小于预设值。
  11. 根据权利要求8所述的方法，其特征在于，还包括：
    设置所述指定并联谐振器的谐振频率小于所述第二谐振器的谐振频率；
    所述将所述多个谐振器按照谐振频率的不同分别设置于不同的晶圆上，包括：
    将所述第二谐振器与所述串联谐振器设置于第一晶圆上，所述指定并联谐振器与其他所述并联谐振器设置于第二晶圆上。
  12. 根据权利要求11所述的方法，其特征在于，还包括：
    设置所述指定并联谐振器的反谐振频率与所述第二谐振器的谐振频率之差小于预 设值。
  13. 根据权利要求8所述的方法，其特征在于，还包括：
    所述指定并联谐振器与电容串联时，将所述电容的一端与相邻两个串联谐振器的节点相连，所述电容的另一端与所述指定并联谐振器的一端相连接，所述指定并联谐振器的另一端与接地电感相连接；
    将所述串联谐振器设置于第一晶圆上，所述第一谐振器和所述电容、所述指定并联谐振器和其他所述并联谐振器设置于第二晶圆上。
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