WO2021135342A1 - 横向扩散金属氧化物半导体器件及其制备方法 - Google Patents

横向扩散金属氧化物半导体器件及其制备方法 Download PDF

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Publication number
WO2021135342A1
WO2021135342A1 PCT/CN2020/113361 CN2020113361W WO2021135342A1 WO 2021135342 A1 WO2021135342 A1 WO 2021135342A1 CN 2020113361 W CN2020113361 W CN 2020113361W WO 2021135342 A1 WO2021135342 A1 WO 2021135342A1
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Prior art keywords
conductivity type
region
field plate
drift region
floating field
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English (en)
French (fr)
Inventor
赵景川
张志丽
张森
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CSMC Technologies Fab2 Co Ltd
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CSMC Technologies Fab2 Co Ltd
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Priority to JP2022538131A priority Critical patent/JP7408813B2/ja
Priority to KR1020227024644A priority patent/KR102707263B1/ko
Priority to US17/789,628 priority patent/US12272749B2/en
Publication of WO2021135342A1 publication Critical patent/WO2021135342A1/zh
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/65—Lateral DMOS [LDMOS] FETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0221—Manufacture or treatment of FETs having insulated gates [IGFET] having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended-drain MOSFETs [EDMOS]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
    • H10D30/0281—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of lateral DMOS [LDMOS] FETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/601—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs 
    • H10D30/603—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs  having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/109—Reduced surface field [RESURF] PN junction structures
    • H10D62/111—Multiple RESURF structures, e.g. double RESURF or 3D-RESURF structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/124—Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
    • H10D62/126—Top-view geometrical layouts of the regions or the junctions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/111—Field plates
    • H10D64/112—Field plates comprising multiple field plate segments
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/111—Field plates
    • H10D64/115—Resistive field plates, e.g. semi-insulating field plates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/111—Field plates
    • H10D64/117—Recessed field plates, e.g. trench field plates or buried field plates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/01—Manufacture or treatment
    • H10D62/051—Forming charge compensation regions, e.g. superjunctions
    • H10D62/058—Forming charge compensation regions, e.g. superjunctions by using trenches, e.g. implanting into sidewalls of trenches or refilling trenches
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/514—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the insulating layers
    • H10D64/516—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the insulating layers the thicknesses being non-uniform

Definitions

  • the present invention relates to the field of semiconductor technology, in particular to a laterally diffused metal oxide semiconductor device and a preparation method thereof.
  • the field plate technology is a relatively common structure, that is, the introduction of vertical Floating field plate structure to reduce the on-resistance of the device while increasing the withstand voltage of the device.
  • the deep groove in the vertical floating field plate structure is located in the conductive channel of the device, the conductive path in the drift zone is reduced, and the current flow path during the device operation is blocked, so that the device still has a higher on-resistance. That is, the existing laterally diffused metal oxide semiconductor device can only reduce the on-resistance of the device to a certain extent by introducing the vertical floating field plate structure, and the reduction range is limited.
  • the present invention provides a laterally diffused metal oxide semiconductor device, including:
  • the drift zone of the second conductivity type is located in the substrate of the first conductivity type, and the first conductivity type is opposite to the second conductivity type;
  • the longitudinal floating field plate array includes a plurality of longitudinal floating field plate structures arranged in multiple rows and multiple columns at intervals.
  • the row direction of the longitudinal floating field plate array is the length direction of the conductive channel, and the column direction is the The width direction of the conductive channel;
  • the vertical floating field plate structure includes a dielectric layer provided on the inner surface of the trench and a conductive layer filled in the trench, and the trench drifts from the second conductivity type The surface of the region penetrates the drift region of the second conductivity type and extends into the substrate of the first conductivity type;
  • a plurality of injection regions of the first conductivity type are located in the drift region of the second conductivity type, and are located between two adjacent longitudinal floating field plate structures in each row.
  • the present invention also provides a method for manufacturing a laterally diffused metal oxide semiconductor device, which includes the following steps:
  • a vertical floating field plate array is formed in the drift zone of the second conductivity type, and the vertical floating field plate array includes a plurality of vertical floating field plate structures arranged in multiple rows and multiple columns at intervals.
  • the empty field plate structure includes a dielectric layer provided on the inner surface of the trench and a conductive layer filled in the trench.
  • the trench penetrates the drift region of the second conductivity type from the surface of the drift region of the second conductivity type. The region extends into the substrate of the first conductivity type; the injection region of the first conductivity type is located between the two adjacent vertical floating field plate structures in each row.
  • FIG. 1 shows a flowchart of a method for manufacturing a laterally diffused metal oxide semiconductor device provided in an embodiment of the present invention
  • step S10 shows a schematic cross-sectional structure diagram of the structure obtained in step S10 in the method for manufacturing a laterally diffused metal oxide semiconductor device provided in an embodiment of the present invention
  • step S11 shows a schematic cross-sectional structure diagram of the structure obtained in step S11 in the method for manufacturing a laterally diffused metal oxide semiconductor device provided in an embodiment of the present invention
  • step S12 is a schematic diagram of the three-dimensional structure of the structure obtained in step S12 in the method for manufacturing a laterally diffused metal oxide semiconductor device provided in an embodiment of the present invention
  • Fig. 5 is a schematic cross-sectional structure diagram of Fig. 4;
  • FIG. 6 is a schematic diagram showing the three-dimensional structure of the structure obtained in step S13 in the method for fabricating a laterally diffused metal oxide semiconductor device provided in an embodiment of the present invention
  • FIG. 7 is a schematic diagram of the cross-sectional structure of FIG. 6;
  • FIG. 8 is a schematic diagram showing a cross-sectional structure of the structure obtained in step S14 in the method for manufacturing a laterally diffused metal oxide semiconductor device provided in an embodiment of the present invention
  • step S15 is a schematic diagram showing a cross-sectional structure of the structure obtained in step S15 in the method for manufacturing a laterally diffused metal oxide semiconductor device provided in an embodiment of the present invention.
  • FIG. 10 is a schematic diagram showing a cross-sectional structure of the structure obtained in step S16 in the method for manufacturing a laterally diffused metal oxide semiconductor device provided in an embodiment of the present invention
  • FIG. 11 is a schematic diagram showing a cross-sectional structure of the structure obtained in step S17 in the method for fabricating a laterally diffused metal oxide semiconductor device provided in an embodiment of the present invention
  • FIG. 12 is a schematic diagram of the three-dimensional structure of the structure obtained in step S18 in the method for fabricating a laterally diffused metal oxide semiconductor device provided in an embodiment of the present invention.
  • FIG. 13 is a schematic diagram showing the cross-sectional structure of FIG. 12;
  • step S18 is a schematic diagram of the overall top view of the structure obtained in step S18 to step S20 in the method for fabricating a laterally diffused metal oxide semiconductor device according to an embodiment of the present invention
  • Fig. 15 shows an enlarged schematic diagram of area A in Fig. 14;
  • 16 is a schematic diagram of a three-dimensional structure of a structure obtained in a method for fabricating a laterally diffused metal oxide semiconductor device provided in another embodiment of the present invention.
  • FIG. 17 is a schematic diagram of the cross-sectional structure of FIG. 16.
  • the present invention provides a method for fabricating a laterally diffused metal oxide semiconductor device, which includes the following steps:
  • S13 forming a longitudinal floating field plate array in the drift zone of the second conductivity type, the longitudinal floating field plate array including a plurality of longitudinal floating field plate structures arranged in multiple rows and multiple columns at intervals, the
  • the vertical floating field plate structure includes a dielectric layer provided on the inner surface of the trench and a conductive layer filled in the trench.
  • the trench penetrates the second conductive layer from the surface of the drift region of the second conductivity type.
  • the drift region of the first conductivity type extends into the substrate of the first conductivity type; the injection region of the first conductivity type is located between the two adjacent vertical floating field plate structures in each row.
  • the vertical floating field plate structure penetrates the drift region of the second conductivity type from the surface of the drift region of the second conductivity type and extends into the substrate of the first conductivity type, so that the surface of the metal oxide semiconductor device and The substrate of the first conductivity type has an equipotential effect, and the potential at the bottom of the vertical floating field plate structure is limited by the surface, thereby improving the stability of the device; the drift of the conductive layer in the vertical floating field plate structure and the second conductivity type There is a certain thickness of the dielectric layer between the first conductivity type and the first conductivity type substrate, so that the charge between the doped ions in the second conductivity type drift region and the vertical floating field plate structure is more easily balanced, and the peak value of the electric field distribution varies from The boundary between the substrate of the first conductivity type and the drift region of the second conductivity type is transferred to the bottom of the vertical floating field plate structure in the substrate of the first conductivity type, which can effectively prevent the device from prematurely hitting during the reverse withstand voltage.
  • a super junction can be formed between two adjacent columns of vertical floating field plate structures Structure, the injection area of the first conductivity type and the vertical floating field plate structure work together to deplete the auxiliary device. While increasing the withstand voltage of the device, the current capability of the device is improved, and the on-resistance of the device is reduced; and each row is adjacent to the longitudinal direction.
  • the conductivity type of the injection region between the floating field plate structures is opposite to the conductivity type of the drift region of the second conductivity type, which is equivalent to adding the charge of the first conductivity type to the non-conducting path of the circuit, so that the second conductivity type is
  • the doping concentration in the drift region can be increased, thereby further reducing the on-resistance of the device.
  • the substrate 101 of the first conductivity type provided in step S10 includes a substrate with a high resistivity.
  • the substrate 101 of the first conductivity type may include but is not limited to A silicon substrate of the first conductivity type, a gallium nitride substrate of the first conductivity type, or a silicon germanium substrate of the first conductivity type, and so on.
  • an ion implantation process may be used to perform ion implantation of the second conductivity type in the substrate 101 of the first conductivity type, so that a partial area of the substrate 101 of the first conductivity type
  • the inversion is the second conductivity type, and serves as the drift region 102 of the second conductivity type; the depth of the drift region 102 of the second conductivity type is smaller than the thickness of the substrate 101 of the first conductivity type.
  • step S12 may include the following steps: implanting ions of the first conductivity type into the drift region 102 of the second conductivity type once to implant the ions of the second conductivity type into the drift region 102 of the second conductivity type.
  • An injection region 103 of the first conductivity type is formed in 102.
  • the number of the injection regions 103 of the first conductivity type is several, and the plurality of injection regions 103 of the first conductivity type may be arranged in an array of multiple rows and columns, that is, the plurality of injection regions 103 of the first conductivity type may be arranged in multiple rows. Multiple columns are arranged at intervals.
  • the column direction of the plurality of implanted regions 103 of the first conductivity type is the width direction of the conductive channel of the subsequently formed device, and the row direction is the length direction of the conductive channel of the subsequently formed device.
  • a plurality of injection regions 103 of the first conductivity type are arranged at equal intervals, that is, a plurality of injection regions 103 of the first conductivity type are arranged at equal intervals along the row direction and the column direction.
  • the depth of the implanted region 103 of the first conductivity type is smaller than the depth of the drift region 102 of the second conductivity type.
  • step S12 may include the following steps:
  • a patterned mask layer (not shown) is formed on the surface of the drift region 102 of the second conductivity type, an opening pattern is formed in the patterned mask layer, and the opening pattern exposes the drift region 102 of the second conductivity type, and the opening
  • the figure defines the shape and position of the injection region 103 of the first conductivity type
  • S122 Perform one ion implantation on the drift region 102 of the second conductivity type based on the patterned mask layer, and form a plurality of implanted regions 103 of the first conductivity type after high temperature push-up.
  • the implanted region 103 of the first conductivity type is located on the upper part of the drift region 102 of the second conductivity type, and the top of the implanted region 103 of the first conductivity type may be the same as that of the drift region 102 of the second conductivity type.
  • the upper surface is flush. As shown in FIGS. 4 to 5, the top surface of the implanted region 103 of the first conductivity type and the upper surface of the drift region 102 of the second conductivity type may be spaced apart.
  • the implanted region 103 of the first conductivity type may also be located in the middle of the drift region 102 of the second conductivity type.
  • the implanted region 103 of the first conductivity type may also be located at the lower part of the drift region 102 of the second conductivity type, and the bottom of the implanted region 103 of the first conductivity type is connected to the drift region of the second conductivity type.
  • the lower surface of 102 has a pitch.
  • the depth of the implanted region 103 of the first conductivity type can be controlled by the energy of ion implantation, that is, the greater the depth of the implanted region 103 of the first conductivity type, the greater the ion implantation energy required. .
  • step S13 may include the following steps:
  • S131 forming a plurality of trenches (not shown) arranged at intervals in multiple rows and multiple columns in the drift region 102 of the second conductivity type, the row direction of the trenches is the length direction of the subsequently formed conductive channel, and the column direction is The width direction of the subsequently formed conductive structure; the surface of the drift region 102 of the second conductivity type of the trench penetrates the drift region 102 of the second conductivity type and extends into the substrate 101 of the first conductivity type;
  • a conductive layer 1042 is formed on the surface of the dielectric layer 1041, and the conductive layer 1042 fills the trench.
  • step S131 specifically, a photolithography and etching process may be used to form the trench.
  • a thermal oxidation process can be used to form an oxide layer (for example, a silicon oxide layer, etc.) on the inner surface of the trench as the dielectric layer 1041; of course, physical vapor deposition can also be used in other examples.
  • the dielectric layer 1041 is formed by a process, a chemical vapor deposition process, or an atomic layer deposition process.
  • the dielectric layer 1041 may also be a nitride layer or an oxynitride layer or the like.
  • a physical vapor deposition process, a chemical vapor deposition process, or an atomic layer deposition process may be used to form the conductive layer 1042.
  • the conductive layer 1042 may include, but is not limited to, a doped polysilicon layer.
  • the conductive layer 1042 and the dielectric layer 1041 together constitute the vertical floating field plate structure 104.
  • the longitudinal floating field plate structure 104 is alternately arranged with the injection regions 103 of the first conductivity type; the width of the injection regions 103 of the first conductivity type ( That is, the size of the injection region 103 of the first conductivity type in the column direction) is less than or equal to the width of the floating field plate structure 104 (the size of the floating field plate structure 104 in the column direction).
  • the width of the injection region 103 of the first conductivity type is less than or equal to the width of the vertical floating field plate structure 104, which can ensure that the injection region 103 of the first conductivity type will not hinder the electron transfer when the subsequently formed device is turned on. flow.
  • a plurality of longitudinal floating field plate structures 104 are arranged at equal intervals along the row direction and the column direction.
  • the number of vertical floating field plate structures 104 in each row is equal to the number of columns of the vertical floating field plate array, and the number of vertical floating field plate structures 104 in each column is equal to the number of rows of the vertical floating field plate array; That is, two adjacent rows of floating field plate structures 104 are arranged in one-to-one correspondence instead of dislocation, and two adjacent columns of floating field plate structures 104 are arranged in one-to-one correspondence instead of being dislocated.
  • the conductive layer 1042 needs to penetrate the drift region 102 of the second conductivity type from the surface of the drift region 102 of the second conductivity type, and extend into the substrate 101 of the first conductivity type, so that the surface of the finally formed device It has the same potential as the substrate 101 of the first conductivity type, thereby improving the stability of the device.
  • step S12 can be interchanged with step S13, that is, in other examples, the vertical floating field plate array structure can be formed in the drift region 102 of the second conductivity type before the second conductivity type drift region 102.
  • An implanted region 103 of the first conductivity type is formed in the drift region 102 of the second conductivity type.
  • the “floating” in the vertical floating field plate structure 104 means that the vertical floating field plate structure 104 is not connected to a potential.
  • step S13 the following steps are further included:
  • a well region 105 of the first conductivity type is formed on the side of the drift region 102 of the second conductivity type, and a well region 106 of the second conductivity type is formed in the drift region 102 of the second conductivity type.
  • the region 106 is located on the side of the vertical floating field plate array away from the well region 105 of the first conductivity type, and has a distance from the vertical floating field plate array, as shown in FIG. 8;
  • the drift buffer area can increase the on-state breakdown voltage of the LDMOS device when working in the forward direction; the well region 105 of the first conductivity type is used as the conductive channel formation region of the device, and its concentration will affect the drift region 102 of the second conductivity type. Depletion and turn-on voltage.
  • S17 Form a source region 110 and a body region of the first conductivity type (that is, the lead-out region of the substrate 101 of the first conductivity type) 109 in the well region 105 of the first conductivity type, and in the well region 106 of the second conductivity type A drain region 111 is formed inside; the source region 110 has a distance from the drift region 102 of the second conductivity type, and the body region 109 of the first conductivity type is located on the side of the source region 110 away from the vertical floating field plate array and is in contact with the source region 110 , As shown in Figure 11;
  • S20 A plurality of conductive equipotential strips 112 are formed on the field oxide layer 107, and each conductive equipotential strip 112 extends along the width direction of the conductive channel and passes through the conductive structure 113 and a row of vertical floating field plate structures 104 located below it. Electrical connection, as shown in Figure 12 to Figure 13.
  • an ion implantation process may be used to form the well region 105 of the first conductivity type and the well region 106 of the second conductivity type; the depth of the well region 105 of the first conductivity type may be equal to the drift of the second conductivity type.
  • the depth of the region 102, the depth of the well region 106 of the second conductivity type is smaller than the depth of the drift region 102 of the second conductivity type.
  • the field oxide layer 107 can be formed by, but not limited to, a thermal oxidation process.
  • the gate 108 formed in step S16 may include, but is not limited to, a polysilicon gate.
  • the gate 108 may include a doped polysilicon gate.
  • an ion implantation process may be used to form the source region 110, the drain region 111, and the body region 109.
  • the body region 109 is a region of the first conductivity type
  • the source region 110 is a region of the second conductivity type
  • the drain region 111 is a region of the second conductivity type; more specifically, the body region 109, the source region 110, and the drain region 111 are all Is a heavily doped region
  • the substrate 101 of the first conductivity type, the drift region 102 of the second conductivity type, the implanted region 103 of the first conductivity type, the well region 105 of the first conductivity type, and the well region of the second conductivity type 106 are lightly doped regions;
  • the so-called “heavy doped regions” refers to the regions where the doping concentration is greater than or equal to 1 ⁇ 10 18 atom/cm 3
  • the so-called “lightly doped regions” refers to the doping concentration less than or equal to 1 ⁇ 10 18 atom/c
  • FIG. 12 is a schematic diagram of the cross-sectional structure of FIG. 12 along the Y direction.
  • the material of the conductive equipotential strip 112 and the conductive structure 113 may be metal, specifically, aluminum, copper, gold, nickel, or the like.
  • the spacing between two adjacent rows of conductive equipotential strips 112 is equal, that is, the column spacing of each conductive equipotential strip 112 is equal, and the column spacing is equal, so that two adjacent longitudinal floating field plate structures 104 can be spaced between each other.
  • the capacitance can be regarded as equal.
  • the conductive equipotential strip 112 is an equipotential ring enclosing a racetrack structure on the layout, as shown in FIG. 14 each conductive equipotential strip 112, the injection region 103 of the first conductivity type, and the longitudinal floating field
  • the slab structures 104 are all located in the runway area 20.
  • the longitudinal floating field plate structures 104 are arranged side by side.
  • the present invention also provides a method for fabricating a laterally diffused metal oxide semiconductor device.
  • the laterally diffused metal oxide semiconductor The manufacturing method of the device is roughly the same as the manufacturing method of the laterally diffused metal oxide semiconductor device shown in FIGS. 1 to 15 in the above embodiment, and the difference between the two is only in step S12: the lateral direction shown in FIGS.
  • step S12 of the method for manufacturing a diffused metal oxide semiconductor device only one ion implantation of the first conductivity type is performed in the drift region 102 of the second conductivity type, and the depth of the formed implantation region 103 of the first conductivity type is reduced; and
  • the first conductivity type ions are implanted multiple times in the drift region 102 of the second conductivity type, so as to form a plurality of ions along the second conductivity type in the drift region 102 of the second conductivity type.
  • multiple sub-implantation regions 1031 of the first conductivity type are formed by performing multiple sub-implantation, which can better assist the depletion of the drift region 102 of the second conductivity type, as compared to the figure
  • the schemes 1 to 15 can further improve the performance of the device.
  • the depth of the implanted region 103 of the first conductivity type is also smaller than the depth of the drift region 102 of the second conductivity type.
  • a plurality of sub-injection regions 1031 of the first conductivity type arranged along the depth direction of the drift region 102 of the second conductivity type may be serially connected in sequence, or may be arranged at intervals.
  • the first conductivity type may be P-type, and the second conductivity type may be N-type; in another example, the first conductivity type is also It may be N-type, and the second conductivity type may be P-type.
  • the present invention also provides a laterally diffused metal oxide semiconductor device, including: a substrate 101 of a first conductivity type; a drift region 102 of a second conductivity type, The drift region 102 of the second conductivity type is located in the substrate 101 of the first conductivity type, and the first conductivity type is opposite to the second conductivity type; the vertical floating field plate array, the vertical floating field plate array includes a plurality of rows and rows.
  • the vertical floating field plate structure 104 is arranged at intervals.
  • the row direction of the vertical floating field plate structure 104 is the length direction of the conductive channel, and the column direction is the width direction of the conductive channel; the vertical floating field plate structure 104 includes a device The dielectric layer 1041 on the inner surface of the trench (not shown) and the conductive layer 1042 filled in the trench.
  • the trench penetrates the drift region 102 of the second conductivity type from the surface of the drift region 102 of the second conductivity type and extends to the second conductivity type drift region 102.
  • a substrate 101 of one conductivity type a plurality of injection regions 103 of the first conductivity type, the injection regions 103 of the first conductivity type are located in the drift region 102 of the second conductivity type, and are located in two adjacent vertical floating field plates in each row Structure 104 between.
  • the vertical floating field plate structure 104 penetrates the drift region 102 of the second conductivity type from the surface of the drift region 102 of the second conductivity type and extends into the substrate 101 of the first conductivity type, so that the metal oxide is diffused laterally.
  • the surface of the semiconductor device and the substrate 101 of the first conductivity type are equipotential, and the potential at the bottom of the vertical floating field plate structure 104 is limited by the surface, thereby improving the stability of the device; the conductive layer in the vertical floating field plate structure 104
  • the charge between 104 is more easily balanced, and the peak of the electric field distribution is transferred from the junction of the first conductivity type substrate 101 and the second conductivity type drift region 102 to the vertical floating field plate in the first conductivity type substrate 101
  • the bottom of the structure 104 can effectively prevent the device from breaking down in the reverse withstand voltage; by forming the first conductivity type implantation in the second conductivity type drift region 102 between each row of adjacent vertical floating field plate structures 104
  • the region 103 can form
  • the injection region 103 of the first conductivity type and the vertical floating field plate structure 104 work together to deplete the auxiliary device and improve the device While withstanding voltage, the current capability of the device is improved, and the on-resistance of the device is reduced; and the conductivity type of the injection region between each row of adjacent vertical floating field plate structures 104 is opposite to the conductivity type of the drift region 102 of the second conductivity type , which is equivalent to adding the charge of the first conductivity type to the non-conducting path of the circuit, so that the doping concentration in the drift region 102 of the second conductivity type can be increased, thereby further reducing the on-resistance of the device.
  • the row direction is the X direction shown in FIG. 12, and the column direction is the Z direction shown in FIG. 12, that is, the X direction is the conductive groove of the device.
  • the length direction of the track, the Z direction is the width direction of the conductive channel of the device, and the Y direction is the vertical direction of the device;
  • FIG. 13 is a schematic diagram of the cross-sectional structure of FIG. 12 along the Y direction.
  • the substrate 101 of the first conductivity type includes a substrate with high resistivity.
  • the substrate 101 of the first conductivity type may include, but is not limited to, a silicon substrate of the first conductivity type, and a first conductivity type.
  • the depth of the drift region 102 of the second conductivity type is smaller than the thickness of the substrate 101 of the first conductivity type.
  • a plurality of injection regions 103 of the first conductivity type are arranged at equal intervals, that is, a plurality of injection regions 103 of the first conductivity type are arranged at equal intervals along the row direction and the column direction.
  • the depth of the implanted region 103 of the first conductivity type is smaller than the depth of the drift region 102 of the second conductivity type.
  • the implanted region 103 of the first conductivity type is located on the upper part of the drift region 102 of the second conductivity type, and the top of the implanted region 103 of the first conductivity type may be the same as that of the drift region 102 of the second conductivity type.
  • the upper surface is flush.
  • the top of the implanted region 103 of the first conductivity type is spaced from the upper surface of the drift region 102 of the second conductivity type.
  • the implanted region 103 of the first conductivity type may also be located in the middle of the drift region 102 of the second conductivity type.
  • the implanted region 103 of the first conductivity type may also be located at the lower part of the drift region 102 of the second conductivity type, and the bottom of the implanted region 103 of the first conductivity type is connected to the drift region of the second conductivity type.
  • the lower surface of 102 has a pitch.
  • the depth of the implanted region 103 of the first conductivity type can be controlled by the energy of ion implantation, that is, the greater the depth of the implanted region 103 of the first conductivity type, the greater the ion implantation energy required. .
  • the dielectric layer 1041 may include but is not limited to an oxide layer, such as a silicon oxide layer, etc.; in other examples, the dielectric layer 1041 may also include a nitride layer or an oxide layer.
  • the conductive layer 1042 may include, but is not limited to, a doped polysilicon layer.
  • the vertical floating field plate structure 104 is alternately arranged with the injection regions 103 of the first conductivity type; the width of the injection regions 103 of the first conductivity type (that is, the injection regions 103 of the first conductivity type are arranged along the The size in the column direction) is less than or equal to the width of the floating field plate structure 104 (the size of the floating field plate structure 104 in the column direction).
  • the width of the injection region 103 of the first conductivity type is less than or equal to the width of the vertical floating field plate structure 104, which can ensure that the injection region 103 of the first conductivity type will not hinder the electron transfer when the subsequently formed device is turned on. flow.
  • a plurality of longitudinal floating field plate structures 104 are arranged at equal intervals along the row direction and the column direction.
  • the number of vertical floating field plate structures 104 in each row is equal to the number of columns of the vertical floating field plate array, and the number of vertical floating field plate structures 104 in each column is equal to the number of rows of the vertical floating field plate array; That is, two adjacent rows of floating field plate structures 104 are arranged in one-to-one correspondence instead of being arranged in a one-to-one correspondence, and two adjacent rows of floating field plate structures 104 are arranged in one-to-one correspondence instead of being arranged in a one-to-one correspondence.
  • the conductive layer 1042 needs to penetrate the drift region 102 of the second conductivity type from the surface of the drift region 102 of the second conductivity type, and extend into the substrate 101 of the first conductivity type, so that the surface of the finally formed device It has the same potential as the substrate 101 of the first conductivity type, thereby improving the stability of the device.
  • the “floating” in the vertical floating field plate structure 104 means that the vertical floating field plate structure 104 is not connected to a potential.
  • the laterally diffused metal oxide semiconductor device further includes: a well region 105 of the first conductivity type.
  • the well region 105 of the first conductivity type is located on the side of the drift region 102 of the second conductivity type and is connected to the second conductivity type.
  • the drift region 102 contacts; the second conductivity type well region 106, the second conductivity type well region 106 is located in the second conductivity type drift region 102, and is located in the vertical floating field plate array away from the first conductivity type well region 105 side, with a distance from the vertical floating field plate array; source region 110, the source region 110 is located in the first conductivity type well region 105, and has a distance from the second conductivity type drift region 102; drain region 111, drain The region 111 is located in the well region 106 of the second conductivity type; the body region 109 of the first conductivity type, and the body region 109 of the first conductivity type is located in the well region 105 of the first conductivity type, and is located in the source region 110 away from the longitudinal direction.
  • the field oxide layer 107, the field oxide layer 107 is located on the drift region 102 of the second conductivity type, and covers the vertical floating field plate array; the gate 108, the gate The pole 108 extends from the first conductivity type well region 105 to the surface of the field oxide layer 107.
  • the drift buffer area of the drain region 111 of the well region 106 of the second conductivity type can increase the on-state breakdown voltage of the LDMOS device when working in the forward direction; the well region 105 of the first conductivity type serves as the conductive channel formation region of the device. The concentration will affect the depletion and turn-on voltage of the drift region 102 of the second conductivity type.
  • the depth of the well region 105 of the first conductivity type may be equal to the depth of the drift region 102 of the second conductivity type, and the depth of the well region 106 of the second conductivity type is smaller than the depth of the drift region 102 of the second conductivity type.
  • the gate 108 may include, but is not limited to, a polysilicon gate.
  • the gate 108 may include a doped polysilicon gate.
  • the body region 109 is a region of the first conductivity type
  • the source region 110 is a region of the second conductivity type
  • the drain region 111 is a region of the second conductivity type; more specifically, the body region 109, the source region 110, and the drain region
  • the regions 111 are all heavily doped regions, and the substrate 101 of the first conductivity type, the drift region 102 of the second conductivity type, the implanted region 103 of the first conductivity type, the well region 105 of the first conductivity type, and the second conductivity type
  • the well regions 106 are lightly doped regions; the so-called “heavy doped regions” refers to regions with a doping concentration greater than or equal to 1 ⁇ 10 18 atom/cm 3 , and the so-called “lightly doped regions” refers to regions with a doping concentration less than or An area equal to 1 ⁇ 10 18 atom/cm 3 .
  • the laterally diffused metal oxide semiconductor device further includes several conductive equipotential strips 112, the conductive equipotential strips 112 are located on the field oxide layer 107; each conductive equipotential strip 112 extends along the width direction of the conductive channel, and The conductive structure 113 penetrating the field oxide layer 107 from the surface of the field oxide layer 107 is electrically connected to a row of vertical floating field plate structures 104 located thereunder.
  • the conductive equipotential strip 112 by providing the conductive equipotential strip 112, and the conductive equipotential strip 112 is electrically connected to a row of vertical floating field plate structure 104 located below it, two adjacent conductive equipotential strips 112 can be regarded as a pair of parallel plate capacitors. , The potential difference is a constant, and the withstand voltage of the device can increase as the vertical floating field plate structure 104 increases.
  • the material of the conductive equipotential strip 112 and the conductive structure 113 may be metal, specifically, aluminum, copper, gold, nickel, or the like.
  • the spacing between two adjacent rows of conductive equipotential strips 112 is equal, that is, the column spacing of each conductive equipotential strip 112 is equal, and the column spacing is equal, so that two adjacent longitudinal floating field plate structures 104 can be spaced between each other.
  • the capacitance can be regarded as equal.
  • the conductive equipotential strips 112 are connected end to end to form an equipotential ring of the racetrack structure, as shown in FIG. 14 for each conductive equipotential strip 112, the injection region 103 of the first conductivity type, and the longitudinal floating field.
  • the slab structures 104 are all located in the runway area 20.
  • the longitudinal floating field plate structures 104 are arranged side by side.
  • the present invention also provides a method for fabricating a laterally diffused metal oxide semiconductor device.
  • the laterally diffused metal oxide semiconductor The device is roughly the same as the laterally diffused metal oxide semiconductor device shown in FIGS. 12 to 15 in the above embodiment, and the difference between the two is only: the laterally diffused metal oxide semiconductor device shown in FIGS. 12 to 15 is only in the first embodiment.
  • the first conductivity type ion implantation is performed once in the second conductivity type drift region 102, and the depth of the first conductivity type implantation region 103 is reduced; however, in this embodiment, the second conductivity type drift region 102 is more frequently implanted.
  • the drift region 102 of the second conductivity type is formed with a plurality of sub-implanted regions 1031 of the first conductivity type arranged along the depth direction of the drift region 102 of the second conductivity type.
  • the implanted region 103 of the first conductivity type is formed by performing multiple sub-implantation, which can better assist the depletion of the drift region 102 of the second conductivity type, as compared to the figure
  • the schemes 1 to 15 can further improve the performance of the device.
  • the depth of the implanted region 103 of the first conductivity type is also smaller than the depth of the drift region 102 of the second conductivity type.
  • a plurality of sub-injection regions 1031 of the first conductivity type arranged along the depth direction of the drift region 102 of the second conductivity type may be serially connected in sequence, or may be arranged at intervals.
  • the first conductivity type may be P-type, and the second conductivity type may be N-type; in another example, the first conductivity type may also be N-type.
  • Type, and the second conductivity type may be P type.
  • FIGS. 4 to 13, FIG. 16 and FIG. 17 is changed to have a number of omitted injection regions 103 of the first conductivity type and a number of vertical floating field plates. Structure 104.

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Abstract

一种横向扩散金属氧化物半导体器件及其制备方法，包括：第一导电类型的衬底（101）；第二导电类型的漂移区（102），位于第一导电类型的衬底内；纵向浮空场板阵列，包括若干个呈多行多列间隔排布的纵向浮空场板结构（104）；纵向浮空场板结构包括设于沟槽内表面的介质层（1041）及填充于沟槽内的导电层（1042），沟槽从第二导电类型的漂移区贯穿第二导电类型的漂移区并延伸至第一导电类型的衬底内；若干个第一导电类型的注入区域（103），位于第二导电类型的漂移区内，且位于各行相邻两纵向浮空场板结构之间。纵向浮空场板结构从第二导电类型的漂移区表面贯穿第二导电类型的漂移区并延伸至第一导电类型的衬底内，使得纵向浮空场板结构底部的电势被表面限制，从而提高了器件的稳定性。

Description

横向扩散金属氧化物半导体器件及其制备方法
相关申请
本申请要求2019年12月31日申请的，申请号为201911418234.7，名称为“横向扩散金属氧化物半导体器件及其制备方法”的中国专利申请的优先权，在此将其全文引入作为参考。
技术领域
本发明涉及半导体技术领域，特别是涉及一种横向扩散金属氧化物半导体器件及其制备方法。
背景技术
对于横向扩散金属氧化物半导体(LDMOS)器件，为了提高器件的击穿电压(BV)，降低导通电阻RDS(on)，场板技术是一种较为常见的结构，即在漂移区内引入纵向浮空场板结构，以在提高器件耐压的同时降低其导通电阻。但是，由于纵向浮空场板结构中的深槽位于器件的导电沟道内，漂移区内的导电路径减少，器件工作时的电流流通的路径被阻挡，使得器件仍具有较高的导通电阻，即现有的横向扩散金属氧化物半导体器件通过引入纵向浮空场板结构只能一定程度的降低器件的导通电阻，降低幅度有限。
发明内容
基于此，有必要提供一种具有新型的场板结构的横向扩散金属氧化物半导体器件及其制备方法，以提高器件的击穿电压并进一步降低器件的导通电阻。
为实现上述目的，本发明提供一种横向扩散金属氧化物半导体器件，包括：
第一导电类型的衬底；
第二导电类型的漂移区，位于所述第一导电类型的衬底内，所述第一导电类型和第二导电类型相反；
纵向浮空场板阵列，包括若干个呈多行多列间隔排布的纵向浮空场板结构，所述纵向浮空场板阵列的行方向为导电沟道的长度方向，列方向为所述导电沟道的宽度方向；所述纵向浮空场板结构包括设于沟槽内表面的介质层及填充于所述沟槽内的导电层，所述沟槽从所述第二导电类型的漂移区表面贯穿所述第二导电类型的漂移区并延伸至所述第一导电类型的衬底内；
若干个第一导电类型的注入区域，位于所述第二导电类型的漂移区内，且位于各行相邻两所述纵向浮空场板结构之间。
本发明还提供一种横向扩散金属氧化物半导体器件的制备方法，包括如下步骤：
提供第一导电类型的衬底；
于所述第一导电类型的衬底内形成第二导电类型的漂移区；
于所述第二导电类型的漂移区内形成第一导电类型的注入区域；
于所述第二导电类型的漂移区内形成纵向浮空场板阵列，所述纵向浮空场板阵列包括若干个呈多行多列间隔排布的纵向浮空场板结构，所述纵向浮空场板结构包括设于沟槽内表面的介质层及填充于所述沟槽内的导电层，所述沟槽从所述第二导电类型的漂移区表面贯穿所述第二导电类型的漂移区并延伸至所述第一导电类型的衬底内；所述第一导电类型的注入区域位于各行相邻两所述纵向浮空场板结构之间。
本申请的一个或多个实施例的细节在下面的附图和描述中提出。本申请的其他特征、目的和优点将从说明书、附图以及权利要求书变得明显。
附图说明
为了更好地描述和说明这里公开的那些发明的实施例和/或示例，可以参考一幅或多幅附图。用于描述附图的附加细节或示例不应当被认为是对所公开的发明、目前描述的实施例和/或示例以及目前理解的这些发明的最佳模式中的任何一者的范围的限制。
图1显示为本发明一个实施例中提供的横向扩散金属氧化物半导体器件的制备方法的流程图；
图2显示为本发明一个实施例中提供的横向扩散金属氧化物半导体器件的制备方法中步骤S10所得结构的截面结构示意图；
图3显示为本发明一个实施例中提供的横向扩散金属氧化物半导体器件的制备方法中步骤S11所得结构的截面结构示意图；
图4显示为本发明一个实施例中提供的横向扩散金属氧化物半导体器件的制备方法中步骤S12所得结构的立体结构示意图；
图5显示为图4的截面结构示意图；
图6显示为本发明一个实施例中提供的横向扩散金属氧化物半导体器件的制备方法中步骤S13所得结构的立体结构示意图；
图7显示为图6的截面结构示意图；
图8显示为本发明一个实施例中提供的横向扩散金属氧化物半导体器件的制备方法中步骤S14所得结构的截面结构示意图；
图9显示为本发明一个实施例中提供的横向扩散金属氧化物半导体器件的制备方法中步骤S15所得结构的截面结构示意图；
图10显示为本发明一个实施例中提供的横向扩散金属氧化物半导体器件的制备方法中步骤S16所得结构的截面结构示意图；
图11显示为本发明一个实施例中提供的横向扩散金属氧化物半导体器件的制备方法中步骤S17所得结构的截面结构示意图；
图12显示为本发明一个实施例中提供的横向扩散金属氧化物半导体器件的制备方法中步骤S18所得结构的立体结构示意图；
图13显示为图12的截面结构示意图；
图14显示为本发明一个实施例中提供的横向扩散金属氧化物半导体器件的制备方法中步骤S18至步骤S20所得结构的整体俯视结构示意图；
图15显示为图14中A区域的放大示意图；
图16显示为本发明另一个实施例中提供的横向扩散金属氧化物半导体器件的制备方法中所得结构的立体结构示意图；
图17显示为图16的截面结构示意图。
具体实施方式
为了便于理解本发明，下面将参照相关附图对本发明进行更全面的描述。附图中给出了本发明的首选实施例。但是，本发明可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使对本发明的公开内容更加透彻全面。
除非另有定义，本文所使用的所有的技术和科学术语与属于本发明的技术领域的技术人员通常理解的含义相同。本文中在本发明的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本发明。本文所使用的术语“及/或”包括一个或多个相关的所列项目的任意的和所有的组合。
在一个实施例中，请参阅图1,本发明提供一种横向扩散金属氧化物半导体器件的制备方法，包括如下步骤：
S10：提供第一导电类型的衬底；
S11：于所述第一导电类型的衬底内形成第二导电类型的漂移区；
S12：于所述第二导电类型的漂移区内形成第一导电类型的注入区域；
S13：于所述第二导电类型的漂移区内形成纵向浮空场板阵列，所述纵向浮空场板阵列包括若干个呈多行多列间隔排布的纵向浮空场板结构，所述纵向浮空场板结构包括设于沟槽内表面的介质层及填充于所述沟槽内的导电层，所述沟槽从所述第二导电类型的漂移区的表面贯穿所述第二导电类型的漂移区并延伸至所述第一导电类型的衬底内；所述第一导电类型的注入区域位于各行相邻两所述纵向浮空场板结构之间。
在上述示例中，纵向浮空场板结构从第二导电类型的漂移区表面贯穿第二导电类型的漂移区并延伸至第一导电类型的衬底内，使得横向扩散金属氧化物半导体器件表面和第一导电类型的衬底存在等势作用，纵向浮空场板结构底部的电势被表面限制，从而提高了器件的稳定性；纵向浮空场板结构中的导电层与第二导电类型的漂移区及第一导电类型的衬底之间具有一定厚度的介质层，这样第二导电类型的漂移区内的掺杂离子和纵向浮空场板结构之间的电荷更易平衡，电场分布的峰值从第一导电类型的衬底与第二导电类型的漂移区的交界处转移至第一导电类型的衬底中的纵向浮 空场板结构的底部，可以有效避免器件在反向耐压时提前击穿；通过在各行相邻纵向浮空场板结构之间的第二导电类型的漂移区内形成第一导电类型的注入区域，可以在相邻两列纵向浮空场板结构之间形成超结结构，第一导电类型的注入区域与纵向浮空场板结构共同作用，辅助器件耗尽，在提高器件耐压的同时，提高器件的电流能力，降低器件的导通电阻；又各行相邻纵向浮空场板结构之间的注入区域的导电类型与第二导电类型的漂移区的导电类型相反，相当于在电路不导通的路径增加了第一导电类型的电荷，使得第二导电类型的漂移区内的掺杂浓度可以得到提升，从而进一步降低了器件的导通电阻。
在一个示例中，如图2所示，步骤S10中提供的第一导电类型的衬底101包括高电阻率的衬底，具体的，所述第一导电类型的衬底101可以包括但不仅限于第一导电类型的硅衬底、第一导电类型的氮化镓衬底或第一导电类型的锗硅衬底等等。
在一个示例中，如图3所示，可以采用离子注入工艺在第一导电类型的衬底101内进行第二导电类型的离子注入，以使得所述第一导电类型的衬底101的部分区域反型为第二导电类型，以作为第二导电类型的漂移区102；第二导电类型的漂移区102的深度小于第一导电类型的衬底101的厚度。
在一个示例中，如图4及图5所示，步骤S12可以包括如下步骤：于第二导电类型的漂移区102内进行一次第一导电类型离子的注入，以于第二导电类型的漂移区102内形成第一导电类型的注入区域103。第一导电类型的注入区域103的数量为若干个，若干个第一导电类型的注入区域103可以呈多行多列的阵列排布，即若干个第一导电类型的注入区域103可以呈多行多列的间隔排布。具体的，若干个第一导电类型的注入区域103的列方向为后续形成的器件的导电沟道的宽度方向，行方向为后续形成的器件的导电沟道的长度方向。
在一个示例中，若干个第一导电类型的注入区域103等间距间隔排布，即若干个第一导电类型的注入区域103沿行方向及列方向均等间距间隔排布。
在一个示例中，第一导电类型的注入区域103的深度小于第二导电类型的漂移区102的深度。
具体的，步骤S12可以包括如下步骤：
S121：于第二导电类型的漂移区102表面形成图形化掩膜层(未示出)，图形化掩膜层内形成有开口图形，开口图形暴露出第二导电类型的漂移区102，且开口图形定义出第一导电类型的注入区域103的形状及位置；
S122：基于图形化掩膜层对第二导电类型的漂移区102进行一次离子注入，经高温推结后形成若干个第一导电类型的注入区域103；
S123：去除图形化掩膜层。
在一个可选地示例中，第一导电类型的注入区域103位于第二导电类 型的漂移区102的上部，且第一导电类型的注入区域103的顶部可以与第二导电类型的漂移区102的上表面相平齐，如图4至图5所示，也可以为第一导电类型的注入区域103的顶部与第二导电类型的漂移区102的上表面具有间距。
在另一个可选地示例中，第一导电类型的注入区域103还可以位于第二导电类型的漂移区102的中部。
在又一个可选地示例中，第一导电类型的注入区域103还可以位于第二导电类型的漂移区102的下部，且第一导电类型的注入区域103的底部与第二导电类型的漂移区102的下表面具有间距。
需要说明的是，在上述示例中，可以通过离子注入的能量来控制第一导电类型的注入区域103的深度，即第一导电类型的注入区域103的深度越大所需的离子注入能量越大。
在一个示例中，如图6至图7所示，步骤S13可以包括如下步骤：
S131：于第二导电类型的漂移区102内形成若干个多行多列间隔排布的沟槽(未标示出)，沟槽的行方向为后续形成的导电沟道的长度方向，列方向为后续形成的导电结构的宽度方向；沟槽第二导电类型的漂移区102表面贯穿第二导电类型的漂移区102并延伸至第一导电类型的衬底101内；
S132：于沟槽的内表面(即侧壁及底部)形成介质层1041；
S133：于介质层1041的表面形成导电层1042，导电层1042填满沟槽。
具体的，步骤S131中，具体的，可以采用光刻及刻蚀工艺形成沟槽。
具体的，步骤S132中，可以采用但不仅限于热氧化工艺于沟槽的内表面形成氧化层(譬如，氧化硅层等等)作为介质层1041；当然，在其他示例中也可以采用物理气相沉积工艺、化学气相沉积工艺或原子层沉积工艺等形成介质层1041，介质层1041也可以为氮化物层或氮氧化物层等等。
具体的，步骤S133中可以采用物理气相沉积工艺、化学气相沉积工艺或原子层沉积工艺形成导电层1042，导电层1042可以包括但不仅限于掺杂多晶硅层。导电层1042与介质层1041共同构成纵向浮空场板结构104。
在一个示例中，形成纵向浮空场板结构104之后，沿行方向，纵向浮空场板结构104与第一导电类型的注入区域103交替排布；第一导电类型的注入区域103的宽度(即第一导电类型的注入区域103沿列方向的尺寸)小于或等于浮空场板结构104的宽度(浮空场板结构104沿列方向的尺寸)。
在上述示例中，第一导电类型的注入区域103的宽度小于或等于纵向浮空场板结构104的宽度，可以确保第一导电类型的注入区域103不会阻碍后续形成的器件导通时电子的流动。
在一个示例中，纵向浮空场板阵列中，若干个纵向浮空场板结构104沿行方向及列方向均等间距间隔排布。
在一个示例中，各行中纵向浮空场板结构104的数量等于纵向浮空场板阵列的列数，各列中纵向浮空场板结构104的数量等于纵向浮空场板阵 列的行数；即相邻两行浮空场板结构104一一对应设置而并非错位排布，且相邻两列浮空场板结构104一一对应设置而并非错位排布。
需要说明的是，导电层1042需从第二导电类型的漂移区102表面贯穿第二导电类型的漂移区102,并延伸至第一导电类型的衬底101内，以使得最终形成的器件的表面和第一导电类型的衬底101等电势，从而提高了器件的稳定性。
需要进一步说明的是，在其他示例中，步骤S12可以与步骤S13互换，即在其他示例中也可以先于第二导电类型的漂移区102内形成纵向浮空场板阵列结构，再于第二导电类型的漂移区102内形成第一导电类型的注入区域103。
需要更进一步说明的是，纵向浮空场板结构104中的“浮空”表示纵向浮空场板结构104不外接电位。
在一个可选的示例中，如图8至图11，步骤S13之后还包括如下步骤：
S14：于第二导电类型的漂移区102一侧形成第一导电类型的阱区105，并于第二导电类型的漂移区102内形成第二导电类型的阱区106，第二导电类型的阱区106位于纵向浮空场板阵列远离第一导电类型的阱区105一侧，且与纵向浮空场板阵列具有间距，如图8所示；第二导电类型的阱区106漏区111的漂移缓冲区，可以提高LDMOS器件在正向工作时的开态击穿电压；第一导电类型的阱区105作为器件的导电沟道形成区域，其浓度将影响第二导电类型的漂移区102的耗尽和导通电压。
S15：于第二导电类型的漂移区102上形成场氧化层107，场氧化层107覆盖纵向浮空场板阵列，如图9所示；
S16：于第一导电类型的阱区105上及场氧化层107上形成栅极108，栅极108自第一导电类型的阱区105延伸至场氧化层107的表面，如图10所示；
S17：于第一导电类型的阱区105内形成源区110及第一导电类型的体区(即第一导电类型的衬底101的引出区)109，并于第二导电类型的阱区106内形成漏区111；源区110与第二导电类型的漂移区102具有间距，第一导电类型的体区109位于源区110远离纵向浮空场板阵列的一侧，并与源区110接触，如图11所示；
S18：于场氧化层107内形成若干个互连孔(未标示出)，互连孔与纵向浮空场板结构104一一对应设置，且暴露出各纵向浮空场板结构104中的导电层1042；
S19：于互连孔内形成导电结构113；
S20：于场氧化层107上形成若干条导电等势条112，各导电等势条112均沿导电沟道宽度方向延伸，且通过导电结构113与位于其下方的一列纵向浮空场板结构104电连接，如图12至图13所示。
具体的，在步骤S14中，可以采用离子注入工艺形成第一导电类型的阱区105及第二导电类型的阱区106；第一导电类型的阱区105的深度可 以等于第二导电类型的漂移区102的深度，第二导电类型的阱区106的深度小于第二导电类型的漂移区102的深度。
具体的，步骤S15中，可以采用但不仅限于热氧化工艺形成场氧化层107。
具体的，步骤S16中形成的栅极108可以包括但不仅限于多晶硅栅极，具体的，栅极108可以包括掺杂多晶硅栅极。
具体的，步骤S17中，可以采用离子注入工艺形成源区110、漏区111及体区109。体区109为第一导电类型的区域，源区110为第二导电类型的区域，漏区111为第二导电类型的区域；更为具体的，体区109、源区110及漏区111均为重掺杂区域，而第一导电类型的衬底101、第二导电类型的漂移区102、第一导电类型的注入区域103、第一导电类型的阱区105及第二导电类型的阱区106均为轻掺杂区域；所谓“重掺杂区域”是指掺杂浓度大于等于1×10 18atom/cm 3的区域，所谓“轻掺杂区域”是指掺杂浓度小于或等于1×10 18atom/cm 3的区域。
需要说明的是，如图12所示，上述示例中，行方向均为图12中所示的X方向，列方向均为图12中所示的Z方向，即X方向为器件的导电沟道的长度方向，Z方向为器件的导电沟道的宽度方向，Y方向为器件的竖直方向；图13为图12沿Y方向的截面结构示意图。
在一个示例中，导电等势条112及导电结构113的材料均可以为金属，具体的，可以为铝、铜、金或镍等等。
在一个示例中，相邻两列导电等势条112的间距相等，即各导电等势条112的列间距相等，列间距相等，可以使得相邻的两个纵向浮空场板结构104之间的电容可以看成是相等的。
在一个示例中，导电等势条112在版图上为围成跑道结构的等势环，如图14中所示的各导电等势条112、第一导电类型的注入区域103及纵向浮空场板结构104均位于跑道区域20内。
在一个示例中，如图15所示，各纵向浮空场板结构104并排设置。
在另一个实施例中，请结合图1至图15继续参阅图16至图17，本发明还提供一种横向扩散金属氧化物半导体器件的制备方法，本实施例中的横向扩散金属氧化物半导体器件的制备方法与上述实施例中图1至图15所示的横向扩散金属氧化物半导体器件的制备方法大致相同，二者的区别仅在于步骤S12不同：如图1至图15所示的横向扩散金属氧化物半导体器件的制备方法中的步骤S12仅于第二导电类型的漂移区102内进行一次第一导电类型离子的注入，形成的第一导电类型的注入区域103的深度减小；而本实施例中的步骤S12中于第二导电类型的漂移区102内进行多次第一导电类型离子的注入，以于第二导电类型的漂移区102内形成包括若干个沿第二导电类型的漂移区102的深度方向排布的第一导电类型的子注入区域1031的所述第一导电类型的注入区域103。在本实施例中，通过进行多次子注入形成多个排布的第一导电类型的子注入区域1031，可以更好的辅 助第二导电类型的漂移区102的耗尽，相较于如图1至图15的方案，可以进一步提升器件的性能。在该实施例中，第一导电类型的注入区域103的深度同样要小于第二导电类型的漂移区102的深度。
在一个示例中，若干个沿第二导电类型的漂移区102的深度方向排布的第一导电类型的子注入区域1031可以依次串接，也可以间隔排布。
在上述各横向扩散金属氧化物半导体器件的制备方法中，在一个示例中，第一导电类型可以为P型，且第二导电类型可以为N型；在另一个示例中，第一导电类型也可以为N型，且第二导电类型可以为P型。
在又一个实施例中，请继续参阅图12至图15，本发明还提供一种横向扩散金属氧化物半导体器件，包括：第一导电类型的衬底101；第二导电类型的漂移区102，第二导电类型的漂移区102位于第一导电类型的衬底101内，第一导电类型和第二导电类型相反；纵向浮空场板阵列，纵向浮空场板阵列包括若干个呈多行多列间隔排布的纵向浮空场板结构104，纵向浮空场板结构104的行方向为导电沟道的长度方向，列方向为导电沟道的宽度方向；纵向浮空场板结构104包括设于沟槽(未标示出)内表面的介质层1041及填充于沟槽内的导电层1042，沟槽从第二导电类型的漂移区102表面贯穿第二导电类型的漂移区102并延伸至第一导电类型的衬底101内；若干个第一导电类型的注入区域103，第一导电类型的注入区域103位于第二导电类型的漂移区102内，且位于各行相邻两纵向浮空场板结构104之间。
在上述示例中，纵向浮空场板结构104从第二导电类型的漂移区102表面贯穿第二导电类型的漂移区102并延伸至第一导电类型的衬底101内，使得横向扩散金属氧化物半导体器件表面和第一导电类型的衬底101存在等势作用，纵向浮空场板结构104底部的电势被表面限制，从而提高了器件的稳定性；纵向浮空场板结构104中的导电层1042与第二导电类型的漂移区102及第一导电类型的衬底101之间具有一定厚度的介质层1041，这样第二导电类型的漂移区102内的掺杂离子和纵向浮空场板结构104之间的电荷更易平衡，电场分布的峰值从第一导电类型的衬底101与第二导电类型的漂移区102的交界处转移至第一导电类型的衬底101中的纵向浮空场板结构104的底部，可以有效避免器件在反向耐压时提前击穿；通过在各行相邻纵向浮空场板结构104之间的第二导电类型的漂移区102内形成第一导电类型的注入区域103，可以在相邻两列纵向浮空场板结构104之间形成超结结构，第一导电类型的注入区域103与纵向浮空场板结构104共同作用，辅助器件耗尽，在提高器件耐压的同时，提高器件的电流能力，降低器件的导通电阻；又各行相邻纵向浮空场板结构104之间的注入区域的导电类型与第二导电类型的漂移区102的导电类型相反，相当于在电路不导通的路径增加了第一导电类型的电荷，使得第二导电类型的漂移区102内的掺杂浓度可以得到提升，从而进一步降低了器件的导通电阻。
需要说明的是，如图12所示，本实施例中，行方向均为图12中所示 的X方向，列方向均为图12中所示的Z方向，即X方向为器件的导电沟道的长度方向，Z方向为器件的导电沟道的宽度方向，Y方向为器件的竖直方向；图13为图12沿Y方向的截面结构示意图。
在一个示例中，第一导电类型的衬底101包括高电阻率的衬底，具体的，所述第一导电类型的衬底101可以包括但不仅限于第一导电类型的硅衬底、第一导电类型的氮化镓衬底或第一导电类型的锗硅衬底等等。
在一个示例中，第二导电类型的漂移区102的深度小于第一导电类型的衬底101的厚度。
在一个示例中，若干个第一导电类型的注入区域103等间距间隔排布，即若干个第一导电类型的注入区域103沿行方向及列方向均等间距间隔排布。
在一个示例中，第一导电类型的注入区域103的深度小于第二导电类型的漂移区102的深度。
在一个可选地示例中，第一导电类型的注入区域103位于第二导电类型的漂移区102的上部，且第一导电类型的注入区域103的顶部可以与第二导电类型的漂移区102的上表面相平齐，如图12至图13所示，也可以为第一导电类型的注入区域103的顶部与第二导电类型的漂移区102的上表面具有间距。
在另一个可选地示例中，第一导电类型的注入区域103还可以位于第二导电类型的漂移区102的中部。
在又一个可选地示例中，第一导电类型的注入区域103还可以位于第二导电类型的漂移区102的下部，且第一导电类型的注入区域103的底部与第二导电类型的漂移区102的下表面具有间距。
需要说明的是，在上述示例中，可以通过离子注入的能量来控制第一导电类型的注入区域103的深度，即第一导电类型的注入区域103的深度越大所需的离子注入能量越大。
在一个示例中，介质层1041可以包括但不仅限于氧化层，譬如氧化硅层等等；在其他示例中，介质层1041也可以包括氮化物层或但氧化物层。
在一个示例中，导电层1042可以包括但不仅限于掺杂多晶硅层。
在一个示例中，沿行方向，纵向浮空场板结构104与第一导电类型的注入区域103交替排布；第一导电类型的注入区域103的宽度(即第一导电类型的注入区域103沿列方向的尺寸)小于或等于浮空场板结构104的宽度(浮空场板结构104沿列方向的尺寸)。
在上述示例中，第一导电类型的注入区域103的宽度小于或等于纵向浮空场板结构104的宽度，可以确保第一导电类型的注入区域103不会阻碍后续形成的器件导通时电子的流动。
在一个示例中，纵向浮空场板阵列中，若干个纵向浮空场板结构104沿行方向及列方向均等间距间隔排布。
在一个示例中，各行中纵向浮空场板结构104的数量等于纵向浮空场 板阵列的列数，各列中纵向浮空场板结构104的数量等于纵向浮空场板阵列的行数；即相邻两行浮空场板结构104一一对应设置而并非错位排布，且相邻两列浮空场板结构104一一对应设置而并非错位排布。
需要说明的是，导电层1042需从第二导电类型的漂移区102表面贯穿第二导电类型的漂移区102,并延伸至第一导电类型的衬底101内，以使得最终形成的器件的表面和第一导电类型的衬底101等电势，从而提高了器件的稳定性。
需要进一步说明的是，纵向浮空场板结构104中的“浮空”表示纵向浮空场板结构104不外接电位。
在一个示例中，横向扩散金属氧化物半导体器件还包括：第一导电类型的阱区105，第一导电类型的阱区105位于第二导电类型的漂移区102一侧，且与第二导电类型的漂移区102接触；第二导电类型的阱区106，第二导电类型的阱区106位于第二导电类型的漂移区102内，且位于纵向浮空场板阵列远离第一导电类型的阱区105一侧，与纵向浮空场板阵列具有间距；源区110，源区110位于第一导电类型的阱区105内，且与第二导电类型的漂移区102具有间距；漏区111，漏区111位于第二导电类型的阱区106内；第一导电类型的体区109，第一导电类型的体区109位于第一导电类型的阱区105内，且位于源区110远离所述纵向浮空场板阵列的一侧，并与源区110接触；场氧化层107，场氧化层107位于第二导电类型的漂移区102上，且覆盖纵向浮空场板阵列；栅极108，栅极108自第一导电类型阱区105延伸至场氧化层107的表面。第二导电类型的阱区106漏区111的漂移缓冲区，可以提高LDMOS器件在正向工作时的开态击穿电压；第一导电类型的阱区105作为器件的导电沟道形成区域，其浓度将影响第二导电类型的漂移区102的耗尽和导通电压。
在一个示例中，第一导电类型的阱区105的深度可以等于第二导电类型的漂移区102的深度，第二导电类型的阱区106的深度小于第二导电类型的漂移区102的深度。
在一个示例中，栅极108可以包括但不仅限于多晶硅栅极，具体的，栅极108可以包括掺杂多晶硅栅极。
具体的，体区109为第一导电类型的区域，源区110为第二导电类型的区域，漏区111为第二导电类型的区域；更为具体的，体区109、源区110及漏区111均为重掺杂区域，而第一导电类型的衬底101、第二导电类型的漂移区102、第一导电类型的注入区域103、第一导电类型的阱区105及第二导电类型的阱区106均为轻掺杂区域；所谓“重掺杂区域”是指掺杂浓度大于等于1×10 18atom/cm 3的区域，所谓“轻掺杂区域”是指掺杂浓度小于或等于1×10 18atom/cm 3的区域。
在一个示例中，横向扩散金属氧化物半导体器件还包括若干条导电等势条112，导电等势条112位于场氧化层107上；各导电等势条112均沿导电沟道宽度方向延伸，且通过从场氧化层107的表面贯穿场氧化层107 的导电结构113与位于其下方的一列纵向浮空场板结构104电连接。
在上述示例中，通过设置导电等势条112，且导电等势条112与位于其下方的一列纵向浮空场板结构104电连接，相邻两导电等势条112可以看成一对平行板电容，其电势差为一个常数，器件的耐压可以随纵向浮空场板结构104的增加而增加。
在一个示例中，导电等势条112及导电结构113的材料均可以为金属，具体的，可以为铝、铜、金或镍等等。
在一个示例中，相邻两列导电等势条112的间距相等，即各导电等势条112的列间距相等，列间距相等，可以使得相邻的两个纵向浮空场板结构104之间的电容可以看成是相等的。
在一个示例中，导电等势条112两两首尾连接围成跑道结构的等势环，如图14中所示的各导电等势条112、第一导电类型的注入区域103及纵向浮空场板结构104均位于跑道区域20内。
在一个示例中，如图15所示，各纵向浮空场板结构104并排设置。
在又一个实施例中，请结合图12至图15继续参阅图16至图17，本发明还提供一种横向扩散金属氧化物半导体器件的制备方法，本实施例中的横向扩散金属氧化物半导体器件与上述实施例中图12至图15所示的横向扩散金属氧化物半导体器件大致相同，二者的区别仅在于：如图12至图15所示的横向扩散金属氧化物半导体器件仅于第二导电类型的漂移区102内进行一次第一导电类型离子的注入，形成的第一导电类型的注入区域103的深度减小；而本实施例中于第二导电类型的漂移区102内进行多次第一导电类型离子的注入，第二导电类型的漂移区102内形成有包括若干个沿第二导电类型的漂移区102的深度方向排布的第一导电类型的子注入区域1031的所述第一导电类型的注入区域103。在本实施例中，通过进行多次子注入形成多个排布的第一导电类型的子注入区域1031，可以更好的辅助第二导电类型的漂移区102的耗尽，相较于如图1至图15的方案，可以进一步提升器件的性能。在该实施例中，第一导电类型的注入区域103的深度同样要小于第二导电类型的漂移区102的深度。
在一个示例中，若干个沿第二导电类型的漂移区102的深度方向排布的第一导电类型的子注入区域1031可以依次串接，也可以间隔排布。
在上述各横向扩散金属氧化物半导体器件中，在一个示例中，第一导电类型可以为P型，且第二导电类型可以为N型；在另一个示例中，第一导电类型也可以为N型，且第二导电类型可以为P型。
需要说明的是，在上述各实施例中，图4至图13、图16及图17中的省略号标示改成有若干个省略的第一导电类型的注入区域103及若干个纵向浮空场板结构104。
以上所述实施例仅表达了本发明的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做 出若干变形和改进，这些都属于本发明的保护范围。因此，本发明专利的保护范围应以所附权利要求为准。

Claims (15)

  1. 一种横向扩散金属氧化物半导体器件，包括：
    第一导电类型的衬底；
    第二导电类型的漂移区，位于所述第一导电类型的衬底内，所述第一导电类型和第二导电类型相反；
    纵向浮空场板阵列，包括若干个呈多行多列间隔排布的纵向浮空场板结构，所述纵向浮空场板阵列的行方向为导电沟道的长度方向，列方向为所述导电沟道的宽度方向；所述纵向浮空场板结构包括设于沟槽内表面的介质层及填充于所述沟槽内的导电层，所述沟槽从所述第二导电类型的漂移区表面贯穿所述第二导电类型的漂移区并延伸至所述第一导电类型的衬底内；及
    若干个第一导电类型的注入区域，位于所述第二导电类型的漂移区内，且位于各行相邻两所述纵向浮空场板结构之间。
  2. 根据权利要求1所述的横向扩散金属氧化物半导体器件，其特征在于，所述第一导电类型的注入区域的宽度小于或等于所述纵向浮空场板结构的宽度。
  3. 根据权利要求1所述的横向扩散金属氧化物半导体器件，其特征在于，所述纵向浮空场板阵列中，若干个所述纵向浮空场板结构沿行方向及列方向均等间距间隔排布。
  4. 根据权利要求1所述的横向扩散金属氧化物半导体器件，其特征在于，所述第一导电类型的注入区域的深度小于所述第二导电类型的漂移区的深度。
  5. 根据权利要求1所述的横向扩散金属氧化物半导体器件，其特征在于，所述第一导电类型的注入区域包括若干个沿所述第二导电类型的漂移区的深度方向排布的第一导电类型的子注入区域。
  6. 根据权利要求1所述的横向扩散金属氧化物半导体器件，其特征在于，所述第一导电类型的注入区域位于所述第二导电类型的漂移区的上部，且所述第一导电类型的注入区域的顶部与所述第二导电类型的漂移区的上表面相平齐或与所述第二导电类型的漂移区的上表面具有间距；或所述第一导电类型的注入区域位于所述第二导电类型的漂移区的中部；或所述第一导电类型的注入区域位于所述第二导电类型的漂移区的下部，且所述第一导电类型的注入区域的底部与所述第二导电类型的漂移区的下表面具有间距。
  7. 根据权利要求1所述的横向扩散金属氧化物半导体器件，其特征在于，各行中所述纵向浮空场板结构的数量等于所述纵向浮空场板阵列的列数，各列中所述纵向浮空场板结构的数量等于所述纵向浮空场板阵列的行数。
  8. 根据权利要求1所述的横向扩散金属氧化物半导体器件，其特征在于，还包括：
    第一导电类型的阱区，位于所述第一导电类型的衬底内，且与所述第二导电类型的漂移区邻接；
    第二导电类型的阱区，位于所述第二导电类型的漂移区内，且位于所述纵向浮空场板阵列远离所述第一导电类型的阱区一侧，与所述纵向浮空场板阵列具有间距；
    源区，位于所述第一导电类型的阱区内，且与所述第二导电类型的漂移区具有间距；
    漏区，位于所述第二导电类型的阱区内；
    第一导电类型的体区，位于所述第一导电类型的阱区内，且位于所述源区远离所述纵向浮空场板阵列的一侧，并与所述源区接触；
    场氧化层，位于所述第二导电类型的漂移区上，且覆盖所述纵向浮空场板阵列；
    栅极，跨设在所述源区和所述第一导电类型阱区上并延伸至所述场氧化层的表面。
  9. 根据权利要求8所述的横向扩散金属氧化物半导体器件，其特征在于，还包括若干条设于所述场氧化层上的导电等势条；各所述导电等势条均沿所述导电沟道宽度方向延伸，且通过贯穿所述场氧化层的导电结构与位于其下方的一列所述纵向浮空场板结构电连接。
  10. 根据权利要求9所述的横向扩散金属氧化物半导体器件，其特征在于，各所述导电等势条在版图上为围成跑道结构的等势环。
  11. 根据权利要求9所述的横向扩散金属氧化物半导体器件，其特征在于，相邻两列所述导电等势条的间距相等。
  12. 一种横向扩散金属氧化物半导体器件的制备方法，包括如下步骤：
    提供第一导电类型的衬底；
    于所述第一导电类型的衬底内形成第二导电类型的漂移区；
    于所述第二导电类型的漂移区内形成第一导电类型的注入区域；
    于所述第二导电类型的漂移区内形成纵向浮空场板阵列，所述纵向浮空场板阵列包括若干个呈多行多列间隔排布的纵向浮空场板结构，所述纵向浮空场板结构包括设于沟槽内表面的介质层及填充于所述沟槽内的导电层，所述沟槽从所述第二导电类型的漂移区表面贯穿所述第二导电类型的漂移区并延伸至所述第一导电类型的衬底内；所述第一导电类型的注入区域位于各行相邻两所述纵向浮空场板结构之间。
  13. 根据权利要求12所述的横向扩散金属氧化物半导体器件的制备方法，其特征在于，于所述第二导电类型的漂移区内形成第一导电类型的注入区域包括如下步骤：
    于所述第二导电类型的漂移区内进行一次第一导电类型离子的注入，以于所述第二导电类型的漂移区内形成所述第一导电类型的注入区域；其中，
    所述第一导电类型的注入区域位于所述第二导电类型的漂移区的上 部，且所述第一导电类型的注入区域的顶部与所述第二导电类型的漂移区的上表面相平齐或与所述第二导电类型的漂移区的上表面具有间距；或所述第一导电类型的注入区域位于所述第二导电类型的漂移区的中部；或所述第一导电类型的注入区域位于所述第二导电类型的漂移区的下部，且所述第一导电类型的注入区域的底部与所述第二导电类型的漂移区的下表面具有间距。
  14. 根据权利要求12所述的横向扩散金属氧化物半导体器件的制备方法，其特征在于，于所述第二导电类型的漂移区内形成第一导电类型的注入区域包括如下步骤：
    于所述第二导电类型的漂移区内进行多次第一导电类型离子的注入，以于所述第二导电类型的漂移区内形成包括若干个沿所述第二导电类型的漂移区的深度方向排布的第一导电类型的子注入区域的所述第一导电类型的注入区域；其中，
    所述第一导电类型的注入区域位于所述第二导电类型的漂移区的上部，且所述第一导电类型的注入区域的顶部与所述第二导电类型的漂移区的上表面相平齐或与所述第二导电类型的漂移区的上表面具有间距；或所述第一导电类型的注入区域位于所述第二导电类型的漂移区的中部；或所述第一导电类型的注入区域位于所述第二导电类型的漂移区的下部，且所述第一导电类型的注入区域的底部与所述第二导电类型的漂移区的下表面具有间距。
  15. 根据权利要求12至14中任一项所述的横向扩散金属氧化物半导体器件的制备方法，其特征在于，于所述第二导电类型的漂移区内形成纵向浮空场板阵列之后还包括如下步骤：
    于所述第二导电类型的漂移区一侧形成第一导电类型的阱区，并于所述第二导电类型的漂移区内形成第二导电类型的阱区，所述第二导电类型的阱区位于所述纵向浮空场板阵列远离所述第一导电类型的阱区一侧，且与所述纵向浮空场板阵列具有间距；
    于所述第二导电类型的漂移区上形成场氧化层，所述场氧化层覆盖所述纵向浮空场板阵列；
    于所述第一导电类型的阱区上及所述场氧化层上形成栅极，所述栅极自所述第一导电类型的阱区延伸至所述场氧化层的表面；
    于所述第一导电类型的阱区内形成源区及第一导电类型的体区，并于所述第二导电类型的阱区内形成漏区；所述源区与所述第二导电类型的漂移区具有间距，所述第一导电类型的体区位于所述源区远离所述纵向浮空场板阵列的一侧，并与所述源区接触；
    于所述场氧化层内形成若干个互连孔，所述互连孔与所述纵向浮空场板结构一一对应设置，且暴露出各所述纵向浮空场板结构中的所述导电层；
    于所述互连孔内形成导电结构；
    于所述场氧化层上形成若干条导电等势条，各所述导电等势条均沿所 述导电沟道宽度方向延伸，且通过所述导电结构与位于其下方的一列所述纵向浮空场板结构电连接。
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