WO2021134833A1 - 一种阵列基板制备方法、阵列基板及液晶显示面板 - Google Patents

一种阵列基板制备方法、阵列基板及液晶显示面板 Download PDF

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Publication number
WO2021134833A1
WO2021134833A1 PCT/CN2020/071914 CN2020071914W WO2021134833A1 WO 2021134833 A1 WO2021134833 A1 WO 2021134833A1 CN 2020071914 W CN2020071914 W CN 2020071914W WO 2021134833 A1 WO2021134833 A1 WO 2021134833A1
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WIPO (PCT)
Prior art keywords
layer
array substrate
insulating layer
alignment mark
hydrophobic film
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PCT/CN2020/071914
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English (en)
French (fr)
Inventor
张霞
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Tcl华星光电技术有限公司
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Priority to US16/645,238 priority Critical patent/US11194199B2/en
Publication of WO2021134833A1 publication Critical patent/WO2021134833A1/zh

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Classifications

    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F9/00—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically
    • G03F9/70—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically for microlithography
    • G03F9/7073—Alignment marks and their environment
    • G03F9/7084—Position of mark on substrate, i.e. position in (x, y, z) of mark, e.g. buried or resist covered mark, mark on rearside, at the substrate edge, in the circuit area, latent image mark, marks in plural levels
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136277—Active matrix addressed cells formed on a semiconductor substrate, e.g. of silicon
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F9/00—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically
    • G03F9/70—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically for microlithography
    • G03F9/7073—Alignment marks and their environment
    • G03F9/708—Mark formation

Definitions

  • This application relates to the field of display technology, and in particular to a method for manufacturing an array substrate, an array substrate, and a liquid crystal display panel.
  • the current thin film transistor liquid crystal display Thin Film Transistor Liquid Crystal Display, TFT-LCD
  • the black matrix Black Matrix, BM
  • spacer Black Spacer, PS
  • Black Photo Spacer (BPS) material is replaced, and the BPS is directly fabricated on one side of the array substrate.
  • BPS is not the first process, so it is necessary to refer to the alignment mark to achieve precise alignment and avoid various display problems caused by alignment deviation.
  • the BPS material has a high optical density. In the wet film full-film process, when the exposure process is started, there is a problem that it is difficult to identify the mark before the process.
  • the existing array substrate has the problem of difficulty in reading the alignment mark and needs to be solved.
  • the present application provides a method for manufacturing an array substrate, an array substrate, and a liquid crystal display panel, so as to alleviate the technical problem that the existing array substrate is difficult to read alignment marks.
  • An embodiment of the present application provides a method for preparing an array substrate, which includes the following steps: Step S10, making an alignment mark, including providing a base substrate, and making an alignment mark on the base substrate. Step S20, preparing a hydrophobic film layer, including preparing an insulating layer on the base substrate with alignment marks, coating a hydrophobic film layer on the insulating layer corresponding to the alignment marks, The hydrophobic film layer is dried. Step S30, preparing a black spacer pattern, including coating a black spacer material on the insulating layer and the hydrophobic film layer, and then exposing, developing, and etching the coated black spacer material to the required Black septa pattern.
  • step S10 it further includes preparing an active layer on the base substrate.
  • the active layer includes a first metal layer and a second metal layer.
  • the mark is formed by at least one of the first metal layer or the second metal layer, and the alignment mark is located in a non-display area of the base substrate.
  • the alignment mark is formed by the first metal layer.
  • the alignment mark is formed by the second metal layer.
  • the material of the hydrophobic film layer includes polyethylene terephthalate.
  • the process of coating the hydrophobic film layer includes one of inkjet printing, spray coating, slit coating, and spin coating.
  • the temperature at which the hydrophobic film layer is dried is 80°C to 150°C.
  • step S20 it further includes preparing a color filter layer before preparing the insulating layer, and preparing the insulating layer on the insulating layer after preparing the insulating layer.
  • the material of the pixel electrode layer is indium tin oxide.
  • the material of the insulating layer includes one or a combination of SiOx, SiNx, and SiON.
  • step S30 after the coating of the black spacer material is completed, the thickness of the black spacer on the hydrophobic film layer is smaller than that on the insulating layer.
  • the thickness of the spacer film enables precise alignment by identifying the alignment mark during the exposure process.
  • the black spacer on the hydrophobic film layer and the black spacer on the insulating layer are continuous.
  • the black spacers on the hydrophobic film layer and the black spacers on the insulating layer are not continuous.
  • step S30 after the coating of the black spacer material is completed, there is no black spacer on the hydrophobic film layer, so that the The alignment mark is used to complete precise alignment.
  • An embodiment of the application provides an array substrate, which includes a display area and a non-display area.
  • the non-display area includes an alignment mark, an insulating layer, a hydrophobic film layer, and a black spacer pattern stacked on a base substrate.
  • the alignment mark is arranged on the base substrate.
  • the insulating layer is arranged on the alignment mark.
  • the hydrophobic film layer is arranged on the insulating layer corresponding to the alignment mark.
  • the black spacer pattern is arranged on the insulating layer. Wherein, the black spacer pattern includes a black matrix and a supporting column.
  • the display area includes an active layer, a color filter layer, an insulating layer, and a pixel electrode layer.
  • the active layer is disposed on the base substrate and includes a first metal layer and a second metal layer.
  • the color filter layer is arranged on the active layer.
  • the insulating layer is disposed on the color filter layer, and the insulating layer extends from the display area to the non-display area.
  • the pixel electrode layer is disposed on the insulating layer.
  • the alignment mark is formed by at least one of the first metal layer or the second metal layer.
  • the material of the hydrophobic film layer includes polyethylene terephthalate.
  • An embodiment of the present application also provides a liquid crystal display panel, which includes a first substrate, a second substrate disposed opposite to the first substrate, and a plurality of liquid crystals disposed between the first substrate and the second substrate.
  • the second substrate includes a display area and a non-display area, and the non-display area includes an alignment mark, an insulating layer, a hydrophobic film layer, and a black spacer pattern stacked on the base substrate.
  • the alignment mark is arranged on the base substrate.
  • the insulating layer is arranged on the alignment mark.
  • the hydrophobic film layer is arranged on the insulating layer corresponding to the alignment mark.
  • the black spacer pattern is arranged on the insulating layer. Wherein, the black spacer pattern includes a black matrix and a supporting column.
  • the display area includes an active layer, a color filter layer, an insulating layer, and a pixel electrode layer.
  • the active layer is disposed on the base substrate and includes a first metal layer and a second metal layer.
  • the color filter layer is arranged on the active layer.
  • the insulating layer is disposed on the color filter layer, and the insulating layer extends from the display area to the non-display area.
  • the pixel electrode layer is disposed on the insulating layer.
  • the alignment mark is formed by at least one of the first metal layer or the second metal layer.
  • the material of the hydrophobic film layer includes polyethylene terephthalate.
  • a hydrophobic film layer is provided on the insulating layer corresponding to the alignment mark to realize the difference in hydrophilicity and hydrophobicity between the alignment mark area and the non-alignment mark area.
  • FIG. 1 is a schematic side view of a film structure of a non-display area of an array substrate provided by an embodiment of the application.
  • FIG. 2 is a schematic side view of a film structure of a display area of an array substrate provided by an embodiment of the application.
  • FIG. 3 is a schematic flowchart of a method for manufacturing an array substrate provided by an embodiment of the application.
  • 4 to 10 are schematic diagrams of a part of the film layer of the array substrate produced in each step of the method for manufacturing the array substrate provided by the embodiments of the application.
  • FIG. 11 is a schematic side view of the structure of a liquid crystal display panel provided by an embodiment of the application.
  • an array substrate 100 which includes a display area and a non-display area (FIG. 1 shows the non-display area of the array substrate 100, and FIG. 2 shows Is the display area of the array substrate 100), and the non-display area includes an alignment mark 23, an insulating layer 40, a hydrophobic film layer 60, and a black spacer (BPS) pattern 70 stacked on the base substrate 10.
  • the alignment mark 23 is arranged on the base substrate 10.
  • the insulating layer 40 is disposed on the alignment mark 23.
  • the hydrophobic film layer 60 is disposed on the insulating layer 40 corresponding to the alignment mark 23.
  • the black spacer pattern 70 is disposed on the insulating layer 60. Wherein, the black spacer pattern 70 includes a black matrix 71 and supporting pillars 72.
  • the display area of the array substrate 100 includes an active layer 20, a color filter layer 30, an insulating layer 40, and a pixel electrode layer 50, as shown in FIG. 2.
  • the active layer 20 includes a first metal layer 21, an interlayer insulating layer 22, and a second metal layer 24, and the alignment mark 23 is formed by the first metal layer 21 or the second metal layer 24 In the non-display area of the array substrate 100.
  • the alignment mark 23 is formed on the non-display area of the array substrate 100 by the first metal layer 21.
  • the array substrate of the present application also includes other conventional film layers such as a buffer layer and an active layer, and the embodiments and drawings of the present application will not describe these conventional film layers.
  • the material of the first metal layer 21 and the second metal layer 24 may be one or an alloy of copper, aluminum, titanium, molybdenum and other metals.
  • the alignment mark 23 may not only be formed by the first metal layer 21 or the second metal layer 24, but may also be a film layer made of metal materials such as copper, aluminum, titanium, and molybdenum.
  • the color filter layer 30 is prepared on the active layer 20, and the color filter layer 30 includes three color resist patterns of red, green, and blue, which are not specifically shown in FIG. 2.
  • the color filter layer 30 is prepared on the array substrate, that is, the color-filter on array (COA) technology, which reduces the difficulty of combining the upper and lower substrates.
  • COA color-filter on array
  • an insulating layer 40 is prepared on the color filter layer 30, and the insulating layer 40 extends from the display area of the array substrate to the non-display area of the array substrate.
  • a pixel electrode layer 50 is prepared on the insulating layer 40, and the pixel electrode layer does not extend to the non-display area of the array substrate.
  • the material of the pixel electrode is a transparent electrode material such as indium tin oxide (ITO).
  • a hydrophobic film layer 60 is prepared on the insulating layer 40, and the hydrophobic film layer 60 is specifically arranged on the insulating layer 40 corresponding to the alignment mark 23. In order to achieve the difference in the hydrophilicity and hydrophobicity of the membrane between the para-labeled region and the non-para-labeled region.
  • the material of the hydrophobic film layer 60 includes polyethylene terephthalate (Polyethylene terephthalate). ethylene terephthalate, PET) and other hydrophobic materials.
  • a black spacer pattern 70 is prepared in the non-display area of the array substrate, and the black spacer pattern 70 includes two parts of a black matrix 71 and a supporting pillar 72.
  • the black matrix 71 is used for shading
  • the supporting column 72 is used for supporting the upper and lower substrates, and controls the thickness of the box.
  • the shape of the support column 72 is a straight column shape
  • the cross-sectional shape of the support column 72 is a rectangle, as shown in the support column 72 in FIG. 1.
  • the black spacer material is coated on the insulating layer 40 and the hydrophobic film layer 60. Due to the existence of the hydrophobic film layer, the film thickness of different regions of the wet film of the black spacer is affected, and the alignment mark area covers black The film thickness of the spacer is reduced or the alignment mark area is not covered by a black spacer, and the shading of this area is reduced, which can effectively improve the difficulty of reading the alignment mark and improve the alignment accuracy.
  • the black spacer (BPS) material is a photoresist.
  • a method for manufacturing an array substrate including the following steps:
  • Step S10 making an alignment mark, includes providing a base substrate 10, and making an alignment mark 23 on the base substrate 1, as shown in FIG. 4.
  • an active layer 20 is prepared on the base substrate 10, and the active layer 20 includes a first metal layer 21 and a second metal layer 24, as shown in FIG. 2.
  • the alignment mark 23 is formed by at least one of the first metal layer 21 or the second metal layer 24, and the alignment mark 23 as shown in FIG. 1 is formed by the first metal layer 21.
  • the alignment mark 23 is located in the non-display area of the base substrate, as shown in FIG. 5 is a schematic bottom view of the alignment mark 23 on the base substrate 10, as shown in FIG. 4 A schematic side view of the alignment mark 23 on the base substrate 10.
  • the active layer also includes conventional film layers such as an active layer and other insulating layers.
  • the active layer is also Thin film transistor (TFT) part on the array substrate.
  • Step S20 preparing a hydrophobic film layer, including preparing an insulating layer 40 on the base substrate 10 on which the alignment mark 23 is made, and coating a hydrophobic film on the insulating layer 40 corresponding to the alignment mark 23 Layer 60, and the hydrophobic film layer 60 is dried, as shown in FIG. 6.
  • a color filter layer 30, an insulating layer 40, and a pixel electrode layer 50 are sequentially prepared on the base substrate 10 on which the alignment mark 23 is prepared, wherein the color filter layer 40 and the pixel electrode layer 50 are located
  • the display area of the base substrate is as shown in FIG. 2.
  • the color filter layer includes three color resist patterns of red, green, and blue, and the color filter layer is prepared on the array substrate, that is, the COA technology, which reduces the difficulty of pairing the upper and lower substrates.
  • the red color resist is coated on the base substrate with the alignment mark, and then the required red color resist pattern is exposed, developed, and etched.
  • the green color resist pattern and the blue color resist pattern are prepared in the same process.
  • the insulating layer extends from the display area of the base substrate to the non-display area.
  • the material of the insulating layer includes one or a combination of inorganic materials such as silicon oxide (SiOx), nitride layer (SiNx), and silicon oxynitride (SiNO).
  • inorganic materials such as silicon oxide are deposited on the color filter layer by a deposition process such as chemical vapor deposition (CVD) to form the insulating layer.
  • CVD chemical vapor deposition
  • the material of the pixel electrode is a transparent electrode material such as indium tin oxide.
  • a hydrophobic film layer is prepared in the non-display area of the base substrate, and the hydrophobic film layer is specifically prepared on the insulating layer corresponding to the alignment mark.
  • inkjet printing Ink jet Print, IJP
  • spray coating Spray coating
  • Slit coating slit coating
  • spin coating spin coating
  • the hydrophobic material such as polyethylene terephthalate (PET) is coated on the corresponding On the insulating layer of the alignment mark.
  • PET polyethylene terephthalate
  • the drying conditions can be determined according to the selected hydrophobic solvent.
  • the drying temperature is selected to be 80°C to 150°C.
  • the hydrophobic film layer is provided on the insulating layer corresponding to the alignment mark to realize the difference in hydrophilicity and hydrophobicity of the film layer between the alignment mark area and the non-alignment mark area.
  • Step S30 preparing a black spacer pattern, including coating a black spacer material on the insulating layer 40 and the hydrophobic film layer 60, and then exposing, developing, and etching the coated black spacer material
  • the required black spacer pattern 70 is formed, as shown in FIG. 7.
  • the black spacer material is coated on the insulating layer 40 and the hydrophobic film layer 60, and then the coated black spacer material is vacuum dried, Pre-baking and other processes. Due to the existence of the hydrophobic film layer 60, the black spacer material is not easy to accumulate in the area where the hydrophobic film layer is provided, forming a distribution state as shown in FIGS. 8 to 10. In FIG.
  • the film thickness of the black spacer material 73' on the hydrophobic film layer is smaller than the film thickness of the black spacer material 73 in the area where the hydrophobic film layer is not provided (that is, on the insulating layer), and
  • the black spacer material 73 ′ on the hydrophobic film layer and the black spacer material 73 in the area where the hydrophobic film layer is not provided are continuously arranged.
  • the black spacer material 73" on the hydrophobic film layer is discontinuous, and the black spacer material 73" is present in only a part of the area.
  • the preliminary processed black spacer film layer is exposed, developed, baked, and etched to prepare the required black spacer pattern, as shown in FIG. 7.
  • the film thickness of the black spacer material on the hydrophobic film layer is smaller than the film thickness of the black spacer material in the area where the hydrophobic film layer is not provided, or there is no black color on the hydrophobic film layer at all.
  • the material distribution of the spacer improves the transmittance of the alignment light source, so that the alignment mark can be read more easily, and the alignment accuracy is improved.
  • a liquid crystal display panel 1000 is provided, as shown in FIG. 11, which includes a first substrate 200, a second substrate 400 and a plurality of liquid crystal molecules 300.
  • the second substrate 400 is disposed opposite to the first substrate 200, and the second substrate 400 includes the array substrate 100 provided in one of the foregoing embodiments.
  • the plurality of liquid crystal molecules 300 are arranged between the first substrate 200 and the second substrate 400.
  • the first substrate 200 is a color filter substrate
  • the second substrate 400 is a COA type array substrate.
  • the present application provides a method for manufacturing an array substrate, an array substrate, and a liquid crystal display panel.
  • the non-display area of the array substrate includes a base substrate, an alignment mark, an insulating layer, a hydrophobic film layer, and a black spacer pattern.
  • a hydrophobic film layer is arranged on the insulating layer corresponding to the alignment mark to realize the difference in hydrophilicity and hydrophobicity between the alignment mark area and the non-alignment mark area.
  • the difficulty in reading the alignment mark can be effectively improved, and the alignment accuracy can be improved.
  • it solves the problem that the alignment time course is prolonged due to the difficulty in reading the alignment mark, which affects the production time, thereby reducing the overall production cost.

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Abstract

本申请提供一种阵列基板制备方法、阵列基板及液晶显示面板。所述阵列基板的非显示区包括衬底基板、对位标记、绝缘层、疏水膜层以及黑色隔垫物图案。所述疏水膜层设置于对应所述对位标记的所述绝缘层上，在涂覆黑色隔垫物材料时，设置有疏水膜层的区域黑色隔垫物膜层的厚度减小，从而有效改善对位标记读取困难的问题。

Description

一种阵列基板制备方法、阵列基板及液晶显示面板 技术领域
本申请涉及显示技术领域，尤其涉及一种阵列基板制备方法、阵列基板以及液晶显示面板。
 背景技术
为缩短工艺制程时间，现行薄膜晶体管液晶显示器（Thin Film Transistor Liquid Crystal Display，TFT- LCD）将黑色矩阵（Black Matrix，BM）和隔垫物（Photo Spacer，PS）功能性融合，直接用黑色隔垫物(Black Photo Spacer，BPS) 材料替代，并将BPS直接制作于阵列基板的一侧。不同于传统液晶面板制作工艺顺序的是，BPS不是第一道制程，因而需要参考对位标记(mark)，实现精准对位，避免因对位偏差引起的诸种显示不良问题。然而BPS材料具有较高的光学密度，在湿膜全膜制程中，开始进行曝光工艺时，存在识别前制程对位Mark困难问题。如果选择光学密度较低材料，遮光效果会受到影响，进而导致漏光或色偏问题。因而，在BPS技术开发中，如何准确读取对位Mark又不影响遮光性能，成为目前亟待解决的技术问题。
因此，现有阵列基板存在对位标记读取困难的问题需要解决。
 技术问题
本申请提供一种阵列基板制备方法、阵列基板以及液晶显示面板，以缓解现有阵列基板存在对位标记读取困难的技术问题。
 技术解决方案
为解决上述问题，本申请提供的技术方案如下：
本申请实施例提供一种阵列基板制备方法，其包括以下步骤：步骤S10，制作对位标记，包括提供一衬底基板，在所述衬底基板上制作对位标记。步骤S20，制备疏水膜层，包括在制作有对位标记的所述衬底基板上制备绝缘层，在对应所述对位标记的所述绝缘层上涂覆一层疏水膜层，并对所述疏水膜层进行干燥处理。步骤S30，制备黑色隔垫物图案，包括在所述绝缘层和所述疏水膜层上涂覆黑色隔垫物材料，然后对涂覆的所述黑色隔垫物材料曝光、显影、蚀刻成需要的黑色隔垫物图案。
在本申请实施例提供的阵列基板制备方法中，在步骤S10中，还包括在所述衬底基板上制备主动层，所述主动层包括第一金属层和第二金属层，所述对位标记由第一金属层或第二金属层中的至少一层形成，且所述对位标记位于所述衬底基板的非显示区。
在本申请实施例提供的阵列基板制备方法中，所述对位标记由所述第一金属层形成。
在本申请实施例提供的阵列基板制备方法中，所述对位标记由所述第二金属层形成。
在本申请实施例提供的阵列基板制备方法中，在步骤S20中，所述疏水膜层的材料包括聚对苯二甲酸乙二醇酯。
在本申请实施例提供的阵列基板制备方法中，涂覆所述疏水膜层的工艺包括喷墨打印、喷雾涂布、狭缝涂布、旋转涂布中的一种。
在本申请实施例提供的阵列基板制备方法中，对所述疏水膜层进行干燥的温度为80℃至150℃。
在本申请实施例提供的阵列基板制备方法中，在步骤S20中，还包括在制备所述绝缘层前先制备彩色滤光层，以及在制备所述绝缘层后，在所述绝缘层上制备像素电极层，其中所述彩色滤光层和所述像素电极层位于所述衬底基板的显示区内。
在本申请实施例提供的阵列基板制备方法中，所述像素电极层的材料为氧化铟锡。
在本申请实施例提供的阵列基板制备方法中，所述绝缘层的材料包括SiOx、SiNx、SiON中的一种或几种的组合物。
在本申请实施例提供的阵列基板制备方法中，在步骤S30中，所述黑色隔垫物材料涂覆完成后，所述疏水膜层上的黑色隔垫物膜厚小于所述绝缘层上黑色隔垫物膜厚，使在曝光工艺中，通过识别所述对位标记以完成精准对位。
在本申请实施例提供的阵列基板制备方法中，所述疏水膜层上的黑色隔垫物与所述绝缘层上黑色隔垫物是连续的。
在本申请实施例提供的阵列基板制备方法中，所述疏水膜层上的黑色隔垫物与所述绝缘层上黑色隔垫物是不连续的。
在本申请实施例提供的阵列基板制备方法中，在步骤S30中，所述黑色隔垫物材料涂覆完成后，所述疏水膜层上无黑色隔垫物，使在曝光工艺中，通过识别所述对位标记以完成精准对位。
本申请实施例提供一种阵列基板，其包括显示区和非显示区，所述非显示区包括在衬底基板上层叠设置的对位标记、绝缘层、疏水膜层以及黑色隔垫物图案。所述对位标记，设置于所述衬底基板上。所述绝缘层，设置于所述对位标记上。所述疏水膜层，设置于对应所述对位标记的所述绝缘层上。所述黑色隔垫物图案，设置于所述绝缘层上。其中，所述黑色隔垫物图案包括黑色矩阵和支撑柱。
在本申请实施例提供的阵列基板中，所述显示区包括主动层、彩色滤光层、绝缘层以及像素电极层。所述主动层，设置于所述衬底基板上，包括第一金属层和第二金属层。所述彩色滤光层，设置于所述主动层上。所述绝缘层，设置于所述彩色滤光层上，所述绝缘层由所述显示区延伸至所述非显示区。所述像素电极层，设置于所述绝缘层上。其中，所述对位标记由所述第一金属层或所述第二金属层中的至少一层形成。
在本申请实施例提供的阵列基板中，所述疏水膜层的材料包括聚对苯二甲酸乙二醇酯。
本申请实施例还提供一种液晶显示面板，其包括第一基板、与所述第一基板相对设置的第二基板以及设置于所述第一基板和所述第二基板之间的多个液晶分子。其中所述第二基板包括显示区和非显示区，所述非显示区包括在衬底基板上层叠设置的对位标记、绝缘层、疏水膜层以及黑色隔垫物图案。所述对位标记，设置于所述衬底基板上。所述绝缘层，设置于所述对位标记上。所述疏水膜层，设置于对应所述对位标记的所述绝缘层上。所述黑色隔垫物图案，设置于所述绝缘层上。其中，所述黑色隔垫物图案包括黑色矩阵和支撑柱。
在本申请实施例提供的液晶显示面板中，所述显示区包括主动层、彩色滤光层、绝缘层以及像素电极层。所述主动层，设置于所述衬底基板上，包括第一金属层和第二金属层。所述彩色滤光层，设置于所述主动层上。所述绝缘层，设置于所述彩色滤光层上，所述绝缘层由所述显示区延伸至所述非显示区。所述像素电极层，设置于所述绝缘层上。其中，所述对位标记由所述第一金属层或所述第二金属层中的至少一层形成。
在本申请实施例提供的液晶显示面板中，所述疏水膜层的材料包括聚对苯二甲酸乙二醇酯。
 有益效果
本申请提供的一种阵列基板制备方法、阵列基板以及液晶显示面板中，在对应对位标记的绝缘层上设置疏水膜层，实现对位标记区与非对位标记区的亲疏水性差异。而后进行黑色隔垫物湿膜涂布时，由于疏水膜层的存在，影响黑色隔垫物湿膜不同区域膜厚，对位标记区域覆盖黑色隔垫物膜厚减少，该区域遮光性降低，从而可有效改善了对位标记读取困难问题，提升了对位精准度。同时解决了因对位标记读取困难导致对位时程延长，影响生产时间（Tact time）的问题，从而降低整个生产成本。
 附图说明
为了更清楚地说明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请实施例提供的阵列基板非显示区的膜层结构侧视示意图。
图2为本申请实施例提供的阵列基板显示区的膜层结构侧视示意图。
图3为本申请实施例提供的阵列基板制备方法的流程示意图。
图4至图10为本申请实施例提供的阵列基板制备方法中各步骤中制得阵列基板部分膜层示意图。
图11为本申请实施例提供的液晶显示面板的侧视结构示意图。
 本发明的实施方式
以下各实施例的说明是参考附加的图示，用以例示本申请可用以实施的特定实施例。本申请所提到的方向用语，例如[上]、[下]、[前]、[后]、[左]、[右]、[内]、[外]、[侧面]等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本申请，而非用以限制本申请。在图中，结构相似的单元是用以相同标号表示。
在一种实施例中，结合图1和图2所示，提供一种阵列基板100，其包括显示区和非显示区（图1示出的为阵列基板100的非显示区，图2示出的为阵列基板100的显示区），所述非显示区包括在衬底基板10上层叠设置的对位标记23、绝缘层40、疏水膜层60以及黑色隔垫物（BPS）图案70。所述对位标记23，设置于所述衬底基板10上。所述绝缘层40，设置于所述对位标记23上。所述疏水膜层60，设置于对应所述对位标记23的所述绝缘层40上。所述黑色隔垫物图案70，设置于所述绝缘层60上。其中，所述黑色隔垫物图案70包括黑色矩阵71和支撑柱72。
具体的，所述阵列基板100的显示区包括主动层20、彩色滤光层30、绝缘层40以及像素电极层50，如图2所示。
具体的，所述主动层20包括第一金属层21、层间绝缘层22、第二金属层24，所述对位标记23由所述第一金属层21或所述第二金属层24形成在所述阵列基板100的非显示区。结合图1和图2，所述对位标记23由第一金属层21形成在所述阵列基板100的非显示区。
需要说明的，本申请的阵列基板还包括缓冲层、有源层等其他常规膜层，本申请实施例及图示不再对此部分常规膜层作说明。
进一步的，所述第一金属层21和所述第二金属层24的材料可以为铜、铝、钛、钼等金属中的一种或几种的合金。所述对位标记23除了可以有所述第一金属层21或所述第二金属层24形成，也可以是有铜、铝、钛、钼等金属材料单独制备的膜层。
具体的，所述彩色滤光层30制备在所述主动层20上，所述彩色滤光层30包括红、绿、蓝三种颜色色阻图案，图2未具体示出。把彩色滤光层30制备在阵列基板上,即阵列上彩色滤光片(Color-filter on Array，COA) 技术，降低上下基板对组的难度。
进一步的，在所述彩色滤光层30上制备绝缘层40，所述绝缘层40由所述阵列基板的显示区延伸至所述阵列基板的非显示区。
进一步的，在所述绝缘层40上制备像素电极层50，所述像素电极层未延伸至所述阵列基板的非显示区。所述像素电极的材料为氧化铟锡（Indium Tin Oxide，ITO）等透明电极材料。
进一步的，如图1所示，在所述绝缘层40上制备疏水膜层60，所述疏水膜层60具体设置在对应于所述对位标记23的所述绝缘层40上。以实现对位标记区与非对位标记区的膜层亲疏水性差异。
进一步的，所述疏水膜层60的材料包括聚对苯二甲酸乙二醇酯（Poly ethylene terephthalate，PET）等疏水性材料。
进一步的，在阵列基板的非显示区制备黑色隔垫物图案70，所述黑色隔垫物图案70包括黑色矩阵71和支撑柱72两部分。所述黑色矩阵71用于遮光，所述支撑柱72用于支撑上下基板，控制盒厚。其中，所述支撑柱72的形状为直柱状，其截面形状为矩形，如图1中的支撑柱72所示。
具体的，在所述绝缘层40以及所述疏水膜层60上涂覆黑色隔垫物材料，由于疏水膜层的存在，影响黑色隔垫物湿膜不同区域膜厚，对位标记区域覆盖黑色隔垫物膜厚减少或对位标记区域无黑色隔垫物覆盖，该区域遮光性降低，从而可有效改善了对位标记读取困难问题，提升了对位精准度。
具体的，所述黑色隔垫物（BPS）材料即为一种光刻胶。
在一种实施例中，提供一种阵列基板制备方法，如图3所示，包括以下步骤：
步骤S10，制作对位标记，包括提供一衬底基板10，在所述衬底基板1上制作对位标记23，如图4所示。
具体的，在所述衬底基板10上制备主动层20，所述主动层20包括第一金属层21和第二金属层24，如图2所示。所述对位标记23由第一金属层21或第二金属层24中的至少一层形成，如图1所示的对位标记23由所述第一金属层21形成。且所述对位标记23位于所述衬底基板的非显示区，如图5所示为所述对位标记23在所述衬底基板10上的下视示意图，如图4所示为所述对位标记23在所述衬底基板10上的侧视示意图。
进一步的，在制备所述主动层前，还需在衬底基板上制备缓冲层等膜层，所述主动层还包括有源层及其他绝缘层等常规膜层，所述主动层也即为阵列基板上的薄膜晶体管（TFT）部分。
步骤S20，制备疏水膜层，包括在制作有对位标记23的所述衬底基板10上制备绝缘层40，在对应所述对位标记23的所述绝缘层40上涂覆一层疏水膜层60，并对所述疏水膜层60进行干燥处理，如图6所示。
具体的，在制备有对位标记23的衬底基板10上依次制备彩色滤光层30、绝缘层40以及像素电极层50，其中所述彩色滤光层40和所述像素电极层50位于所述衬底基板的显示区内，如图2所示。
具体的，所述彩色滤光层包括红、绿、蓝三种颜色色阻图案，把彩色滤光层制备在阵列基板上,即COA技术，降低上下基板对组的难度。
具体的，把红色色阻涂覆在制作有对位标记的衬底基板上，然后曝光、显影、蚀刻出需要的红色色阻图案。绿色色阻图案和蓝色色阻图案用同样的工艺方法制备。
具体的，所述绝缘层由所述衬底基板的显示区延伸至非显示区。所述绝缘层的材料包括氧化硅（SiOx）、氮化层（SiNx）、氮氧化硅（SiNO）等无机材料中的一种或几种的组合物。
进一步的，把氧化硅等无机材料通过化学气相沉积法（Chemical Vapor Deposition, CVD）等沉积工艺沉积在所述彩色滤光层上制成所述绝缘层。
具体的，所述像素电极的材料为氧化铟锡等透明电极材料。
具体的，衬底基板显示区的膜层制备完成后，在衬底基板的非显示区制备疏水膜层，所述疏水膜层具体制备在对应于所述对位标记的所述绝缘层上。
具体的，采用喷墨打印（Ink jet Print,IJP）、喷雾涂布（Spray coating）、狭缝涂布（Slit coating）、旋转涂布（Spin coating）等涂布工艺中的一种，把聚对苯二甲酸乙二醇酯（PET）等疏水材料涂布在对应于所述对位标记的所述绝缘层上。其中喷墨打印可以定点吐出，且对显示区影响最小，最经济。
进一步的，对涂布的疏水膜层记性干燥处理，干燥条件可根据所选择疏水溶剂而定，本实施例选用干燥温度为80℃至150℃。
进一步的，在对应于所述对位标记的所述绝缘层上设置所述疏水膜层，以实现对位标记区与非对位标记区的膜层亲疏水性差异。
步骤S30，制备黑色隔垫物图案，包括在所述绝缘层40和所述疏水膜层60上涂覆黑色隔垫物材料，然后对涂覆的所述黑色隔垫物材料曝光、显影、蚀刻成需要的黑色隔垫物图案70，如图7所示。
具体的，采用制备疏水膜层同样的涂布工艺，在所述绝缘层40和所述疏水膜层60上涂布黑色隔垫物材料，然后对涂布的黑色隔垫物材料进行真空干燥、预烘烤等工序。由于所述疏水膜层60的存在，使黑色隔垫物材料不易在设置有疏水膜层的区域聚积，形成如图8至图10的分布状态。在图8中，所述疏水膜层上的黑色隔垫物材料73’的膜厚小于未设置疏水膜层区域（即在所述绝缘层上）的黑色隔垫物材料73的膜厚，且所述疏水膜层上的黑色隔垫物材料73’与未设置疏水膜层区域的黑色隔垫物材料73是连续设置的。在图9中，所述疏水膜层上的黑色隔垫物材料73”为非连续的，仅部分区域存在黑色隔垫物材料73”。在图10中，所述疏水膜层上完全没有黑色隔垫物材料分布。
进一步的，对经过初步处理的黑色隔垫物膜层进行曝光、显影、烘烤、蚀刻等工艺，制备出需要的黑色隔垫物图案，如图7所示。
具体的，在曝光工艺中，由于所述疏水膜层上的黑色隔垫物材料的膜厚小于未设置疏水膜层区域的黑色隔垫物材料的膜厚或所述疏水膜层上完全没有黑色隔垫物材料分布，提高了对位光源的透过率，从而更容易读取到所述对位标记，提高了对位的精确度。
在一种实施例中，提供一种液晶显示面板1000，如图11所示，其包括第一基板200、第二基板400以及多个液晶分子300。所述第二基板400，与所述第一基板200相对设置，所述第二基板400包括如前述实施例其中之一提供的阵列基板100。所述多个液晶分子300，设置于所述第一基板200和所述第二基板400之间。
具体的，所述第一基板200为彩膜基板，所述第二基板400为COA型阵列基板。
根据上述实施例可知：
本申请提供的一种阵列基板制备方法、阵列基板以及液晶显示面板，所述阵列基板的非显示区包括衬底基板、对位标记、绝缘层、疏水膜层以及黑色隔垫物图案。在对应对位标记的绝缘层上设置疏水膜层，实现对位标记区与非对位标记区的亲疏水性差异。而后进行黑色隔垫物湿膜涂布时，由于疏水膜层的存在，影响黑色隔垫物湿膜不同区域膜厚，对位标记区域覆盖黑色隔垫物膜厚减少，该区域遮光性降低，从而可有效改善了对位标记读取困难问题，提升了对位精准度。同时解决了因对位标记读取困难导致对位时程延长，影响生产时间的问题，从而降低整个生产成本。
综上所述，虽然本申请已以优选实施例揭露如上，但上述优选实施例并非用以限制本申请，本领域的普通技术人员，在不脱离本申请的精神和范围内，均可作各种更动与润饰，因此本申请的保护范围以权利要求界定的范围为准。

Claims (20)

  1. 一种阵列基板制备方法，其包括以下步骤：
    步骤S10，制作对位标记，包括提供一衬底基板，在所述衬底基板上制作对位标记；
    步骤S20，制备疏水膜层，包括在制作有对位标记的所述衬底基板上制备绝缘层，在对应所述对位标记的所述绝缘层上涂覆一层疏水膜层，并对所述疏水膜层进行干燥处理；以及
    步骤S30，制备黑色隔垫物图案，包括在所述绝缘层和所述疏水膜层上涂覆黑色隔垫物材料，然后对涂覆的所述黑色隔垫物材料曝光、显影、蚀刻成需要的黑色隔垫物图案。
  2. 根据权利要求1所述的阵列基板制备方法，其中，在步骤S10中，还包括在所述衬底基板上制备主动层，所述主动层包括第一金属层和第二金属层，所述对位标记由所述第一金属层或所述第二金属层中的至少一层形成，且所述对位标记位于所述衬底基板的非显示区。
  3. 根据权利要求2所述的阵列基板制备方法，其中，所述对位标记由所述第一金属层形成。
  4. 根据权利要求2所述的阵列基板制备方法，其中，所述对位标记由所述第二金属层形成。
  5. 根据权利要求1所述的阵列基板制备方法，其中，在步骤S20中，所述疏水膜层的材料包括聚对苯二甲酸乙二醇酯。
  6. 根据权利要求5所述的阵列基板制备方法，其中，涂覆所述疏水膜层的工艺包括喷墨打印、喷雾涂布、狭缝涂布、旋转涂布中的一种。
  7. 根据权利要求5所述的阵列基板制备方法，其中，对所述疏水膜层进行干燥的温度为80℃至150℃。
  8. 根据权利要求1所述的阵列基板制备方法，其中，在步骤S20中，还包括在制备所述绝缘层前先制备彩色滤光层，以及在制备所述绝缘层后，在所述绝缘层上制备像素电极层，其中所述彩色滤光层和所述像素电极层位于所述衬底基板的显示区内。
  9. 根据权利要求8所述的阵列基板制备方法，其中，所述像素电极层的材料为氧化铟锡。
  10. 根据权利要求8所述的阵列基板制备方法，其中，所述绝缘层的材料包括SiOx、SiNx、SiON中的一种或几种的组合物。
  11. 根据权利要求1所述的阵列基板制备方法，其中，在步骤S30中，所述黑色隔垫物材料涂覆完成后，所述疏水膜层上的黑色隔垫物膜厚小于所述绝缘层上黑色隔垫物膜厚，使在曝光工艺中，通过识别所述对位标记以完成精准对位。
  12. 根据权利要求11所述的阵列基板制备方法，其中，所述疏水膜层上的黑色隔垫物与所述绝缘层上黑色隔垫物是连续的。
  13. 根据权利要求11所述的阵列基板制备方法，其中，所述疏水膜层上的黑色隔垫物与所述绝缘层上黑色隔垫物是不连续的。
  14. 根据权利要求1所述的阵列基板制备方法，其中，在步骤S30中，所述黑色隔垫物材料涂覆完成后，所述疏水膜层上无黑色隔垫物，使在曝光工艺中，通过识别所述对位标记以完成精准对位。
  15. 一种阵列基板，其包括显示区和非显示区，所述非显示区包括：
    衬底基板；
    对位标记，设置于所述衬底基板上；
    绝缘层，设置于所述对位标记上；
    疏水膜层，设置于对应所述对位标记的所述绝缘层上；以及
    黑色隔垫物图案，设置于所述绝缘层上；
    其中，所述黑色隔垫物图案包括黑色矩阵和支撑柱。
  16. 根据权利要求15所述的阵列基板，其中，所述显示区包括：
    主动层，设置于所述衬底基板上，包括第一金属层和第二金属层；
    彩色滤光层，设置于所述主动层上；
    绝缘层，设置于所述彩色滤光层上，所述绝缘层由所述显示区延伸至所述非显示区；以及
    像素电极层，设置于所述绝缘层上；
    其中，所述对位标记由所述第一金属层或所述第二金属层中的至少一层形成。
  17. 根据权利要求15所述的阵列基板，其中，所述疏水膜层的材料包括聚对苯二甲酸乙二醇酯。
  18. 一种液晶显示面板，其包括：
    第一基板；
    第二基板，与所述第一基板相对设置；以及
    多个液晶分子，设置于所述第一基板和所述第二基板之间；
    其中，所述第二基板包括显示区和非显示区，所述非显示区包括：
    衬底基板；
    对位标记，设置于所述衬底基板上；
    绝缘层，设置于所述对位标记上；
    疏水膜层，设置于对应所述对位标记的所述绝缘层上；以及
    黑色隔垫物图案，设置于所述绝缘层上；
    其中，所述黑色隔垫物图案包括黑色矩阵和支撑柱。
  19. 根据权利要求18所述的液晶显示面板，其中，所述显示区包括：
    主动层，设置于所述衬底基板上，包括第一金属层和第二金属层；
    彩色滤光层，设置于所述主动层上；
    绝缘层，设置于所述彩色滤光层上，所述绝缘层由所述显示区延伸至所述非显示区；以及
    像素电极层，设置于所述绝缘层上；
    其中，所述对位标记由所述第一金属层或所述第二金属层中的至少一层形成。
  20. 根据权利要求18所述的液晶显示面板，其中，所述疏水膜层的材料包括聚对苯二甲酸乙二醇酯。
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