WO2021114281A1 - 一种电子元件、带电子元件的电路板和电子设备 - Google Patents

一种电子元件、带电子元件的电路板和电子设备 Download PDF

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Publication number
WO2021114281A1
WO2021114281A1 PCT/CN2019/125365 CN2019125365W WO2021114281A1 WO 2021114281 A1 WO2021114281 A1 WO 2021114281A1 CN 2019125365 W CN2019125365 W CN 2019125365W WO 2021114281 A1 WO2021114281 A1 WO 2021114281A1
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WIPO (PCT)
Prior art keywords
circuit board
electronic component
chip
pad
output
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PCT/CN2019/125365
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English (en)
French (fr)
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WO2021114281A8 (zh
Inventor
何晨阳
莫瑞明
孙捷
Original Assignee
华为技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to EP19955622.6A priority Critical patent/EP4064337A4/en
Priority to PCT/CN2019/125365 priority patent/WO2021114281A1/zh
Priority to JP2022535671A priority patent/JP7472287B2/ja
Priority to CN201980102721.4A priority patent/CN115066748A/zh
Publication of WO2021114281A1 publication Critical patent/WO2021114281A1/zh
Priority to US17/837,445 priority patent/US20220304138A1/en
Publication of WO2021114281A8 publication Critical patent/WO2021114281A8/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0201—Thermal arrangements, e.g. for cooling, heating or preventing overheating
    • H05K1/0203—Cooling of mounted components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/66—High-frequency adaptations
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
    • H01L2223/64—Impedance arrangements
    • H01L2223/66—High-frequency adaptations
    • H01L2223/6605—High-frequency electrical connections
    • H01L2223/6611—Wire connections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
    • H01L2223/64—Impedance arrangements
    • H01L2223/66—High-frequency adaptations
    • H01L2223/6644—Packaging aspects of high-frequency amplifiers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
    • H01L2223/64—Impedance arrangements
    • H01L2223/66—High-frequency adaptations
    • H01L2223/6644—Packaging aspects of high-frequency amplifiers
    • H01L2223/6655—Matching arrangements, e.g. arrangement of inductive and capacitive components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
    • H01L2223/64—Impedance arrangements
    • H01L2223/66—High-frequency adaptations
    • H01L2223/6661—High-frequency adaptations for passive devices
    • H01L2223/6677—High-frequency adaptations for passive devices for antenna, e.g. antenna included within housing of semiconductor device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15172—Fan-out arrangement of the internal vias
    • H01L2924/15173—Fan-out arrangement of the internal vias in a single layer of the multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0237—High frequency adaptations
    • H05K1/0243—Printed circuits associated with mounted high frequency components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0271—Arrangements for reducing stress or warp in rigid printed circuit boards, e.g. caused by loads, vibrations or differences in thermal expansion
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09009—Substrate related
    • H05K2201/09036—Recesses or grooves in insulating substrate
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09009—Substrate related
    • H05K2201/09072—Hole or recess under component or special relationship between hole and component

Definitions

  • This application relates to the technical field of electronic equipment, and in particular to an electronic component, a circuit board with an electronic component, and an electronic device.
  • the circuit board In electronic equipment such as wireless base stations, with the highly integrated and high-density arrangement of electronic components on the circuit board, the circuit board needs to be dissipated. At the same time, in order to integrate more electronic components on the circuit board, the electronic components tend to Modularization.
  • FIG. 1 is a modular electronic component 01 in the prior art.
  • the electronic component 01 includes a carrier board 011, a chip 012, an input pad 013, an output pad 014, and a plastic package.
  • Layer 015 the carrier 011 includes a first surface 011a and a second surface 011b opposite, the chip 012 is arranged on the first surface 011a, the input pad 013 and the output pad 014 are arranged on the second surface 011b, the input end of the chip 012 passes
  • the first metalized via 016 is connected to the input pad 013, the output terminal of the chip 012 is connected to the output pad 014 through the second metalized via 017, and the plastic encapsulation layer 015 is disposed on the first surface 011a of the carrier 011, and Chip 012 is wrapped inside.
  • the electronic component 01 shown in Figure 1 is usually mounted on the circuit board.
  • Figure 2 is a schematic diagram of the structure when the electronic component 01 is mounted on the circuit board 02. See Figure 2.
  • the carrier 011 of the electronic component 01 is attached to the circuit board 02.
  • the input pad and output pad of the component 01 are respectively soldered to the output pad and the input pad on the circuit board 02, and the surface of the circuit board 02 away from the electronic component 01 is attached to the heat sink 03 through a colloidal heat-conducting material.
  • the heat generated by the chip 012 in the electronic component 01 is transferred to the heat sink 03 via the carrier board 011 and the circuit board 02 in order to realize the cooling of the electronic component 01.
  • This cooling path is long and the heat dissipation efficiency is low.
  • the electronic component 01 is attached to the surface of the circuit board facing the heat sink in a flip-chip method.
  • Figure 3 shows that the electronic component 01 is attached to the circuit board 02 in a flip-chip manner.
  • the carrier board 011 of the electronic component 01 is directly attached to the radiator 03, and the heat dissipation path of the electronic component 01 is shorter and the heat dissipation efficiency is higher.
  • an electrical connection structure needs to be provided in the electronic component 01 to lead out the input and output ends of the chip 012 to achieve electrical connection with the circuit board 02.
  • the input pad 013 and output pad 014 of the electronic component 01 are arranged on the first surface 011a of the carrier board 011, the input end of the chip 012 is connected to the input pad 013, and the output end of the chip 012 is connected to the output pad 014,
  • the input pad 013 and the output pad 014 are respectively soldered with copper pillars A.
  • the copper pillars A are packaged in the packaging layer 015, and the end surface of the copper pillar A away from the carrier 011 is not covered by the packaging layer 015, and the electronic component 01 passes through the two
  • the surface of the copper pillar A away from the carrier board 011 is soldered to the input pads and output pads of the circuit board 02.
  • the processing accuracy and assembly accuracy of the copper pillar A are required to be high, but due to the small size of the electronic component 01, the diameter and length of the copper pillar A that can be installed in the electronic component 01 It is smaller, the processing is more difficult, the precision is lower, and the assembly precision of the copper pillar A on the carrier board 011 is smaller, so it is easy to affect the input and output impedance matching performance of the electronic component 01.
  • a printed circuit board B with metalized vias is used to replace the copper pillar A in the solution shown in Figure 3, and the input pad 013 and the output pad 014 pass through
  • the two metalized vias on the printed circuit board B are connected to the input pads and output pads of the circuit board 2.
  • the dimensional accuracy of the metalized vias can be made higher. It can reduce the impact on the input and output impedance matching performance of the electronic component 01 to a certain extent.
  • the printed circuit board B with metalized vias still inevitably has errors during the processing and assembly process. It will still affect the input and output impedance matching performance of the electronic component 01.
  • the embodiments of the present application provide an electronic component, a circuit board with an electronic component, and an electronic device, which can shorten the heat dissipation path of the electronic component, improve the heat dissipation efficiency of the electronic component, and at the same time ensure the input and output impedance matching performance of the electronic component.
  • some embodiments of the present application provide an electronic component, including a carrier board and a first input pad provided on a first surface of the carrier board, at least one chip and a first output pad.
  • the chip includes but is not limited to For the power amplifier chip, the first input pad, at least one chip, and the first output pad are connected in sequence, the first input pad and the first output pad are directly arranged on the first surface of the carrier, and the first input pad
  • the surface away from the carrier board and the surface of the first output pad away from the carrier board constitute a partial area of the outer surface of the electronic component.
  • the electronic components provided by the embodiments of the present application are flip-chip mounted on the circuit board and attached to the heat sink, the heat generated by at least one chip in the electronic component during operation can be directly transferred to the electronic component through the carrier board.
  • the heat sink, the circuit board with electronic components has a shorter heat dissipation path and higher heat dissipation efficiency.
  • the first input pad and the first output pad are directly arranged on the first surface of the carrier board, and the surface of the first input pad facing away from the carrier board and the surface of the first output pad facing away from the carrier board constitute electronic components Part of the outer surface area, that is, the surface of the first input pad facing away from the carrier board and the surface of the first output pad facing away from the carrier board are exposed, the first input pad facing away from the surface of the carrier board and the first output soldering pad The surface of the disk away from the carrier board is not covered.
  • the first input pad and the first output pad can be directly soldered to the output pad and the input pad on the circuit board.
  • the first input pad and the first output pad are respectively connected to the There is no intermediate connection structure between the output pad and the input pad on the circuit board.
  • the lead-out path of the input and output ends of the chip in the electronic component is shorter, and the precision of the lead-out line is high.
  • the input and output impedance matching performance of the electronic component can be obtained. Effective guarantee.
  • the carrier board includes a heat dissipation layer and a dielectric layer that are stacked; the dielectric layer is provided with at least one accommodating groove, the accommodating groove penetrates the dielectric layer, the area on the surface of the heat dissipation layer opposite to the accommodating groove, the side surface of the accommodating groove The surface of the dielectric layer away from the heat dissipation layer constitutes the first surface of the carrier board.
  • At least one chip is arranged in at least one accommodating groove and fixed to the area on the surface of the heat dissipation layer opposite to the accommodating groove.
  • the first input pad and the first output solder The disk is arranged on the surface of the dielectric layer away from the heat dissipation layer.
  • the heat generated during operation of at least one chip can be quickly transferred from the heat dissipation layer to the heat sink, which is beneficial to improve the heat dissipation performance of the electronic component.
  • the dielectric layer has insulating properties, the dielectric layer can realize the connection between the first input pad and the heat dissipation layer, between the first output pad and the heat dissipation layer, and between the first input pad, at least one chip, and the first output. The insulation between the connection lines between the pads and the heat dissipation layer prevents short circuits.
  • the at least one chip is disposed in the at least one receiving groove, it is possible to prevent the at least one chip from protruding out of the outline of the carrier board, thereby avoiding interference between the at least one chip and the circuit board when the electronic component is connected to the circuit board.
  • an impedance matching circuit is further included; the first input pad, the at least one chip, and the first output pad are connected by an impedance matching circuit.
  • impedance matching is performed on the input, output, or level of at least one chip through an impedance matching circuit, so that the microwave signal energy is transmitted as much as possible to the at least one chip or circuit board connected to the output terminal of the electronic component. On other loads.
  • At least one chip includes one chip
  • the impedance matching circuit includes a first impedance matching circuit and a second impedance matching circuit
  • the first input pad is connected to the input end of the chip through the first impedance matching circuit
  • the output end of the chip passes through
  • the second impedance matching circuit is connected to the first output pad
  • the first impedance matching circuit matches the output impedance of the load connected to the first input pad on the circuit board to the input impedance of the chip
  • the second impedance matching circuit matches the output of the chip
  • the impedance is matched to the input impedance of the load connected to the first output pad on the circuit board.
  • the at least one chip includes two chips
  • the impedance matching circuit includes a first impedance matching circuit, a second impedance matching circuit, and a third impedance matching circuit
  • the first input pad is connected to the input of one chip through the first impedance matching circuit.
  • the output terminal of the one chip is connected to the input terminal of the other chip through the third impedance matching circuit
  • the output terminal of the other chip is connected to the first output pad through the second impedance matching circuit
  • the first impedance matching circuit Match the output impedance of the load connected to the first input pad on the circuit board to the input impedance of the one chip
  • the third impedance matching circuit matches the output impedance of the one chip to the input impedance of the other chip
  • the matching circuit matches the output impedance of the other chip to the input impedance of the load connected to the first output pad on the circuit board.
  • connection line between the first input pad, the at least one chip, and the first output pad includes a first part and a second part.
  • the first part is disposed on the surface of the dielectric layer away from the heat dissipation layer, and the second part is connected to the first part.
  • the electronic component further includes an encapsulation layer, the encapsulation layer is arranged on the first surface of the carrier board, and the encapsulation layer wraps the at least one chip and the second part.
  • the chip and the second part are protected by the encapsulation layer to prevent the second part from being scratched during the transportation of the electronic components, and at the same time to prevent water and dust from contacting the chip, thereby prolonging the service life of the chip.
  • the packaging layer is disposed on the first surface of the carrier board through a glue dispensing process.
  • the glue dispensing process has high precision when manufacturing the packaging layer, and prevents the packaging layer from covering the first input pads and the first output pads to affect the welding of the first input pads and the first output pads with the circuit board.
  • At least one chip is a power amplifier chip.
  • the at least one chip includes multiple chips, and the multiple chips are connected in series between the first input pad and the first output pad.
  • some embodiments of the present application provide a circuit board with electronic components, including a circuit board and the electronic components described in any of the above technical solutions, and the first surface of the circuit board is provided with a second output pad and a second output pad.
  • the input pad, the second output pad and the second input pad are connected to the circuit of the circuit board, the electronic component is located on the side of the second output pad and the second input pad far away from the circuit board, and the carrier board of the electronic component
  • the first surface of the electronic component faces the circuit board, the first input pad and the second output pad of the electronic component are directly soldered, and the first output pad and the second input pad of the electronic component are directly soldered.
  • the heat generated by at least one chip in the electronic component during operation can be directly conducted to the heat dissipation through the carrier board.
  • the heat dissipation path of the circuit board with electronic components is shorter and the heat dissipation efficiency is higher.
  • the first input pad and the first output pad are directly arranged on the first surface of the carrier board, the first input pad, the at least one chip, and the first output pad are connected in sequence, and the electronic components are connected through the first input solder
  • the disk and the first output pad are respectively directly soldered to the second output pad and the second input pad of the circuit board, so between the first input pad and the second output pad and between the first output pad and the second input
  • the lead-out path of the input end and the output end of the chip in the electronic component is short, the lead-out line has a high precision, and the input and output impedance matching performance of the electronic component can be effectively guaranteed.
  • the electronic component includes an impedance matching circuit, and the first input pad, at least one chip of the electronic component, and the first output pad are connected by an impedance matching circuit; the circuit board is provided with a recess at a position opposite to the impedance matching circuit.
  • the groove and the impedance matching circuit are accommodated in the groove. In this way, the distance between the impedance matching circuit and the laminated wiring in the circuit board is extended by the groove, and the laminated wiring in the circuit board is prevented from affecting the impedance matching circuit.
  • the impedance matching circuit is avoided through the groove to avoid interference between the impedance matching circuit and the circuit board.
  • a metal shielding layer is provided on the side and bottom surface of the groove.
  • the metal shielding layer can shield and isolate the impedance matching circuit from the laminated wiring in the circuit board, and avoid the impedance matching circuit from being affected by the laminated wiring in the circuit board.
  • the depth of the groove is 2 mm to 3 mm.
  • the depth of the groove is moderate, which can avoid the impedance matching circuit while taking into account the structural strength of the circuit board and the performance of the impedance matching circuit.
  • the circuit board with electronic components is a large-scale multiple-input multiple-output antenna transceiver circuit board.
  • some embodiments of the present application provide an electronic device, including a heat sink and a circuit board with electronic components as described in any of the above technical solutions.
  • the heat sink is located on the side of the electronic components away from the circuit board, and the electronic components are away from the circuit board.
  • the surface of the circuit board is attached to the surface of the heat sink, or there is a gap between the surface of the electronic component away from the circuit board and the surface of the heat sink, and the gap is filled with a thermally conductive material.
  • the electronic device provided by the embodiment of the application because the electronic device includes the circuit board with electronic components as described in any of the above technical solutions, the electronic device provided by the embodiment of the application is similar to the electronic device with electronic components described in any of the above technical solutions
  • the circuit board can solve the same technical problem and achieve the same expected effect.
  • the electronic device is a wireless base station.
  • FIG. 1 is a schematic diagram of the structure of an electronic component in the prior art
  • FIG. 2 is a schematic diagram of the assembly structure of the first electronic component, circuit board and heat sink in the prior art
  • FIG. 3 is a schematic diagram of an assembly structure of a second electronic component, a circuit board and a heat sink in the prior art
  • FIG. 4 is a schematic diagram of the assembly structure of a third type of electronic component, circuit board and heat sink in the prior art
  • FIG. 5 is a schematic structural diagram of an electronic device provided by an embodiment of this application.
  • FIG. 6 is a schematic structural diagram of a first circuit board with electronic components provided by an embodiment of the application.
  • FIG. 7 is a schematic structural diagram of a first electronic component provided by an embodiment of the application.
  • FIG. 8 is a schematic structural diagram of a second type of electronic component provided by an embodiment of the application.
  • Figure 9 is a cross-sectional view of the electronic component shown in Figure 8 along section A-A;
  • FIG. 10 is a schematic structural diagram of a third electronic component provided by an embodiment of the application.
  • Figure 11 is a cross-sectional view of the electronic component shown in Figure 10 along section B-B;
  • FIG. 12 is a schematic structural diagram of a fourth type of electronic component provided by an embodiment of the application.
  • Figure 13 is a cross-sectional view of the electronic component shown in Figure 12 along section C-C;
  • FIG. 14 is a schematic structural diagram of a second circuit board with electronic components provided by an embodiment of the application.
  • FIG. 15 is a schematic structural diagram of a fifth electronic component provided by an embodiment of the application.
  • the embodiments of the present application relate to electronic components, circuit boards with electronic components, and electronic equipment.
  • the concepts involved in the above embodiments are briefly described below:
  • Electronic equipment refers to equipment that has electronic circuits inside and uses electronic technology software to function;
  • Circuit board refers to a structure composed of a dielectric layer and lines, pads, and vias arranged on the dielectric layer, which are used to realize the interconnection between electronic components to form an electronic circuit with specific functions;
  • Electric polarization refers to the phenomenon that a macroscopically unequal electric dipole moment is generated under the action of an external electric field, thereby forming a macroscopically bound charge
  • Dielectric refers to a substance that can produce electrical polarization, including crystalline dielectric layers and amorphous dielectric layers.
  • the resistivity of dielectrics is generally very high and has insulating properties;
  • Dielectric layer refers to a layered structure composed of dielectric
  • Electronic components are the basic elements in electronic circuits. They are usually individually packaged and have two or more pins;
  • Impedance matching circuit is a part of microwave electronics. It is mainly used on transmission lines to achieve the purpose that all high-frequency microwave signals can be transmitted to the load point. There is almost no signal reflected back to the source point, thereby improving energy benefit.
  • FIG. 5 provides an electronic device according to some embodiments of the application.
  • the electronic device includes but is not limited to a wireless base station.
  • the electronic device includes a heat sink 1 and a circuit board with electronic components.
  • the radiator 1 includes, but is not limited to, a fin type radiator and a refrigerant cooling type radiator.
  • Fig. 6 is a circuit board with electronic components provided by some embodiments of the application.
  • the circuit board 2 with electronic components is an electronic circuit structure with specific functions, such as a large-scale multiple-input multiple-output (massive multiple input multiple output) in a wireless base station.
  • Multiple-input multiple-output (Massive MIMO) antenna transceiver circuit board as shown in FIG. 6, the circuit board 2 with electronic components includes a circuit board 21 and electronic components 22.
  • FIG. 7 is an electronic component 22 provided by some embodiments of the application.
  • the electronic component 22 includes but is not limited to a power amplifier module (PAM).
  • PAM power amplifier module
  • the electronic component 22 includes a carrier board 221 and settings The first input pad 222, at least one chip 223 and the first output pad 224 on the first surface 221a of the carrier 221, the chip 223 includes but is not limited to a power amplifier chip, the first input pad 222, at least one chip 223.
  • the first output pads 224 are sequentially connected.
  • the first input pads 222 and the first output pads 224 are directly disposed on the first surface 221a of the carrier board 221, and the first input pads 222 are away from the surface of the carrier board 221
  • the surface of the first output pad 224 away from the carrier board 221 constitutes a partial area of the outer surface of the electronic component 22.
  • first input pad 222 and the first output pad 224 are directly disposed on the first surface 221a of the carrier board 221, that is, the first input pad 222 and the first output pad 224 are directly connected to each other.
  • the first surface 221a of the carrier board 221 is in contact with and fixed, and there is no intermediate connection between the first input pad 222 and the first surface 221a of the carrier board 221 and between the first output pad 224 and the first surface 221a of the carrier board 221 structure.
  • the surface of the first input pad 222 away from the carrier board 221 and the surface of the first output pad 224 away from the carrier board 221 constitute a partial area of the outer surface of the electronic component 22, that is, the first input pad
  • the surface of 222 away from the carrier board 221 and the surface of the first output pad 224 away from the carrier board 221 are exposed.
  • the surface of the first input pad 222 away from the carrier board 221 and the surface of the first output pad 224 away from the carrier board 221 are not covered. .
  • the at least one chip 223 may include one chip 223 or multiple chips 223, which is not specifically limited herein.
  • the at least one chip 223 includes a plurality of chips 223, and the plurality of chips 223 are connected in series between the first input pad 222 and the first output pad 224.
  • the first surface 21a of the circuit board 21 is provided with a second output pad 211 and a second input pad 212, and the second output pad 211 and the second input pad 212 are connected to the circuit of the circuit board 21.
  • the electronic component 22 is located on the side of the second output pad 211 and the second input pad 212 away from the circuit board 21, and the first surface 221a of the carrier board 221 of the electronic component 22 faces the circuit board 21, and the first surface of the electronic component 22
  • An input pad 222 is directly welded to the second output pad 212, and the first output pad 224 of the electronic component 22 is directly welded to the second input pad 211.
  • first input pad 222 and the second output pad 212 of the electronic component 22 are directly soldered, that is, the first input pad 222 and the second output pad 212 of the electronic component 22 directly contact and are soldered. There is no intermediate connection structure between the first input pad 222 and the second output pad 212 of the electronic component 22.
  • first output pad 224 of the electronic component 22 and the second input pad 211 are directly soldered, that is, the first output pad 224 of the electronic component 22 and the second input pad 211 are directly contacted and soldered. There is no intermediate connection structure between the first output pad 224 and the second input pad 211 of the element 22.
  • the heat sink 1 is located on the side of the electronic element 22 away from the circuit board 21, and the surface of the electronic element 22 away from the circuit board 21 is attached to the surface of the heat sink 1.
  • the thermally conductive material 3 includes, but is not limited to, thermally conductive silicone grease and thermally conductive silicone cloth.
  • the heat generated by at least one chip 223 in the electronic component 22 during operation can be directly conducted to the heat sink 1 through the carrier 221, and the circuit board 2 with electronic components has a shorter heat dissipation path and higher heat dissipation efficiency.
  • the first input pad 222 and the first output pad 224 are directly arranged on the first surface 221a of the carrier board 221, the first input pad 222, the at least one chip 223, and the first output pad 224 are connected in sequence,
  • the electronic component 22 is directly soldered with the second output pad 212 and the second input pad 211 of the circuit board 21 through the first input pad 222 and the first output pad 224, respectively, so the first input pad 222 and the second output pad 222 are directly soldered to the second output pad 212 and the second input pad 211 of the circuit board 21.
  • the lead-out path of the input end and the output end of the chip 223 in the electronic component 22 is shorter, and the lead-out line has a higher precision.
  • the input and output impedance matching performance of the electronic component 22 can be effectively guaranteed.
  • the carrier board 221 includes a heat dissipation layer 2211 and a dielectric layer 2212 that are stacked;
  • the material of the layer 2211 includes, but is not limited to, aluminum-based metals and copper.
  • the dielectric layer 2212 has insulating properties.
  • the dielectric layer 2212 is provided with at least one receiving groove 2213, which penetrates the dielectric layer 2212, and the surface of the heat dissipation layer 2211 is
  • the area 221a1 opposite to the groove 2213, the side surface 221a2 of the accommodating groove 2213, and the surface 221a3 of the dielectric layer 2212 away from the heat dissipation layer 2211 constitute the first surface 221a of the carrier board 221.
  • At least one chip 223 is disposed in the at least one accommodating groove 2213 and interacts with the heat dissipation layer.
  • the area 221a1 on the surface of the 2211 opposite to the receiving groove 2213 is fixed, and the first input pad 222 and the first output pad 224 are disposed on the surface 221a3 of the dielectric layer 2212 away from the heat dissipation layer 2211.
  • the heat generated during operation of the at least one chip 223 can be quickly transferred from the heat dissipation layer 2211 to the heat sink, which is beneficial to improve the heat dissipation performance of the electronic component 22.
  • the dielectric layer 2212 since the dielectric layer 2212 has insulating properties, the dielectric layer 2212 can realize the connection between the first input pad 222 and the heat dissipation layer 2211, between the first output pad 224 and the heat dissipation layer 2211, and the first input pad 222, The connection line between the at least one chip 223 and the first output pad 224 is insulated from the heat dissipation layer 2211 to prevent short circuits.
  • the at least one chip 223 is disposed in the at least one receiving groove 2213, it is possible to prevent the at least one chip 223 from protruding out of the outline of the carrier board 221, thereby preventing the at least one chip 223 from interacting with each other when the electronic component 22 is connected to the circuit board 21. Interference occurs between the circuit boards.
  • the other load connected to the output terminal in some embodiments, as shown in FIG. 10 or FIG. 11, further includes an impedance matching circuit 225; between the first input pad 222, the at least one chip 223, and the first output pad 224 It is connected through this impedance matching circuit 225.
  • the structure of the impedance matching circuit 225 includes, but is not limited to, a microstrip line and an electronic component connected to form an electronic circuit.
  • impedance matching is performed on the input, output or inter-stage of at least one chip 223 through the impedance matching circuit 225, so that the microwave signal energy is transmitted to the at least one chip 223 or the circuit board and the electronic component 22 as much as possible.
  • Other loads connected to the output terminal are possible.
  • the structure of the impedance matching circuit 225 can be described in detail through the following two examples:
  • Example 1 As shown in FIGS. 10 and 11, at least one chip 223 includes one chip 223, the impedance matching circuit 225 includes a first impedance matching circuit 2251 and a second impedance matching circuit 2252, and the first input pad 222 passes through the first impedance
  • the matching circuit 2251 is connected to the input terminal of the chip 223, the output terminal of the chip 223 is connected to the first output pad 224 through the second impedance matching circuit 2252, and the first impedance matching circuit 2251 connects the circuit board to the first input pad 222
  • the output impedance of the load is matched to the input impedance of the chip 223, and the second impedance matching circuit 2252 matches the output impedance of the chip 223 to the input impedance of the load connected to the first output pad 224 on the circuit board.
  • Example 2 As shown in FIGS. 12 and 13, at least one chip 223 includes two chips 223, and the impedance matching circuit 225 includes a first impedance matching circuit 2251, a second impedance matching circuit 2252, and a third impedance matching circuit 2253.
  • the input pad 222 is connected to the input terminal of a chip 223 through the first impedance matching circuit 2251, and the output terminal of the one chip 223 is connected to the input terminal of another chip 223 through the third impedance matching circuit 2253.
  • the output terminal is connected to the first output pad 224 through the second impedance matching circuit 2252.
  • the first impedance matching circuit 2251 matches the output impedance of the load connected to the first input pad 222 on the circuit board to the input impedance of the one chip 223
  • the third impedance matching circuit 2253 matches the output impedance of the one chip 223 to the input impedance of the other chip 223
  • the second impedance matching circuit 2252 matches the output impedance of the other chip 223 to the circuit board and the first output The input impedance of the load to which the pad 224 is connected.
  • the circuit board 21 is composed of a plurality of circuit board units stacked, and each circuit board unit is provided with wiring, in order to avoid the impedance matching circuit 225 and the circuit board 21 when the electronic component 22 is connected to the circuit board 21.
  • the distance is too close, and the laminated traces in the circuit board 21 affect the performance of the impedance matching circuit 225, or to avoid interference between the impedance matching circuit 225 and the circuit board 21 when the electronic component 22 is connected to the circuit board 21
  • a groove 23 is provided on the circuit board 21 opposite to the impedance matching circuit 225, and the impedance matching circuit 225 is accommodated in the groove 23.
  • the distance between the impedance matching circuit 225 and the laminated wiring in the circuit board 21 is extended by the groove 23, and the laminated wiring in the circuit board 21 is prevented from affecting the impedance matching circuit 225.
  • the impedance matching circuit 225 is avoided through the groove 23 to avoid interference between the impedance matching circuit 225 and the circuit board 21.
  • a metal shielding layer is provided on the side and bottom of the groove 23 .
  • the metal shielding layer can shield and isolate the impedance matching circuit 225 from the laminated wiring in the circuit board 21, and prevent the impedance matching circuit 225 from being affected by the laminated wiring in the circuit board 21.
  • the depth of the groove 23 can be 1mm, 2mm, 3mm, etc., which is not specifically limited here, and can be specifically based on the height of the impedance matching circuit 225 protruding from the first surface 221a of the carrier board 221, and the structural strength requirements of the circuit board 21
  • the depth of the groove 23 has a comprehensive design on the performance of the impedance matching circuit 225, so that the groove 23 can accommodate the impedance matching circuit 225, ensure the structural strength of the circuit board 21, and weaken the circuit board 21 as much as possible.
  • the effect of stacked traces on the performance of the impedance matching circuit 225 is 2 mm to 3 mm.
  • the depth d of the groove 23 is within this range, the depth d of the groove 23 is moderate, which can avoid the impedance matching circuit 225.
  • the structural strength of the circuit board 21 and the performance of the impedance matching circuit 225 are both considered.
  • the connection line 100 between the first input pad 222, the at least one chip 223, and the first output pad 224 includes a first portion 101 and a second portion 101.
  • Part 102, in some embodiments, the connecting line 100 is also the impedance matching circuit 225 shown in FIGS. 10-13, the first part 101 is disposed on the surface 221a3 of the dielectric layer 2212 away from the heat dissipation layer 2211, and the second part 102 is connected to Between the first part 101 and the at least one chip 223, the second part 102 is suspended. The first part 101 is supported by the dielectric layer 2212.
  • the second part 102 is suspended in the air and the strength of the connection line is low. In the process of transportation, it is easy to be scratched when subjected to external force.
  • the chip 223 if the chip 223 is exposed and disposed, the chip 223 will be corroded by water and dust in the air during long-term transportation or storage, which will shorten the service life of the chip 223.
  • the electronic component 22 further includes an encapsulation layer 226.
  • the material of the encapsulation layer 226 is an insulating material, including but not limited to epoxy and silicone plastics.
  • the encapsulation layer 226 is disposed on the first surface 221a of the carrier 221, and the packaging layer 226 wraps at least one chip 223 and the second part 102 inside.
  • the chip 223 and the second part 102 are protected by the encapsulation layer 226 to prevent the second part 102 from being scratched during the transportation of the electronic component 22, and at the same time, to prevent water and dust from contacting the chip 223, which improves the electronic component 22 in
  • the yield rate in the processing and assembly process protects the chip 223 from external moisture and other factors, ensuring the long-term reliability of the electronic component products.
  • the encapsulation layer 226 may be disposed on the first surface 221a of the carrier board 221 by a packaging machine, or may be disposed on the first surface 221a of the carrier board 221 by a dispenser, which is not specifically limited herein.
  • the encapsulation layer 226 is disposed on the first surface 221a of the carrier 221 through a glue dispensing process.
  • the precision of the encapsulation layer 226 is made by the glue dispensing process to prevent the encapsulation layer 226 from covering the first input pad 222.
  • the first output pad 224 to affect the welding of the first input pad 222 and the first output pad 224 with the circuit board.
  • the encapsulation layer 226 is contained in the groove 23, so as to avoid the encapsulation layer 226 through the groove 23 and prevent the encapsulation layer 226 and the circuit Interference occurs between the plates 21.

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Abstract

一种电子元件(22)、带电子元件(22)的电路板(21)和电子设备，涉及电子设备技术领域，能够缩短电子元件(22)的散热路径，提高电子元件(22)的散热效率，同时保证电子元件(22)的输入输出阻抗匹配性能。该电子元件(22)包括载板(221)和设置于所述载板(221)的第一表面(221a)的第一输入焊盘(222)、至少一个芯片(223)和第一输出焊盘(224)，所述第一输入焊盘(222)、所述至少一个芯片(223)、所述第一输出焊盘(224)依次连接，所述第一输入焊盘(222)和所述第一输出焊盘(224)直接设置于所述载板(221)的第一表面(221a)上，且所述第一输入焊盘(222)背离所述载板(221)的表面和所述第一输出焊盘(224)背离所述载板(221)的表面构成所述电子元件(22)的外表面的部分区域。电子元件(22)用作功率放大器。

Description

一种电子元件、带电子元件的电路板和电子设备 技术领域
本申请涉及电子设备技术领域，尤其涉及一种电子元件、带电子元件的电路板和电子设备。
背景技术
在诸如无线基站等电子设备中，随着电路板上电子元件的高集成性高密度排布，需要对电路板进行散热，同时，为了在电路板上集成更多的电子元件，电子元件趋向于模组化。
示例的，图1为现有技术中的一种模组化的电子元件01，如图1所示，该电子元件01包括载板011、芯片012、输入焊盘013、输出焊盘014和塑封层015，载板011包括相对的第一表面011a和第二表面011b，芯片012设置于第一表面011a，输入焊盘013和输出焊盘014设置于第二表面011b，芯片012的输入端通过第一金属化过孔016与输入焊盘013连接，芯片012的输出端通过第二金属化过孔017与输出焊盘014连接，塑封层015设置于载板011的第一表面011a，并将芯片012包裹在内。
图1所示电子元件01通常正装于电路板上，图2为电子元件01正装于电路板02上时的结构示意图，参见图2，电子元件01的载板011与电路板02相贴，电子元件01的输入焊盘和输出焊盘分别与电路板02上的输出焊盘和输入焊盘焊接，电路板02背离电子元件01的表面通过胶体导热材料与散热器03相贴。这样，电子元件01内芯片012产生的热量依次经由载板011、电路板02传导至散热器03，以实现电子元件01的冷却，此冷却路径较长，散热效率较低。为了提高电子元件的散热效率，在一些现有技术中，电子元件01采用倒装方式贴附于电路板朝向散热器的表面，图3为电子元件01采用倒装方式贴附于电路板02朝向散热器03的表面时的结构示意图，参见图3，电子元件01的载板011直接与散热器03相贴，电子元件01的散热路径较短，散热效率较高。而当电子元件01倒装时，需要在电子元件01内设置电连接结构以引出芯片012的输入端和输出端来实现与电路板02的电连接，在一些现有方案中，如图3所示，电子元件01的输入焊盘013和输出焊盘014设置于载板011的第一表面011a，芯片012的输入端与输入焊盘013连接，芯片012的输出端与输出焊盘014连接，输入焊盘013和输出焊盘014上分别焊接有铜柱A，铜柱A封装于封装层015内，且铜柱A远离载板011的一端端面未被封装层015覆盖，电子元件01通过两根铜柱A远离载板011的表面焊接于电路板02的输入焊盘和输出焊盘上。为了实现电子元件01的良好阻抗匹配，对铜柱A的加工精度和装配精度要求较高，但是由于电子元件01的尺寸较小，因此能够安装于电子元件01内的铜柱A的直径和长度较小，加工难度较大，精度较低，且铜柱A在载板011上的装配精度较小，因此容易影响电子元件01的输入输出阻抗匹配性能。在另一些现有方案中，如图4所示，采用设有金属化过孔的印制电路板B替代图3所示方案中的铜柱A，输入焊盘013和输出焊盘014分别通过印制电路板B上的两个金属化过孔与电路板2的输入焊盘和输出焊盘连接，在印制 电路板B的支撑下，金属化过孔的尺寸精度可以制作得较高，能够在一定程度上减小对电子元件01的输入输出阻抗匹配性能的影响，但是，该设有金属化过孔的印制电路板B在加工和装配过程中，仍然不可避免的会存在误差，仍会影响电子元件01的输入输出阻抗匹配性能。
发明内容
本申请的实施例提供一种电子元件、带电子元件的电路板和电子设备，能够缩短电子元件的散热路径，提高电子元件的散热效率，同时保证电子元件的输入输出阻抗匹配性能。
为达到上述目的，本申请的实施例采用如下技术方案：
第一方面，本申请一些实施例提供一种电子元件，包括载板和设置于该载板的第一表面的第一输入焊盘、至少一个芯片和第一输出焊盘，芯片包括但不仅限于功率放大器芯片，第一输入焊盘、至少一个芯片、第一输出焊盘依次连接，第一输入焊盘和第一输出焊盘直接设置于载板的第一表面上，且第一输入焊盘背离载板的表面和第一输出焊盘背离载板的表面构成电子元件的外表面的部分区域。
与现有技术相比，由于本申请实施例提供的电子元件在倒装于电路板上并与散热器相贴时，电子元件内至少一个芯片在工作时产生的热量可以通过载板直接传导至散热器，带电子元件的电路板散热路径较短，散热效率较高。同时，由于第一输入焊盘和第一输出焊盘直接设置于载板的第一表面上，且第一输入焊盘背离载板的表面和第一输出焊盘背离载板的表面构成电子元件的外表面的部分区域，也即是，第一输入焊盘背离载板的表面和第一输出焊盘背离载板的表面裸露设置，第一输入焊盘背离载板的表面和第一输出焊盘背离载板的表面无遮盖，第一输入焊盘和第一输出焊盘可以直接焊接于电路板上的输出焊盘和输入焊盘上，第一输入焊盘和第一输出焊盘分别与电路板上的输出焊盘和输入焊盘之间无中间连接结构，电子元件内芯片的输入端和输出端的引出路径较短，引出线路的精度较高，电子元件的输入输出阻抗匹配性能能够得到有效保证。
可选的，载板包括层叠设置的散热层和电介质层；电介质层上设有至少一个容纳槽，容纳槽贯穿该电介质层，散热层的表面上与容纳槽相对的区域、容纳槽的侧面和电介质层远离散热层的表面构成载板的第一表面，至少一个芯片设置于至少一个容纳槽内并与散热层的表面上与容纳槽相对的区域固定，第一输入焊盘和第一输出焊盘设置于电介质层远离散热层的表面。这样一来，由于散热层的导热性能较优，因此至少一个芯片工作时产生的热量可以由散热层快速传导至散热器，有利于提高电子元件的散热性能。同时，由于电介质层具有绝缘性能，因此该电介质层可以实现第一输入焊盘与散热层之间、第一输出焊盘与散热层之间以及第一输入焊盘、至少一个芯片、第一输出焊盘之间的连接线路与散热层之间的绝缘隔离，防止出现短路。而且，由于至少一个芯片设置于至少一个容纳槽内，因此可以避免至少一个芯片凸出载板的轮廓外，从而避免至少一个芯片在电子元件连接于电路板上时与电路板之间产生干涉。
可选的，还包括阻抗匹配电路；第一输入焊盘、至少一个芯片和第一输出焊盘之间通过阻抗匹配电路连接。这样一来，通过阻抗匹配电路对至少一个芯片的输入、输出或级间进行阻抗匹配，以使微波信号能量尽可能多地传输至至少一个芯片或者电路 板上与该电子元件的输出端连接的其他负载上。
可选的，至少一个芯片包括一个芯片，阻抗匹配电路包括第一阻抗匹配电路和第二阻抗匹配电路，第一输入焊盘通过第一阻抗匹配电路与芯片的输入端连接，芯片的输出端通过第二阻抗匹配电路与第一输出焊盘连接，第一阻抗匹配电路将电路板上与第一输入焊盘连接的负载的输出阻抗匹配到芯片的输入阻抗，第二阻抗匹配电路将芯片的输出阻抗匹配到电路板上与第一输出焊盘连接的负载的输入阻抗。这样一来，电路板上与第一输入焊盘连接的负载输出的信号能够全部传输至芯片，芯片输出的信号能够全部传输至电路板上与第一输出焊盘连接的负载，由此减小了信号反射，降低了信号能量的损失。
可选的，至少一个芯片包括两个芯片，阻抗匹配电路包括第一阻抗匹配电路、第二阻抗匹配电路和第三阻抗匹配电路，第一输入焊盘通过第一阻抗匹配电路与一个芯片的输入端连接，该一个芯片的输出端通过第三阻抗匹配电路与另一个芯片的输入端连接，该另一个芯片的输出端通过第二阻抗匹配电路与第一输出焊盘连接，第一阻抗匹配电路将电路板上与第一输入焊盘连接的负载的输出阻抗匹配到该一个芯片的输入阻抗，第三阻抗匹配电路将该一个芯片的输出阻抗匹配到该另一个芯片的输入阻抗，第二阻抗匹配电路将该另一个芯片的输出阻抗匹配到电路板上与第一输出焊盘连接的负载的输入阻抗。这样一来，电路板上与第一输入焊盘连接的负载输出的信号能够全部传输至该一个芯片，该一个芯片输出的信号能够全部传输至该另一个芯片，该另一个芯片输出的信号能够全部传输至电路板上与第一输出焊盘连接的负载，由此减小了信号反射，降低了信号能量的损失。
可选的，第一输入焊盘、至少一个芯片和第一输出焊盘之间的连接线路包括第一部分和第二部分，第一部分设置于电介质层远离散热层的表面，第二部分连接于第一部分与至少一个芯片之间；电子元件还包括封装层，封装层设置于载板的第一表面，且封装层将至少一个芯片和第二部分包裹在内。这样一来，通过封装层对芯片和第二部分形成保护，以避免第二部分在电子元件运输过程中被刮断，同时避免水和粉尘接触芯片，由此延长了芯片的使用寿命。
可选的，封装层通过点胶工艺设置于载板的第一表面。点胶工艺制作封装层时的精度较高，避免封装层覆盖到第一输入焊盘和第一输出焊盘上而影响第一输入焊盘和第一输出焊盘与电路板的焊接。
可选的，至少一个芯片为功率放大器芯片。
可选的，至少一个芯片包括多个芯片，多个芯片串联连接于第一输入焊盘与第一输出焊盘之间。
第二方面，本申请一些实施例提供一种带电子元件的电路板，包括电路板和如上任一技术方案所述的电子元件，电路板的第一表面设有第二输出焊盘和第二输入焊盘，第二输出焊盘和第二输入焊盘连接于电路板的电路中，电子元件位于第二输出焊盘和第二输入焊盘远离电路板的一侧，且电子元件的载板的第一表面朝向电路板，电子元件的第一输入焊盘与第二输出焊盘直接焊接，电子元件的第一输出焊盘与第二输入焊盘直接焊接。
与现有技术相比，当本申请实施例提供的带电子元件的电路板通过电子元件与散 热器贴合时，电子元件内至少一个芯片在工作时产生的热量可以通过载板直接传导至散热器，带电子元件的电路板散热路径较短，散热效率较高。同时，由于第一输入焊盘和第一输出焊盘直接设置于载板的第一表面上，第一输入焊盘、至少一个芯片、第一输出焊盘依次连接，电子元件通过第一输入焊盘和第一输出焊盘分别与电路板的第二输出焊盘和第二输入焊盘直接焊接，因此第一输入焊盘与第二输出焊盘之间以及第一输出焊盘与第二输入焊盘之间无中间连接结构，电子元件内芯片的输入端和输出端的引出路径较短，引出线路的精度较高，电子元件的输入输出阻抗匹配性能能够得到有效保证。
可选的，电子元件包括阻抗匹配电路，第一输入焊盘、电子元件的至少一个芯片和第一输出焊盘之间通过阻抗匹配电路连接；电路板上与阻抗匹配电路相对的位置设有凹槽，阻抗匹配电路容纳于凹槽内。这样一来，通过凹槽拉远了阻抗匹配电路与电路板内层叠走线之间的距离，避免电路板内的层叠走线对阻抗匹配电路产生影响。同时通过凹槽避让阻抗匹配电路，避免阻抗匹配电路与电路板之间产生干涉。
可选的，凹槽的侧面和底面上均设有金属屏蔽层。金属屏蔽层能够屏蔽隔离阻抗匹配电路与电路板内的层叠走线，避免阻抗匹配电路受到电路板内的层叠走线的影响。
可选的，所述凹槽的深度为2mm～3mm。凹槽的深度在此范围内时，凹槽的深度适中，能够在避让阻抗匹配电路的同时，兼顾电路板的结构强度和阻抗匹配电路的性能。
可选的，带电子元件的电路板为大规模多输入多输出天线收发电路板。
第三方面，本申请一些实施例提供一种电子设备，包括散热器和如上任一技术方案所述的带电子元件的电路板，散热器位于电子元件远离电路板的一侧，且电子元件远离电路板的表面与散热器的表面贴合，或者，电子元件远离电路板的表面与散热器的表面之间具有间隙，该间隙内填充有导热材料。
本申请实施例提供的电子设备，由于该电子设备包括如上任一技术方案所述的带电子元件的电路板，因此本申请实施例提供的电子设备与如上任一技术方案所述的带电子元件的电路板能够解决相同的技术问题，并达到相同的预期效果。
可选的，电子设备为无线基站。
附图说明
图1为现有技术中的一种电子元件的结构示意图；
图2为现有技术中的第一种电子元件、电路板和散热器的装配结构示意图；
图3为现有技术中的第二种电子元件、电路板和散热器的装配结构示意图；
图4为现有技术中的第三种电子元件、电路板和散热器的装配结构示意图；
图5为本申请实施例提供的一种电子设备的结构示意图；
图6为本申请实施例提供的第一种带电子元件的电路板的结构示意图；
图7为本申请实施例提供的第一种电子元件的结构示意图；
图8为本申请实施例提供的第二种电子元件的结构示意图；
图9为图8所示电子元件沿截面A-A的剖视图；
图10为本申请实施例提供的第三种电子元件的结构示意图；
图11为图10所示电子元件沿截面B-B的剖视图；
图12为本申请实施例提供的第四种电子元件的结构示意图；
图13为图12所示电子元件沿截面C-C的剖视图；
图14为本申请实施例提供的第二种带电子元件的电路板的结构示意图；
图15为本申请实施例提供的第五种电子元件的结构示意图。
附图标记：
01-电子元件；011-载板；012-芯片；013-输入焊盘；014-输出焊盘；015-塑封层；011a-载板的第一表面；011b-载板的第二表面；016-第一金属化过孔；017-第二金属化过孔；02-电路板；03-散热器；1-散热器；2-带电子元件的电路板；21-电路板；21a-电路板的第一表面；211-第二输出焊盘；212-第二输入焊盘；22-电子元件；221-载板；221a-载板的第一表面；2211-散热层；2212-电介质层；2213-容纳槽；221a1-散热层的表面上与容纳槽相对的区域；221a2-容纳槽的侧面；221a3-电介质层远离散热层的表面；222-第一输入焊盘；223-芯片；224-第一输出焊盘；225-阻抗匹配电路；2251-第一阻抗匹配电路；2252-第二阻抗匹配电路；2253-第三阻抗匹配电路；226-封装层；23-凹槽；100-连接线路；101-连接线路的第一部分；102-连接线路的第二部分。
具体实施方式
本申请实施例涉及电子元件、带电子元件的电路板和电子设备，以下对上述实施例涉及到的概念进行简单说明：
电子设备，是指内部具有电子电路，并应用电子技术软件发挥作用的设备；
电路板，是指由电介质层以及设置于电介质层上的线路、焊盘、过孔组成的结构，用于实现电子元件之间的相互连接以构成一个具有特定功能的电子电路；
电极化，是指在外电场作用下产生宏观上不等于零的电偶极矩，由此形成宏观束缚电荷的现象；
电介质，是指能够产生电极化现象的物质，包括晶态电介质层和非晶态电介质层，电介质的电阻率一般都很高，具有绝缘性能；
电介质层，是指由电介质组成的层状结构；
电子元件，是电子电路中的基本元素，通常是个别封装，并具有两个或两个以上的引脚；
阻抗匹配电路，阻抗匹配是微波电子学里的一部分，主要用于传输线上，来达到所有高频的微波信号皆能传至负载点的目的，几乎不会有信号反射回来源点，从而提升能源效益。
在诸如无线基站等电子设备中，随着电子元件在电路板上的高集成性高密度排布，需要对带电子元件的电路板进行有效散热。同时，电子元件内芯片的输入端和输出端的引出线路需做到高精度，以保证电子元件的阻抗匹配性能。
为了达到上述两个目的，图5为本申请一些实施例提供一种电子设备，该电子设备包括但不限于无线基站，如图5所示，电子设备包括散热器1和带电子元件的电路板2。散热器1包括但不限于翅片式散热器和冷媒冷却式散热器。
图6为本申请一些实施例提供的一种带电子元件的电路板，该带电子元件的电路板2为具有特定功能的电子电路结构，比如为无线基站内的大规模多输入多输出(massive multiple-input multiple-output，Massive MIMO)天线收发电路板，如图6所 示，带电子元件的电路板2包括电路板21和电子元件22。
图7为本申请一些实施例提供的一种电子元件22，该电子元件22包括但不限于功放模组(power amplifier module，PAM)，如图7所示，电子元件22包括载板221和设置于该载板221的第一表面221a的第一输入焊盘222、至少一个芯片223和第一输出焊盘224，芯片223包括但不仅限于功率放大器芯片，第一输入焊盘222、至少一个芯片223、第一输出焊盘224依次连接，第一输入焊盘222和第一输出焊盘224直接设置于载板221的第一表面221a上，且第一输入焊盘222背离载板221的表面和第一输出焊盘224背离载板221的表面构成电子元件22的外表面的部分区域。
需要说明的是，第一输入焊盘222和第一输出焊盘224直接设置于载板221的第一表面221a上，也即是，第一输入焊盘222和第一输出焊盘224直接与载板221的第一表面221a接触并固定，第一输入焊盘222与载板221的第一表面221a之间以及第一输出焊盘224与载板221的第一表面221a之间无中间连接结构。
需要说明的是，第一输入焊盘222背离载板221的表面和第一输出焊盘224背离载板221的表面构成电子元件22的外表面的部分区域，也即是，第一输入焊盘222背离载板221的表面和第一输出焊盘224背离载板221的表面裸露设置，第一输入焊盘222背离载板221的表面和第一输出焊盘224背离载板221的表面无遮盖。
至少一个芯片223可以包括一个芯片223，也可以包括多个芯片223，在此不做具体限定。在一些实施例中，至少一个芯片223包括多个芯片223，多个芯片223串联连接于第一输入焊盘222与第一输出焊盘224之间。
如图6所示，电路板21的第一表面21a设有第二输出焊盘211和第二输入焊盘212，第二输出焊盘211和第二输入焊盘212连接于电路板21的电路中，电子元件22位于第二输出焊盘211和第二输入焊盘212远离电路板21的一侧，且电子元件22的载板221的第一表面221a朝向电路板21，电子元件22的第一输入焊盘222与第二输出焊盘212直接焊接，电子元件22的第一输出焊盘224与第二输入焊盘211直接焊接。
需要说明的是，电子元件22的第一输入焊盘222与第二输出焊盘212直接焊接，也即是，电子元件22的第一输入焊盘222与第二输出焊盘212直接接触并焊接，电子元件22的第一输入焊盘222与第二输出焊盘212之间无中间连接结构。
同理，电子元件22的第一输出焊盘224与第二输入焊盘211直接焊接，也即是，电子元件22的第一输出焊盘224与第二输入焊盘211直接接触并焊接，电子元件22的第一输出焊盘224与第二输入焊盘211之间无中间连接结构。
如图5所示，散热器1位于电子元件22远离电路板21的一侧，且电子元件22远离电路板21的表面与散热器1的表面贴合。
或者，电子元件22远离电路板21的表面与散热器1的表面之间具有间隙，该间隙内填充有导热材料3。导热材料3包括但不限于导热硅脂胶和导热矽胶布。
这样一来，电子元件22内至少一个芯片223在工作时产生的热量可以通过载板221直接传导至散热器1，带电子元件的电路板2散热路径较短，散热效率较高。
同时，由于第一输入焊盘222和第一输出焊盘224直接设置于载板221的第一表面221a上，第一输入焊盘222、至少一个芯片223、第一输出焊盘224依次连接，电子元件22通过第一输入焊盘222和第一输出焊盘224分别与电路板21的第二输出焊 盘212和第二输入焊盘211直接焊接，因此第一输入焊盘222与第二输出焊盘212之间以及第一输出焊盘224与第二输入焊盘211之间无中间连接结构，电子元件22内芯片223的输入端和输出端的引出路径较短，引出线路的精度较高，电子元件22的输入输出阻抗匹配性能能够得到有效保证。
为了使载板221能够将芯片223工作时产生的热量传导至散热器，在一些实施例中，如图8和图9所示，载板221包括层叠设置的散热层2211和电介质层2212；散热层2211的材料包括但不限于铝系金属和铜，电介质层2212具有绝缘性能，电介质层2212上设有至少一个容纳槽2213，该容纳槽2213贯穿电介质层2212，散热层2211的表面上与容纳槽2213相对的区域221a1、容纳槽2213的侧面221a2和电介质层2212远离散热层2211的表面221a3构成载板221的第一表面221a，至少一个芯片223设置于至少一个容纳槽2213内并与散热层2211的表面上与容纳槽2213相对的区域221a1固定，第一输入焊盘222和第一输出焊盘224设置于电介质层2212远离散热层2211的表面221a3。
这样一来，由于散热层2211的导热性能较优，因此至少一个芯片223工作时产生的热量可以由散热层2211快速传导至散热器，有利于提高电子元件22的散热性能。同时，由于电介质层2212具有绝缘性能，因此该电介质层2212可以实现第一输入焊盘222与散热层2211之间、第一输出焊盘224与散热层2211之间以及第一输入焊盘222、至少一个芯片223、第一输出焊盘224之间的连接线路与散热层2211之间的绝缘隔离，防止出现短路。而且，由于至少一个芯片223设置于至少一个容纳槽2213内，因此可以避免至少一个芯片223凸出载板221的轮廓外，从而避免至少一个芯片223在电子元件22连接于电路板21上时与电路板之间产生干涉。
当电子元件22工作于微波信号下时，为了减小至少一个芯片223的输入反射和输出反射，以使微波信号能量尽可能多地传输至至少一个芯片223或者电路板上与该电子元件22的输出端连接的其他负载上，在一些实施例中，如图10或图11所示，还包括阻抗匹配电路225；第一输入焊盘222、至少一个芯片223、第一输出焊盘224之间通过该阻抗匹配电路225连接。阻抗匹配电路225的结构包括但不限于微带线和电子元器件连接形成电子电路。
这样一来，通过阻抗匹配电路225对至少一个芯片223的输入、输出或级间进行阻抗匹配，以使微波信号能量尽可能多地传输至至少一个芯片223或者电路板上与该电子元件22的输出端连接的其他负载上。
阻抗匹配电路225的结构可以通过以下两个示例进行详细说明：
示例一：如图10和图11所示，至少一个芯片223包括一个芯片223，阻抗匹配电路225包括第一阻抗匹配电路2251和第二阻抗匹配电路2252，第一输入焊盘222通过第一阻抗匹配电路2251与芯片223的输入端连接，芯片223的输出端通过第二阻抗匹配电路2252与第一输出焊盘224连接，第一阻抗匹配电路2251将电路板上与第一输入焊盘222连接的负载的输出阻抗匹配到芯片223的输入阻抗，第二阻抗匹配电路2252将芯片223的输出阻抗匹配到电路板上与第一输出焊盘224连接的负载的输入阻抗。
这样一来，电路板上与第一输入焊盘222连接的负载输出的信号能够全部传输至 芯片223，芯片223输出的信号能够全部传输至电路板上与第一输出焊盘224连接的负载，由此减小了信号反射，降低了信号能量的损失。
示例二：如图12和图13所示，至少一个芯片223包括两个芯片223，阻抗匹配电路225包括第一阻抗匹配电路2251、第二阻抗匹配电路2252和第三阻抗匹配电路2253，第一输入焊盘222通过第一阻抗匹配电路2251与一个芯片223的输入端连接，该一个芯片223的输出端通过第三阻抗匹配电路2253与另一个芯片223的输入端连接，该另一个芯片223的输出端通过第二阻抗匹配电路2252与第一输出焊盘224连接，第一阻抗匹配电路2251将电路板上与第一输入焊盘222连接的负载的输出阻抗匹配到该一个芯片223的输入阻抗，第三阻抗匹配电路2253将该一个芯片223的输出阻抗匹配到该另一个芯片223的输入阻抗，第二阻抗匹配电路2252将该另一个芯片223的输出阻抗匹配到电路板上与第一输出焊盘224连接的负载的输入阻抗。
这样一来，电路板上与第一输入焊盘222连接的负载输出的信号能够全部传输至该一个芯片223，该一个芯片223输出的信号能够全部传输至该另一个芯片223，该另一个芯片223输出的信号能够全部传输至电路板上与第一输出焊盘224连接的负载，由此减小了信号反射，降低了信号能量的损失。
电路板21由多个电路板单元层叠设置，每个电路板单元上均设有走线，为了避免阻抗匹配电路225在电子元件22连接于电路板21上时与电路板21内的层叠走线的距离过近，而使电路板21内的层叠走线影响阻抗匹配电路225的性能，或者，为了避免阻抗匹配电路225在电子元件22连接于电路板21上时与电路板21之间产生干涉，在一些实施例中，如图14所示，电路板21上与阻抗匹配电路225相对的位置设有凹槽23，阻抗匹配电路225容纳于凹槽23内。
这样一来，通过凹槽23拉远了阻抗匹配电路225与电路板21内层叠走线之间的距离，避免电路板21内的层叠走线对阻抗匹配电路225产生影响。同时通过凹槽23避让阻抗匹配电路225，避免阻抗匹配电路225与电路板21之间产生干涉。
为了进一步避免阻抗匹配电路225在电子元件22连接于电路板21上时受到电路板21内的层叠走线的影响，在一些实施例中，凹槽23的侧面和底面上均设有金属屏蔽层。金属屏蔽层能够屏蔽隔离阻抗匹配电路225与电路板21内的层叠走线，避免阻抗匹配电路225受到电路板21内的层叠走线的影响。
凹槽23的深度可以为1mm、2mm、3mm等等，在此不做具体限定，具体可以根据阻抗匹配电路225凸出载板221的第一表面221a的高度大小、电路板21的结构强度要求以及凹槽23的深度对阻抗匹配电路225的性能的影响大小进行综合设计，以使凹槽23能够容纳阻抗匹配电路225，保证电路板21的结构强度，并尽可能地削弱电路板21内的层叠走线对阻抗匹配电路225的性能的影响。在一些实施例中，如图14所示，凹槽23的深度d为2mm～3mm，凹槽23的深度d在此范围内时，凹槽23的深度适中，能够在避让阻抗匹配电路225的同时，兼顾电路板21的结构强度和阻抗匹配电路225的性能。
如图8和图9所示，载板221的第一表面221a上，第一输入焊盘222、至少一个芯片223、第一输出焊盘224之间的连接线路100包括第一部分101和第二部分102，在一些实施例中，连接线路100也即是图10～图13所示的阻抗匹配电路225，第一部 分101设置于电介质层2212远离散热层2211的表面221a3，第二部分102连接于第一部分101与至少一个芯片223之间，第二部分102悬空设置。第一部分101受电介质层2212的支撑，在电子元件22搬运过程中，受外力作用时，不容易被刮断，而第二部分102由于悬空设置，且连接线路的强度较低，在电子元件22搬运过程中，受外力作用时，容易被刮断。另外，若芯片223裸露设置，则长时间运输或存放过程中，芯片223会受到空气中的水和灰尘的侵蚀，导致芯片223的使用寿命缩短。
为了解决上述问题，在一些实施例中，如图15所示，电子元件22还包括封装层226，封装层226的材料为绝缘材料，包括但不限于环氧类和硅酮类塑料，封装层226设置于载板221的第一表面221a，且封装层226将至少一个芯片223和第二部分102包裹在内。
这样一来，通过封装层226对芯片223和第二部分102形成保护，以避免第二部分102在电子元件22运输过程中被刮断，同时避免水和粉尘接触芯片223，提升电子元件22在加工组装过程中的成品率，保护芯片223受免受外部湿气等因素侵蚀，保证电子元件产品使用的长期可靠性。
封装层226可以通过封装机设置于载板221的第一表面221a，也可以通过点胶机设置于载板221的第一表面221a，在此不做具体限定。在一些实施例中，封装层226通过点胶工艺设置于载板221的第一表面221a上，点胶工艺制作封装层226时的精度较高，避免封装层226覆盖到第一输入焊盘222和第一输出焊盘224上而影响第一输入焊盘222和第一输出焊盘224与电路板的焊接。
需要说明的是，当该具有封装层226的电子元件22安装于电路板21上时，封装层226容纳于凹槽23，以通过凹槽23对封装层226形成避让，防止封装层226与电路板21之间产生干涉。
在本说明书的描述中，具体特征、结构、材料或者特点可以在任何的一个或多个实施例或示例中以合适的方式结合。
最后应说明的是：以上实施例仅用以说明本申请的技术方案，而非对其限制；尽管参照前述实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的精神和范围。

Claims (13)

  1. 一种电子元件，其特征在于，包括载板和设置于所述载板的第一表面的第一输入焊盘、至少一个芯片和第一输出焊盘，所述第一输入焊盘、所述至少一个芯片、所述第一输出焊盘依次连接，所述第一输入焊盘和所述第一输出焊盘直接设置于所述载板的第一表面上，且所述第一输入焊盘背离所述载板的表面和所述第一输出焊盘背离所述载板的表面构成所述电子元件的外表面的部分区域。
  2. 根据权利要求1所述的电子元件，其特征在于，所述载板包括层叠设置的散热层和电介质层；
    所述电介质层上设有至少一个容纳槽，所述容纳槽贯穿所述电介质层，所述散热层的表面上与所述容纳槽相对的区域、所述容纳槽的侧面和所述电介质层远离所述散热层的表面构成所述载板的第一表面，所述至少一个芯片设置于所述至少一个容纳槽内并与所述散热层的表面上与所述容纳槽相对的区域固定，所述第一输入焊盘和所述第一输出焊盘设置于所述电介质层远离所述散热层的表面。
  3. 根据权利要求2所述的电子元件，其特征在于，还包括阻抗匹配电路；
    所述第一输入焊盘、所述至少一个芯片和所述第一输出焊盘之间通过所述阻抗匹配电路连接。
  4. 根据权利要求2或3所述的电子元件，其特征在于，所述第一输入焊盘、所述至少一个芯片和所述第一输出焊盘之间的连接线路包括第一部分和第二部分，所述第一部分设置于所述电介质层远离所述散热层的表面，所述第二部分连接于所述第一部分与所述至少一个芯片之间；
    所述电子元件还包括封装层，所述封装层设置于所述载板的第一表面，且所述封装层将所述至少一个芯片和所述第二部分包裹在内。
  5. 根据权利要求4所述的电子元件，其特征在于，所述封装层通过点胶工艺设置于所述载板的第一表面。
  6. 根据权利要求1～5中任一项所述的电子元件，其特征在于，所述至少一个芯片为功率放大器芯片。
  7. 根据权利要求1～6中任一项所述的电子元件，其特征在于，所述至少一个芯片包括多个芯片，所述多个芯片串联连接于所述第一输入焊盘与所述第一输出焊盘之间。
  8. 一种带电子元件的电路板，其特征在于，包括电路板和权利要求1～7中任一项所述的电子元件，所述电路板的第一表面设有第二输出焊盘和第二输入焊盘，所述第二输出焊盘和所述第二输入焊盘连接于所述电路板的电路中，所述电子元件位于所述第二输出焊盘和所述第二输入焊盘远离所述电路板的一侧，且所述电子元件的载板的第一表面朝向所述电路板，所述电子元件的第一输入焊盘与所述第二输出焊盘直接焊接，所述电子元件的第一输出焊盘与所述第二输入焊盘直接焊接。
  9. 根据权利要求8所述的带电子元件的电路板，其特征在于，所述电子元件包括阻抗匹配电路，所述第一输入焊盘、所述电子元件的至少一个芯片和所述第一输出焊盘之间通过所述阻抗匹配电路连接；
    所述电路板上与所述阻抗匹配电路相对的位置设有凹槽，所述阻抗匹配电路容纳于所述凹槽内。
  10. 根据权利要求9所述的带电子元件的电路板，其特征在于，所述凹槽的侧面和底面上均设有金属屏蔽层。
  11. 根据权利要求9或10所述的带电子元件的电路板，其特征在于，所述凹槽的深度为2mm～3mm。
  12. 根据权利要求8～11中任一项所述的带电子元件的电路板，其特征在于，所述带电子元件的电路板为大规模多输入多输出天线收发电路板。
  13. 一种电子设备，其特征在于，包括散热器和权利要求8～12中任一项所述的带电子元件的电路板，所述散热器位于所述电子元件远离所述电路板的一侧，且所述电子元件远离所述电路板的表面与所述散热器的表面贴合，或者，所述电子元件远离所述电路板的表面与所述散热器的表面之间具有间隙，所述间隙内填充有导热材料。
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US20220304138A1 (en) 2022-09-22
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