WO2021109508A1 - 基于同步机实现多信号源同步输出的同步系统、同步方法及校准方法 - Google Patents

基于同步机实现多信号源同步输出的同步系统、同步方法及校准方法 Download PDF

Info

Publication number
WO2021109508A1
WO2021109508A1 PCT/CN2020/094393 CN2020094393W WO2021109508A1 WO 2021109508 A1 WO2021109508 A1 WO 2021109508A1 CN 2020094393 W CN2020094393 W CN 2020094393W WO 2021109508 A1 WO2021109508 A1 WO 2021109508A1
Authority
WO
WIPO (PCT)
Prior art keywords
signal source
synchronization
source devices
machine
signal
Prior art date
Application number
PCT/CN2020/094393
Other languages
English (en)
French (fr)
Inventor
毛为勇
生兆东
冯艳红
王悦
王铁军
李维森
Original Assignee
普源精电科技股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 普源精电科技股份有限公司 filed Critical 普源精电科技股份有限公司
Publication of WO2021109508A1 publication Critical patent/WO2021109508A1/zh

Links

Images

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04JMULTIPLEX COMMUNICATION
    • H04J3/00Time-division multiplex systems
    • H04J3/02Details
    • H04J3/06Synchronising arrangements
    • H04J3/0635Clock or time synchronisation in a network
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00Automatic control of frequency or phase; Synchronisation
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04JMULTIPLEX COMMUNICATION
    • H04J3/00Time-division multiplex systems
    • H04J3/02Details
    • H04J3/06Synchronising arrangements
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04JMULTIPLEX COMMUNICATION
    • H04J3/00Time-division multiplex systems
    • H04J3/02Details
    • H04J3/06Synchronising arrangements
    • H04J3/0635Clock or time synchronisation in a network
    • H04J3/0638Clock or time synchronisation among nodes; Internode synchronisation

Definitions

  • the present invention relates to the field of communication technology, and more specifically, to a synchronization system, a synchronization method and a calibration method for realizing synchronous output of multiple signal sources based on a synchronization machine.
  • the present invention provides a synchronization system, a synchronization method and a calibration method based on a synchronization machine to realize synchronous output of multiple signal sources.
  • the technical solutions are as follows:
  • a synchronization system based on a synchronization machine to realize multi-signal source and multi-channel synchronization output.
  • the synchronization system includes a synchronization machine and multiple signal source devices.
  • the synchronization machine has a plurality of communication interfaces, and each of the signal source devices is connected to one of the communication interfaces.
  • the synchronization machine is used to receive the input calibration signal and the sampling clock signal, and perform power division on the input calibration signal and the sampling clock signal respectively, so as to provide each of the signal source devices with a homologous calibration signal and a homologous sampling
  • the clock signal enables multiple signal source devices to output signals synchronously.
  • the synchronization system further includes a control device that communicates with the synchronization machine and a plurality of the signal source devices respectively, and the control device is used to control the synchronization And the working status of each of the signal source devices.
  • the synchronization machine has M communication interfaces, and each communication interface is used to communicate with one of the signal source devices.
  • Each signal source device includes N output channels.
  • the synchronization system includes M signal source devices, and the M signal source devices are connected to the M communication interfaces of the synchronization machine in a one-to-one correspondence.
  • each of the communication interfaces includes a first port, a second port, and a third port
  • each of the signal source devices includes a fourth port, a fifth port, and a sixth port.
  • the first port and the fourth port are correspondingly connected
  • the second port and the fifth port are correspondingly connected
  • the third port and the sixth port are correspondingly connected.
  • the synchronization machine sends the homologous sampling clock signal to the corresponding signal source device through the first port of each communication interface.
  • the synchronization machine sends the homologous calibration signal to the corresponding signal source device through the second port of each communication interface.
  • the synchronization machine communicates with the corresponding signal source device through the third port of each communication interface.
  • the synchronization machine is also used to configure any one of the multiple signal source devices as the primary signal source device, and configure the remaining signal source devices as auxiliary signals Source device.
  • the main signal source device is used to provide the input calibration signal for the synchronization machine.
  • the main signal source device is used to provide the input sampling clock signal for the synchronization machine, or the synchronization machine receives a sampling clock signal provided from outside.
  • a calibration method for realizing multi-signal source and multi-channel synchronous output based on a synchronization machine is applied to the above-mentioned synchronization system.
  • the calibration method includes: using the synchronization machine to signal any one of the multiple signal source devices.
  • the source device is configured as a main signal source device, and the remaining signal source devices are configured as auxiliary signal source devices; each of the signal source devices is provided with a homogenous sampling clock signal through the synchronization machine; and the main signal source device is used Send a calibration signal to the synchronization machine; divide the calibration signal by the synchronization machine, and provide a homologous calibration signal to each of the signal source devices; each of the signal source devices receives all When the same source calibration signal is used, the link delay value from the main signal source device to its own signal source device is calculated through each of the signal source devices, and the link delay value is defined as the time of the own signal source device Reference; and, calculating and adjusting the loop delay of each channel by each of the signal source devices, so that the loop delay of each channel is consistent with the time reference of the signal source device itself.
  • the calibration method further includes: controlling the synchronization machine through a control device to start a synchronization calibration process.
  • the calibration method before sending a calibration signal to the synchronization machine through the main signal source device, the calibration method further includes: controlling each signal source device to enter the synchronization calibration mode through the synchronization machine.
  • providing a homogenous sampling clock signal to each of the signal source devices through the synchronization machine includes: receiving a sampling clock signal from the main signal source device or externally provided by the synchronization machine ; Perform power division on the received sampling clock signal by the synchronization machine to provide a homologous sampling clock signal to each of the signal source devices.
  • the loop delay of each channel of each signal source device is calculated and adjusted so that the loop delay of each channel is equal to the time of the signal source device itself.
  • the reference consistent includes: controlling each of the signal source devices to enter the internal multi-channel synchronization calibration mode through the synchronization machine; calculating the loop delay of each channel of each of the signal source devices through each of the signal source devices; The signal source device analyzes and compares the calculation results of the loop delay of each channel; each of the signal source devices adjusts the loop delay of each channel according to the comparison result, so that the loop of each channel The delay is consistent with the time reference of the signal source device itself.
  • a synchronization method for realizing multi-channel synchronization output of multiple signal source devices based on a synchronization machine includes: executing any one of the above-mentioned calibration methods; and, after the execution of the calibration method is completed, passing through the The synchronizing machine switches each signal source device to the normal working mode to realize the simultaneous output of multiple signal source devices and multiple channels.
  • This synchronization system based on the synchronization machine to realize the synchronous output of multiple signal sources and multiple channels, through a synchronization machine to provide each signal source device with a homologous calibration signal and a homologous sampling clock signal, so that multiple signal source devices can output synchronously signal.
  • One synchronous machine can support the synchronous output of multi-channel signals of multiple signal source devices. If the interface design of one synchronous machine is expanded, one synchronous machine can also support the synchronous output of more signal source devices.
  • the synchronization system can also start the synchronization machine calibration mode according to the user configuration parameter changes, so that the synchronization machine automatically realizes multi-signal sources and multi-channels. Synchronous calibration output.
  • Figure 1 is a schematic diagram of the wiring between part of the equipment included in the N8241 signal source synchronization system of Agilent.
  • Figure 2 is a timing diagram of Agilent's N8241 signal source synchronization system.
  • Figure 3 is a schematic diagram of wiring between some devices included in the AWG7122C signal source synchronization system of Tektronix.
  • Figure 4 is a schematic diagram of the connection between the rear panel of multiple signal source devices and the rear panel of the synchronizer in the AWG70000 signal source synchronization system of Tektronix.
  • Figure 5 is a schematic diagram of the connection between the front panel of multiple signal source devices and the front panel of the sync machine in the AWG70000 signal source synchronization system of Tektronix.
  • FIG. 6 is a partial structural diagram of a synchronization system based on a synchronization machine to realize multi-signal source and multi-channel synchronous output according to an embodiment of the present invention.
  • FIG. 7 is a schematic diagram of the internal logic structure of a synchronous machine provided by an embodiment of the present invention.
  • FIG. 8 is a schematic flowchart of a calibration method for realizing multi-signal source and multi-channel synchronous output based on a synchronization machine according to an embodiment of the present invention.
  • FIG. 9 is a schematic flowchart of another calibration method based on a synchronization machine to realize synchronous output of multiple signal sources and multiple channels according to an embodiment of the present invention.
  • the technical means are different, and the achieved performance indicators are also very different.
  • the number of synchronization channels generally does not exceed 32 channels.
  • the delay deviation index is also different.
  • Figure 1 is a schematic diagram of the wiring of part of the equipment included in the N8241 signal source synchronization system of Agilent
  • Figure 2 is a timing diagram of the N8241 signal source synchronization system of Agilent.
  • the synchronization system 100 includes two signal source devices: a main signal source device and an auxiliary signal source device as an example to introduce the synchronization system. It is understandable that the synchronization system 100 may include multiple auxiliary signal source devices.
  • the number 1 means: power splitter;
  • the number 2 means: SMB adapting tee;
  • the number 3 means: 10-inch SMA cable assembly;
  • the number 4 means: SMB cable assembly;
  • the number 5 means: adapter Adapter/Adapter.
  • the synchronization system 100 establishes a synchronized output timing between multiple signal source devices by sharing a sample clock signal (Sample Clock), and using a synchronized clock signal (Sync Clock) and a trigger signal (Trigger).
  • the synchronization system 100 uses delay design methods such as clock signals and trigger signals to achieve synchronous output between multiple signal source devices.
  • the design is relatively simple, but the hardware wiring and line delay requirements are very strict, including clock lines and
  • the trigger synchronization line should be designed with equal length. It should be noted that, in the synchronization system 100 shown in FIG. 1, the cables connected to the CH1OUT ports of the main signal source device and the auxiliary signal source device must be of equal length, which also reflects the connection of the synchronization system 100 Strictness.
  • each device needs to accurately collect the phases of the clock signal and the trigger signal.
  • the synchronization accuracy that the synchronization system 100 can achieve generally has great limitations. With the increase in the number of devices that need to be synchronized, the synchronization system 100 The achievable synchronization accuracy will get worse and worse.
  • Figure 3 is a schematic diagram of the connections between some devices included in the Tektronix AWG7122C signal source synchronization system.
  • the synchronization system 200 uses an oscilloscope to measure the output delay deviation of two signal source devices AWG7122C, and then manually adjusts the signal source output delay, thereby realizing multi-channel synchronous output of multiple signal source devices.
  • the synchronization system 200 needs to rely on high-end oscilloscope equipment, and manual operation by the user is time-consuming.
  • the signal source has too many output channels, it is not convenient to calibrate, and the measurement accuracy of the oscilloscope may not necessarily meet the accuracy requirements.
  • Figure 4 is a schematic diagram of the connection between the rear panel of multiple signal source devices and the rear panel of the synchronizer in the AWG70000 signal source synchronization system of Tektronix.
  • Figure 5 is the AWG70000 signal of Tektronix.
  • the synchronization system 300 uses a synchronization machine 301 to realize the synchronization output of up to 4 AWG signal source devices 302, which is mainly by connecting the output of the CH1 channel of each signal source device 302 to the synchronization machine 301, through the synchronization machine 301
  • the above phase delay detection circuit calculates the output delay deviation between the four signal source devices 302, and then controls each signal source device 302 to adjust the phase output.
  • the design principle of the synchronization system 300 is similar to the design principle of using an oscilloscope to detect the output delay deviation between multiple signal source devices. The difference is that the synchronization system 300 can accurately detect each device on the synchronization machine 301. The output phase of the signal source device 302 is then controlled through a command interface to control each signal source device 302 to adjust the output delay. That is, the synchronization system 300 can automatically control each signal source device 302 to adjust their output phases without the user needing to manually Adjusting the output phase of each signal source device 302 can bring a better user experience to the user.
  • the embodiment of the present invention provides a synchronization system and method for realizing multi-signal source and multi-channel synchronous output based on a synchronous machine, and multiple signal source devices are realized by using one synchronous machine. Precise synchronization output between.
  • the synchronization system can support the synchronous output of M signal source devices and N output channel signals, and the synchronization output delay deviation of all channels is less than 20ps.
  • M is an integer not less than 2
  • N is an integer greater than or equal to M.
  • the synchronization system can extend the clock signal output port, calibration signal output port and command interface of the synchronization machine, so that the synchronization machine can support the synchronization output of more signal source devices, and the synchronization output delay deviation index will not decrease.
  • FIG. 6 is a partial structural diagram of a synchronization system based on a synchronization machine to realize multi-signal source and multi-channel synchronous output according to an embodiment of the present invention. Schematic diagram of the internal logical structure of the machine.
  • the synchronization system 600 includes a synchronization machine 61 and multiple signal source devices 62.
  • the synchronization machine 61 has a plurality of communication interfaces 611, and each of the signal source devices 62 is correspondingly connected to one communication interface 611.
  • the synchronization machine 61 is used to receive the input calibration signal and sampling clock signal, and perform power division on the input calibration signal and sampling clock signal, for example, perform 1 minute 8 fan-out on the input calibration signal and sampling clock signal, respectively, In order to provide each of the signal source devices 62 with a homologous calibration signal and a homologous sampling clock signal, so that multiple signal source devices 62 can output signals synchronously.
  • the signal sources of the multiple signal source devices 62 are AWG signal sources
  • the synchronization machine 61 has M communication interfaces 611, where M is an integer not less than 2.
  • the device 62 is in communication connection, that is, one sync machine 61 can connect to eight AWG signal source devices 62 through eight communication interfaces 611 at the same time.
  • the eight AWG signal source devices 62 are sequentially numbered AWG0, AWG1,..., AWG7, and are connected to the eight communication interfaces Port0, Port1,..., Port7 of the synchronization machine 61 in a one-to-one correspondence.
  • each AWG signal source device may include one or more output channels.
  • each AWG signal source device 62 includes 8 output channels as an example, and the 8 output channels are sequentially numbered CH0, ..., CH7.
  • the synchronization machine 61 and each AWG signal source device 62 transmit at least three kinds of signals related to the synchronization calibration signal: a homologous sampling clock signal, a homologous calibration signal, and a command signal.
  • each of the communication interfaces 611 includes a first port P1, a second port P2, and a third port P3.
  • each of the AWG signal source devices 62 includes a fourth port P4, a fifth port P5, and a sixth port P6.
  • the first port P1 and the fourth port P4 are correspondingly connected
  • the second port P2 and the fifth port P5 are correspondingly connected
  • the third port P3 and the sixth port P6 are correspondingly connected.
  • the synchronization machine 61 sends the homologous sampling clock signal to the corresponding AWG signal source device 62 through the first port P1 of each communication interface 611.
  • the synchronization machine 61 sends the homologous calibration signal to the corresponding AWG signal source device 62 through the second port P2 of each communication interface 611.
  • the synchronization machine 61 communicates with the corresponding AWG signal source device 62 through the third port P3 of each communication interface 611.
  • the synchronization machine 61 provides a homologous calibration signal and a homologous sampling clock signal to each AWG signal source device 62 through the communication interface 611.
  • each AWG signal source device 62 is connected by a two-way command line, so that the synchronization machine 61 can control and query the synchronization calibration operation of each AWG signal source device 62.
  • the synchronization system 600 may further include a control device 63, and the control device 63 may be, for example, a computer host.
  • the control device 63 communicates with the synchronizer 61 and the multiple AWG signal source devices 62 through the bus 64, respectively, and is used to control the working state of the synchronizer 61 and each of the AWG signal source devices 62 .
  • control device 63 may also communicate with the synchronization machine 61 and multiple signal source devices 62 through other communication methods, such as USB.
  • the synchronization machine 61 is also used to configure any one of the multiple signal source devices 62 as the main signal source device, and to configure the rest of the signal source devices 62.
  • the signal source device 62 is configured as an auxiliary signal source device.
  • the synchronization machine 61 configures the signal source device numbered AWG0 as the main signal source device, and configures the remaining signal source devices AWG1 to AWG7 as auxiliary signal source devices.
  • the main signal source device AWG0 is used to provide a calibration signal for the synchronization machine 61. That is, as shown in FIG. 7, the calibration signal input to the synchronization machine 61 is provided to the synchronization machine 61 by the main signal source device AWG0.
  • the main signal source device AWG0 is also used to provide the sampling clock signal for the synchronization machine 61.
  • the sampling clock signal may also be externally sent to the synchronization machine 61, which is not limited in the embodiment of the present invention. That is, as shown in FIG. 7, the sampling clock signal input to the synchronizer 61 is provided to the synchronizer 61 by the main signal source device AWG0 or sent to the synchronizer 61 by an external device.
  • the synchronization machine 61 also includes a synchronous clock signal output port Sync Clk Out and an external trigger signal input port Trigger In1/Trigger In2.
  • the synchronous clock signal output port Sync Clk Out is used to output a synchronous clock signal for use by the user, and the synchronous clock signal may adopt a frequency-divided clock of the sampling clock signal.
  • the external trigger signal input port Trigger In1/Trigger In2 adopts an SMA interface, and a user can input a trigger signal through the input port to control the working state of the synchronous machine 61.
  • the synchronization system 600 based on the synchronization machine to achieve multi-signal source and multi-channel synchronous output, through a synchronization machine 61 to provide each signal source device 62 with a homologous calibration signal and a homologous sampling clock signal, so that Multiple signal source devices 62 output synchronously, and one sync machine 61 can support the synchronous output of up to 8 signal source devices 62, that is, 64-channel synchronous output, and the experimental results show that the synchronous output delay deviation of all channels is less than 20ps.
  • the interface design of a synchronous machine is expanded, that is, the clock signal output port, calibration signal output port and command interface of the synchronous machine are expanded, so that one synchronous machine can also support the synchronous output of more signal source devices. , And the synchronization output delay deviation index will not decrease.
  • the synchronization system 600 can also start the synchronization machine calibration mode according to the changes in the user configuration parameters, so that the synchronization machine 61 automatically realizes multi-channel synchronous calibration output of multiple signal source devices.
  • sampling clock signal distribution circuit and the calibration signal distribution circuit of the synchronization machine 61 do not require 8 signal lines to be strictly equal in length, which relaxes the design requirements and difficulty of the synchronization calibration hardware circuit, and the synchronization of multiple signal source devices The output deviation can still be less than 20ps.
  • another embodiment of the present invention also provides a calibration method for realizing multi-signal source and multi-channel synchronous output based on a synchronization machine.
  • FIG. 8 is a schematic flowchart of a calibration method for realizing multi-signal source and multi-channel synchronous output based on a synchronization machine according to an embodiment of the present invention. The calibration method is applied to the synchronization system 600 described above.
  • the calibration method includes:
  • any one of the multiple signal source devices 62 is configured as a primary signal source device through the synchronization machine 61, and the remaining signal source devices are configured as auxiliary signal source devices.
  • each of the signal source devices 62 is provided with a homologous sampling clock signal through the synchronizer 61.
  • the step S802 may include:
  • the synchronization machine 61 performs power division on the received sampling clock signal, for example, performs one division and eight fan-out on the sampling clock signal, so as to provide each of the signal source devices 62 with a homogenous sampling clock signal.
  • Step S803 Send a calibration signal to the synchronization machine 61 through the main signal source device.
  • step S804 the calibration signal is divided into power by the synchronizer 61, and a homologous calibration signal is provided to each of the signal source devices 62.
  • Step S805 When each of the signal source devices 62 receives the homologous calibration signal, calculate the link delay value from the main signal source device to its own signal source device through each of the signal source devices 62, And define the link delay value as the time reference of its own signal source device.
  • Step S806 Calculate and adjust the loop delay of each channel of each signal source device 62 so that the loop delay of each channel is consistent with the time reference of the signal source device 62 itself.
  • the step S806 may include:
  • Each of the signal source devices 62 adjusts the loop delay of each channel according to the comparison result, so that the loop delay of each channel is consistent with the time reference of the signal source device 62 itself.
  • FIG. 9 is a schematic flowchart of another calibration method for realizing multi-signal source and multi-channel synchronous output based on a synchronization machine according to an embodiment of the present invention.
  • step S900 the synchronization machine 61 is controlled by the control device 63 to start the synchronization calibration process.
  • any one of the multiple signal source devices 62 is configured as a primary signal source device through the synchronization machine 61, and the remaining signal source devices are configured as auxiliary signal source devices.
  • each of the signal source devices 62 is provided with a homologous sampling clock signal through the synchronization machine 61.
  • steps S901-S902 in this embodiment reference may be made to the related technical details of steps S801-S802 in the embodiment shown in FIG. 8, which will not be repeated here.
  • each signal source device 62 is controlled by the synchronization machine 61 to enter the synchronization calibration mode.
  • Step S904 Send a calibration signal to the synchronization machine 61 through the main signal source device.
  • Step S905 Perform power division of the calibration signal by the synchronizer 61, and provide each of the signal source devices 62 with a homologous calibration signal.
  • Step S906 When each of the signal source devices 62 receives the homologous calibration signal, each signal source device 62 calculates the link delay value from the main signal source device to its own signal source device, and defines The link delay value is the time reference of the own signal source device.
  • step S907 the loop delay of each channel of each signal source device 62 is calculated and adjusted, so that the loop delay of each channel is consistent with the time reference of the signal source device 62 itself.
  • steps S904-S907 in this embodiment reference may be made to the related technical details of steps S803-S806 in the embodiment shown in FIG. 8, which will not be repeated here.
  • the calibration method provided by the present invention for realizing multi-signal source and multi-channel synchronous output based on a synchronization machine has the same principle as the foregoing system embodiment, and will not be repeated here.
  • a synchronization method for realizing multi-signal source and multi-channel synchronous output based on a synchronization machine is also provided.
  • the synchronization method includes:
  • each signal source device 62 is switched to the normal working mode by the synchronization machine 61, so as to realize multi-channel synchronous output of multiple signal source devices.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

本申请提供了一种基于同步机实现多信号源多通道同步输出的同步系统、同步方法及校准方法。该同步系统包括同步机和多台信号源设备。该同步机通过多个通信接口与多台信号源设备对应连接。该同步机对输入的校准信号和采样时钟信号分别进行功分,以给每一台信号源设备提供同源校准信号和同源采样时钟信号,使多台信号源设备能够同步输出信号。该同步系统通过一台同步机可支持多达8台信号源设备的同步输出,即64通道同步输出。若扩展一台同步机的接口设计,一台同步机还可以支持更多台信号源设备的同步输出。并且,在该同步系统搭建完毕之后,不需要反复拆接线,用户可以反复上电配置,该同步系统也能够根据用户配置参数的变化启动同步机校准模式。

Description

基于同步机实现多信号源同步输出的同步系统、同步方法及校准方法
本申请要求于2019年12月2日提交中国专利局、申请号为201911212659.2,发明名称为“基于同步机实现多台信号源同步的系统、方法及校准方法”的中国专利申请的优先权,其全部内容通过引用结合在本申请中。
技术领域
本发明涉及通信技术领域,更具体地说,涉及一种基于同步机实现多信号源同步输出的同步系统、同步方法及校准方法。
背景技术
随着电子信息产业的高速发展,各个行业对测试测量的要求越来越高。在各个具有测试测量应用需求的行业中,例如无线通信中的MIMO通信、雷达阵列控制和量子计算机中量子比特控制等等,怎样实现信号源多达几十个通道的同步输出,是一个非常普遍的需求。
但是,一般高端信号源设备大多只支持2/4/8通道,怎样实现多台信号源的同步输出,是本领域目前的技术难点之一。
发明内容
有鉴于此,为解决上述问题,本发明提供一种基于同步机实现多信号源同步输出的同步系统、同步方法及校准方法,技术方案如下:
一种基于同步机实现多信号源多通道同步输出的同步系统,所述同步系统包括同步机和多台信号源设备。其中,所述同步机具有多个通信接口,每台所述信号源设备对应连接一个所述通信接口。所述同步机用于接收输入的校准信号和采样时钟信号,并对输入的校准信号和采样时钟信号分别进行功分,以给每一台所述信号源设备提供同源校准信号和同源采样时钟信号,使多台所述信号源设备能够同步输出信号。
优选的,在上述同步系统中,所述同步系统还包括控制设备,所述控制设备与所述同步机和多台所述信号源设备分别进行通信连接,所述控制设备用于控制所述同步机和各台所述信号源设备的工作状态。
优选的,在上述同步系统中,所述同步机具有M个通信接口,每个通信接口均用于与一台所述信号源设备通信连接。每台信号源设备均包括N个输出通道。
优选的,在上述同步系统中,所述同步系统包括M台信号源设备,所述M台信号源设备与所述同步机的M个通信接口一一对应连接。
优选的,在上述同步系统中,每一所述通信接口包括第一端口、第二端口和第三端口,每一所述信号源设备包括第四端口、第五端口和第六端口。其中,所述第一端口和所述第四端口对应连接,所述第二端口和所述第五端口对应连接,所述第三端口和所述第六端口对应连接。所述同步机通过各个所述通信接口的第一端口向相应的所述信号源设备发送所述同源采样时钟信号。所述同步机通过各个所述通信接口的第二端口向相应的所述信号源设备发送所述同源校准信号。所述同步机通过各个所述通信接口的第三端口与相应的所述信号源设备进行相互通信。
优选的,在上述同步系统中,所述同步机还用于将多台所述信号源设备中的任意一台信号源设备配置为主信号源设备,以及将其余的信号源设备配置为辅信号源设备。
优选的,在上述同步系统中,所述主信号源设备用于为所述同步机提供所述输入的校准信号。
优选的,在上述同步系统中,所述主信号源设备用于为所述同步机提供所述输入的采样时钟信号,或,所述同步机接收外部提供的采样时钟信号。
一种基于同步机实现多信号源多通道同步输出的校准方法,所述校准方法应用于上述的同步系统中,所述校准方法包括:通过同步机将多台信号源设备中的任意一台信号源设备配置为主信号源设备,以及将其余的信号源设备配置为辅信号源设备;通过所述同步机给各台所述信号源设备提供同源采样时钟信号;通过所述主信号源设备给所述同步机发送校准信号;通过所述同步机将所述校准信号进行功分,并给各台所述信号源设备提供同源校准信号;在每一台所述信号源设备接收到所述同源校准信号时,通过各台所述信号源设备计算所述主信号源设备到自身信号源设备的链路时延值,并定义所述链路时延值为自身信号源设备的时间基准;以及,通过各台所述信号源设备计算并调整自身的每一个通道的环路延时,以使每一个通道的环路延时与所述信号源设备自身的时间基准保持一致。
优选的,在上述校准方法中,在通过所述同步机将多台信号源设备中的任意一台信号源设备配置为主信号源设备,以及将其余的信号源设备配置为辅信号源设备之前,所述校准方法还包括:通过控制设备控制所述同步机启动同步校准流程。
优选的,在上述校准方法中,在通过所述主信号源设备给所述同步机发送校准信号之前,所述校准方法还包括:通过所述同步机控制各台信号源设备进入同步校准模式。
优选的,在上述校准方法中,通过所述同步机给各台所述信号源设备提供同源采样时钟信号,包括:通过所述同步机接收所述主信号源设备或外部提供的采样时钟信号;通过所述同步机对接收到的所述采样时钟信号进行功分,以给各台所述信号源设备提供同源采样时钟信号。
优选的,在上述校准方法中,通过各台所述信号源设备计算并调整自身的每一个通道的环路延时,以使每一个通道的环路延时与所述信号源设备自身的时间基准保持一致,包括:通过所述同步机控制各台所述信号源设备进入内部多通道同步校准模式;通过各台所述信号源设备计算自身的每一个通道的环路延时;通过各台所述信号源设备对每一个通道的环路延时的计算结果进行分析对比;通过各台所述信号源设备依据对比结果调整每一个通道的环路延时,以使每一个通道的环路延时与所述信号源设备自身的时间基准保持一致。
一种基于同步机实现多信号源设备多通道同步输出的同步方法,所述同步方法包括:执行上述任一项所述的校准方法;以及,当在所述校准方法执行完成后,通过所述同步机将各台信号源设备切换至正常工作模式,以实现多信号源设备多通道的同步输出。
相较于现有技术,本发明实现的有益效果为:
该基于同步机实现多信号源多通道同步输出的同步系统,通过一台同步机给每一台信号源设备提供同源校准信号和同源采样时钟信号,以使多台信号源设备能够同步输出信号。一台同步机可支持多台信号源设备的多通道信号的同步输出,若扩展一台同步机的接口设计,一台同步机还可以支持更多台信号源设备的同步输出。
并且,在该同步系统搭建完毕之后,不需要反复拆接线,用户可以反复上电配置,该同步系统也能够根据用户配置参数的变化启动同步机校准模式,使同步机自动实现多信号源多通道同步校准输出。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案,下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍,显而易见地,下面描述中的附图仅仅是本发明的实施例,对于本领域普通技术人员来讲,在不付出创造性劳动的前提下,还可以根据提供的附图获得其他的附图。
图1为Agilent公司的N8241信号源同步系统包括的部分设备之间的连线示意图。
图2为Agilent公司的N8241信号源同步系统的时序图。
图3为泰克公司的AWG7122C信号源同步系统包括的部分设备之间的连线示意图。
图4为泰克公司的AWG70000信号源同步系统中的多台信号源设备后面板与同步机后面板之间的连线示意图。
图5为泰克公司的AWG70000信号源同步系统中的多台信号源设备前面板与同步机前面板之间的连线示意图。
图6为本发明实施例提供的一种基于同步机实现多信号源多通道同步输出的同步系统的部分结构示意图。
图7为本发明实施例提供的一种同步机的内部逻辑结构示意图。
图8为本发明实施例提供的一种基于同步机实现多信号源多通道同步输出的校准方法的流程示意图。
图9为本发明实施例提供的另一种基于同步机实现多信号源多通道同步输出的校准方法的流程示意图。
具体实施方式
下面将结合本发明实施例中的附图,对本发明实施例中的技术方案进行清楚、完整地描述,显然,所描述的实施例仅仅是本发明的一部分实施例,而不是全部的实施例。基于本发明中的实施例,本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例,都属于本发明保护的范围。
目前市场上有一些能够实现多信号源多通道同步输出的方案,但技术手段各不相同,所达到的性能指标也存在很大的差异,比如支持同步通道数一般不超过32通道、同步通道时延偏差指标也不一样等。
申请人在发明创造过程中是基于目前现有技术中存在的几种比较典型的信号源同步方案来提出本发明的技术方案,下面先对目前现有技术中存在的几种比较典型的信号源同步方案进行简单阐述。
一、Agilent公司的N8241信号源同步方案
请参考图1-图2,其中,图1为Agilent公司的N8241信号源同步系统包括的部分设备的连线示意图,图2为Agilent公司的N8241信号源同步系统的时序图。图1中以同步系统100包括两台信号源设备:一台主信号源设备和一台辅信号源设备为例,对该同步系统进行介绍。可以理解 的是,该同步系统100可包括多台辅信号源设备。其中,在图1中,标号1表示:功分器;标号2表示:SMB适配三通头;标号3表示:10英寸SMA电缆组件;标号4表示:SMB电缆组件;标号5表示:转接器/适配器。
该同步系统100通过共享采样时钟信号(Sample Clock),并用同步时钟信号(Sync Clock)和触发信号(Trigger),建立多台信号源设备间的同步输出时序。该同步系统100通过时钟信号和触发信号等延时设计方式来实现多台信号源设备之间的同步输出,设计比较简单,但是对硬件连线和线路延时要求均很严格,包括时钟线和触发同步线要等长设计。需要说明的是,在图1所示的同步系统100中,与主信号源设备和辅信号源设备的CH1OUT端口连接的电缆线必须是等长,进而也体现出该同步系统100对连线的严格性。另外,每台设备都需要精确采集到时钟信号和触发信号的相位,该同步系统100所能实现的同步精度一般有很大的局限,随着需要同步的设备数量的增多,该同步系统100所能实现的同步精度也会越来越差。
二、泰克泰克公司的AWG7122C信号源同步方案
请参考图3,图3为泰克公司的AWG7122C信号源同步系统包括的部分设备之间的连线示意图。
该同步系统200采用示波器测量2台信号源设备AWG7122C的输出时延偏差,然后手动调整信号源输出时延,从而实现多台信号源设备的多通道同步输出。
但是,该同步系统200需要借助高端的示波器设备,且用户手动操作耗时。另外,如果信号源输出通道过多时,也不方便校准,并且示波器的测量精度也不一定能满足精度要求。
三、泰克公司的AWG70000信号源同步方案
请参考图4-图5,图4为泰克公司的AWG70000信号源同步系统中的多台信号源设备后面板与同步机后面板之间的一种连线示意图,图5为泰克公司的AWG70000信号源同步系统中的多台信号源设备前面板与同步机前面板之间的一种连线示意图。
该同步系统300采用了同步机301,实现多达4台AWG信号源设备302同步输出,其主要是通过将每一台信号源设备302的CH1通道的输出连接到同步机301,通过同步机301上的相位时延检测电路,来计算4台信号源设备302之间的输出时延偏差,然后控制每一台信号源设备302调整相位输出。
实际上,该同步系统300的设计原理与用示波器检测多个信号源设备之间的输出时延偏差 的设计原理类似,不同的是,该同步系统300可在同步机301上精确检测每一台信号源设备302的输出相位,然后通过命令接口控制每台信号源设备302调整输出时延,即,该同步系统300可以自动控制各台信号源设备302调整各自的输出相位,不需要用户去手动调整每台信号源设备302的输出相位,从而可给用户带来较好的使用体验。
但是,在需要使用信号源设备302的CH1通道的输出时,需要先将连接在同步机301上的输出线拧下,然后将输出线连接到测试设备上。并且,如果用户更改配置参数或者重启设备,均需要重新连线和校准,其操作比较复杂,从而影响用户使用体验效果。
针对现有技术中存在的上述各种问题,本发明实施例提供了一种基于同步机实现多信号源多通道同步输出的同步系统及方法,通过使用一台同步机来实现多台信号源设备之间的精确同步输出。该同步系统可支持M台信号源设备、N个输出通道信号的同步输出,所有通道同步输出时延偏差小于20ps。其中,M为不小于2的整数,N为大于或等于M的整数。并且,该同步系统可通过扩展同步机的时钟信号输出端口、校准信号输出端口和命令接口,使同步机能够支持更多台信号源设备的同步输出,而且同步输出时延偏差指标不会下降。
为使本发明的上述目的、特征和优点能够更加明显易懂,下面结合附图和具体实施方式对本发明作进一步详细的说明。
请参考图6-图7,图6为本发明实施例提供的一种基于同步机实现多信号源多通道同步输出的同步系统的部分结构示意图,图7为本发明实施例提供的一种同步机的内部逻辑结构示意图。
所述同步系统600包括同步机61和多台信号源设备62。其中,所述同步机61具有多个通信接口611,每台所述信号源设备62对应连接一个所述通信接口611。
所述同步机61用于接收输入的校准信号和采样时钟信号,并对输入的校准信号和采样时钟信号分别进行功分,例如对输入的校准信号和采样时钟信号分别进行1分8扇出,以给每一台所述信号源设备62提供同源校准信号和同源采样时钟信号,从而使多台所述信号源设备62能够同步输出信号。
在该实施例中,所述多台信号源设备62的信号源采用AWG信号源,所述同步机61具有M个通信接口611,其中,M为不小于2的整数。本实施例中以8个通信接口611为例,即M=8,8个所述通信接口611依次编号为Port0、Port1、…、Port7,每个通信接口611均用于与一台AWG信号源设备62通信连接,即1台同步机61可通过8个通信接口611同时连接8台AWG信号源设备62。所述8台AWG信号源设备62依次编号为AWG0、AWG1、…、AWG7,并与所述同步机61 的8个通信接口Port0、Port1、…、Port7一一对应连接。
需要说明的是,所述同步机61具有的多个通信接口611并非都需要接一台AWG信号源设备62,具体需要接入多少台AWG信号源设备62,需视情况而定。
在本发明实施例中,仅仅以8个通信接口611一一对应连接8台AWG信号源设备62为例进行说明。
在该实施例中,各台AWG信号源设备可包括一个或多个输出通道。本实施例中以每台AWG信号源设备62均包括8个输出通道为例,8个输出通道依次编号为CH0、…、CH7。
其中,如图6所示,所述同步机61与每一台AWG信号源设备62之间至少传输3种与同步校准信号有关的信号:同源采样时钟信号、同源校准信号、指令信号。
具体的,每一所述通信接口611包括第一端口P1、第二端口P2和第三端口P3。相应地,每一所述AWG信号源设备62包括第四端口P4、第五端口P5和第六端口P6。其中,所述第一端口P1和所述第四端口P4对应连接,所述第二端口P2和所述第五端口P5对应连接,所述第三端口P3和所述第六端口P6对应连接。
所述同步机61通过各个所述通信接口611的第一端口P1向相应的所述AWG信号源设备62发送所述同源采样时钟信号。
所述同步机61通过各个所述通信接口611的第二端口P2向相应的所述AWG信号源设备62发送所述同源校准信号。
所述同步机61通过各个所述通信接口611的第三端口P3与相应的所述AWG信号源设备62进行相互通信。
也就是说,所述同步机61通过所述通信接口611给每台AWG信号源设备62提供同源校准信号和同源采样时钟信号。
并且,所述同步机61和每台AWG信号源设备62之间都通过双向指令线连接,从而可使所述同步机61能够控制和查询各台AWG信号源设备62的同步校准操作。
进一步的,基于本发明上述实施例,如图6所示,所述同步系统600还可以包括控制设备63,所述控制设备63例如可以是电脑主机。所述控制设备63通过总线64与所述同步机61和多台所述AWG信号源设备62分别进行通信连接,用于控制所述同步机61和各台所述AWG信号源设备62的工作状态。
需要说明的是,所述控制设备63还可以通过其它通信方式,例如USB等,与所述同步机61和多台所述信号源设备62进行通信连接。
进一步的,基于本发明上述实施例,所述同步机61还用于将多台所述信号源设备62中的任意一台所述信号源设备62配置为主信号源设备,以及将其余的所述信号源设备62配置为辅信号源设备。如图6所示,所述同步机61将编号为AWG0的信号源设备配置为主信号源设备,以及将其余的信号源设备AWG1~AWG7配置为辅信号源设备。
其中,所述主信号源设备AWG0用于为所述同步机61提供校准信号。即,如图7所示,输入到所述同步机61的校准信号由所述主信号源设备AWG0提供给所述同步机61。
进一步的,基于本发明上述实施例,如图6所示,所述主信号源设备AWG0还用于为所述同步机61提供所述采样时钟信号。
但是,需要说明的是,在其他实施例中,所述采样时钟信号也可以由外部发送给所述同步机61,在本发明实施例中并不作限定。即,如图7所示,输入到所述同步机61的采样时钟信号由所述主信号源设备AWG0提供给所述同步机61或由外部设备发送给所述同步机61。
如图7所示,所述同步机61还包括同步时钟信号输出端口Sync Clk Out和外部触发信号输入端口Trigger In1/Trigger In2。
其中,同步时钟信号输出端口Sync Clk Out用于输出同步时钟信号,以提供给用户使用,所述同步时钟信号可采用采样时钟信号的分频时钟。
所述外部触发信号输入端口Trigger In1/Trigger In2采用SMA接口,用户可通过该输入端口输入触发信号,进而控制所述同步机61的工作状态。
通过上述描述可知,该基于同步机实现多信号源多通道同步输出的同步系统600,通过一台同步机61给每一台信号源设备62提供同源校准信号和同源采样时钟信号,以使多台信号源设备62同步输出,一台同步机61可支持多达8台信号源设备62的同步输出,即64通道同步输出,并且实验结果表明,所有通道同步输出时延偏差小于20ps。
进一步地,若扩展一台同步机的接口设计,即,扩展同步机的时钟信号输出端口、校准信号输出端口和命令接口等,使一台同步机还可以支持更多台信号源设备的同步输出,而且同步输出时延偏差指标不会下降。
进一步地,在所述同步系统600搭建完毕之后,不需要反复拆接线,用户可以反复上电配置,所述同步系统600也能够根据用户配置参数的变化启动同步机校准模式,使所述同步机61自动实现多台信号源设备多通道同步校准输出。
进一步地,所述同步机61的采样时钟信号分发电路和校准信号分发电路,不要求8路信号线严格等长,放宽了同步校准硬件电路的设计要求和难度,而多台信号源设备的同步输出偏差 仍然可以小于20ps。
基于本发明上述全部实施例,本发明另一实施例还提供了一种基于同步机实现多信号源多通道同步输出的校准方法。请参考图8,图8为本发明实施例提供的一种基于同步机实现多信号源多通道同步输出的校准方法的流程示意图。所述校准方法应用于上述的同步系统600中。
所述校准方法包括:
步骤S801,通过同步机61将多台信号源设备62中的任意一台信号源设备配置为主信号源设备,以及将其余的信号源设备配置为辅信号源设备。
步骤S802,通过所述同步机61给各台所述信号源设备62提供同源采样时钟信号。
具体地,在一种实施例中,所述步骤S802可包括:
通过所述同步机61接收所述主信号源设备或外部提供的采样时钟信号;
通过所述同步机61对接收到采样时钟信号进行功分,例如对所述采样时钟信号进行1分8扇出,以给每台所述信号源设备62提供同源采样时钟信号。
步骤S803,通过所述主信号源设备给所述同步机61发送校准信号。
步骤S804,通过所述同步机61将所述校准信号进行功分,并给各台所述信号源设备62提供同源校准信号。
步骤S805,在每台所述信号源设备62接收到所述同源校准信号时,通过各台所述信号源设备62计算所述主信号源设备到自身信号源设备的链路时延值,并定义所述链路时延值为自身信号源设备的时间基准。
步骤S806,通过各台所述信号源设备62计算并调整自身的每一个通道的环路延时,以使每一个通道的环路延时与所述信号源设备62自身的时间基准保持一致。
具体地,在一种实施例中,所述步骤S806可包括:
通过所述同步机61控制各台信号源设备62进入内部多通道同步校准模式;
通过各台所述信号源设备62计算自身的每一个通道的环路延时;
通过各台所述信号源设备62对每一个通道的环路延时的计算结果进行分析对比;
通过各台所述信号源设备62依据对比结果调整每一个通道的环路延时,以使每一个通道的环路延时与所述信号源设备62自身的时间基准保持一致。
进一步的,基于本发明上述实施例,请参考图9,图9为本发明实施例提供的另一种基于同步机实现多信号源多通道同步输出的校准方法的流程示意图。
步骤S900,通过控制设备63控制所述同步机61启动同步校准流程。
步骤S901,通过同步机61将多台信号源设备62中的任意一台信号源设备配置为主信号源设备,以及将其余的信号源设备配置为辅信号源设备。
步骤S902,通过所述同步机61给各台所述信号源设备62提供同源采样时钟信号。
其中,本实施例的步骤S901-S902的具体技术细节可参考如图8所示的实施例的步骤S801-S802的相关技术细节,在此不再赘述。
步骤S903,通过所述同步机61控制各台信号源设备62进入同步校准模式。
步骤S904,通过所述主信号源设备给所述同步机61发送校准信号。
步骤S905,通过所述同步机61将所述校准信号进行功分,并给各台所述信号源设备62提供同源校准信号。
步骤S906,在每台所述信号源设备62接收到所述同源校准信号时,通过各台信号源设备62计算所述主信号源设备到自身信号源设备的链路时延值,并定义所述链路时延值为自身信号源设备的时间基准。
步骤S907,通过各台所述信号源设备62计算并调整自身的每一个通道的环路延时,以使每一个通道的环路延时与所述信号源设备62自身的时间基准保持一致。
其中,本实施例的步骤S904-S907的具体技术细节可参考如图8所示的实施例的步骤S803-S806的相关技术细节,在此不再赘述。
需要说明的是,本发明提供的一种基于同步机实现多信号源多通道同步输出的校准方法与上述系统实施例的原理相同,在此不再赘述。
基于本发明上述全部实施例,在本发明另一实施例中还提供了一种基于同步机实现多信号源多通道同步输出的同步方法。
所述同步方法包括:
执行上述实施例提供的所述的校准方法;以及,
当在所述校准方法执行完成后,通过所述同步机61将各台信号源设备62切换至正常工作模式,以实现多台信号源设备多通道的同步输出。
以上对本发明所提供的一种基于同步机实现多台信号源设备同步输出的同步系统、同步方法及校准方法进行了详细介绍,本文中应用了具体个例对本发明的原理及实施方式进行了阐述,以上实施例的说明只是用于帮助理解本发明的核心思想。同时,对于本领域的一般技术人员,依据本发明的思想,在具体实施方式及应用范围上均会有改变之处,综上所述,本说明书内容不应理解为对本发明的限制。
需要说明的是,本说明书中的各个实施例均采用递进的方式描述,每个实施例重点说明的都是与其他实施例的不同之处,各个实施例之间相同相似的部分互相参见即可。对于实施例公开的装置而言,由于其与实施例公开的方法相对应,所以描述的比较简单,相关之处参见方法部分说明即可。
还需要说明的是,在本文中,诸如第一和第二等之类的关系术语仅仅用来将一个实体或者操作与另一个实体或操作区分开来,而不一定要求或者暗示这些实体或操作之间存在任何这种实际的关系或者顺序。而且,术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含,从而使得包括一系列要素的过程、方法、物品或者设备所固有的要素,或者是还包括为这些过程、方法、物品或者设备所固有的要素。在没有更多限制的情况下,由语句“包括一个……”限定的要素,并不排除在包括所述要素的过程、方法、物品或者设备中还存在另外的相同要素。
对所公开的实施例的上述说明,使本领域专业技术人员能够实现或使用本发明。对这些实施例的多种修改对本领域的专业技术人员来说将是显而易见的,本文中所定义的一般原理可以在不脱离本发明的精神或范围的情况下,在其它实施例中实现。因此,本发明将不会被限制于本文所示的这些实施例,而是要符合与本文所公开的原理和新颖特点相一致的最宽的范围。

Claims (14)

  1. 一种基于同步机实现多信号源多通道同步输出的同步系统,其特征在于,所述同步系统包括同步机和多台信号源设备;
    其中,所述同步机具有多个通信接口,每台所述信号源设备对应连接一个所述通信接口;
    所述同步机用于接收输入的校准信号和采样时钟信号,并对输入的校准信号和采样时钟信号分别进行功分,以给每一台所述信号源设备提供同源校准信号和同源采样时钟信号,使多台所述信号源设备能够同步输出信号。
  2. 根据权利要求1所述的同步系统,其特征在于,所述同步系统还包括控制设备,所述控制设备与所述同步机和多台所述信号源设备分别进行通信连接,所述控制设备用于控制所述同步机和各台所述信号源设备的工作状态。
  3. 根据权利要求2所述的同步系统,其特征在于,所述同步机具有M个通信接口,每个通信接口均用于与一台所述信号源设备通信连接,其中,M为大于或等于2的整数;各台信号源设备包括一个或多个输出通道。
  4. 根据权利要求3所述的同步系统,其特征在于,所述同步系统包括M台信号源设备,所述M台信号源设备与所述同步机的M个通信接口一一对应连接。
  5. 根据权利要求1至4任意一项所述的同步系统,其特征在于,每一所述通信接口包括第一端口、第二端口和第三端口;
    每一所述信号源设备包括第四端口、第五端口和第六端口;
    其中,所述第一端口和所述第四端口对应连接,所述第二端口和所述第五端口对应连接,所述第三端口和所述第六端口对应连接;
    所述同步机通过各个所述通信接口的第一端口向相应的所述信号源设备发送所述同源采样时钟信号;
    所述同步机通过各个所述通信接口的第二端口向相应的所述信号源设备发送所述同源校准信号;
    所述同步机通过各个所述通信接口的第三端口与相应的所述信号源设备进行相互通信。
  6. 根据权利要求1至4任意一项所述的同步系统,其特征在于,所述同步机还用于将多台所述信号源设备中的任意一台信号源设备配置为主信号源设备,以及将其余的信号源设备配置为辅信号源设备。
  7. 根据权利要求6所述的同步系统,其特征在于,所述主信号源设备用于为所述同步机提供所述输入的校准信号。
  8. 根据权利要求6所述的同步系统,其特征在于,所述主信号源设备用于为所述同步机提供所述输入的采样时钟信号;
    或,所述同步机接收外部提供的采样时钟信号。
  9. 一种基于同步机实现多信号源多通道同步输出的校准方法,所述校准方法应用于权利要求1至8任意一项所述的同步系统中,其特征在于,所述校准方法包括:
    通过同步机将多台信号源设备中的任意一台信号源设备配置为主信号源设备,以及将其余的信号源设备配置为辅信号源设备;
    通过所述同步机给各台所述信号源设备提供同源采样时钟信号;
    通过所述主信号源设备给所述同步机发送校准信号;
    通过所述同步机将所述校准信号进行功分,并给各台所述信号源设备提供同源校准信号;
    在每一台所述信号源设备接收到所述同源校准信号时,通过各台所述信号源设备计算所述主信号源设备到自身信号源设备的链路时延值,并定义所述链路时延值为自身信号源设备的时间基准;以及
    通过各台所述信号源设备计算并调整自身的每一个通道的环路延时,以使每一个通道的环路延时与所述信号源设备自身的时间基准保持一致。
  10. 根据权利要求9所述的校准方法,其特征在于,在通过所述同步机将多台信号源设备中的任意一台信号源设备配置为主信号源设备,以及将其余的信号源设备配置为辅信号源设备之前,所述校准方法还包括:
    通过控制设备控制所述同步机启动同步校准流程。
  11. 根据权利要求10所述的校准方法,其特征在于,在通过所述主信号源设备给所述同步机发送校准信号之前,所述校准方法还包括:
    通过所述同步机控制各台信号源设备进入同步校准模式。
  12. 根据权利要求9所述的校准方法,其特征在于,通过所述同步机给各台所述信号源设备提供同源采样时钟信号,包括:
    通过所述同步机接收所述主信号源设备或外部提供的采样时钟信号;
    通过所述同步机对接收到的所述采样时钟信号进行功分,以给各台所述信号源设备提供同源采样时钟信号。
  13. 根据权利要求9所述的校准方法,其特征在于,通过各台所述信号源设备计算并调整自身的每一个通道的环路延时,以使每一个通道的环路延时与所述信号源设备自身的时间基准保持一致,包括:
    通过所述同步机控制各台所述信号源设备进入内部多通道同步校准模式;
    通过各台所述信号源设备计算自身的每一个通道的环路延时;
    通过各台所述信号源设备对每一个通道的环路延时的计算结果进行分析对比;
    通过各台所述信号源设备依据对比结果调整每一个通道的环路延时,以使每一个通道的环路延时与所述信号源设备自身的时间基准保持一致。
  14. 一种基于同步机实现多信号源设备多通道同步输出的同步方法,其特征在于,所述同步方法包括:
    执行如权利要求9-13任意一项所述的校准方法;以及
    当在所述校准方法执行完成后,通过所述同步机将各台信号源设备切换至正常工作模式,以实现多信号源设备多通道的同步输出。
PCT/CN2020/094393 2019-12-02 2020-06-04 基于同步机实现多信号源同步输出的同步系统、同步方法及校准方法 WO2021109508A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201911212659.2A CN112994817B (zh) 2019-12-02 2019-12-02 基于同步机实现多台信号源同步的系统、方法及校准方法
CN201911212659.2 2019-12-02

Publications (1)

Publication Number Publication Date
WO2021109508A1 true WO2021109508A1 (zh) 2021-06-10

Family

ID=76221237

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2020/094393 WO2021109508A1 (zh) 2019-12-02 2020-06-04 基于同步机实现多信号源同步输出的同步系统、同步方法及校准方法

Country Status (2)

Country Link
CN (1) CN112994817B (zh)
WO (1) WO2021109508A1 (zh)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113630119B (zh) * 2021-07-14 2024-04-05 普源精电科技股份有限公司 时间交织adc的失调失配校准方法及校准器
CN113595551B (zh) * 2021-07-14 2024-04-05 普源精电科技股份有限公司 时间交织adc的增益失配校准方法及校准器
CN117278188B (zh) * 2023-11-21 2024-02-23 深圳市鼎阳科技股份有限公司 一种信号源同步系统及其同步方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100008460A1 (en) * 2008-07-11 2010-01-14 Integrated Device Technology, Inc. Synchronous de-skew with programmable latency for multi-lane high speed serial interface
US20130076409A1 (en) * 2011-09-27 2013-03-28 Lecroy Corporation Multiple Channel Distributed System and Method
CN103364602A (zh) * 2012-03-29 2013-10-23 北京普源精电科技有限公司 一种可产生多路同步时钟的示波器
CN107863967A (zh) * 2017-11-15 2018-03-30 中国电子科技集团公司第四十研究所 一种多通道同步输出校准装置及方法
CN109547020A (zh) * 2018-11-12 2019-03-29 中电科仪器仪表有限公司 一种具有时钟同步跟踪功能的多路输出信号放大电路

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1235341C (zh) * 2003-02-21 2006-01-04 明基电通股份有限公司 可同步各半导体组件时钟信号源的方法及系统
CN104618042B (zh) * 2015-03-10 2017-03-29 上海创远仪器技术股份有限公司 实现多通道信号分析同步与时延校正的系统及方法
CN104796213B (zh) * 2015-03-19 2017-04-26 南京科远自动化集团股份有限公司 一种多重冗余控制器的时钟同步控制系统及方法
CN108370612B (zh) * 2015-12-09 2020-11-06 华为技术有限公司 一种基带单元之间时钟同步的方法、装置及系统
CN107104670A (zh) * 2017-03-20 2017-08-29 成都智明达电子股份有限公司 基于单脉冲触发pll时基的多板卡同步采集方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100008460A1 (en) * 2008-07-11 2010-01-14 Integrated Device Technology, Inc. Synchronous de-skew with programmable latency for multi-lane high speed serial interface
US20130076409A1 (en) * 2011-09-27 2013-03-28 Lecroy Corporation Multiple Channel Distributed System and Method
CN103364602A (zh) * 2012-03-29 2013-10-23 北京普源精电科技有限公司 一种可产生多路同步时钟的示波器
CN107863967A (zh) * 2017-11-15 2018-03-30 中国电子科技集团公司第四十研究所 一种多通道同步输出校准装置及方法
CN109547020A (zh) * 2018-11-12 2019-03-29 中电科仪器仪表有限公司 一种具有时钟同步跟踪功能的多路输出信号放大电路

Also Published As

Publication number Publication date
CN112994817B (zh) 2022-07-26
CN112994817A (zh) 2021-06-18

Similar Documents

Publication Publication Date Title
WO2021109508A1 (zh) 基于同步机实现多信号源同步输出的同步系统、同步方法及校准方法
CN112260689A (zh) 自适应延时补偿串行adc采样系统采样校准方法
CN109495698A (zh) 视频传输切换装置
TW201727506A (zh) 用以切換多個電腦裝置介面之系統及其方法及用以切換 多個快速周邊組件互連(PCIe)匯流排之系統
CN103809659A (zh) 用于高速接口的时钟校准的设备和方法
CN109104260B (zh) 板卡式多通道数据采集系统的同步方法
CN104378114A (zh) 一种实现多通道模数转换器同步的方法
WO2021143083A1 (zh) 高速接口的固定延时电路
JP4474532B2 (ja) 信号発生システム
KR20210002515A (ko) 수신 회로, 수신 회로의 재구성 방법 및 전자 기기
CN109032498A (zh) 一种多fpga的多通道采集系统的波形量化同步方法
US8994424B2 (en) Distributing multiplexing logic to remove multiplexor latency on the output path for variable clock cycle, delayed signals
CN105227257A (zh) 一种改进型时钟同步镜像延迟电路
KR102006068B1 (ko) 인터페이스 변환장치
CN103645658B (zh) 一种多片信号转换器的相位同步方法、装置及fpga控制器
US20120271980A1 (en) Test device and method for testing serial ports of computing device
US20170046297A1 (en) Thunderbolt Sharing Console and Switching Method Thereof
CN115936130A (zh) 基于fpga的多片dac脉冲输出同步与相位调节方法及系统
CN114720933A (zh) 时延校准装置、示波器、时延校准系统及时延校准方法
CN112994871A (zh) 一种同步机级联多通道同步输出装置及方法
CN110471881B (zh) 一种实现多个从设备与spi主设备快速通讯方法
CN112671461A (zh) 一种空间光调制器集群控制方法及系统
TWI742918B (zh) 多通道群之時序校準裝置及方法
TWI733117B (zh) 支援多聲道輸入功能的音訊處理電路
CN111061336A (zh) 一种多通道输出可调延时的时钟发生器

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 20894979

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 20894979

Country of ref document: EP

Kind code of ref document: A1