WO2021109243A1 - 存储结构及其擦除方法 - Google Patents

存储结构及其擦除方法 Download PDF

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Publication number
WO2021109243A1
WO2021109243A1 PCT/CN2019/125963 CN2019125963W WO2021109243A1 WO 2021109243 A1 WO2021109243 A1 WO 2021109243A1 CN 2019125963 W CN2019125963 W CN 2019125963W WO 2021109243 A1 WO2021109243 A1 WO 2021109243A1
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storage
bank
memory
erasing
block
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PCT/CN2019/125963
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English (en)
French (fr)
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郑钟倍
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武汉新芯集成电路制造有限公司
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Priority to US17/049,972 priority Critical patent/US11366603B2/en
Publication of WO2021109243A1 publication Critical patent/WO2021109243A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
    • G11C16/16—Circuits for erasing electrically, e.g. erase voltage switching circuits for erasing blocks, e.g. arrays, words, groups
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0646—Horizontal data movement in storage systems, i.e. moving data in between storage devices or systems
    • G06F3/0652—Erasing, e.g. deleting, data cleaning, moving of data to a wastebasket
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/0614—Improving the reliability of storage systems
    • G06F3/0619—Improving the reliability of storage systems in relation to data integrity, e.g. data losses, bit errors
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0638—Organizing or formatting or addressing of data
    • G06F3/064—Management of blocks
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0658—Controller construction arrangements
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0659—Command handling arrangements, e.g. command buffers, queues, command scheduling
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0673—Single storage device
    • G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/3468—Prevention of overerasure or overprogramming, e.g. by verifying whilst erasing or writing
    • G11C16/3477—Circuits or methods to prevent overerasing of nonvolatile memory cells, e.g. by detecting onset or cessation of current flow in cells and using the detector output to terminate erasing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1042—Read-write modes for single port memories, i.e. having either a random port or a serial port using interleaving techniques, i.e. read-write of one part of the memory while preparing another part
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
    • G11C2211/564—Miscellaneous aspects
    • G11C2211/5648—Multilevel memory programming, reading or erasing operations wherein the order or sequence of the operations is relevant
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2216/00—Indexing scheme relating to G11C16/00 and subgroups, for features not directly covered by these groups
    • G11C2216/12—Reading and writing aspects of erasable programmable read-only memories
    • G11C2216/18—Flash erasure of all the cells in an array, sector or block simultaneously

Definitions

  • the present invention relates to the technical field of semiconductor devices, in particular to a storage structure and an erasing method thereof.
  • flash memory The main features of flash memory are fast working speed, small unit area, high integration, good reliability, re-erasable over 100,000 times, and reliable data retention for more than 10 years, which can replace other memories and be embedded in circuits in large quantities.
  • NOR flash Non-volatile flash memory of NOR structure and NAND structure.
  • NOR flash Non-volatile flash memory of NOR structure and NAND structure.
  • Nor Flash has a small unit area and short read (write) operation time, so it is widely used.
  • Nor Flash is based on floating gate flash technology. In order to save area, its storage area is generally placed in a matrix form, and then logically divided into many storage blocks (Block). When erasing, the storage block is used as the storage area.
  • the erasing operation includes the preprogramming step (Preprogram), the erasing step (Erase) and the over erasing repair step (Over Erase Correction, OEC).
  • the preprogramming step is to change the binary value "1" in the memory block to all "0";
  • the erasing step is to apply a larger erase pulse to the memory block, so that the threshold voltage of the memory block is lower than a specific level;
  • the over-erase repair step is to repair the over-erased memory through the repair operation The block is repaired to avoid its threshold voltage is too low.
  • the non-volatile flash memory Since the erasing operation requires these three steps, and the non-volatile flash memory also integrates a large number of storage blocks, the overall erasing operation of the non-volatile flash memory is very time-consuming compared with the read operation and the write operation. How to improve the overall erasing efficiency of non-volatile flash memory is a technical problem that needs to be solved urgently.
  • the purpose of the present invention is to provide a storage structure and an erasing method thereof, so as to solve the problem of low efficiency of overall erasing of non-volatile flash memory.
  • the present invention provides a storage structure that can perform an erase operation on the storage blocks B 1 , B 2 ,..., B n , where n is an integer greater than or equal to 3, including: the first bank, the first bank, and the first bank. Two memory banks, a third memory bank, and a controller.
  • the memory blocks are alternately arranged in the first memory bank, the second memory bank, and the third memory bank according to their numbers.
  • the controller is used to control the memory
  • the block performs an erasing operation in sequence according to the number in a set erasing manner, and the erasing operation includes sequentially performing a first process, a second process, and a third process;
  • the erasing method includes: when the storage block B i is performing the third process, the storage block B i+1 is performing the second process, and the storage block B i+2 is performing the first process, where i ⁇ [1, n -2].
  • the remaining memory blocks are sequentially performed after the erasing mode; memory blocks B i After the third process is completed, the storage block B i+1 completes the second process, and the storage block B i+2 completes the first process, the storage block B i+1 executes the third process; until the storage block B n-1 completes the first process After the second process, the storage block B n-1 executes the third process, while the storage block B n executes the second process; after the storage block B n completes the second process, the third process is executed separately.
  • the first process includes a pre-programming step
  • the second process includes an erasing step
  • the third process includes an over-erase repair step.
  • the number of storage blocks in the first storage bank, the second storage bank, and the third storage bank are all the same.
  • the number of storage blocks in the first storage bank is the same as that in the second storage bank
  • the number of storage blocks in the third storage bank is the same as the number of storage blocks in the first storage bank and the second storage bank.
  • the number of storage blocks in the first storage bank is different; or the number of storage blocks in the second storage bank is the same as the number of storage blocks in the third storage bank, and the number of storage blocks in the first storage bank is the same as the number of storage blocks in the second storage bank.
  • the number of memory blocks in the third memory bank and the third memory bank are different.
  • the storage structure includes M storage banks, where M ⁇ 3.
  • the controller includes:
  • a first memory bank controller connected to and controlling the first memory bank
  • a second memory bank controller connected to and controlling the second memory bank
  • a third memory bank controller connected to and controlling the third memory bank
  • the chip controller is connected to the first memory bank controller, the second memory bank controller, and the third memory bank controller, and can operate the first memory bank controller, the second memory bank controller, and the third memory bank controller synchronously.
  • the memory block in the memory bank controller is connected to the first memory bank controller, the second memory bank controller, and the third memory bank controller, and can operate the first memory bank controller, the second memory bank controller, and the third memory bank controller synchronously.
  • the storage structure is Nor flash memory.
  • the present invention also provides an erasing method of a storage structure, which is used to perform an erasing operation on the storage blocks B 1 , B 2 ,..., B n , where n is an integer greater than or equal to 3, including:
  • the storage blocks are alternately arranged in the first storage bank, the second storage bank, and the third storage bank according to the serial number;
  • the erasing operation includes sequentially performing the first process, the second process, and the third process
  • the erasing method includes: when the memory block B i executes the third process, the memory block B i+1 executes the first process. In the second process, the storage block B i+2 is executing the first process, where i ⁇ [1, n-2].
  • the method for erasing the storage structure is to erase the storage structure as a whole.
  • the erasing operation can be performed on the memory blocks B 1 , B 2 ,..., B n , where n is an integer greater than or equal to 3, including: the first memory bank , A second memory bank, a third memory bank, and a controller, the memory blocks are alternately arranged in the first memory bank, the second memory bank, and the third memory bank according to the serial number, and the controller is used to control all
  • the memory block is sequentially erased according to the number in the set erasing mode, and the erasing operation includes sequentially performing the first process, the second process, and the third process; the erasing mode includes: memory block B When i is performing the third process, the storage block B i+1 is performing the second process, and the storage block B i+2 is performing the first process, where i ⁇ [1, n-2].
  • three adjacent memory blocks perform the first process, the second process and the third process synchronously, thereby saving the erasing time of the overall erasing of the memory structure, improving the erasing efficiency, and does not require additional circuits , Can be implemented without increasing costs.
  • Figure 1 is a schematic structural diagram of a storage structure
  • FIG. 2 is a specific flowchart of the erasing method of the storage structure in FIG. 1;
  • FIG. 3 is a schematic structural diagram of a storage structure provided by an embodiment of the present invention.
  • 100-storage structure 110-chip controller; Bank0-first bank; Bank1-second bank;
  • 200-storage structure 210-chip controller; 220-first bank controller; 230-second bank controller; 240-third bank controller; Bank2-first bank; Bank3-second storage Bank; Bank4-The third bank.
  • FIG. 1 is a schematic structural diagram of a storage structure 100.
  • the memory structure 100 includes two memory banks, namely a first memory bank Bank0 and a second memory bank Bank1. Both the first memory bank Bank0 and the second memory bank Bank1 are coupled to the chip.
  • the controller 110 is configured to control the first bank Bank0 and the second bank Bank1 to perform operations such as reading, writing, and erasing.
  • a total of n (n ⁇ 2) memory blocks are stored in the first bank Bank0 and the second bank Bank1, and n memory blocks are stored between the first bank Bank0 and the second bank Bank1.
  • the memory blocks in the first bank Bank0 and the second bank Bank1 are arranged in sequence.
  • the n memory blocks are numbered in sequence: B 1 , B 2 ,..., B n , where, Set in the first bank Bank0, Set in the second bank Bank1.
  • FIG. 2 is a flowchart of the overall erasing of the storage structure 100.
  • the erase operation is performed sequentially in the order of B 1 , B 2 ,..., B n.
  • B 1 the Erase
  • OEC over-erase repair step
  • FIG. 3 is a schematic structural diagram of the storage structure provided by this embodiment.
  • the storage structure 200 is, for example, Nor Flash, which includes at least three banks, namely a first bank Bank2, a second bank Bank3, and a third bank Bank4.
  • a total of n (n ⁇ 3) memory blocks are stored in the first bank Bank2, the second bank Bank3, and the third bank Bank4, and n memory blocks are stored in the first bank Bank2 and the second bank.
  • the banks Bank3 and the third bank Bank4 are evenly distributed, and the bank blocks are alternately arranged in the first bank Bank2, the second bank Bank3, and the third bank Bank4 according to their numbers.
  • n memory blocks are sequentially numbered as: B 1 , B 2 ,..., B n .
  • n is a multiple of 3.
  • the memory blocks B 1 , B 4 , B 7 ,..., B n-2 are set in the first bank Bank2
  • the memory blocks B 2 , B 5 , B 8 ,..., B n-1 are set In the second bank Bank3, bank blocks B 3 , B 6 , B 9 ,..., B n are set in the third bank Bank4, and at this time, the first bank Bank2 and the second bank
  • the number of memory blocks stored in the bank Bank3 and the third bank Bank4 are the same.
  • n is not a multiple of 3
  • the number of memory banks in the first bank Bank2 and the second bank Bank3 are the same, and the third bank Bank4
  • the storage block in the first bank Bank2 and the second bank Bank3 is one less storage block
  • the number of storage blocks in the second bank Bank3 and the third bank Bank4 there is one more storage block in the first bank Bank2 than in the second bank Bank3 and the third bank Bank4, but this does not affect the implementation of the present invention.
  • the number of memory banks is not limited to 3, and it can be M (M ⁇ 3), and M is preferably a multiple of 3. When M is not a multiple of 3, the solution of this patent can also be implemented for most of the memory banks.
  • the storage structure 200 further includes a controller, and the controller includes a chip controller 210, a first bank controller 220, a second bank controller 230, and a third bank controller 240.
  • the first bank controller 220 is connected to and controls the first bank Bank2
  • the second bank controller 230 is connected to and controls the second bank Bank3
  • the third bank controller 240 is connected And control the third bank Bank4.
  • the chip controller 210 is coupled to the first bank controller 220, the second bank controller 230, and the third bank controller 240, and is used to control the first bank Bank2 and the third bank controller 240.
  • the second bank Bank3 and the third bank Bank4 perform operations such as reading, writing, and erasing.
  • this embodiment adopts The chip controller 210 controls the first bank controller 220, the second bank controller 230, and the third bank controller 240 as a whole, while the first bank controller 220, the first bank controller 220, and the third bank controller 240
  • the second bank controller 230 and the third bank controller 240 respectively control the first bank Bank2, the second bank Bank3, and the third bank Bank4, so they can be controlled by the chip controller 210 Simultaneously operate the memory blocks in the first bank Bank2, the second bank Bank3, and the third bank Bank4.
  • the first bank controller 220, the second bank controller 230, the third bank controller 240, and the chip controller 210 can be integrated into the same control unit , Or modularize multiple control units such as 2, 3, etc., which can be done by those skilled in the art. This embodiment provides a better solution.
  • This embodiment also provides an erasing method of the storage structure 200, which is used to erase the storage structure 200 as a whole.
  • the storage blocks are alternately arranged in the first bank Bank2, the second bank Bank3, and the third bank Bank4 according to the serial number.
  • the controller controls the storage blocks B 1 , B 2 ,..., B n to perform erasing operations in sequence according to the number in a set erasing manner, and each of the storages All the blocks need to execute the first process, the second process, and the third process in sequence before the erase operation is completed.
  • the erasing method includes: when the storage block B i is performing the third process, the storage block B i+1 is performing the second process, and the storage block B i+2 is performing the first process, where i ⁇ [1, n -2]. That is to say, for the three storage blocks with adjacent numbers, the storage block B i performs the third process, the storage block B i+1 performs the second process, and the storage block B i+2 performs the first process simultaneously.
  • the storage block B i completes the third process
  • the storage block B i+1 completes the second process
  • the storage block B i+2 completes the first process
  • the storage block B i is erased; the storage block B i+1 performs the third process.
  • the storage block B i+2 executes the second process
  • the storage block Bi+3 executes the first process.... This continues in a pipeline manner until the storage block B n is erased, and the storage structure 200 completes the entire Erase.
  • the first process includes a preprogram step (Preprogram)
  • the second process includes an erase step (Erase)
  • the third process includes an over-erase repair step (OEC).
  • Preprogram a preprogram step
  • Erase an erase step
  • OEC over-erase repair step
  • FIG. 4 is a specific flowchart of the erasing method of the storage structure 200 provided by this embodiment. Next, the erasing method of the storage structure 200 provided in this embodiment will be described in detail with reference to FIGS. 3 and 4.
  • the first memory block B 1 performs preprogrammed step; memory block after completion of pre-programmed steps B 1, B 1 performs memory block erasing step, while the memory block performing preprogrammed Step B 2; B 1 when the memory block After the erasing step is completed and the memory block B 2 has completed the pre-programming step, the memory block B 1 has performed the erasing repair step, while the memory block B 2 has performed the erasing step, and the memory block B 3 has performed the pre-programming step; when the memory block B 1 After the erase repair step has been completed, the memory block B 2 has completed the erase step, and the memory block B 3 has completed the pre-programming step, the memory block B 1 has been erased (B 1 Erase Done).
  • the storage block B 2 has performed the erasing repair step, while the storage block B 3 has performed the erasing step, and the storage block B 4 has performed the pre-programming step; when the storage block B 2 has completed the erasing repair step, the storage block B 3 is completed After the erasing step and the memory block B 4 completes the pre-programming step, the memory block B 2 is erased (B 2 Erase Done)... Then proceed sequentially until the memory block B n-2 has completed the erasing repair step, the memory block B n-1 has completed the erasing step, and the memory block B n has completed the pre-programming step, and the memory block B n-2 has been erased.
  • B n-2 Erase Done Then the memory block B n-1 has been erased and repaired, and the memory block B n has been erased.
  • the memory block B n-1 has completed the erase and repair step and the memory block B n
  • the memory block B n-1 is erased (B n-1 Erase Done); then the memory block B n needs to be erased and repaired separately, and the memory block B n is erased and repaired after the erase repair step is completed.
  • B n is erased (B n Erase Done), and the storage structure 200 has been erased as a whole.
  • the erasing method of the storage structure provided in FIG. 2 requires that each storage block individually complete the erasing operation before performing the erasing operation of the next storage block.
  • the storage block B i executes the third process
  • the storage block B i+1 performs the second process
  • the storage block B i+2 performs the first process synchronously, which can save erasing time and improve erasing efficiency.
  • the time t 1 of the pre-programming step 50 ms
  • the time t 2 of the erasing step 80 ms
  • the time t 3 of the erasing repair step 20 ms
  • the erasing method of the storage structure provided in this embodiment can increase the erasing efficiency by about 46.5%.
  • the erasure saving time calculated above is a reference value. According to different manufacturing processes and operating modes of flash memory, pre-programming time, erasing time, and over-erasing repair time will all vary.
  • the erasing operation can be performed on the memory blocks B 1 ... B n , where n is an integer greater than or equal to 3, including: the first memory bank, the first memory bank, and the first memory block. Two memory banks, a third memory bank, and a controller.
  • the memory blocks are alternately arranged in the first memory bank, the second memory bank, and the third memory bank according to their numbers.
  • the controller is used to control the memory Blocks are erased in sequence according to the number in the set erasing mode.
  • the erasing operation includes performing the first process, the second process and the third process in sequence; the erasing mode includes: the memory block B i is in When the third process is performed, the storage block B i+1 is performing the second process, and the storage block B i+2 is performing the first process, where i ⁇ [1, n-2].
  • three adjacent memory blocks perform the first process, the second process and the third process synchronously, thereby saving the erasing time of the overall erasing of the memory structure, improving the erasing efficiency, and does not require additional circuits , Can be implemented without increasing costs.

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Abstract

一种存储结构及其擦除方法，能够对存储块执行擦除操作，包括：第一存储体、第二存储体、第三存储体及控制器，所述存储块按照编号顺次交替设置在所述第一存储体、第二存储体和第三存储体中，所述控制器用于控制所述存储块以设定的擦除方式按照编号顺次执行第一过程、第二过程和第三过程的擦除过程；所述擦除方式包括：存储块Bi在执行第三过程时，存储块Bi+1执行第二过程，存储块Bi+2在执行第一过程，其中，i∈[1，n-2]。所述方法中，相邻三个存储块同步进行第一过程、第二过程和第三过程，从而节约了存储结构整体擦除的擦除时间，提高了擦除的效率，并且不需要额外的电路，不增加成本。

Description

存储结构及其擦除方法 技术领域
本发明涉及半导体器件技术领域，尤其涉及一种存储结构及其擦除方法。
背景技术
闪存的主要特点是工作速度快、单元面积小、集成度高、可靠性好、可重复擦写10万次以上，数据可靠保持超过10年，从而可以大量的代替其他存储器嵌入到电路中。现在市场上主要的两种闪存是NOR结构和NAND结构的非易失性闪存，其中，NOR闪存(Nor Flash)单元面积小且读(写)操作时间短，因此被广泛的应用。目前主流的Nor Flash均是基于浮栅闪存技术，为了节约面积，其存储区域一般都是采用矩阵形式集中放置，然后在逻辑上分成很多存储块(Block)，在擦除时，以存储块为单位顺次进行擦除操作。通常擦除操作包括预编程步骤(Pre program)、擦除步骤(Erase)和过擦除修复步骤(Over Erase Correction，OEC)，预编程步骤是将存储块中的二进制值“1”全部变成“0”；擦除步骤是对存储块施加较大的擦除脉冲，从而使得存储块的阈值电压低于一特定的电平值；过擦除修复步骤是通过修复操作对过擦除的存储块进行修复，以避免其阈值电压过低。由于擦除操作需要这三个步骤，非易失性闪存也集成了大量的存储块，所以与读操作及写操作相比，非易失性闪存的整体擦除操作非常耗时。如何提高非易失性闪存整体擦除的效率，是目前亟待解决的技术问题。
发明内容
本发明的目的在于提供一种存储结构及其擦除方法，以解决非易失性闪存整体擦除的效率低的问题。
为了达到上述目的，本发明提供了一种存储结构，能够对存储块B 1,B 2,…,B n执行擦除操作，n为大于或等于3的整数，包括：第一存储体、第二存储体、第三存储体及控制器，所述存储块按照编号顺次交替设置在所述第一存储体、第二存储体和第三存储体中，所述控制器用于控制所述存储块以设定的擦除方式按照编号顺次进行擦除操作，所述擦除操作包括顺次执行第一过程、第二过程 和第三过程；
所述擦除方式包括：存储块B i在执行第三过程时，存储块B i+1在执行第二过程，存储块B i+2在执行第一过程，其中，i∈[1，n-2]。
可选的，存储块B 1完成第一过程之后，存储块B 1执行第二过程，同时存储块B 2执行第一过程，之后依次对其余存储块执行所述擦除方式；存储块B i完成第三过程、存储块B i+1完成第二过程以及存储块B i+2完成第一过程之后，存储块B i+1再执行第三过程；直至，存储块B n-1完成第二过程之后，存储块B n-1执行第三过程，同时存储块B n执行第二过程；存储块B n完成第二过程之后，单独执行第三过程。
可选的，所述第一过程包括预编程步骤，所述第二过程包括擦除步骤，所述第三过程包括过擦除修复步骤。
可选的，所述第一存储体、第二存储体及第三存储体中的存储块的数量均相同。
可选的，所述第一存储体与所述第二存储体中的存储块的数量相同，所述第三存储体中的存储块的数量与所述第一存储体和所述第二存储体中的存储块的数量不相同；或者所述第二存储体与所述第三存储体中的存储块的数量相同，所述第一存储体中的存储块的数量与所述第二存储体和所述第三存储体中的存储块的数量不相同。
可选的，所述存储结构包括M个存储体，其中，M≥3。
可选的，所述控制器包括：
第一存储体控制器，连接并控制所述第一存储体；
第二存储体控制器，连接并控制所述第二存储体；
第三存储体控制器，连接并控制所述第三存储体；
芯片控制器，连接所述第一存储体控制器、所述第二存储体控制器和第三存储体控制器，并能够同步操作第一存储体控制器、第二存储体控制器和第三存储体控制器中的存储块。
可选的，所述存储结构为Nor闪存。
本发明还提供了一种存储结构的擦除方法，用于对存储块B 1,B 2,…,B n执行擦除操作，n为大于或等于3的整数，包括：
所述存储块按照编号顺次交替设置在第一存储体、第二存储体和第三存储 体中；
控制所述存储块以设定的擦除方式按照编号顺次进行擦除操作；
其中，所述擦除操作包括顺次执行第一过程、第二过程和第三过程，所述擦除方式包括：存储块B i在执行第三过程时，存储块B i+1在执行第二过程，存储块B i+2在执行第一过程，其中，i∈[1，n-2]。
可选的，所述存储结构的擦除方法是对所述存储结构进行整体擦除。
在本发明实施例提供的存储结构及其擦除方法中，能够对存储块B 1,B 2,…,B n执行擦除操作，n为大于或等于3的整数，包括：第一存储体、第二存储体、第三存储体及控制器，所述存储块按照编号顺次交替设置在所述第一存储体、第二存储体和第三存储体中，所述控制器用于控制所述存储块以设定的擦除方式按照编号顺次进行擦除操作，所述擦除操作包括顺次执行第一过程、第二过程和第三过程；所述擦除方式包括：存储块B i在执行第三过程时，存储块B i+1在执行第二过程，存储块B i+2在执行第一过程，其中，i∈[1，n-2]。本发明中的相邻三个存储块同步进行第一过程、第二过程和第三过程，从而节约了存储结构整体擦除的擦除时间，提高了擦除的效率，并且不需要额外的电路，可以在不增加成本的情况下实施。
附图说明
图1为一种存储结构的结构示意图；
图2为图1中的存储结构的擦除方法的具体流程图；
图3为本发明实施例提供的存储结构的结构示意图；
图4为本发明实施例提供的存储结构的擦除方法的具体流程图；
其中，附图标记为：
100-存储结构；110-芯片控制器；Bank0-第一存储体；Bank1-第二存储体；
200-存储结构；210-芯片控制器；220-第一存储体控制器；230-第二存储体控制器；240-第三存储体控制器；Bank2-第一存储体；Bank3-第二存储体；Bank4-第三存储体。
具体实施方式
图1为一种存储结构100的结构示意图。如图1所示，所述存储结构100包括两个存储体，分别为第一存储体Bank0和第二存储体Bank1，所述第一存储 体Bank0和所述第二存储体Bank1都耦合至芯片控制器110，所述芯片控制器110用于控制所述第一存储体Bank0和所述第二存储体Bank1执行诸如读取、写入和擦除的操作。所述第一存储体Bank0和所述第二存储体Bank1中总共存储有n(n≥2)个存储块，n个存储块在所述第一存储体Bank0和所述第二存储体Bank1之间平均分配，并且所述第一存储体Bank0和所述第二存储体Bank1中的存储块是顺序排列的。为了便于描述，对n个存储块按顺序编号为：B 1,B 2,…,B n，其中，
Figure PCTCN2019125963-appb-000001
设置在所述第一存储体Bank0中，
Figure PCTCN2019125963-appb-000002
设置在所述第二存储体Bank1中。
图2为所述存储结构100进行整体擦除的流程图。如图2所示，对所述存储结构100进行整体擦除时，是B 1,B 2,…,B n的顺序顺次执行擦除操作的。具体为：首先对B 1执行预编程步骤(Pre program)，然后对存储块B 1执行擦除步骤(Erase)，接着对B 1执行过擦除修复步骤(OEC)，三个步骤结束后，B 1完成擦除(Erase Done)。接下来，对存储块B 2顺次执行预编程步骤、擦除步骤和过擦除修复步骤，以完成对存储块B 2的擦除。然后依次往下执行，直至最后一个存储块B n完成擦除，所述存储结构100完成了整体擦除。
这种存储结构100的擦除方法对于每个存储块单独重复三个步骤，上一个存储块完成擦除操作后才对下一个存储块进行擦除操作，由于所述存储结构100中的存储块通常很多(例如n＝256)，完成存储结构100的整体擦除需要非常多的时间，擦除效率低。
下面将结合示意图对本发明的具体实施方式进行更详细的描述。根据下列描述，本发明的优点和特征将更清楚。需说明的是，附图均采用非常简化的形式且均使用非精准的比例，仅用以方便、明晰地辅助说明本发明实施例的目的。存储块、存储体的编号是为了便于对技术方案进行说明而进行设置，并不意味着必须对存储块、存储体设置相应的编号，也不意味着必须按照本专利的编号方式进行编号本方案才能实施。
基于此，图3为本实施例提供的存储结构的结构示意图。如图3所示，所述存储结构200例如是Nor闪存(Nor Flash)，其包括至少三个存储体，分别为 第一存储体Bank2、第二存储体Bank3及第三存储体Bank4，所述第一存储体Bank2、所述第二存储体Bank3及第三存储体Bank4中总共存储有n(n≥3)个存储块，n个存储块在所述第一存储体Bank2、所述第二存储体Bank3及第三存储体Bank4之间平均分配，所述存储块按照编号顺次交替设置在所述第一存储体Bank2、所述第二存储体Bank3及第三存储体Bank4中。为了便于描述，对n个存储块按顺序编号为：B 1,B 2,…,B n，本实施例中，n为3的倍数。这样一来，存储块B 1,B 4,B 7,…,B n-2设置在所述第一存储体Bank2中，存储块B 2,B 5,B 8,…,B n-1设置在所述第二存储体Bank3中，存储块B 3,B 6,B 9,…,B n设置在所述第三存储体Bank4中，此时所述第一存储体Bank2、所述第二存储体Bank3和所述第三存储体Bank4中存储的存储块的数量是相同的。
当然，当n不为3的倍数时，可以有以下两种情况：1)所述第一存储体Bank2与所述第二存储体Bank3中的存储块的数量相同，所述第三存储体Bank4中的存储块比所述第一存储体Bank2和所述第二存储体Bank3中的存储块少一个；2)所述第二存储体Bank3与所述第三存储体Bank4中的存储块的数量相同，所述第一存储体Bank2中的存储块比所述第二存储体Bank3和所述第三存储体Bank4中的存储块多一个，但这并不影响本发明的实施。并且，存储体的数量也不限于3个，可以为M(M≥3)个，M优选为3的倍数，当M不为3的倍数时也可对其中多数存储体实施本专利的方案。
进一步，所述存储结构200还包括控制器，所述控制器包括芯片控制器210、第一存储体控制器220、第二存储体控制器230及第三存储体控制器240。所述第一存储体控制器220连接并控制所述第一存储体Bank2，所述第二存储体控制器230连接并控制所述第二存储体Bank3，所述第三存储体控制器240连接并控制所述第三存储体Bank4。所述芯片控制器210耦合至所述第一存储体控制器220、所述第二存储体控制器230和所述第三存储体控制器240，用于控制所述第一存储体Bank2、所述第二存储体Bank3和所述第三存储体Bank4执行诸如读取、写入和擦除等操作。由于第一存储体Bank2、所述第二存储体Bank3和所述第三存储体Bank4的地址和偏置条件(需要在源极、漏极或栅极施加的电压)均不同，本实施例采用所述芯片控制器210整体控制所述第一存储体控制器220、所述第二存储体控制器230和所述第三存储体控制器240，而所述第一存储体控制器220、所述第二存储体控制器230和所述第三存储体控制器240分别控制第 一存储体Bank2、所述第二存储体Bank3和所述第三存储体Bank4，所以可以通过所述芯片控制器210同时操作所述第一存储体Bank2、所述第二存储体Bank3和所述第三存储体Bank4中的存储块。
应理解，根据现有的集成电路设计和制造技术，可以将第一存储体控制器220、第二存储体控制器230、第三存储体控制器240以及芯片控制器210集成为同一个控制单元，或模块化2个、3个等多个控制单元，这对本领域技术人员而言均是能够做到的，本实施例是提供了一种较优的解决方案。
本实施例还提供了所述存储结构200的擦除方法，用于对所述存储结构200进行整体擦除。具体的，首先将所述存储块按照编号顺次交替设置在第一存储体Bank2、第二存储体Bank3和第三存储体Bank4中。当所述存储结构200需要整体擦除时，所述控制器控制存储块B 1,B 2,…,B n以设定的擦除方式按照编号顺次进行擦除操作，每个所述存储块均需要顺次执行第一过程、第二过程和第三过程才算是完成了擦除操作。所述擦除方式包括：存储块B i在执行第三过程时，存储块B i+1在执行第二过程，存储块B i+2在执行第一过程，其中，i∈[1，n-2]。也就是说，对于编号相邻的三个存储块，存储块B i执行第三过程、存储块B i+1执行第二过程以及存储块B i+2执行第一过程是同步进行的，当存储块B i完成第三过程、存储块B i+1完成第二过程之后且存储块B i+2完成第一过程之后，存储块B i完成擦除；存储块B i+1执行第三过程，同时存储块B i+2执行第二过程、存储块B i+3执行第一过程…，这样以流水线的方式继续下去，直至存储块B n完成擦除，所述存储结构200完成整体擦除。
本实施例中，所述第一过程包括预编程步骤(Pre program)，所述第二过程包括擦除步骤(Erase)，所述第三过程包括过擦除修复步骤(OEC)。
图4为本实施例提供的所述存储结构200的擦除方法的具体流程图。接下来将结合图3和图4对本实施例提供的存储结构200的擦除方法作详细的描述。
如图4所示，首先存储块B 1执行预编程步骤；存储块B 1完成预编程步骤之后，存储块B 1执行擦除步骤，同时存储块B 2执行预编程步骤；当存储块B 1完成擦除步骤并且存储块B 2完成预编程步骤之后，存储块B 1执行过擦除修复步骤，同时存储块B 2执行擦除步骤，存储块B 3执行预编程步骤；当存储块B 1完成过擦除修复步骤、存储块B 2完成擦除步骤且存储块B 3完成预编程步骤之后，存储块B 1完成擦除(B 1 Erase Done)。接下来，存储块B 2执行过擦除修复步骤，同 时存储块B 3执行擦除步骤，存储块B 4执行预编程步骤；当存储块B 2完成过擦除修复步骤、存储块B 3完成擦除步骤且存储块B 4完成预编程步骤之后，存储块B 2完成擦除(B 2 Erase Done)…。然后依次往下执行，直至存储块B n-2完成过擦除修复步骤、存储块B n-1完成擦除步骤且存储块B n完成预编程步骤之后，存储块B n-2完成擦除(B n-2 Erase Done)；接着存储块B n-1执行过擦除修复步骤，同时存储块B n执行擦除步骤，当存储块B n-1完成过擦除修复步骤且存储块B n完成擦除步骤之后，存储块B n-1完成擦除(B n-1 Erase Done)；然后存储块B n需要单独执行过擦除修复步骤，存储块B n完成过擦除修复步骤之后，B n完成擦除(B n Erase Done)，所述存储结构200完成了整体擦除。
图2提供的存储结构的擦除方法需要每个存储块单独完成擦除操作后再进行下一个存储块的擦除操作，而本实施例中，由于存储块B i执行第三过程、存储块B i+1执行第二过程以及存储块B i+2执行第一过程同步进行，可以节约擦除的时间，提高了擦除效率。
为了证明本实施例提供的存储结构的擦除方法提高了擦除效率，做如下假设和计算：
假设n＝256，预编程步骤的时间t 1＝50ms，擦除步骤的时间t 2＝80ms，过擦除修复步骤的时间t 3＝20ms；
采用图2提供的存储结构的擦除方法擦除整个存储结构需要的时间T 1为：
T 1＝(50ms+80ms+20ms)*256＝38.4s
采用图4提供的存储结构的擦除方法擦除整个存储结构需要的时间T 2为：
T 2＝50ms+80ms*256+20ms＝20.58s
可见，相较于图2提供的存储结构的擦除方法来说，本实施例提供的存储结构的擦除方法可以提高约46.5％的擦除效率。
上述计算的擦除节约时间均为参考值。闪存根据制作工艺的不同，操作模式的不同，预编程时间、擦除时间以及过擦除修复时间均会有所变化。
综上，在本发明实施例提供的存储结构及其擦除方法中，能够对存储块B 1…B n执行擦除操作，n为大于或等于3的整数，包括：第一存储体、第二存储体、第三存储体及控制器，所述存储块按照编号顺次交替设置在所述第一存储体、第二存储体和第三存储体中，所述控制器用于控制所述存储块以设定的擦除方式按照编号顺次进行擦除操作，所述擦除操作包括顺次执行第一过程、第二过 程和第三过程；所述擦除方式包括：存储块B i在执行第三过程时，存储块B i+1在执行第二过程，存储块B i+2在执行第一过程，其中，i∈[1，n-2]。本发明中的相邻三个存储块同步进行第一过程、第二过程和第三过程，从而节约了存储结构整体擦除的擦除时间，提高了擦除的效率，并且不需要额外的电路，可以在不增加成本的情况下实施。
上述仅为本发明的优选实施例而已，并不对本发明起到任何限制作用。任何所属技术领域的技术人员，在不脱离本发明的技术方案的范围内，对本发明揭露的技术方案和技术内容做任何形式的等同替换或修改等变动，均属未脱离本发明的技术方案的内容，仍属于本发明的保护范围之内。

Claims (10)

  1. 一种存储结构，能够对存储块B 1,B 2,…,B n执行擦除操作，n为大于或等于3的整数，其特征在于，包括：第一存储体、第二存储体、第三存储体及控制器，所述存储块按照编号顺次交替设置在所述第一存储体、第二存储体和第三存储体中，所述控制器用于控制所述存储块以设定的擦除方式按照编号顺次进行擦除操作，所述擦除操作包括顺次执行第一过程、第二过程和第三过程；
    所述擦除方式包括：存储块B i在执行第三过程时，存储块B i+1在执行第二过程，存储块B i+2在执行第一过程，其中，i∈[1，n-2]。
  2. 如权利要求1所述的存储结构，其特征在于，存储块B 1完成第一过程之后，存储块B 1执行第二过程，同时存储块B 2执行第一过程，之后依次对其余存储块执行所述擦除方式；存储块B i完成第三过程、存储块B i+1完成第二过程以及存储块B i+2完成第一过程之后，存储块B i+1再执行第三过程；直至，存储块B n-1完成第二过程之后，存储块B n-1执行第三过程，同时存储块B n执行第二过程，存储块B n完成第二过程之后，单独执行第三过程。
  3. 如权利要求1或2所述的存储结构，其特征在于，所述第一过程包括预编程步骤，所述第二过程包括擦除步骤，所述第三过程包括过擦除修复步骤。
  4. 如权利要求1或2所述的存储结构，其特征在于，所述第一存储体、第二存储体及第三存储体中的存储块的数量均相同。
  5. 如权利要求1或2所述的存储结构，其特征在于，所述第一存储体与所述第二存储体中的存储块的数量相同，所述第三存储体中的存储块的数量与所述第一存储体和所述第二存储体中的存储块的数量不相同；或者所述第二存储体与所述第三存储体中的存储块的数量相同，所述第一存储体中的存储块的数量与所述第二存储体和所述第三存储体中的存储块的数量不相同。
  6. 如权利要求1或2所述的存储结构，其特征在于，所述存储结构包括M个存储体，其中，M≥3。
  7. 如权利要求1所述的存储结构，其特征在于，所述控制器包括：
    第一存储体控制器，连接并控制所述第一存储体；
    第二存储体控制器，连接并控制所述第二存储体；
    第三存储体控制器，连接并控制所述第三存储体；
    芯片控制器，连接所述第一存储体控制器、所述第二存储体控制器和第三存储体控制器，并能够同步操作第一存储体控制器、第二存储体控制器和第三存储体控制器中的存储块。
  8. 如权利要求1或7所述的存储结构，其特征在于，所述存储结构为Nor闪存。
  9. 一种存储结构的擦除方法，用于对存储块B 1,B 2,…,B n执行擦除操作，n为大于或等于3的整数，其特征在于，包括：
    所述存储块按照编号顺次交替设置在第一存储体、第二存储体和第三存储体中；
    控制所述存储块以设定的擦除方式按照编号顺次进行擦除操作；
    其中，所述擦除操作包括顺次执行第一过程、第二过程和第三过程，所述擦除方式包括：存储块B i在执行第三过程时，存储块B i+1执行第二过程，存储块B i+2在执行第一过程，其中，i∈[1，n-2]。
  10. 如权利要求9所述的存储结构的擦除方法，其特征在于，所述存储结构的擦除方法是对所述存储结构进行整体擦除。
PCT/CN2019/125963 2019-12-02 2019-12-17 存储结构及其擦除方法 WO2021109243A1 (zh)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101800078A (zh) * 2009-02-11 2010-08-11 北京芯技佳易微电子科技有限公司 一种非易失存储器的擦除方法及装置
US20110176369A1 (en) * 2010-01-19 2011-07-21 Elite Semiconductor Memory Technology Inc. Erase verification method of flash memory apparatus
CN103488462A (zh) * 2013-09-06 2014-01-01 暨南大学 一种改进型8051ip核
CN103700401A (zh) * 2012-09-28 2014-04-02 广明光电股份有限公司 快闪存储器编程及读取的方法
CN107102816A (zh) * 2016-02-23 2017-08-29 爱思开海力士有限公司 存储系统及其操作方法

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3920501B2 (ja) * 1999-04-02 2007-05-30 株式会社東芝 不揮発性半導体記憶装置及びそのデータ消去制御方法
CN103310839B (zh) * 2012-03-15 2016-01-20 旺宏电子股份有限公司 缩短擦除操作的方法与装置
US10203884B2 (en) * 2016-03-30 2019-02-12 Intel Corporation Methods and apparatus to perform erase-suspend operations in memory devices

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101800078A (zh) * 2009-02-11 2010-08-11 北京芯技佳易微电子科技有限公司 一种非易失存储器的擦除方法及装置
US20110176369A1 (en) * 2010-01-19 2011-07-21 Elite Semiconductor Memory Technology Inc. Erase verification method of flash memory apparatus
CN103700401A (zh) * 2012-09-28 2014-04-02 广明光电股份有限公司 快闪存储器编程及读取的方法
CN103488462A (zh) * 2013-09-06 2014-01-01 暨南大学 一种改进型8051ip核
CN107102816A (zh) * 2016-02-23 2017-08-29 爱思开海力士有限公司 存储系统及其操作方法

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