WO2021109244A1 - 存储结构及其擦除方法 - Google Patents

存储结构及其擦除方法 Download PDF

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Publication number
WO2021109244A1
WO2021109244A1 PCT/CN2019/125965 CN2019125965W WO2021109244A1 WO 2021109244 A1 WO2021109244 A1 WO 2021109244A1 CN 2019125965 W CN2019125965 W CN 2019125965W WO 2021109244 A1 WO2021109244 A1 WO 2021109244A1
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Prior art keywords
erasing
storage
memory
bank
block
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PCT/CN2019/125965
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English (en)
French (fr)
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郑钟倍
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武汉新芯集成电路制造有限公司
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Priority to US17/050,457 priority Critical patent/US20220051726A1/en
Publication of WO2021109244A1 publication Critical patent/WO2021109244A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
    • G11C16/16—Circuits for erasing electrically, e.g. erase voltage switching circuits for erasing blocks, e.g. arrays, words, groups
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0638—Organizing or formatting or addressing of data
    • G06F3/064—Management of blocks
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0646—Horizontal data movement in storage systems, i.e. moving data in between storage devices or systems
    • G06F3/0652—Erasing, e.g. deleting, data cleaning, moving of data to a wastebasket
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0658—Controller construction arrangements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/102—External programming circuits, e.g. EPROM programmers; In-circuit programming or reprogramming; EPROM emulators
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/32—Timing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/344—Arrangements for verifying correct erasure or for detecting overerased cells
    • G11C16/345—Circuits or methods to detect overerased nonvolatile memory cells, usually during erasure verification
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/3468—Prevention of overerasure or overprogramming, e.g. by verifying whilst erasing or writing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/3468—Prevention of overerasure or overprogramming, e.g. by verifying whilst erasing or writing
    • G11C16/3477—Circuits or methods to prevent overerasing of nonvolatile memory cells, e.g. by detecting onset or cessation of current flow in cells and using the detector output to terminate erasing

Definitions

  • the present invention relates to the technical field of semiconductor devices, in particular to a storage structure and an erasing method thereof.
  • flash memory The main features of flash memory are fast working speed, small unit area, high integration, good reliability, re-erasable over 100,000 times, and reliable data retention for more than 10 years, which can replace other memories and be embedded in circuits in large quantities.
  • NOR flash Non-volatile flash memory of NOR structure and NAND structure.
  • NOR flash Non-volatile flash memory of NOR structure and NAND structure.
  • Nor Flash has a small unit area and short read (write) operation time, so it is widely used.
  • Nor Flash is based on floating gate flash technology. In order to save area, its storage area is generally placed in a matrix form, and then logically divided into many storage blocks (Block). When erasing, the storage block is used as the storage area.
  • the erasing operation includes the preprogramming step (Preprogram), the erasing step (Erase) and the over erasing repair step (Over Erase Correction, OEC).
  • the preprogramming step is to change the binary value "1" in the memory block to all "0";
  • the erasing step is to apply a larger erase pulse to the memory block, so that the threshold voltage of the memory block is lower than a specific level;
  • the over-erase repair step is to repair the over-erased memory through the repair operation The block is repaired to avoid its threshold voltage is too low.
  • the non-volatile flash memory Since the erasing operation requires these three steps, and the non-volatile flash memory also integrates a large number of storage blocks, the overall erasing operation of the non-volatile flash memory is very time-consuming compared with the read operation and the write operation. How to improve the overall erasing efficiency of non-volatile flash memory is a technical problem that needs to be solved urgently.
  • the purpose of the present invention is to provide a storage structure and an erasing method thereof, so as to solve the problem of low efficiency of overall erasing of non-volatile flash memory.
  • the present invention provides a storage structure that can perform erasing operations on storage blocks B 1 ... B n , where n is an integer greater than or equal to 2, including: a first bank, a second bank, and control
  • the memory block is alternately arranged in the first memory bank and the second memory bank according to the serial number, and the controller is used to control the memory block to perform the serially in accordance with the serial number in a set erasing manner
  • An erasing operation, the erasing operation includes sequentially performing a first process and a second process;
  • the erasing method includes: when the storage block B i is performing the second process, the storage block B i+1 is performing the first process, where i ⁇ [1, n-1].
  • the first process includes a pre-programming step and an erasing step
  • the second process includes an over-erase repair step.
  • the first erasing step includes a pre-programming step
  • the second process includes an erasing step and an over-erase repair step.
  • the number of storage blocks in the first storage bank and the second storage bank are the same or different.
  • the storage structure includes M storage banks, where M ⁇ 2.
  • the controller includes:
  • a first memory bank controller connected to and controlling the first memory bank
  • a second memory bank controller connected to and controlling the second memory bank
  • a chip controller is connected to the first memory bank controller and the second memory bank controller, and can control the memory blocks to sequentially perform erasing operations according to their numbers.
  • the storage structure is Nor flash memory.
  • the present invention also provides an erasing method of a storage structure, which is used to perform an erasing operation on the storage blocks B 1 ... B n , where n is an integer greater than or equal to 2, including:
  • the storage blocks are alternately arranged in the first storage bank and the second storage bank according to the serial number
  • the erasing operation includes performing the first process and the second process in sequence, and the erasing manner includes: when the memory block B i is performing the second process, the memory block B i+1 is performing the first process, wherein , I ⁇ [1, n-1].
  • the method for erasing the storage structure is used to erase the storage structure as a whole.
  • the erasing operation can be performed on the storage blocks B 1 ... B n , where n is an integer greater than or equal to 2, and the storage structure includes a first memory bank and a second memory block.
  • the storage block is alternately arranged in the first storage bank and the second storage bank according to the serial number, and the controller is used to control the storage block to use the set erasing method according to the serial number.
  • the erasing operation is performed sequentially, and the erasing operation includes performing the first process and the second process in sequence; the erasing method includes: when the memory block B i is performing the second process, the memory block B i+1 is executing The first process, where i ⁇ [1, n-1].
  • two adjacent storage blocks perform the first process and the second process synchronously, thereby saving the erasing time of the overall erasing of the storage structure, improving the erasing efficiency, and does not require additional circuits, which can be Implemented in the case of increased costs.
  • Figure 1 is a schematic structural diagram of a storage structure
  • FIG. 2 is a specific flowchart of the erasing method of the storage structure in FIG. 1;
  • Embodiment 3 is a schematic structural diagram of a storage structure provided by Embodiment 1 of the present invention.
  • Embodiment 4 is a specific flowchart of a method for erasing a storage structure provided by Embodiment 1 of the present invention
  • FIG. 5 is a specific flowchart of a method for erasing a storage structure provided by the second embodiment of the present invention.
  • 100-storage structure 110-chip controller; Bank0-first bank; Bank1-second bank;
  • 200-storage structure 210-chip controller; 220-first bank controller; 230-second bank controller; Bank2-first bank; Bank3-second bank.
  • FIG. 1 is a schematic structural diagram of a storage structure 100.
  • the memory structure 100 includes two memory banks, namely a first memory bank Bank0 and a second memory bank Bank1. Both the first memory bank Bank0 and the second memory bank Bank1 are coupled to the chip.
  • the controller 110 is configured to control the first bank Bank0 and the second bank Bank1 to perform operations such as reading, writing, and erasing.
  • a total of n (n ⁇ 2) memory blocks are stored in the first bank Bank0 and the second bank Bank1, and n memory blocks are stored between the first bank Bank0 and the second bank Bank1.
  • the memory blocks in the first bank Bank0 and the second bank Bank1 are arranged in sequence.
  • the n memory blocks are numbered in sequence: B 1 , B 2 ,..., B n , where, Set in the first bank Bank0, Set in the second bank Bank1.
  • FIG. 2 is a flowchart of the overall erasing of the storage structure 100.
  • the erase operation is performed sequentially in the order of B 1 , B 2 ,..., B n.
  • B 1 the Erase
  • OEC over-erase repair step
  • FIG. 3 is a schematic structural diagram of the storage structure provided by this embodiment.
  • the storage structure 200 is, for example, Nor Flash, which includes at least two banks, namely a first bank Bank2 and a second bank Bank3.
  • the storage blocks They are alternately arranged in the first bank Bank2 and the second bank Bank3 according to the serial number.
  • the n memory blocks are sequentially numbered as: B 1 , B 2 ,..., B n , in this embodiment, n is an even number.
  • the odd-numbered memory blocks B 1 , B 3 ,..., B n-1 are set in the first memory bank Bank2
  • the even-numbered memory blocks B 2 , B 4 ,..., B n are set In the second memory bank Bank3, at this time, the number of memory blocks stored in the first memory bank Bank2 and the second memory bank Bank3 are the same.
  • the memory block stored in the first memory bank Bank2 is one more memory block than the memory block stored in the second memory bank Bank3, but this does not affect the implementation of the present invention.
  • the storage structure 200 further includes a controller, and the controller includes a chip controller 210, a first memory bank controller 220, and a second memory bank controller 230.
  • the first bank controller 220 is connected to and controls the first bank Bank2
  • the second bank controller 230 is connected to and controls the second bank Bank3
  • the chip controller 210 is coupled to the
  • the first bank controller 220 and the second bank controller 230 are used to control the first bank Bank2 and the second bank Bank3 to perform operations such as reading, writing, and erasing.
  • this embodiment uses the chip controller 210 to control the entire The first bank controller 220 and the second bank controller 230, and the first bank controller 220 and the second bank controller 230 respectively control the first bank Bank2 and the second bank Since there are two banks Bank3, the chip controller 210 can simultaneously operate the memory blocks in the first bank Bank2 and the second bank Bank3.
  • the first memory controller 220, the second memory controller 230, and the chip controller 210 can be integrated into the same control unit, or two modules can be modularized.
  • This embodiment also provides an erasing method of the storage structure 200, which is used to erase the storage structure 200 as a whole.
  • the storage blocks are alternately arranged in the first bank Bank2 and the second bank Bank3 according to the serial numbers.
  • the controller controls the storage blocks B 1 , B 2 ,..., B n to perform erasing operations in sequence according to the number in a set erasing manner, and each of the storages All blocks need to execute the first process and the second process in sequence to complete the erase operation.
  • the erasing method includes: when the storage block B i is performing the second process, the storage block B i+1 is performing the first process, where i ⁇ [1, n-1].
  • the storage block B i performs the second process and the storage block B i+1 performs the first process synchronously.
  • the memory block B i completes the second process and the storage block After B i+1 completes the first process, the memory block B i is erased; the memory block B i+1 executes the second process, while the memory block B i+1 executes the first process..., which continues in a pipeline manner, Until the memory block B n is erased, the memory structure 200 is erased as a whole.
  • the first process includes a pre program step
  • the second process includes an erase step (Erase) and an over-erase repair step (OEC). Therefore, when the storage block B i executes the second process, it actually executes the two steps of the erase step (Erase) and the over-erase repair step (OEC) in sequence; while the storage block B i+1 executes the first process, the actual Only one step of the pre program (Pre program) has been executed.
  • FIG. 4 is a specific flowchart of the erasing method of the storage structure 200 provided by this embodiment. Next, the erasing method of the storage structure 200 provided in this embodiment will be described in detail with reference to FIGS. 3 and 4.
  • the first memory block B 1 performs preprogrammed step; memory block after completion of pre-programmed steps B 1, B 1 sequentially executes the memory block erasing step and over-erase repair step, while the memory block performing pre-B 2 Programming step: After the memory block B 1 completes the erasing step and the over-erase repair step and the memory block B 2 completes the pre-programming step, the memory block B 1 is erased (B 1 Erase Done).
  • the memory block B 2 performs the erasing step and the over-erase repair step in sequence, while the memory block B 3 performs the pre-programming step; when the memory block B 2 completes the erase step and the over-erase repair step and the memory block B 3 After the pre-programming step is completed, the memory block B 2 is erased (B 2 Erase Done)...
  • the memory block B n-1 completes the erase (B n-1 Erase Done )
  • the memory block B n needs to perform the erasing step and the over erasing repair step separately and sequentially.
  • B n completes the erasing (B n Erase Done)
  • the storage structure 200 completes the overall erasing.
  • the erasing method of the storage structure provided in FIG. 2 requires that each storage block individually complete the erasing operation before performing the erasing operation of the next storage block.
  • each storage block B i performs the second process and The storage block B i+1 performs the first process synchronously, which can save erasing time and improve erasing efficiency.
  • the time t 1 of the pre-programming step 50 ms
  • the time t 2 of the erasing step 80 ms
  • the time t 3 of the erasing repair step 20 ms
  • the erasing method of the storage structure provided in this embodiment can improve the erasing efficiency by about 33.2%.
  • the first process includes a pre-programming step and an erasing step
  • the second process includes an over-erase repair step. Therefore, when the memory block B i executes the second process, it actually only performs one step of the erase repair step; while the memory block B i+1 executes the first process, in fact, only the pre-programming step and the erase are performed sequentially. Step these two steps.
  • FIG. 5 is a specific flowchart of the erasing method of the storage structure 200 provided by this embodiment. Next, the erasing method of the storage structure 200 provided in this embodiment will be described in detail with reference to FIGS. 3 and 5.
  • the memory block B 2 has performed the erasing repair step, while the memory block B 3 has performed the pre-programming step and the erasing step; when the memory block B 2 has completed the erasing repair step and the memory block B 3 has completed the pre-programming and erasing steps
  • the memory block B 2 is erased (B 2 Erase Done)... Then proceed sequentially until the memory block B n-1 has completed the erasing repair step and the memory block B n has completed the pre-programming and erasing steps, and the memory block B n-1 is erased (B n-1 Erase Done ), at this time, the memory block B n needs to perform the erasing repair step separately.
  • B n is erased (B n Erase Done), and the storage structure 200 has completed the overall erasing.
  • the time t 1 of the pre-programming step 50 ms
  • the time t 2 of the erasing step 80 ms
  • the time t 3 of the erasing repair step 20 ms
  • the erasing method of the storage structure provided in this embodiment can improve the erasing efficiency by about 13.3%.
  • the erasure saving time calculated in the first and second embodiments are all reference values. According to different manufacturing processes and operating modes of flash memory, pre-programming time, erasing time, and over-erasing repair time will all vary. Therefore, it can be known that the erasing time saved in the second embodiment is not necessarily greater than Example one is low.
  • the number of memory banks in the first and second embodiments is not limited to two. It can be M, and M is preferably a multiple of 2. When M is not a multiple of 2, the patent can also be implemented for most of the memory banks. Program.
  • the erasing operation can be performed on the storage blocks B 1 ... B n , where n is an integer greater than or equal to 2, and the storage structure includes the first storage
  • the storage block is alternately arranged in the first storage bank and the second storage bank according to the serial number, and the controller is used to control the storage block to set
  • the erasing method performs the erasing operation in sequence according to the number, and the erasing operation includes performing the first process and the second process in sequence; the erasing mode includes: when the second process is executed for the storage block B i, the storage block B i+1 is performing the first process, where i ⁇ [1, n-1].
  • two adjacent storage blocks perform the first process and the second process synchronously, thereby saving the erasing time of the overall erasing of the storage structure, improving the erasing efficiency, and does not require additional circuits, which can be Implemented in the case of increased costs.

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Abstract

本发明提供了一种存储结构及其擦除方法，能够对存储块B 1…B n执行擦除操作，n为大于或等于2的整数，所述存储结构包括第一存储体、第二存储体及控制器，所述存储块按照编号顺次交替设置在所述第一存储体和所述第二存储体中，所述控制器用于控制所述存储块以设定的擦除方式按照编号顺次进行擦除操作，所述擦除操作包括顺次执行第一过程和第二过程；所述擦除方式包括：存储块B i在执行第二过程时，存储块B i+1在执行第一过程，其中，i∈[1，n-1]。本发明中的相邻两个存储块同步进行第一过程和第二过程，从而节约了存储结构整体擦除的擦除时间，提高了擦除的效率，并且不需要额外的电路，可以在不增加成本的情况下实施。

Description

存储结构及其擦除方法 技术领域
本发明涉及半导体器件技术领域，尤其涉及一种存储结构及其擦除方法。
背景技术
闪存的主要特点是工作速度快、单元面积小、集成度高、可靠性好、可重复擦写10万次以上，数据可靠保持超过10年，从而可以大量的代替其他存储器嵌入到电路中。现在市场上主要的两种闪存是NOR结构和NAND结构的非易失性闪存，其中，NOR闪存(Nor Flash)单元面积小且读(写)操作时间短，因此被广泛的应用。目前主流的Nor Flash均是基于浮栅闪存技术，为了节约面积，其存储区域一般都是采用矩阵形式集中放置，然后在逻辑上分成很多存储块(Block)，在擦除时，以存储块为单位顺次进行擦除操作。通常擦除操作包括预编程步骤(Pre program)、擦除步骤(Erase)和过擦除修复步骤(Over Erase Correction，OEC)，预编程步骤是将存储块中的二进制值“1”全部变成“0”；擦除步骤是对存储块施加较大的擦除脉冲，从而使得存储块的阈值电压低于一特定的电平值；过擦除修复步骤是通过修复操作对过擦除的存储块进行修复，以避免其阈值电压过低。由于擦除操作需要这三个步骤，非易失性闪存也集成了大量的存储块，所以与读操作及写操作相比，非易失性闪存的整体擦除操作非常耗时。如何提高非易失性闪存整体擦除的效率，是目前亟待解决的技术问题。
发明内容
本发明的目的在于提供一种存储结构及其擦除方法，以解决非易失性闪存整体擦除的效率低的问题。
为了达到上述目的，本发明提供了一种存储结构，能够对存储块B 1…B n执行擦除操作，n为大于或等于2的整数，包括：第一存储体、第二存储体及控制器，所述存储块按照编号顺次交替设置在所述第一存储体和所述第二存储体中，所述控制器用于控制所述存储块以设定的擦除方式按照编号顺次进行擦除操作，所述擦除操作包括顺次执行第一过程和第二过程；
所述擦除方式包括：存储块B i在执行第二过程时，存储块B i+1在执行第一过程，其中，i∈[1，n-1]。
可选的，存储块B 1完成第一过程之后，存储块B 1执行第二过程，同时存储块B 2执行第一过程；之后依次对其余存储块执行所述擦除方式；存储块B i完成第二过程且存储块B i+1完成第一过程之后，存储块B i+1再执行第二过程；直至，存储块B n执行完第一过程之后，单独执行第二过程。
可选的，所述第一过程包括预编程步骤和擦除步骤，所述第二过程包括过擦除修复步骤。
可选的，所述第一擦除步骤包括预编程步骤，所述第二过程包括擦除步骤和过擦除修复步骤。
可选的，所述第一存储体及所述第二存储体中的存储块的数量相同或不相同。
可选的，所述存储结构包括M个存储体，其中，M≥2。
可选的，所述控制器包括：
第一存储体控制器，连接并控制所述第一存储体；
第二存储体控制器，连接并控制所述第二存储体；
芯片控制器，连接所述第一存储体控制器和所述第二存储体控制器，并能够控制所述存储块按照编号顺次进行擦除操作。
可选的，所述存储结构为Nor闪存。
本发明还提供了一种存储结构的擦除方法，用于对存储块B 1…B n执行擦除操作，n为大于或等于2的整数，包括：
所述存储块按照编号顺次交替设置在第一存储体及第二存储体中；
控制所述存储块以设定的擦除方式按照编号顺次进行擦除操作；
其中，所述擦除操作包括顺次执行第一过程和第二过程，所述擦除方式包括：存储块B i在执行第二过程时，存储块B i+1在执行第一过程，其中，i∈[1，n-1]。
可选的，所述存储结构的擦除方法用于对所述存储结构进行整体擦除。
在本发明提供的存储结构及其擦除方法中，能够对存储块B 1…B n执行擦除操作，n为大于或等于2的整数，所述存储结构包括第一存储体、第二存储体及控制器，所述存储块按照编号顺次交替设置在所述第一存储体和所述第二存储 体中，所述控制器用于控制所述存储块以设定的擦除方式按照编号顺次进行擦除操作，所述擦除操作包括顺次执行第一过程和第二过程；所述擦除方式包括：存储块B i在执行第二过程时，存储块B i+1在执行第一过程，其中，i∈[1，n-1]。本发明中的相邻两个存储块同步进行第一过程和第二过程，从而节约了存储结构整体擦除的擦除时间，提高了擦除的效率，并且不需要额外的电路，可以在不增加成本的情况下实施。
附图说明
图1为一种存储结构的结构示意图；
图2为图1中的存储结构的擦除方法的具体流程图；
图3为本发明实施例一提供的存储结构的结构示意图；
图4为本发明实施例一提供的存储结构的擦除方法的具体流程图；
图5为本发明实施例二提供的存储结构的擦除方法的具体流程图；
其中，附图标记为：
100-存储结构；110-芯片控制器；Bank0-第一存储体；Bank1-第二存储体；
200-存储结构；210-芯片控制器；220-第一存储体控制器；230-第二存储体控制器；Bank2-第一存储体；Bank3-第二存储体。
具体实施方式
图1为一种存储结构100的结构示意图。如图1所示，所述存储结构100包括两个存储体，分别为第一存储体Bank0和第二存储体Bank1，所述第一存储体Bank0和所述第二存储体Bank1都耦合至芯片控制器110，所述芯片控制器110用于控制所述第一存储体Bank0和所述第二存储体Bank1执行诸如读取，写入和擦除的操作。所述第一存储体Bank0和所述第二存储体Bank1中总共存储有n(n≥2)个存储块，n个存储块在所述第一存储体Bank0和所述第二存储体Bank1之间平均分配，并且所述第一存储体Bank0和所述第二存储体Bank1中的存储块是顺序排列的。为了便于描述，对n个存储块按顺序编号为：B 1,B 2,…,B n，其中，
Figure PCTCN2019125965-appb-000001
设置在所述第一存储体Bank0中，
Figure PCTCN2019125965-appb-000002
设置在所 述第二存储体Bank1中。
图2为所述存储结构100进行整体擦除的流程图。如图2所示，对所述存储结构100进行整体擦除时，是B 1,B 2,…,B n的顺序顺次执行擦除操作的。具体为：首先对B 1执行预编程步骤(Pre program)，然后对存储块B 1执行擦除步骤(Erase)，接着对B 1执行过擦除修复步骤(OEC)，三个步骤结束后，B 1完成擦除(Erase Done)。接下来，对存储块B 2顺次执行预编程步骤、擦除步骤和过擦除修复步骤，以完成对存储块B 2的擦除。然后依次往下执行，直至最后一个存储块B n完成擦除，所述存储结构100完成了整体擦除。
这种存储结构100的擦除方法对于每个存储块单独重复三个步骤，上一个存储块完成擦除操作后才对下一个存储块进行擦除操作，由于所述存储结构100中的存储块通常很多(例如n＝256)，完成存储结构100的整体擦除需要非常多的时间，擦除效率低。
下面将结合示意图对本发明的具体实施方式进行更详细的描述。根据下列描述，本发明的优点和特征将更清楚。需说明的是，附图均采用非常简化的形式且均使用非精准的比例，仅用以方便、明晰地辅助说明本发明实施例的目的。存储块、存储体的编号是为了便于对技术方案进行说明而进行设置，并不意味着必须对存储块、存储体设置相应的编号，也不意味着必须按照本专利的编号方式进行编号本方案才能实施。
【实施例一】
基于此，图3为本实施例提供的存储结构的结构示意图。如图3所示，所述存储结构200例如是Nor闪存(Nor Flash)，其包括至少两个存储体，分别为第一存储体Bank2和第二存储体Bank3，所述第一存储体Bank2和所述第二存储体Bank3中总共存储有n(n≥2)个存储块，n个存储块在所述第一存储体Bank2和所述第二存储体Bank3之间平均分配，所述存储块按照编号顺次交替设置在所述第一存储体Bank2和所述第二存储体Bank3中。为了便于描述，对n个存储块按顺序编号为：B 1,B 2,…,B n，本实施例中，n为偶数。这样一来，编号为奇数的存储块B 1,B 3,…,B n-1设置在所述第一存储体Bank2中，编号为偶数的存储块B 2,B 4,…,B n设置在所述第二存储体Bank3中，此时所述第一存储体Bank2和所述第二存储体Bank3中存储的存储块的数量是相同的。
当然，当n为奇数时，所述第一存储体Bank2中存储的存储块比所述第二 存储体Bank3中存储的存储块多一个，但这并不影响本发明的实施。
进一步，所述存储结构200还包括控制器，所述控制器包括芯片控制器210、第一存储体控制器220及第二存储体控制器230。所述第一存储体控制器220连接并控制所述第一存储体Bank2，所述第二存储体控制器230连接并控制所述第二存储体Bank3，所述芯片控制器210耦合至所述第一存储体控制器220和所述第二存储体控制器230，用于控制所述第一存储体Bank2和所述第二存储体Bank3执行诸如读取，写入和擦除等操作。由于第一存储体Bank2和所述第二存储体Bank3的地址和偏置条件(需要在源极、漏极或栅极施加的电压)不同，本实施例采用所述芯片控制器210整体控制所述第一存储体控制器220和所述第二存储体控制器230，而所述第一存储体控制器220和所述第二存储体控制器230分别控制第一存储体Bank2和所述第二存储体Bank3，所以可以通过所述芯片控制器210同时操作所述第一存储体Bank2和所述第二存储体Bank3中的存储块。
应理解，根据现有的集成电路设计和制造技术，可以将第一存储体控制器220、所述第二存储体控制器230以及芯片控制器210集成为同一个控制单元，或模块化2个、4个等多个控制单元，这对本领域技术人员而言均是能够做到的，本实施例是提供了一种较优的解决方案。
本实施例还提供了所述存储结构200的擦除方法，用于对所述存储结构200进行整体擦除。具体的，首先将所述存储块按照编号顺次交替设置在第一存储体Bank2和第二存储体Bank3中。当所述存储结构200需要整体擦除时，所述控制器控制存储块B 1,B 2,…,B n以设定的擦除方式按照编号顺次进行擦除操作，每个所述存储块均需要顺次执行第一过程和第二过程才算是完成了擦除操作。所述擦除方式包括：存储块B i在执行第二过程时，存储块B i+1在执行第一过程，其中，i∈[1，n-1]。也就是说，对于编号相邻的两个存储块，存储块B i执行第二过程和存储块B i+1执行第一过程是同步进行的，当存储块B i完成第二过程且存储块B i+1完成第一过程之后，存储块B i完成擦除；存储块B i+1执行第二过程，同时存储块B i+1执行第一过程…，这样以流水线的方式继续下去，直至存储块B n完成擦除，所述存储结构200完成整体擦除。
本实施例中，所述第一过程包括预编程步骤(Pre program)，所述第二过程包括擦除步骤(Erase)和过擦除修复步骤(OEC)。所以存储块B i执行第二过 程时，实际上是顺次执行了擦除步骤(Erase)和过擦除修复步骤(OEC)两个步骤；而存储块B i+1执行第一过程，实际上只执行了预编程步骤(Pre program)一个步骤。
图4为本实施例提供的所述存储结构200的擦除方法的具体流程图。接下来将结合图3和图4对本实施例提供的存储结构200的擦除方法作详细的描述。
如图4所示，首先存储块B 1执行预编程步骤；存储块B 1完成预编程步骤之后，存储块B 1顺次执行擦除步骤和过擦除修复步骤，同时存储块B 2执行预编程步骤；当存储块B 1完成擦除步骤和过擦除修复步骤并且存储块B 2完成预编程步骤之后，存储块B 1完成擦除(B 1 Erase Done)。接下来，存储块B 2顺次执行擦除步骤和过擦除修复步骤，同时存储块B 3执行预编程步骤；当存储块B 2完成擦除步骤和过擦除修复步骤并且存储块B 3完成预编程步骤之后，存储块B 2完成擦除(B 2 Erase Done)…。然后依次往下执行，直至存储块B n-1完成擦除步骤和过擦除修复步骤且存储块B n完成预编程步骤之后，存储块B n-1完成擦除(B n-1 Erase Done)，此时存储块B n需要单独顺次执行擦除步骤和过擦除修复步骤。当B n完成擦除步骤和过擦除修复步骤之后，B n完成擦除(B n Erase Done)，所述存储结构200完成了整体擦除。
图2提供的存储结构的擦除方法需要每个存储块单独完成擦除操作后再进行下一个存储块的擦除操作，而本实施例中，由于每个存储块B i执行第二过程和存储块B i+1执行第一过程同步进行，可以节约擦除的时间，提高了擦除效率。
为了证明本实施例提供的存储结构的擦除方法提高了擦除效率，做如下假设和计算：
假设n＝256，预编程步骤的时间t 1＝50ms，擦除步骤的时间t 2＝80ms，过擦除修复步骤的时间t 3＝20ms；
采用图2提供的存储结构的擦除方法擦除整个存储结构需要的时间T 1为：
T 1＝(50ms+80ms+20ms)*256＝38.4s
采用图4提供的存储结构的擦除方法擦除整个存储结构需要的时间T 2为：
T 2＝50ms+(80ms+20ms)*256＝25.65s
可见，相较于图2提供的存储结构的擦除方法来说，本实施例提供的存储结构的擦除方法可以提高约33.2％的擦除效率。
【实施例二】
与实施例一不同的是，本实施例中，所述第一过程包括预编程步骤和擦除步骤，所述第二过程包括过擦除修复步骤。所以存储块B i执行第二过程时，实际上只执行了过擦除修复步骤一个步骤；而存储块B i+1执行第一过程，实际上是顺次只执行了预编程步骤和擦除步骤这两个步骤。
图5为本实施例提供的所述存储结构200的擦除方法的具体流程图。接下来将结合图3和图5对本实施例提供的存储结构200的擦除方法作详细的描述。
如图5所示，首先存储块B 1顺次执行预编程步骤和擦除步骤；存储块B 1完成预编程步骤和擦除步骤之后，存储块B 1执行过擦除修复步骤，同时存储块B 2顺次执行预编程步骤和擦除步骤；当存储块B 1完成过擦除修复步骤并且存储块B 2完成预编程步骤和擦除步骤之后，存储块B 1完成擦除(B 1 Erase Done)。接下来，存储块B 2执行过擦除修复步骤，同时存储块B 3执行预编程步骤和擦除步骤；当存储块B 2完成过擦除修复步骤并且存储块B 3完成预编程步骤和擦除步骤之后，存储块B 2完成擦除(B 2 Erase Done)…。然后依次往下执行，直至存储块B n-1完成过擦除修复步骤且存储块B n完成预编程步骤和擦除步骤之后，存储块B n-1完成擦除(B n-1 Erase Done)，此时存储块B n需要单独执行过擦除修复步骤。当B n完成过擦除修复步骤之后，B n完成擦除(B n Erase Done)，所述存储结构200完成了整体擦除。
为了证明本实施例提供的存储结构的擦除方法提高了擦除效率，做与实施例一相同的假设和计算：
假设n＝256，预编程步骤的时间t 1＝50ms，擦除步骤的时间t 2＝80ms，过擦除修复步骤的时间t 3＝20ms；
采用图5提供的存储结构的擦除方法擦除整个存储结构需要的时间T 2为：
T 2＝(50ms+80ms)*256+20ms＝33.3s
可见，相较于图2提供的存储结构的擦除方法来说，本实施例提供的存储结构的擦除方法可以提高约13.3％的擦除效率。
在实施例一和二中所计算的擦除节约时间均为参考值。闪存根据制作工艺的不同，操作模式的不同，预编程时间、擦除时间以及过擦除修复时间均会有所变化，因此可以知晓的是，实施例二所节省的擦除时间并不一定比实施例一 低。
并且，在实施例一和二中存储体的数量也不限于2个，可以为M个，M优选为2的倍数，当M不为2的倍数时也可对其中多数存储体实施本专利的方案。
综上，在本发明实施例提供的存储结构及其擦除方法中，能够对存储块B 1…B n执行擦除操作，n为大于或等于2的整数，所述存储结构包括第一存储体、第二存储体及控制器，所述存储块按照编号顺次交替设置在所述第一存储体和所述第二存储体中，所述控制器用于控制所述存储块以设定的擦除方式按照编号顺次进行擦除操作，所述擦除操作包括顺次执行第一过程和第二过程；所述擦除方式包括：存储块B i在执行第二过程时，存储块B i+1在执行第一过程，其中，i∈[1，n-1]。本发明中的相邻两个存储块同步进行第一过程和第二过程，从而节约了存储结构整体擦除的擦除时间，提高了擦除的效率，并且不需要额外的电路，可以在不增加成本的情况下实施。
上述仅为本发明的优选实施例而已，并不对本发明起到任何限制作用。任何所属技术领域的技术人员，在不脱离本发明的技术方案的范围内，对本发明揭露的技术方案和技术内容做任何形式的等同替换或修改等变动，均属未脱离本发明的技术方案的内容，仍属于本发明的保护范围之内。

Claims (10)

  1. 一种存储结构，能够对存储块B 1…B n执行擦除操作，n为大于或等于2的整数，其特征在于，包括：第一存储体、第二存储体及控制器，所述存储块按照编号顺次交替设置在所述第一存储体和所述第二存储体中，所述控制器用于控制所述存储块以设定的擦除方式按照编号顺次进行擦除操作，所述擦除操作包括顺次执行第一过程和第二过程；
    所述擦除方式包括：存储块B i在执行第二过程时，存储块B i+1在执行第一过程，其中，i∈[1，n-1]。
  2. 如权利要求1所述的存储结构，其特征在于，存储块B 1完成第一过程之后，存储块B 1执行第二过程，同时存储块B 2执行第一过程；之后依次对其余存储块执行所述擦除方式，存储块B i完成第二过程且存储块B i+1完成第一过程之后，存储块B i+1再执行第二过程；直至，存储块B n执行完第一过程之后，单独执行第二过程。
  3. 如权利要求1或2所述的存储结构，其特征在于，所述第一过程包括预编程步骤和擦除步骤，所述第二过程包括过擦除修复步骤。
  4. 如权利要求1或2所述的存储结构，其特征在于，所述第一擦除步骤包括预编程步骤，所述第二过程包括擦除步骤和过擦除修复步骤。
  5. 如权利要求1或2所述的存储结构，其特征在于，所述第一存储体及所述第二存储体中的存储块的数量相同或不相同。
  6. 如权利要求1或2所述的存储结构，其特征在于，所述存储结构包括M个存储体，其中，M≥2。
  7. 如权利要求1所述的存储结构，其特征在于，所述控制器包括：
    第一存储体控制器，连接并控制所述第一存储体；
    第二存储体控制器，连接并控制所述第二存储体；
    芯片控制器，连接所述第一存储体控制器和所述第二存储体控制器，并能够同步操作所述第一存储体控制器和所述第二存储体控制器中的存储块。
  8. 如权利要求1或7所述的存储结构，其特征在于，所述存储结构为Nor闪存。
  9. 一种存储结构的擦除方法，用于对存储块B 1…B n执行擦除操作，n为大 于或等于2的整数，其特征在于，包括：
    所述存储块按照编号顺次交替设置在第一存储体及第二存储体中；
    控制所述存储块以设定的擦除方式按照编号顺次进行擦除操作；
    其中，所述擦除操作包括顺次执行第一过程和第二过程，所述擦除方式包括：存储块B i在执行第二过程时，存储块B i+1在执行第一过程，其中，i∈[1，n-1]。
  10. 如权利要求9所述的存储结构的擦除方法，其特征在于，所述存储结构的擦除方法用于对所述存储结构进行整体擦除。
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