WO2021109242A1 - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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Publication number
WO2021109242A1
WO2021109242A1 PCT/CN2019/125961 CN2019125961W WO2021109242A1 WO 2021109242 A1 WO2021109242 A1 WO 2021109242A1 CN 2019125961 W CN2019125961 W CN 2019125961W WO 2021109242 A1 WO2021109242 A1 WO 2021109242A1
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Prior art keywords
layer
substrate
trench
trench filling
opening
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PCT/CN2019/125961
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English (en)
French (fr)
Inventor
杨帆
胡胜
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武汉新芯集成电路制造有限公司
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Priority to US16/976,829 priority Critical patent/US11791367B2/en
Publication of WO2021109242A1 publication Critical patent/WO2021109242A1/zh
Priority to US18/364,921 priority patent/US20230378232A1/en
Priority to US18/365,759 priority patent/US20230378233A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14603—Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/1463—Pixel isolation structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14632—Wafer-level processed structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/1464—Back illuminated imager structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14643—Photodiode arrays; MOS imagers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
    • H01L27/14685—Process for coatings or optical elements

Definitions

  • the present invention relates to the field of semiconductor integrated circuit manufacturing, in particular to a semiconductor device and a manufacturing method thereof.
  • CMOS Imaging Sensor BSI-CIS
  • DTI Deep Trench Isolation
  • BSI-CIS Backside Metal Grid
  • the purpose of the present invention is to provide a semiconductor device and a manufacturing method thereof, so that the metal grid layer is electrically connected to the exposed part of the substrate and/or the trench filling structure, thereby enabling the semiconductor device to be electrically connected. Optimization and improvement in performance.
  • the present invention provides a method for manufacturing a semiconductor device, including:
  • the buffer dielectric layer is etched to form a first opening that exposes at least a part of the substrate around the top sidewall of the trench filling structure and/or at least a part of the top of the trench filling structure ;as well as,
  • a metal grid layer is formed on the buffer dielectric layer, and the metal grid layer fills the first opening so as to be electrically connected to the exposed portion of the substrate and/or the trench filling structure.
  • the step of forming the trench filling structure in the substrate of the pixel region includes:
  • a first patterned photoresist layer is formed on the pad oxide layer, and the pad oxide layer and at least part of the thickness of the substrate are processed using the first patterned photoresist layer as a mask. Etching to form a trench in the substrate of the pixel area;
  • filling material also covers the isolation oxide layer on the periphery of the trench;
  • An etching or chemical mechanical polishing process is used to remove the filling material, the isolation oxide layer and the pad oxide layer on the surface of the substrate covering the periphery of the trench to form a trench filling structure in the trench.
  • the filling material includes a first conductive metal layer
  • the situation where the first opening at least exposes a part of the top of the trench filling structure includes: the first opening surrounds the top of the trench filling structure The sidewalls are opened to expose the first conductive metal layer on the top sidewall of the trench-filled structure, and/or the first opening is located on the top surface of the trench-filled structure to expose the Part or all of the top surface of the first conductive metal layer of the trench filling structure.
  • the step of etching the buffer dielectric layer to form the first opening includes:
  • a second patterned photoresist layer is formed on the buffer medium layer, and the buffer medium layer is etched using the second patterned photoresist layer as a mask to etch the buffer medium layer in the pixel area.
  • the first opening is formed in the buffer medium layer of, and the first opening exposes at least a part of the substrate surrounding the top sidewall of the trench-filled structure and/or at least a part of the top of the trench-filled structure; and ,
  • the second patterned photoresist layer is removed.
  • the step of forming the metal grid layer on the buffer medium layer includes:
  • a third patterned photoresist layer is formed on the second conductive metal layer, and the second conductive metal layer is etched by using the third patterned photoresist layer as a mask.
  • the pixel area forms a metal grid layer, and the metal grid layer is electrically connected to the portion of the substrate exposed by the first opening and/or the trench filling structure; and,
  • the third patterned photoresist layer is removed.
  • the substrate further has a pad area located at the periphery of the pixel area, and a metal interconnection structure and a plug structure located above the metal interconnection structure are formed in the substrate of the pad area, The bottom of the plug structure is electrically connected to the metal interconnection structure.
  • the trench filling structure when the trench filling structure includes the first conductive metal layer filled in the trenches of the pixel region, the trench filling structure is formed in the substrate of the pixel region while simultaneously forming the trench filling structure in the substrate of the pixel region.
  • the plug structure is in the substrate of the pad area.
  • the buffer medium layer is also covered on the substrate surface of the pad area, so that the buffer medium layer
  • the plug structure is buried; while the buffer dielectric layer on the pixel area is etched to form the first opening, the buffer dielectric layer on the pad area is also etched , To form a second opening that exposes the top surface of the portion of the plug structure; and, while forming the metal grid layer on the buffer medium layer of the pixel area, A pad structure is also formed on the buffer dielectric layer of the pad area, and the pad structure fills the second opening to be electrically connected to the exposed top of the plug structure.
  • the present invention also provides a semiconductor device, including:
  • the substrate has a pixel area
  • the buffer medium layer is formed on the surface of the substrate of the pixel area, the buffer medium layer has a first opening, and the first opening exposes at least a part of the substrate and the periphery of the top sidewall of the trench filling structure /Or at least part of the top of the trench filling structure;
  • a metal grid layer is formed on the buffer dielectric layer, and the metal grid layer fills the first opening to be electrically connected to the exposed portion of the substrate and/or the trench filling structure.
  • the trench filling structure includes an isolation oxide layer covering the surface of the trench in the substrate and a filling material filled in the trench, and the isolation oxide layer is at least located in the filling material. Between the sidewall of the material and the substrate.
  • the filling material includes a first conductive metal layer
  • the situation where the first opening at least exposes a part of the top of the trench filling structure includes: the first opening surrounds the top of the trench filling structure The sidewalls are opened to expose the first conductive metal layer on the top sidewall of the trench-filled structure, and/or the first opening is located on the top surface of the trench-filled structure to expose the Part or all of the top surface of the first conductive metal layer of the trench filling structure.
  • the substrate further has a pad area located at the periphery of the pixel area, and a metal interconnection structure and a plug structure located above the metal interconnection structure are formed in the substrate of the pad area, The bottom of the plug structure is electrically connected to the metal interconnection structure.
  • the plug structure when the trench filling structure includes a first conductive metal layer filled in the trenches of the pixel region, includes: located on a part of the top surface where the metal interconnection structure is exposed An isolation oxide layer on the sidewall of the via hole, and a first conductive metal layer filling the via hole.
  • the buffer dielectric layer is further formed on the surface of the substrate of the pad area, and the buffer dielectric layer has a second opening exposing the top surface of the part of the plug structure;
  • a pad structure is also formed on the buffer dielectric layer of the disk area, and the pad structure fills the second opening to be electrically connected with the exposed plug structure.
  • the manufacturing method of the semiconductor device of the present invention is to form a trench filling structure in the substrate of the pixel area; cover the buffer dielectric layer on the surface of the substrate of the pixel area, and the buffer dielectric layer connects the groove
  • the trench filling structure is buried; the buffer dielectric layer is etched to form a first opening that exposes at least a part of the substrate and/or the trench around the top sidewall of the trench filling structure At least part of the top of the trench filling structure; and forming a metal grid layer on the buffer medium layer, the metal grid layer filling the first opening, so that the metal grid layer and the exposed Part of the substrate and/or the trench filling structure are electrically connected, thereby enabling the optimization and improvement of the electrical performance of the semiconductor device.
  • the semiconductor device of the present invention includes: a trench filling structure formed in the substrate of the pixel region; a buffer dielectric layer formed on the surface of the substrate of the pixel region, the buffer dielectric layer having a first opening , The first opening exposes at least a part of the substrate at the periphery of the top sidewall of the trench filling structure and/or at least a part of the top of the trench filling structure; and, the metal formed on the buffer dielectric layer
  • the metal grid layer fills the first opening, so that the metal grid layer is electrically connected to the exposed part of the substrate and/or the trench filling structure, thereby enabling the semiconductor
  • the device is optimized and improved in terms of electrical performance.
  • 1a to 1j are schematic diagrams of a semiconductor device during the manufacturing process
  • FIG. 2 is a flowchart of a method of manufacturing a semiconductor device according to an embodiment of the present invention
  • 3a to 3i are schematic diagrams of the device of Embodiment 1 in the manufacturing method of the semiconductor device shown in FIG. 2;
  • FIG. 4a to 4e are schematic diagrams of the device of the second embodiment in the manufacturing method of the semiconductor device shown in FIG. 2;
  • 5a to 5e are schematic diagrams of the device in the third embodiment of the manufacturing method of the semiconductor device shown in FIG. 2;
  • FIG. 6 is a schematic diagram of a device of Embodiment 4 in the method of manufacturing a semiconductor device shown in FIG. 2;
  • FIG. 7a to 7i are schematic diagrams of the device of Embodiment 5 in the manufacturing method of the semiconductor device shown in FIG. 2;
  • a manufacturing process of the metal grid layer in the pixel area and the pad structure in the pad area is as follows:
  • a substrate 10 having a pixel area 11 and a pad area 12 is provided, and a metal interconnect structure 121 is formed in the pad area 12;
  • a pad oxide layer 13 is formed on the substrate 10
  • a first patterned photoresist layer 14 is formed on the pad oxide layer 13, and the first patterned The photoresist layer 14 is a mask.
  • the pad oxide layer 13 on the pixel region 11 and the substrate 10 at least part of the thickness are etched to form a trench 111 in the pixel region 11 to remove all The first patterned photoresist layer 14;
  • a first isolation oxide layer 1121 is formed on the surface of the trench 111 and the surface of the substrate 10, and a conductive metal layer 1122 is filled in the trench 111, and the conductive metal layer 1122 covers the substrate 10.
  • a chemical mechanical polishing process can be used to remove the conductive metal layer 1122, the first isolation oxide layer 1121, and the pad oxide layer 13 covering the substrate 10, so as to A trench filling structure 112 is formed in the trench 111;
  • a buffer dielectric layer 15 and a metal grid film layer 161 are sequentially formed to cover the substrate 10;
  • a second patterned photoresist layer 17 is formed on the metal grid film layer 161, and the second patterned photoresist layer 17 is used as a mask.
  • the metal grid film layer 161 is etched to form a metal grid layer 16 on the buffer medium layer 15 of the pixel area 11, and the second patterned photoresist layer 17 is removed, wherein the pixel area
  • the metal grid layer 16 on 11 is correspondingly located above the trench filling structure 112;
  • a dielectric layer 18 is formed on the buffer dielectric layer 15, and the dielectric layer 18 bury the metal grid layer 16;
  • a groove 122 is formed in the substrate 10 above the metal interconnect structure 121 of the pad area 12;
  • a second isolation oxide layer 123 is formed on the surface of the groove 122, and the second isolation oxide layer 123 burys the dielectric layer 18; and at the bottom of the groove 122 Forming an opening 124 that exposes part of the top surface of the metal interconnect structure 121;
  • the opening 124 and the groove 122 are filled with metal material, and the metal material in the groove 122 is etched so that the bottom of the groove 122 and the groove 122 are etched.
  • a pad structure 125 is formed in the opening 124, and the bottom of the pad structure 125 is electrically connected to the metal interconnection structure 121.
  • the present invention provides a semiconductor device and a manufacturing method thereof, which can make electrical connection between the metal grid layer and the underlying substrate and/or trench filling structure, thereby enabling the electrical performance of the semiconductor device. Optimization and improvement.
  • FIG. 2 is a flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present invention.
  • the method for manufacturing a semiconductor device includes:
  • Step S11 providing a substrate with a pixel area
  • Step S12 forming a trench filling structure in the substrate of the pixel area
  • Step S13 covering a buffer dielectric layer on the substrate surface of the pixel area, and the buffer dielectric layer burying the trench filling structure;
  • Step S14 The buffer dielectric layer is etched to form a first opening that exposes at least a part of the substrate around the top sidewall of the trench filling structure and/or the trench filling structure At least part of the top
  • Step S15 A metal grid layer is formed on the buffer medium layer, and the metal grid layer fills the first opening so as to be electrically connected to the exposed part of the substrate and/or the trench filling structure. connection.
  • FIGS. 3a to 7i are also schematic longitudinal cross-sectional views of the semiconductor device.
  • a substrate 20 having a pixel region 21 is provided.
  • the material of the substrate 20 can be any suitable substrate known to those skilled in the art, for example, it can be at least one of the following materials: silicon (Si), germanium (Ge), silicon germanium (SiGe) ), silicon carbon (SiC), silicon germanium carbon (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP) or other III/V compound semiconductors.
  • a trench filling structure 212 is formed in the substrate 20 of the pixel region 21.
  • the step of forming the trench filling structure 212 in the substrate 20 of the pixel region 21 includes: first, as shown in FIG. 3a, a pad oxide layer 23 is covered on the surface of the substrate 20 of the pixel region 21, and The pad oxide layer 23 is used to protect the surface of the substrate 20 when the first patterned photoresist layer 24 is formed by subsequent photolithography; then, as shown in FIG. 3a and FIG. 3b, a first patterned photoresist layer 24 is formed. The photoresist layer 24 is on the pad oxide layer 23.
  • the pad oxide layer 23 and at least a part of the thickness of the substrate 20 are processed Etch to form a trench 211 in the substrate 20 of the pixel region 21; then, as shown in FIG. 3b, remove the first patterned photoresist layer 24; then, an isolation oxide layer 2121 is formed on On the surface of the trench 211 and the pad oxide layer 23, the isolation oxide layer 2121 in the trench 211 may be located only on the sidewall of the trench 211, or both may be located on the surface of the trench 211.
  • the trench 211 may be a deep trench with a depth of 1 ⁇ m to 5 ⁇ m. It should be noted that the depth of the trench 211 is not limited to this depth range, and a suitable depth may be formed according to the performance requirements of the semiconductor device. ⁇ 211 ⁇ Groove 211.
  • the filling material may include a dielectric material or a metal material, or both a dielectric material and a metal material; when the filling material is a metal material, as shown in FIG. 3c, the trench filling structure 212 includes The isolation oxide layer 2121 on the surface of the trench 211 and the first conductive metal layer 2122 filling the trench 211 (that is, the filling material is the first conductive metal layer 2122).
  • the dielectric material may include at least one of silicon dioxide, silicon nitride, tetraethyl orthosilicate, borosilicate glass, phosphosilicate glass, borophosphosilicate glass, and silicon oxynitride, and the metal material may include tungsten, At least one of nickel, aluminum, silver, gold, and titanium.
  • top surface of the trench filling structure 212 may be flush with the top surface of the substrate 20, or the top surface of the trench filling structure 212 may be higher than the top surface of the substrate 20, or, Only the top surface of the filling material in the trench filling structure 212 is higher than the top surface of the substrate 20.
  • a buffer dielectric layer 25 is covered on the surface of the substrate 20 of the pixel region 21, and the buffer dielectric layer 25 bury the trench filling structure 212 inside.
  • the material of the buffer medium layer 25 may include at least one of silicon dioxide, silicon nitride, tetraethyl orthosilicate, borosilicate glass, phosphosilicate glass, borophosphosilicate glass, and silicon oxynitride.
  • the buffer dielectric layer 25 is etched to form a first opening.
  • the first opening exposes at least a portion of the substrate 20 at the periphery of the top sidewall of the trench filling structure 212 or at least a portion of the top of the trench filling structure 212, or at least exposes the trench filling structure A portion of the substrate 20 at the periphery of the top sidewall of 212 and at least a portion of the top of the trench filling structure 212.
  • the first opening exposes at least a portion of the substrate 20 at the periphery of the top sidewall of the trench filling structure 212, that is, the first opening is disposed at least around the top periphery of the trench filling structure 212 , To expose at least a portion of the substrate 20 surrounding the top periphery of the trench filling structure 212.
  • the situation where the first opening exposes at least part of the top of the trench filling structure 212 includes: when the top surface of the trench filling structure 212 is higher than the top surface of the substrate 20, the first opening It may be opened only around the top sidewall of the trench filling structure 212 to expose the isolation oxide layer 2121 on the top sidewall of the trench filling structure 212. At this time, the first opening also exposes the isolation oxide layer 2121 on the top sidewall of the trench filling structure 212.
  • the first opening may Only open around the top sidewall of the trench filling structure 212 to expose the filling material on the top sidewall of the trench filling structure 212; when the top surface of the trench filling structure 212 is higher than or equal to
  • the first opening may also be located on the top surface of the trench filling structure 212 to expose part or all of the top surface of the trench filling structure 212, including exposing The filling material and/or part or all of the top surface of the isolation oxide layer 2121; when the top surface of the trench filling structure 212 is higher than the top surface of the substrate 20, the first opening is also The isolation oxide layer 2121 or the filling material on the top sidewall of the trench filling structure 212 and a part or all of the top surface of the trench filling structure 212 can be exposed
  • the situation where the first opening exposes at least a part of the top of the trench filling structure 212 includes: the first opening surrounds the trench filling structure 212 The top sidewall is opened to expose the first conductive metal layer 2122 on the top sidewall of the trench filling structure 212; or, the first opening is located on the top surface of the trench filling structure 212 to expose Part or all of the top surface of the first conductive metal layer 2122 of the trench filling structure 212; or, the first opening simultaneously exposes the first conductive metal on the top sidewall of the trench filling structure 212 Part or all of the top surface of the first conductive metal layer 2122 of the layer 2122 and the trench filling structure 212.
  • the step of forming the first opening 2131 may include: forming a second patterned photoresist layer 261 on the buffer dielectric layer 25 (as shown in FIG. 3e), so that the second The patterned photoresist layer 261 is a mask, and the buffer medium layer 25 is etched to form the first opening 2131 in the buffer medium layer 25 of the pixel region 21, and the first opening 2131 A portion of the substrate 20 at the periphery of the top sidewall of the trench filling structure 212 and the entire top surface of the trench filling structure 212 are exposed, as shown in FIG. 3f.
  • the step of forming the first opening 2132 may include: forming a second patterned photoresist layer 262 on the buffer dielectric layer 25 (as shown in FIG. 4a), so as to The second patterned photoresist layer 262 is a mask, and the buffer dielectric layer 25 is etched to form the first opening 2132 in the buffer dielectric layer 25 of the pixel region 21.
  • the opening 2132 exposes part of the top surface of the trench filling structure 212, for example, the top surface of the part of the filling material, as shown in FIG. 4b, the filling material is the first conductive metal layer 2122, Then, the first opening 2132 exposes the top surface of the portion of the first conductive metal layer 2122 of the trench filling structure 212.
  • the step of forming the first opening 2133 may include: forming a second patterned photoresist layer 263 on the buffer dielectric layer 25 (as shown in FIG. 5a), so that the The second patterned photoresist layer 263 is a mask, and the buffer dielectric layer 25 is etched to form the first opening 2133 in the buffer dielectric layer 25 of the pixel area 21, as shown in FIG. 5b As shown, the first opening 2133 exposes a portion of the substrate 20 around the top sidewall of the trench filling structure 212.
  • the second patterned photoresist layer is removed.
  • a metal grid layer is formed on the buffer dielectric layer 25, and the metal grid layer fills the first opening, It is electrically connected to the exposed part of the substrate 20 or the trench filling structure 212, or is electrically connected to the exposed part of the substrate 20 and the trench filling structure 212 at the same time. Since the metal grid layer can be electrically connected to the exposed portion of the substrate 20 and/or the trench filling structure 212, the electrical performance of the semiconductor device can be optimized and improved, such as optimization and improvement. Dark current of semiconductor devices.
  • the metal grid layer is only electrically connected to the exposed part of the substrate 20; when the first opening at least exposes the groove
  • the corresponding situation that the metal grid layer is electrically connected to the underlying structure includes: when the top surface of the trench filling structure 212 is high On the top surface of the substrate 20, and the first opening is only opened around the top sidewall of the trench filling structure 212 (that is, the isolation oxide layer 2121 on the top sidewall is exposed), then the metal grid The layer is also only electrically connected to the exposed part of the substrate 20; when only the top surface of the filling material in the trench filling structure 212 is higher than the top surface of the substrate 20, and the first opening It is opened only around the top sidewall of the trench filling structure 212.
  • the filling material is the first conductive metal layer 2122, the metal grid layer and the top sidewall of the trench filling structure 212
  • the first conductive metal layer 2122 is electrically connected; when the top surface of the trench filling structure 212 is higher than or equal to the top surface of the substrate 20, and the first opening is located in the filling of the trench filling structure 212
  • the top surface is electrically connected; when the top surface of the trench filling structure 212 is higher than the top surface of the substrate 20, and the first opening simultaneously exposes the top sidewall of the trench filling structure 212
  • the metal grid layer is simultaneously connected to the part of the substrate 20 and the first conductive metal.
  • the layer 2122 is electrically connected.
  • the method of forming the metal grid layer on the buffer medium layer 25 may be include:
  • the step of forming the metal grid layer 214 on the buffer dielectric layer 25 includes: first, as shown in FIG. 3g, a second conductive metal layer 27 is formed to cover the buffer dielectric layer 25 , And the second conductive metal layer 27 fills the first opening 2131; then, a third patterned photoresist layer 281 is formed on the second conductive metal layer 27 (as shown in FIG. 3h) Using the third patterned photoresist layer 281 as a mask, the second conductive metal layer 27 is etched to form a metal grid layer 214 in the pixel area 21 (as shown in FIG. 3i ), the metal grid layer 214 and the part of the substrate 20 at the periphery of the top sidewall of the trench filling structure 212 exposed by the first opening 2131 and the entire top surface of the trench filling structure 212 are electrically connected Sexual connection.
  • the step of forming the metal grid layer 215 on the buffer medium layer 25 includes: first, as shown in FIG. 4c, a second conductive metal layer 27 is formed to cover the buffer medium layer 25, and the second conductive metal layer 27 fills the first opening 2132; then, a third patterned photoresist layer 282 is formed on the second conductive metal layer 27 (as shown in FIG. 4d) (Shown), using the third patterned photoresist layer 282 as a mask, the second conductive metal layer 27 is etched to form a metal grid layer 215 in the pixel area 21 (as shown in FIG. 4e (Shown), the metal grid layer 215 is electrically connected to the top surface of the portion of the first conductive metal layer 2122 of the trench filling structure 212 exposed by the first opening 2132.
  • the step of forming the metal grid layer 216 on the buffer medium layer 25 includes: first, as shown in FIG. 5c, a second conductive metal layer 27 is formed to cover the buffer medium layer 25, and the second conductive metal layer 27 fills the first opening 2133; then, a third patterned photoresist layer 283 is formed on the second conductive metal layer 27 (as shown in FIG. 5d) (Shown), using the third patterned photoresist layer 283 as a mask to etch the second conductive metal layer 27 to form a metal grid layer 216 in the pixel area 21 (as shown in FIG. 5e (Shown), the metal grid layer 216 is electrically connected to a portion of the substrate 20 on the periphery of the top sidewall of the trench filling structure 212 exposed by the first opening 2133.
  • the material of the second conductive metal layer 27 may include at least one of nickel, aluminum, silver, gold, titanium, and copper.
  • the metal grid layer 217 may also be in contact with a portion of the substrate 20 and the trench filling structure on the periphery of the top sidewall of the trench filling structure 212 exposed by the first opening.
  • the top surface of the portion of the first conductive metal layer 2122 of 212 is electrically connected.
  • the substrate further has a pad area located at the periphery of the pixel area, and a metal interconnect structure and a plug structure located above the metal interconnect structure are formed in the substrate of the pad area.
  • the bottom of the plug structure is electrically connected with the metal interconnection structure, and the top of the plug structure is also electrically connected with a pad structure.
  • other metal structures other than the metal interconnection structure may also be formed in the substrate of the pad area, and the bottom of the plug structure is electrically connected to the metal structure; for example,
  • the metal structure may be a conductive contact plug, and the bottom of the plug structure is electrically connected to the conductive contact plug.
  • the metal structure is a metal interconnection structure.
  • the filling material in the trench filling structure is a dielectric material
  • the plug structure since the plug structure has a metal material, the trench filling structure in the pixel area and the plug structure in the pad area need to be manufactured separately
  • the filling material in the trench filling structure is a metal material
  • the plug structure since the plug structure has a metal material, the trench filling structure in the pixel area and the plug structure in the pad area can be They can be made separately or at the same time.
  • the metal material in the plug structure is different from the first conductive metal layer in the trench filling structure Another conductive metal layer; when the trench filling structure in the pixel area and the plug structure in the pad area are fabricated at the same time, the metal material in the plug structure is also the first in the trench filling structure A conductive metal layer.
  • the other isolation oxide layer in the plug structure is only located where the metal is exposed. Part of the top surface of the interconnect structure is on the sidewall of the through hole.
  • the other isolation oxide layer in the plug structure is the same as the isolation oxide layer in the trench filling structure, and only the isolation oxide layer is provided on the sidewall of the trench of the pixel region, the The trench filling structure in the pixel area and the plug structure in the pad area can be fabricated at the same time; when another isolation oxide layer in the plug structure is the same as the isolation oxide layer in the trench filling structure, When both the sidewall and bottom wall of the trench in the pixel area have the isolation oxide layer, the trench filling structure in the pixel area and the plug structure in the pad area can be fabricated at the same time, but an additional step is required The other isolation oxide layer on the bottom wall of the through hole is removed; when the material of the other isolation oxide layer in the plug structure and the isolation oxide layer in the trench filling structure
  • the metal grid layer of the pixel area and the pad structure of the pad area can also be fabricated at the same time.
  • the metal grid layer of the pixel area and the pad structure of the pad area are successively in different processes.
  • the process is complicated, the process integration is low, and the process cost is higher. Therefore, if the trench filling structure and the metal grid layer of the pixel area are fabricated at the same time as the plug structure and the pad structure of the pad area, the complexity of the process can be reduced, the integration of the process can be improved, and the production can be reduced. cost.
  • a substrate 20 having a pixel area 21 and a pad area 22 is provided, and the pad area 22 is located at the periphery of the pixel area 21.
  • a metal interconnect structure 221 is formed in the substrate 20 of the pad area 22.
  • a trench filling structure 212 is formed in the substrate 20 of the pixel region 21 and the plug structure 223 is formed in the substrate 20 of the pad region 22 at the same time.
  • the forming steps include: first, as shown in FIG. 7a, a pad oxide layer 23 is covered on the surface of the substrate 20 of the pixel area 21 and the pad area 22, and the pad oxide layer 23 is used to form a first pattern in subsequent photolithography. When the photoresist layer 24 is formed, the surface of the substrate 20 is protected; then, as shown in FIGS.
  • a first patterned photoresist layer 24 is formed on the pad oxide layer 23 .
  • the pad oxide layer 23 and at least a part of the thickness of the substrate 20 are etched so that the substrate 20 of the pixel region 21 A trench 211 is formed in and a through hole 222 is formed in the substrate 20 of the pad region 22.
  • the through hole 222 exposes a portion of the top surface of the metal interconnect structure 221, and the depth of the trench 211 is The depth is the same as that of the through hole 222; then, as shown in FIG.
  • the first patterned photoresist layer 24 is removed; then, an isolation oxide layer is formed on the trench 211, the through hole 222 and the On the surface of the pad oxide layer 23 (in order to facilitate the description of the subsequent steps, the isolation oxide layer in the trench 211 is an isolation oxide layer 2121, and the isolation oxide layer in the via 222 is an isolation oxide layer 2231, Different filling patterns are also used for identification in FIG. 7c), wherein the isolation oxide layer 2121 in the trench 211 may be located only on the sidewall of the trench 211, or both may be located on the sidewall of the trench 211.
  • the isolation oxide layer 2231 in the through hole 222 is only located on the side wall of the through hole 222; then, the trench 211 and the through hole 222 are filled with a first conductive metal layer (In order to facilitate the description of the subsequent steps, the first conductive metal layer in the trench 211 is the first conductive metal layer 2122, and the first conductive metal layer in the through hole 222 is the first conductive metal layer 2232, In FIG.
  • the first conductive metal layer also covers the isolation oxide layer on the periphery of the trench 211 and the through hole 222; then, etching is used Or the chemical mechanical polishing process removes the first conductive metal layer, the isolation oxide layer and the pad oxide layer 23 on the surface of the substrate 20 covering the periphery of the trench 211 and the through hole 222, so as to be in the trench
  • a trench filling structure 212 is formed in the groove 211 and a plug structure 223 is formed in the through hole 222, and the bottom of the first conductive metal layer 2232 in the plug structure 223 is electrically connected to the metal interconnection structure 221 , As shown in Figure 7c.
  • a buffer dielectric layer 25 is covered on the surface of the substrate 20 of the pixel region 21 and the pad region 22, and the buffer dielectric layer 25 covers the trench filling structure 212 and the plug Structure 223 is buried inside.
  • the buffer medium layer 25 is etched to form a first opening 2131 in the buffer medium layer 25 of the pixel region 21 and the buffer medium layer 25 in the pad region 22
  • a second opening 224 is formed in the first opening 2131, and the first opening 2131 exposes a portion of the substrate 20 at the periphery of the top sidewall of the trench filling structure 212 and the entire top surface of the trench filling structure 212, and the second The opening 224 exposes the top surface of the part of the plug structure 223.
  • the step of forming the first opening 2131 and the second opening 224 may include: forming a second patterned photoresist layer 261 on the buffer medium layer 25 (as shown in FIG.
  • the second patterned photoresist layer 261 is a mask, and the buffer medium layer 25 is etched to form the first opening 2131 in the buffer medium layer 25 of the pixel area 21 and the pad
  • a second opening 224 is formed in the buffer medium layer 25 of the region 22.
  • the first opening 2131 exposes a portion of the substrate 20 and the trench around the top sidewall of the trench filling structure 212 The entire top surface of the structure 212 is filled, and the second opening 224 exposes part or all of the top surface of the first conductive metal layer 2232 of the plug structure 223.
  • a metal grid layer 214 is formed on the buffer dielectric layer 25 of the pixel region 21 and a pad structure 225 is formed on the buffer dielectric layer 25 of the pad region 22 at the same time ,
  • the metal grid layer 214 fills the first opening 2131 to be electrically connected to the exposed portion of the substrate 20 and the trench filling structure 212; the pad structure 225 fills the
  • the second opening 224 is electrically connected to the exposed top of the plug structure 223.
  • the steps of simultaneously forming the metal grid layer 214 on the buffer medium layer 25 of the pixel area 21 and forming the pad structure 225 on the buffer medium layer 25 of the pad area 22 include: First, as shown in the figure As shown in 7g, a second conductive metal layer 27 is formed to cover the buffer dielectric layer 25, and the second conductive metal layer 27 fills the first opening 2131 and the second opening 224; then, forming The third patterned photoresist layer 281 is on the second conductive metal layer 27 (as shown in FIG. 7h).
  • the second The conductive metal layer 27 is etched to form a metal grid layer 214 in the pixel area 21 and a pad structure 225 in the pad area 22 (as shown in FIG. 7i).
  • the metal grid layer 214 and The portion of the substrate 20 at the periphery of the top sidewall of the trench filling structure 212 exposed by the first opening 2131 is electrically connected to the entire top surface of the trench filling structure 212, and the pad structure 225 is electrically connected to the entire top surface of the trench filling structure 212.
  • the exposed top surface of part or all of the first conductive metal layer 2232 of the plug structure 223 is electrically connected.
  • the various steps in the above-mentioned semiconductor device manufacturing method are not limited to the above-mentioned formation sequence, and the sequence of the various steps can be adjusted adaptively.
  • the method for manufacturing a semiconductor device includes: providing a substrate with a pixel area; forming a trench filling structure in the substrate of the pixel area; covering a buffer medium layer in the pixel area On the surface of the substrate, and the buffer dielectric layer burying the trench filling structure; etching the buffer dielectric layer to form a first opening, the first opening at least exposes the trench filling structure A part of the substrate at the periphery of the top sidewall of the structure and/or at least a part of the top of the trench filling structure; and forming a metal grid layer on the buffer dielectric layer, the metal grid layer filling the first The opening is electrically connected to the exposed part of the substrate and/or the trench filling structure.
  • the manufacturing method of the semiconductor device of the present invention enables the metal grid layer to be electrically connected to the exposed part of the substrate and/or the trench filling structure, thereby enabling the optimization and improvement of the electrical performance of the semiconductor device.
  • An embodiment of the present invention provides a semiconductor device.
  • the semiconductor device includes a substrate, a trench filling structure, a buffer dielectric layer, and a metal grid layer.
  • the substrate has a pixel area; the trench filling structure is formed in In the substrate of the pixel area; the buffer medium layer is formed on the surface of the substrate of the pixel area, the buffer medium layer has a first opening, and the first opening at least exposes the trench filling structure Part of the substrate at the periphery of the top sidewall and/or at least part of the top of the trench filling structure; the metal grid layer is formed on the buffer dielectric layer, and the metal grid layer fills the first opening , To be electrically connected to the exposed part of the substrate and/or the trench filling structure.
  • the substrate 20 has a pixel area 21.
  • the material of the substrate 20 can be any suitable substrate known to those skilled in the art. For details, refer to step S11, which will not be repeated here.
  • the trench filling structure 212 is formed in the substrate 20 of the pixel region 21.
  • the trench filling structure 212 includes an isolation oxide layer 2121 covering the surface of the trench 211 in the substrate 20 and a filling material filled in the trench 211.
  • the isolation oxide layer 2121 is at least located on the surface of the trench 211. Between the sidewall of the filling material and the substrate 20, that is, the isolation oxide layer 2121 may be located only on the sidewall of the trench 211, or both may be located on the sidewall and bottom wall of the trench 211 on.
  • the trench 211 may be a deep trench with a depth of 1 ⁇ m to 5 ⁇ m. It should be noted that the depth of the trench 211 is not limited to this depth range, and a suitable depth may be formed according to the performance requirements of the semiconductor device. ⁇ 211 ⁇ Groove 211.
  • the filling material may include a dielectric material or a metal material, or both a dielectric material and a metal material; when the filling material is a metal material, the trench filling structure 212 includes a surface formed on the trench 211 The isolation oxide layer 2121 and the first conductive metal layer 2122 filling the trench 211 (that is, the filling material is the first conductive metal layer 2122).
  • the dielectric material may include at least one of silicon dioxide, silicon nitride, tetraethyl orthosilicate, borosilicate glass, phosphosilicate glass, borophosphosilicate glass, and silicon oxynitride
  • the metal material may include tungsten, At least one of nickel, aluminum, silver, gold, and titanium.
  • top surface of the trench filling structure 212 may be flush with the top surface of the substrate 20, or the top surface of the trench filling structure 212 may be higher than the top surface of the substrate 20, or, Only the top surface of the filling material in the trench filling structure 212 is higher than the top surface of the substrate 20.
  • the buffer medium layer 25 is formed on the surface of the substrate 20 of the pixel region 21, the buffer medium layer 25 has a first opening, and the first opening exposes at least the top sidewall of the trench filling structure 212 A portion of the substrate 20 on the periphery or a portion of the top of the trench-filled structure 212, or at least a portion of the substrate 20 and a portion of the trench-filled structure 212 around the top sidewall of the trench-filled structure 212 are exposed top.
  • the material of the buffer medium layer 25 may include at least one of silicon dioxide, silicon nitride, tetraethyl orthosilicate, borosilicate glass, phosphosilicate glass, borophosphosilicate glass, and silicon oxynitride.
  • the first opening exposes at least a part of the substrate 20 around the top sidewall of the trench filling structure 212, that is, the first opening is disposed at least around the top periphery of the trench filling structure 212, At least a portion of the substrate 20 surrounding the top periphery of the trench filling structure 212 is exposed.
  • the situation where the first opening exposes at least part of the top of the trench filling structure 212 includes: when the top surface of the trench filling structure 212 is higher than the top surface of the substrate 20, the first opening It is opened around the top sidewall of the trench filling structure 212 to expose the isolation oxide layer 2121 on the top sidewall of the trench filling structure 212.
  • the first opening also exposes the trench Part of the substrate 20 at the periphery of the top sidewall of the filling structure 212; when only the top surface of the filling material in the trench filling structure 212 is higher than the top surface of the substrate 20, the first opening surrounds the The top sidewall of the trench filling structure 212 is opened to expose the filling material on the top sidewall of the trench filling structure 212; when the top surface of the trench filling structure 212 is higher than or equal to the substrate 20
  • the first opening may also be located on the top surface of the trench filling structure 212 to expose part or all of the top surface of the trench filling structure 212, including exposing the filling material And/or part or all of the top surface of the isolation oxide layer 2121; when the top surface of the trench filling structure 212 is higher than the top surface of the substrate 20, the first opening may also be exposed at the same time
  • the situation where the first opening exposes at least a part of the top of the trench filling structure 212 includes: the first opening surrounds the trench filling structure 212 The top sidewall is opened to expose the first conductive metal layer 2122 on the top sidewall of the trench filling structure 212; or, the first opening is located on the top surface of the trench filling structure 212 to expose Part or all of the top surface of the first conductive metal layer 2122 of the trench filling structure 212; or, the first opening simultaneously exposes the first conductive metal on the top sidewall of the trench filling structure 212 Part or all of the top surface of the first conductive metal layer 2122 of the layer 2122 and the trench filling structure 212.
  • the metal grid layer is formed on the buffer dielectric layer 25, and the metal grid layer fills the first opening so as to be electrically connected to the exposed portion of the substrate 20 or the trench filling structure 212. Or electrically connected to the exposed portion of the substrate 20 and the trench filling structure 212 at the same time. Since the metal grid layer can be electrically connected to the exposed portion of the substrate 20 and/or the trench filling structure 212, the electrical performance of the semiconductor device can be optimized and improved, such as optimization and improvement. Dark current of semiconductor devices.
  • the metal grid layer is only electrically connected to the exposed part of the substrate 20; when the first opening at least exposes the groove When filling a part of the top of the trench filling structure 212, according to the different situations listed above, the corresponding situation where the metal grid layer is electrically connected to the underlying structure includes: when the top surface of the trench filling structure 212 is higher than all When the top surface of the substrate 20 and the first opening is opened around the top sidewall of the trench filling structure 212 (that is, the isolation oxide layer 2121 on the top sidewall is exposed), the metal gate The grid layer is also only electrically connected to the exposed part of the substrate 20; when only the top surface of the filling material in the trench filling structure 212 is higher than the top surface of the substrate 20, and the first The opening is opened around the top sidewall of the trench filling structure 212.
  • the filling material is the first conductive metal layer 2122, the metal grid layer and the top sidewall of the trench filling structure 212
  • the first conductive metal layer 2122 is electrically connected; when the top surface of the trench filling structure 212 is higher than or equal to the top surface of the substrate 20, and the first opening is located in the filling of the trench filling structure 212
  • the top surface is electrically connected; when the top surface of the trench filling structure 212 is higher than the top surface of the substrate 20, and the first opening simultaneously exposes the top sidewall of the trench filling structure 212
  • the metal grid layer is simultaneously connected to the part of the substrate 20 and the first conductive metal.
  • the layer 2122 is electrically connected.
  • the metal grid layer 214 is electrically connected to the The part of the substrate 20 on the periphery of the top sidewall of the trench filling structure 212 exposed by the first opening is electrically connected to the entire top surface of the trench filling structure 212; as shown in FIG. 4e, the metal gate The grid layer 215 is electrically connected to the top surface of the portion of the first conductive metal layer 2122 of the trench filling structure 212 exposed by the first opening; as shown in FIG.
  • the metal grid layer 216 is electrically connected to the Part of the substrate 20 on the periphery of the top sidewall of the trench filling structure 212 exposed by the first opening is electrically connected; as shown in FIG. 6, the metal grid layer 217 is exposed to the first opening.
  • a portion of the substrate 20 on the periphery of the top sidewall of the trench-filled structure 212 and the top surface of a portion of the first conductive metal layer 2122 of the trench-filled structure 212 are electrically connected.
  • the substrate further has a pad area located at the periphery of the pixel area, and a metal interconnect structure and a plug structure located above the metal interconnect structure are formed in the substrate of the pad area.
  • the bottom of the plug structure is electrically connected with the metal interconnection structure, and the top of the plug structure is also electrically connected with a pad structure.
  • other metal structures other than the metal interconnection structure may also be formed in the substrate of the pad area, and the bottom of the plug structure is electrically connected to the metal structure; for example,
  • the metal structure may be a conductive contact plug, and the bottom of the plug structure is electrically connected to the conductive contact plug.
  • the metal structure is a metal interconnection structure.
  • the filling material in the trench filling structure is a dielectric material
  • the plug structure since the plug structure has a metal material, the trench filling structure in the pixel area and the plug structure in the pad area need to be manufactured separately
  • the filling material in the trench filling structure is a metal material
  • the plug structure since the plug structure has a metal material, the trench filling structure in the pixel area and the plug structure in the pad area can be They can be made separately or at the same time.
  • the metal material in the plug structure is different from the first conductive metal layer in the trench filling structure Another conductive metal layer; when the trench filling structure in the pixel area and the plug structure in the pad area are fabricated at the same time, the metal material in the plug structure is also the first in the trench filling structure A conductive metal layer.
  • the other isolation oxide layer in the plug structure is only located where the metal is exposed. Part of the top surface of the interconnect structure is on the sidewall of the through hole.
  • the other isolation oxide layer in the plug structure is the same as the isolation oxide layer in the trench filling structure, and only the isolation oxide layer is provided on the sidewall of the trench of the pixel region, the The trench filling structure in the pixel area and the plug structure in the pad area can be fabricated at the same time; when another isolation oxide layer in the plug structure is the same as the isolation oxide layer in the trench filling structure, When both the sidewall and bottom wall of the trench in the pixel area have the isolation oxide layer, the trench filling structure in the pixel area and the plug structure in the pad area can be fabricated at the same time, but an additional step is required The other isolation oxide layer on the bottom wall of the through hole is removed; when the material of the other isolation oxide layer in the plug structure and the isolation oxide layer in the trench filling structure
  • the metal grid layer of the pixel area and the pad structure of the pad area can also be fabricated at the same time.
  • the metal grid layer of the pixel area and the pad structure of the pad area are successively in different processes.
  • the process is complicated, the process integration is low, and the process cost is higher. Therefore, if the trench filling structure and the metal grid layer of the pixel area are fabricated at the same time as the plug structure and the pad structure of the pad area, the complexity of the process can be reduced, the integration of the process can be improved, and the production can be reduced. cost.
  • the metal grid layer of the pixel area is electrically connected to the exposed part of the substrate and/or the trench filling structure, please refer to the above description, and will not be repeated here.
  • the portion of the substrate 20 and the outer periphery of the top sidewall of the trench filling structure 212 exposed by the metal grid layer 214 and the first opening 2131 and the trench filling structure 212 Take the case where all the top surfaces are electrically connected as an example.
  • the trench filling structure 212 and the metal grid layer 214 of the pixel area 21 and the plug structure 223 and the pad structure of the pad area 22 formed at the same time 225 to explain:
  • the plug structure 223 includes: The isolation oxide layer on the sidewall of the through hole 222 on a part of the top surface of the metal interconnect structure 221 is exposed, and the first conductive metal layer that fills the through hole 222 is exposed.
  • the isolation oxide layer on the surface of the trench 211 is an isolation oxide layer 2121
  • the isolation oxide layer on the surface of the via 222 is an isolation oxide layer 2231
  • the first conductive metal layer in the trench 211 is the first conductive metal layer.
  • a conductive metal layer 2122, the first conductive metal layer in the through hole 222 is the first conductive metal layer 2232, and different filling patterns are also used for identification in FIG. 7i.
  • the isolation oxide layer 2121 in the trench 211 may be located only on the sidewalls of the trench 211, or both may be located on the sidewalls and the bottom wall of the trench 211.
  • the isolation oxide layer 2231 is only located on the sidewall of the through hole 222; the bottom of the first conductive metal layer 2232 in the plug structure 223 is electrically connected to the metal interconnect structure 221.
  • the buffer medium layer 25 is formed on the surface of the substrate 20 of the pixel region 21 and the pad region 22, and a first opening 2131 is formed in the buffer medium layer 25 of the pixel region 21 and the solder
  • a second opening 224 is formed in the buffer medium layer 25 of the panel area 22, and the first opening 2131 exposes a portion of the substrate 20 on the periphery of the top sidewall of the trench filling structure 212 and the gap of the trench filling structure 212.
  • the second opening 224 may expose a portion of the top surface of the plug structure 223, and the second opening 224 may expose a portion or part of the first conductive metal layer 2232 of the plug structure 223. The entire top surface.
  • a metal grid layer 214 is formed on the buffer dielectric layer 25 of the pixel region 21, a pad structure 225 is formed on the buffer dielectric layer 25 of the pad region 22, and the metal grid layer 214 fills the first
  • An opening 2131 is electrically connected to the exposed part of the substrate 20 and the trench filling structure 212; the pad structure 225 fills the second opening 224 to be connected to the exposed portion of the substrate 20 and the trench filling structure 212.
  • the top of the bolt structure 223 is electrically connected.
  • the semiconductor device includes: a substrate having a pixel area; a trench filling structure formed in the substrate in the pixel area; a buffer dielectric layer formed in the substrate in the pixel area On the surface, the buffer medium layer has a first opening that exposes at least a part of the substrate around the top sidewall of the trench filling structure and/or at least a part of the top of the trench filling structure; And, a metal grid layer is formed on the buffer dielectric layer, and the metal grid layer fills the first opening so as to be electrically connected to the exposed portion of the substrate and/or the trench filling structure connection.
  • the semiconductor device of the present invention electrically connects the metal grid layer with the exposed part of the substrate and/or the trench filling structure, thereby enabling the optimization and improvement of the electrical performance of the semiconductor device.

Abstract

一种半导体器件及其制造方法，所述半导体器件的制造方法包括：(S12)形成沟槽填充结构于像素区的衬底中；(S13)覆盖缓冲介质层于所述像素区的衬底表面上，且所述缓冲介质层将所述沟槽填充结构掩埋在内；(S14)刻蚀所述缓冲介质层，以形成至少暴露出所述沟槽填充结构的顶部侧壁外围的部分衬底和/或所述沟槽填充结构的部分顶部的第一开口；(S15)形成金属栅格层于所述缓冲介质层上且填充所述第一开口，以与暴露出的所述部分衬底和/或所述沟槽填充结构的部分顶部电性连接。上述技术方案使得金属栅格层与暴露出的所述部分衬底和/或所述沟槽填充结构的部分顶部电性连接，进而使得能够对半导体器件进行电学性能方面的优化和改善。

Description

半导体器件及其制造方法 技术领域
本发明涉及半导体集成电路制造领域，特别涉及一种半导体器件及其制造方法。
背景技术
在背照式CMOS图像传感器(Back-side Illumination CMOS Imagination Sensor，简称BSI-CIS)的制作工艺中，深沟槽隔离(Deep Trench Isolation，简称DTI)技术和背面金属栅格(Backside Metal Grid，简称BMG)技术的配合使用能够使得背照式CMOS图像传感器具有更好的光学性能。
但是，在现有的制作背照式CMOS图像传感器的工艺过程中，制作的像素区的金属栅格与下方的衬底和深沟槽填充结构之间存在缓冲介质层，使得金属栅格与下方的衬底和深沟槽填充结构之间仅是物理连接，无法进行电性连接，从而导致无法对背照式CMOS图像传感器进行电学性能方面的优化和改善。
因此，如何对像素区的金属栅格的制作工艺进行改进，以使得金属栅格与下方的衬底和/或沟槽填充结构之间实现电性连接，进而使得能够对半导体器件进行电学性能方面的优化和改善是目前亟需解决的问题。
发明内容
本发明的目的在于提供一种半导体器件及其制造方法，使得金属栅格层与暴露出的所述部分衬底和/或所述沟槽填充结构电性连接，进而使得能够对半导体器件进行电学性能方面的优化和改善。
为实现上述目的，本发明提供了一种半导体器件的制造方法，包括：
提供一具有像素区的衬底；
形成沟槽填充结构于所述像素区的衬底中；
覆盖缓冲介质层于所述像素区的衬底表面上，且所述缓冲介质层将所述沟槽填充结构掩埋在内；
刻蚀所述缓冲介质层，以形成第一开口，所述第一开口至少暴露出所述沟 槽填充结构的顶部侧壁外围的部分衬底和/或所述沟槽填充结构的至少部分顶部；以及，
形成金属栅格层于所述缓冲介质层上，所述金属栅格层填充所述第一开口，以与暴露出的所述部分衬底和/或所述沟槽填充结构电性连接。
可选的，形成所述沟槽填充结构于所述像素区的衬底中的步骤包括：
覆盖垫氧化层于所述像素区的衬底表面；
形成第一图案化的光刻胶层于所述垫氧化层上，以所述第一图案化的光刻胶层为掩膜，对所述垫氧化层以及至少部分厚度的所述衬底进行刻蚀，以在所述像素区的衬底中形成沟槽；
去除所述第一图案化的光刻胶层；
形成隔离氧化层于所述沟槽和所述垫氧化层的表面上；
在所述沟槽中填满填充材料，且所述填充材料还覆盖在所述沟槽外围的所述隔离氧化层上；以及，
采用刻蚀或者化学机械研磨工艺去除覆盖于所述沟槽外围的所述衬底的表面上的填充材料、隔离氧化层和垫氧化层，以在所述沟槽中形成沟槽填充结构。
可选的，所述填充材料包括第一导电金属层，所述第一开口至少暴露出所述沟槽填充结构的部分顶部的情形包括：所述第一开口围绕所述沟槽填充结构的顶部侧壁开设，以暴露出所述沟槽填充结构的顶部侧壁上的第一导电金属层，和/或，所述第一开口位于所述沟槽填充结构的顶表面上，以暴露出所述沟槽填充结构的第一导电金属层的部分或全部的顶表面。
可选的，刻蚀所述缓冲介质层，以形成所述第一开口的步骤包括：
形成第二图案化的光刻胶层于所述缓冲介质层上，以所述第二图案化的光刻胶层为掩膜，对所述缓冲介质层进行刻蚀，以在所述像素区的缓冲介质层中形成所述第一开口，所述第一开口至少暴露出所述沟槽填充结构的顶部侧壁外围的部分衬底和/或所述沟槽填充结构的至少部分顶部；以及，
去除所述第二图案化的光刻胶层。
可选的，形成所述金属栅格层于所述缓冲介质层上的步骤包括：
形成第二导电金属层覆盖于所述缓冲介质层上，且所述第二导电金属层将所述第一开口填满；
形成第三图案化的光刻胶层于所述第二导电金属层上，以所述第三图案化 的光刻胶层为掩膜，对所述第二导电金属层进行刻蚀，以在所述像素区形成金属栅格层，所述金属栅格层与所述第一开口暴露出的所述部分衬底和/或所述沟槽填充结构电性连接；以及，
去除所述第三图案化的光刻胶层。
可选的，所述衬底还具有位于所述像素区外围的焊盘区，所述焊盘区的衬底中形成有金属互连结构以及位于所述金属互连结构上方的插栓结构，所述插栓结构的底部与所述金属互连结构电性连接。
可选的，当所述沟槽填充结构包括填充在所述像素区的沟槽中的第一导电金属层时，在形成沟槽填充结构于所述像素区的衬底中的同时，一道形成所述插栓结构于所述焊盘区的衬底中。
可选的，在覆盖所述缓冲介质层于所述像素区的衬底表面上的同时，还覆盖所述缓冲介质层于所述焊盘区的衬底表面上，以使得所述缓冲介质层将所述插栓结构掩埋在内；在刻蚀所述像素区上的所述缓冲介质层，以形成所述第一开口的同时，还刻蚀所述焊盘区上的所述缓冲介质层，以形成第二开口，所述第二开口暴露出所述插栓结构的部分的顶部表面；以及，在形成所述金属栅格层于所述像素区的所述缓冲介质层上的同时，还形成焊盘结构于所述焊盘区的所述缓冲介质层上，所述焊盘结构填满所述第二开口，以与暴露出的所述插栓结构的顶部电性连接。
本发明还提供了一种半导体器件，包括：
衬底，具有像素区；
沟槽填充结构，形成于所述像素区的衬底中；
缓冲介质层，形成于所述像素区的衬底表面上，所述缓冲介质层具有第一开口，所述第一开口至少暴露出所述沟槽填充结构的顶部侧壁外围的部分衬底和/或所述沟槽填充结构的至少部分顶部；以及，
金属栅格层，形成于所述缓冲介质层上，所述金属栅格层填充所述第一开口，以与暴露出的所述部分衬底和/或所述沟槽填充结构电性连接。
可选的，所述沟槽填充结构包括覆盖于所述衬底中的沟槽的表面上的隔离氧化层和填充于所述沟槽中的填充材料，所述隔离氧化层至少位于所述填充材料的侧壁和所述衬底之间。
可选的，所述填充材料包括第一导电金属层，所述第一开口至少暴露出所 述沟槽填充结构的部分顶部的情形包括：所述第一开口围绕所述沟槽填充结构的顶部侧壁开设，以暴露出所述沟槽填充结构的顶部侧壁上的第一导电金属层，和/或，所述第一开口位于所述沟槽填充结构的顶表面上，以暴露出所述沟槽填充结构的第一导电金属层的部分或全部的顶表面。
可选的，所述衬底还具有位于所述像素区外围的焊盘区，所述焊盘区的衬底中形成有金属互连结构以及位于所述金属互连结构上方的插栓结构，所述插栓结构的底部与所述金属互连结构电性连接。
可选的，当所述沟槽填充结构包括填充在所述像素区的沟槽中的第一导电金属层时，所述插栓结构包括：位于暴露出所述金属互连结构的部分顶表面的通孔的侧壁上的隔离氧化层，以及填满所述通孔的第一导电金属层。
可选的，所述缓冲介质层还形成于所述焊盘区的衬底表面上，且所述缓冲介质层具有暴露出所述插栓结构的部分的顶部表面的第二开口；所述焊盘区的缓冲介质层上还形成有焊盘结构，所述焊盘结构填满所述第二开口，以与暴露出的所述插栓结构电性连接。
与现有技术相比，本发明的技术方案具有以下有益效果：
1、本发明的半导体器件的制造方法，通过形成沟槽填充结构于像素区的衬底中；覆盖缓冲介质层于所述像素区的衬底表面上，且所述缓冲介质层将所述沟槽填充结构掩埋在内；刻蚀所述缓冲介质层，以形成第一开口，所述第一开口至少暴露出所述沟槽填充结构的顶部侧壁外围的部分衬底和/或所述沟槽填充结构的至少部分顶部；以及，形成金属栅格层于所述缓冲介质层上，所述金属栅格层填充所述第一开口，以使得所述金属栅格层与暴露出的所述部分衬底和/或所述沟槽填充结构电性连接，进而使得能够对半导体器件进行电学性能方面的优化和改善。
2、本发明的半导体器件，由于包括：形成于像素区的衬底中的沟槽填充结构；形成于所述像素区的衬底表面上的缓冲介质层，所述缓冲介质层具有第一开口，所述第一开口至少暴露出所述沟槽填充结构的顶部侧壁外围的部分衬底和/或所述沟槽填充结构的至少部分顶部；以及，形成于所述缓冲介质层上的金属栅格层，所述金属栅格层填充所述第一开口，以使得金属栅格层与暴露出的所述部分衬底和/或所述沟槽填充结构电性连接，进而使得能够对半导体器件进行电学性能方面的优化和改善。
附图说明
图1a～1j是一种半导体器件的制造过程中的器件示意图；
图2是本发明一实施例的半导体器件的制造方法的流程图；
图3a～3i是图2所示的半导体器件的制造方法中的实施例一的器件示意图；
图4a～4e是图2所示的半导体器件的制造方法中的实施例二的器件示意图；
图5a～5e是图2所示的半导体器件的制造方法中的实施例三的器件示意图；
图6是图2所示的半导体器件的制造方法中的实施例四的器件示意图；
图7a～7i是图2所示的半导体器件的制造方法中的实施例五的器件示意图；
其中，附图1a～7i的附图标记说明如下：
10-衬底；11-像素区；111-沟槽；112-沟槽填充结构；1121-第一隔离氧化层；1122-导电金属层；12-焊盘区；121-金属互连结构；122-凹槽；123-第二隔离氧化层；124-开口；125-焊盘结构；13-垫氧化层；14-第一图案化的光刻胶层；15-缓冲介质层；16-金属栅格层；161-金属栅格膜层；17-第二图案化的光刻胶层；18-介质层；
20-衬底；21-像素区；211-沟槽；212-沟槽填充结构；2121-隔离氧化层；2122-第一导电金属层；2131、2132、2133-第一开口；214、215、216、217-金属栅格层；22-焊盘区；221-金属互连结构；222-通孔；223-插栓结构；2231-隔离氧化层；2232-第一导电金属层；224-第二开口；225-焊盘结构；23-垫氧化层；24-第一图案化的光刻胶层；25-缓冲介质层；261、262、263-第二图案化的光刻胶层；27-第二导电金属层；281、282、283-第三图案化的光刻胶层。
具体实施方式
一种像素区的金属栅格层和焊盘区的焊盘结构的制作工艺如下：
如图1a所示，提供一具有像素区11和焊盘区12的衬底10，所述焊盘区12中形成有金属互连结构121；
如图1a和1b所示，在所述衬底10上形成一垫氧化层13，形成第一图案化的光刻胶层14于所述垫氧化层13上，以所述第一图案化的光刻胶层14为掩膜，对所述像素区11上的垫氧化层13和至少部分厚度的所述衬底10进行刻蚀，以在所述像素区11中形成沟槽111，去除所述第一图案化的光刻胶层14；
如图1c所示，形成第一隔离氧化层1121于所述沟槽111的表面和所述衬底 10的表面，并填充导电金属层1122于所述沟槽111中，且所述导电金属层1122覆盖于所述衬底10上，可以采用化学机械研磨工艺将覆盖于所述衬底10上的所述导电金属层1122、第一隔离氧化层1121和垫氧化层13去除，以在所述沟槽111中形成沟槽填充结构112；
如图1d所示，依次形成缓冲介质层15和金属栅格膜层161覆盖于所述衬底10上；
如图1e和1f所示，形成第二图案化的光刻胶层17于所述金属栅格膜层161上，以所述第二图案化的光刻胶层17为掩膜，对所述金属栅格膜层161进行刻蚀，以在所述像素区11的缓冲介质层15上形成金属栅格层16，去除所述第二图案化的光刻胶层17，其中，所述像素区11上的金属栅格层16对应地位于所述沟槽填充结构112的上方；
如图1g所示，形成介质层18于所述缓冲介质层15上，且所述介质层18将所述金属栅格层16掩埋在内；
如图1h所示，在所述焊盘区12的金属互连结构121的上方的衬底10中形成一凹槽122；
如图1i所示，在所述凹槽122的表面上形成第二隔离氧化层123，所述第二隔离氧化层123将所述介质层18掩埋在内；并在所述凹槽122的底部形成一开口124，所述开口124将所述金属互连结构121的部分顶表面暴露出来；
如图1j所示，填充金属材料于所述开口124中和所述凹槽122中，并对所述凹槽122中的金属材料进行刻蚀，以在所述凹槽122的底部和所述开口124中形成焊盘结构125，所述焊盘结构125的底部与所述金属互连结构121电性连接。
显然，由上述步骤可知，像素区的金属栅格层与下方的衬底和沟槽填充结构之间存在缓冲介质层，使得金属栅格层与下方的衬底和沟槽填充结构之间仅是物理连接，无法进行电性连接，从而导致无法对半导体器件进行电学性能方面的优化和改善。因此，本发明提出了一种半导体器件及其制造方法，能够使得金属栅格层与下方的衬底和/或沟槽填充结构之间实现电性连接，进而使得能够对半导体器件进行电学性能方面的优化和改善。
为使本发明的目的、优点和特征更加清楚，以下结合附图2～7i对本发明提出的半导体器件及其制造方法作进一步详细说明。需说明的是，附图均采用非 常简化的形式且均使用非精准的比例，仅用以方便、明晰地辅助说明本发明实施例的目的。
本发明一实施例提供一种半导体器件的制造方法，参阅图2，图2是本发明一实施例的半导体器件的制造方法的流程图，所述半导体器件的制造方法包括：
步骤S11、提供一具有像素区的衬底；
步骤S12、形成沟槽填充结构于所述像素区的衬底中；
步骤S13、覆盖缓冲介质层于所述像素区的衬底表面上，且所述缓冲介质层将所述沟槽填充结构掩埋在内；
步骤S14、刻蚀所述缓冲介质层，以形成第一开口，所述第一开口至少暴露出所述沟槽填充结构的顶部侧壁外围的部分衬底和/或所述沟槽填充结构的至少部分顶部；
步骤S15、形成金属栅格层于所述缓冲介质层上，所述金属栅格层填充所述第一开口，以与暴露出的所述部分衬底和/或所述沟槽填充结构电性连接。
下面参阅图3a～7i更为详细的介绍本实施例提供的半导体器件的制造方法，图3a～7i也是半导体器件的纵向截面示意图。
按照步骤S11，提供一具有像素区21的衬底20。所述衬底20的材质可以为本领域技术人员熟知的任意合适的底材，例如可以是以下所提到的材料中的至少一种：硅(Si)、锗(Ge)、锗硅(SiGe)、碳硅(SiC)、碳锗硅(SiGeC)、砷化铟(InAs)、砷化镓(GaAs)、磷化铟(InP)或者其它III/V化合物半导体。
参阅图3a～3c，按照步骤S12，形成沟槽填充结构212于所述像素区21的衬底20中。形成所述沟槽填充结构212于所述像素区21的衬底20中的步骤包括：首先，如图3a所示，覆盖垫氧化层23于所述像素区21的衬底20表面，所述垫氧化层23用于在后续光刻形成第一图案化的光刻胶层24时，对所述衬底20的表面进行保护；然后，如图3a和图3b所示，形成第一图案化的光刻胶层24于所述垫氧化层23上，以所述第一图案化的光刻胶层24为掩膜，对所述垫氧化层23以及至少部分厚度的所述衬底20进行刻蚀，以在所述像素区21的衬底20中形成沟槽211；接着，如图3b所示，去除所述第一图案化的光刻胶层24；接着，形成隔离氧化层2121于所述沟槽211和所述垫氧化层23的表面上，所述沟槽211中的隔离氧化层2121可以仅位于所述沟槽211的侧壁上，也可以 均位于所述沟槽211的侧壁和底壁上；接着，在所述沟槽211中填满填充材料，且所述填充材料还覆盖在所述沟槽211外围的所述隔离氧化层2121上；接着，采用刻蚀或者化学机械研磨工艺去除覆盖于所述沟槽211外围的所述衬底20的表面上的填充材料、隔离氧化层2121和垫氧化层23，以在所述沟槽211中形成沟槽填充结构212，如图3c所示。其中，所述沟槽211可以是深度为1μm～5μm的深沟槽，需要说明的是，所述沟槽211的深度不仅限于此深度范围，可以根据半导体器件的性能需求形成合适深度的所述沟槽211。
其中，所述填充材料可以包括介质材料或金属材料，或同时包括介质材料和金属材料；当所述填充材料为金属材料时，如图3c所示，所述沟槽填充结构212包括形成于所述沟槽211的表面的隔离氧化层2121和填满所述沟槽211的第一导电金属层2122(即所述填充材料为所述第一导电金属层2122)。所述介质材料可以包括二氧化硅、氮化硅、正硅酸乙酯、硼硅玻璃、磷硅玻璃、硼磷硅玻璃、氮氧硅中的至少一种，所述金属材料可以包括钨、镍、铝、银、金、钛中的至少一种。
另外，所述沟槽填充结构212的顶表面可以与所述衬底20的顶表面齐平，或者，所述沟槽填充结构212的顶表面高于所述衬底20的顶表面，或者，仅所述沟槽填充结构212中的填充材料的顶表面高于所述衬底20的顶表面。
参阅图3d，按照步骤S13，覆盖缓冲介质层25于所述像素区21的衬底20表面上，且所述缓冲介质层25将所述沟槽填充结构212掩埋在内。所述缓冲介质层25的材质可以包括二氧化硅、氮化硅、正硅酸乙酯、硼硅玻璃、磷硅玻璃、硼磷硅玻璃、氮氧硅中的至少一种。
参阅图3e～3f、图4a～4b以及图5a～5b，按照步骤S14，刻蚀所述缓冲介质层25，以形成第一开口。所述第一开口至少暴露出所述沟槽填充结构212的顶部侧壁外围的部分的衬底20或所述沟槽填充结构212的至少部分顶部，或者，至少暴露出所述沟槽填充结构212的顶部侧壁外围的部分的衬底20和所述沟槽填充结构212的至少部分顶部。
其中，所述第一开口至少暴露出所述沟槽填充结构212的顶部侧壁外围的部分的衬底20，即是指所述第一开口至少环绕所述沟槽填充结构212的顶部外围设置，以至少暴露出环绕所述沟槽填充结构212的顶部外围的部分的衬底20。
所述第一开口至少暴露出所述沟槽填充结构212的部分顶部的情形包括： 当所述沟槽填充结构212的顶表面高于所述衬底20的顶表面时，所述第一开口可以仅围绕所述沟槽填充结构212的顶部侧壁开设，以暴露出所述沟槽填充结构212的顶部侧壁上的隔离氧化层2121，此时，所述第一开口也暴露出所述沟槽填充结构212的顶部侧壁外围的部分衬底20；当仅所述沟槽填充结构212中的填充材料的顶表面高于所述衬底20的顶表面时，所述第一开口可以仅围绕所述沟槽填充结构212的顶部侧壁开设，以暴露出所述沟槽填充结构212的顶部侧壁上的填充材料；当所述沟槽填充结构212的顶表面高于或等于所述衬底20的顶表面时，所述第一开口也可以位于所述沟槽填充结构212的顶表面上，以暴露出所述沟槽填充结构212的部分或全部的顶表面，包括暴露出所述填充材料和/或所述隔离氧化层2121的部分或全部的顶表面；当所述沟槽填充结构212的顶表面高于所述衬底20的顶表面时，所述第一开口也可以同时暴露出所述沟槽填充结构212的顶部侧壁上的隔离氧化层2121或填充材料以及暴露出所述沟槽填充结构212的部分或全部的顶表面。
当所述填充材料包括第一导电金属层2122时，所述第一开口至少暴露出所述沟槽填充结构212的部分顶部的情形包括：所述第一开口围绕所述沟槽填充结构212的顶部侧壁开设，以暴露出所述沟槽填充结构212的顶部侧壁上的第一导电金属层2122；或者，所述第一开口位于所述沟槽填充结构212的顶表面上，以暴露出所述沟槽填充结构212的第一导电金属层2122的部分或全部的顶表面；或者，所述第一开口同时暴露出所述沟槽填充结构212的顶部侧壁上的第一导电金属层2122和所述沟槽填充结构212的第一导电金属层2122的部分或全部的顶表面。
对于上述的所述第一开口暴露出底部结构的不同情形，形成所述第一开口的不同方法举例如下：
参阅图3e～3f，形成所述第一开口2131的步骤可以包括：形成第二图案化的光刻胶层261于所述缓冲介质层25上(如图3e所示)，以所述第二图案化的光刻胶层261为掩膜，对所述缓冲介质层25进行刻蚀，以在所述像素区21的缓冲介质层25中形成所述第一开口2131，所述第一开口2131暴露出所述沟槽填充结构212的顶部侧壁外围的部分衬底20和所述沟槽填充结构212的全部的顶表面，如图3f所示。
或者，参阅图4a～4b，形成所述第一开口2132的步骤可以包括：形成第二 图案化的光刻胶层262于所述缓冲介质层25上(如图4a所示)，以所述第二图案化的光刻胶层262为掩膜，对所述缓冲介质层25进行刻蚀，以在所述像素区21的缓冲介质层25中形成所述第一开口2132，所述第一开口2132暴露出所述沟槽填充结构212的部分的顶表面，例如暴露出所述填充材料的部分的顶表面，如图4b所示，所述填充材料为所述第一导电金属层2122，则所述第一开口2132暴露出所述沟槽填充结构212的第一导电金属层2122的部分的顶表面。
或者，参阅图5a～5b，形成所述第一开口2133的步骤可以包括：形成第二图案化的光刻胶层263于所述缓冲介质层25上(如图5a所示)，以所述第二图案化的光刻胶层263为掩膜，对所述缓冲介质层25进行刻蚀，以在所述像素区21的缓冲介质层25中形成所述第一开口2133，如图5b所示，所述第一开口2133暴露出所述沟槽填充结构212的顶部侧壁外围的部分衬底20。
另外，形成所述第一开口之后，去除所述第二图案化的光刻胶层。
参阅图3g～3i、图4c～4e、图5c～5e以及图6，按照步骤S15，形成金属栅格层于所述缓冲介质层25上，所述金属栅格层填充所述第一开口，以与暴露出的所述部分衬底20或所述沟槽填充结构212电性连接，或者同时与暴露出的所述部分衬底20和所述沟槽填充结构212电性连接。由于所述金属栅格层能够与暴露出的所述部分衬底20和/或所述沟槽填充结构212电性连接，使得能够对半导体器件进行电学性能方面的优化和改善，例如优化和改善半导体器件的暗电流。
当所述第一开口仅暴露出所述部分衬底20时，所述金属栅格层仅与暴露出的所述部分衬底20电性连接；当所述第一开口至少暴露出所述沟槽填充结构212的部分顶部时，根据上述步骤S14中列出的情形，对应的所述金属栅格层与下方的结构电性连接的情形包括：当所述沟槽填充结构212的顶表面高于所述衬底20的顶表面，且所述第一开口仅围绕所述沟槽填充结构212的顶部侧壁开设(即暴露顶部侧壁上的隔离氧化层2121)，则所述金属栅格层也仅与暴露出的所述部分衬底20电性连接；当仅所述沟槽填充结构212中的填充材料的顶表面高于所述衬底20的顶表面，且所述第一开口仅围绕所述沟槽填充结构212的顶部侧壁开设，所述填充材料为所述第一导电金属层2122时，所述金属栅格层与所述沟槽填充结构212的顶部侧壁上的第一导电金属层2122电性连接；当所述沟槽填充结构212的顶表面高于或等于所述衬底20的顶表面，且所述第一开口位于所述沟槽填充结构212的填充材料的顶表面上，所述填充材料为所述第一导 电金属层2122时，所述金属栅格层与所述沟槽填充结构212的暴露出的部分或全部的第一导电金属层2122的顶表面电性连接；当所述沟槽填充结构212的顶表面高于所述衬底20的顶表面，且所述第一开口同时暴露出所述沟槽填充结构212的顶部侧壁上的隔离氧化层2121或第一导电金属层2122以及暴露出所述第一导电金属层2122的部分或全部的顶表面时，所述金属栅格层同时与所述部分衬底20和第一导电金属层2122电性连接。
根据步骤S14中的所述第一开口暴露出底部结构的不同情形，与形成所述第一开口的不同方法相对应的，形成所述金属栅格层于所述缓冲介质层25上的方法可以包括：
参阅图3g～3i，形成所述金属栅格层214于所述缓冲介质层25上的步骤包括：首先，如图3g所示，形成第二导电金属层27覆盖于所述缓冲介质层25上，且所述第二导电金属层27将所述第一开口2131填满；然后，形成第三图案化的光刻胶层281于所述第二导电金属层27上(如图3h所示)，以所述第三图案化的光刻胶层281为掩膜，对所述第二导电金属层27进行刻蚀，以在所述像素区21形成金属栅格层214(如图3i所示)，所述金属栅格层214与所述第一开口2131暴露出的所述沟槽填充结构212的顶部侧壁外围的部分衬底20和所述沟槽填充结构212的全部的顶表面电性连接。
或者，参阅图4c～4e，形成所述金属栅格层215于所述缓冲介质层25上的步骤包括：首先，如图4c所示，形成第二导电金属层27覆盖于所述缓冲介质层25上，且所述第二导电金属层27将所述第一开口2132填满；然后，形成第三图案化的光刻胶层282于所述第二导电金属层27上(如图4d所示)，以所述第三图案化的光刻胶层282为掩膜，对所述第二导电金属层27进行刻蚀，以在所述像素区21形成金属栅格层215(如图4e所示)，所述金属栅格层215与所述第一开口2132暴露出的所述沟槽填充结构212的第一导电金属层2122的部分的顶表面电性连接。
或者，参阅图5c～5e，形成所述金属栅格层216于所述缓冲介质层25上的步骤包括：首先，如图5c所示，形成第二导电金属层27覆盖于所述缓冲介质层25上，且所述第二导电金属层27将所述第一开口2133填满；然后，形成第三图案化的光刻胶层283于所述第二导电金属层27上(如图5d所示)，以所述第三图案化的光刻胶层283为掩膜，对所述第二导电金属层27进行刻蚀，以在 所述像素区21形成金属栅格层216(如图5e所示)，所述金属栅格层216与所述第一开口2133暴露出的所述沟槽填充结构212的顶部侧壁外围的部分衬底20电性连接。
另外，形成所述金属栅格层之后，去除所述第三图案化的光刻胶层。所述第二导电金属层27的材质可以包括镍、铝、银、金、钛、铜中的至少一种。
另外，如图6所示，所述金属栅格层217也可以与所述第一开口暴露出的所述沟槽填充结构212的顶部侧壁外围的部分衬底20以及所述沟槽填充结构212的第一导电金属层2122的部分的顶表面电性连接。
另外，所述衬底还具有位于所述像素区外围的焊盘区，所述焊盘区的衬底中形成有金属互连结构以及位于所述金属互连结构上方的插栓结构，所述插栓结构的底部与所述金属互连结构电性连接，所述插栓结构的顶部还电性连接有焊盘结构。需要说明的是，所述焊盘区的衬底中也可以形成有所述金属互连结构之外的其它的金属结构，所述插栓结构的底部与所述金属结构电性连接；例如，所述金属结构可以为导电接触插栓，所述插栓结构的底部与所述导电接触插栓电性连接。下面均以所述金属结构为金属互连结构进行说明。
当所述沟槽填充结构中的填充材料为介质材料时，由于所述插栓结构中具有金属材料，使得所述像素区的沟槽填充结构与所述焊盘区的插栓结构需要分开制作；当所述沟槽填充结构中的填充材料为金属材料时，由于所述插栓结构中具有金属材料，因此，所述像素区的沟槽填充结构与所述焊盘区的插栓结构可以分开制作，也可以同时制作。
当所述像素区的沟槽填充结构与所述焊盘区的插栓结构分开制作时，所述插栓结构中的金属材料是与所述沟槽填充结构中的第一导电金属层不同的另一导电金属层；当所述像素区的沟槽填充结构与所述焊盘区的插栓结构同时制作时，则所述插栓结构中的金属材料也是所述沟槽填充结构中的第一导电金属层。
由于所述插栓结构的底部与所述金属互连结构电性连接，那么，当所述插栓结构中具有另一隔离氧化层时，所述另一隔离氧化层仅位于暴露出所述金属互连结构的部分顶表面的通孔的侧壁上。当所述插栓结构中的另一隔离氧化层与所述沟槽填充结构中的隔离氧化层相同，且仅所述像素区的沟槽的侧壁上具有所述隔离氧化层时，所述像素区的沟槽填充结构与所述焊盘区的插栓结构可以同时制作；当所述插栓结构中的另一隔离氧化层与所述沟槽填充结构中的隔 离氧化层相同，但所述像素区的沟槽的侧壁和底壁上均具有所述隔离氧化层时，所述像素区的沟槽填充结构与所述焊盘区的插栓结构可以同时制作，只是需要增加一个步骤将所述通孔的底壁上的另一隔离氧化层去除；当所述插栓结构中的另一隔离氧化层与所述沟槽填充结构中的隔离氧化层的材质等不相同时，所述像素区的沟槽填充结构与所述焊盘区的插栓结构需要分开制作。
当所述像素区的沟槽填充结构与所述焊盘区的插栓结构能够同时制作时，所述像素区的金属栅格层和所述焊盘区的焊盘结构也能够同时制作。
根据图1a至图1j所示的像素区的金属栅格层和焊盘区的焊盘结构的制作工艺可知，像素区的金属栅格层和焊盘区的焊盘结构先后在不同的工艺中进行制作时，导致工艺复杂、工艺整合度低，进而导致工艺成本较高。因此，若所述像素区的沟槽填充结构和金属栅格层与所述焊盘区的插栓结构和焊盘结构同时制作，能够降低工艺的复杂度、提高工艺的整合度，进而降低生产成本。
下面参阅7a～7i对所述像素区的沟槽填充结构和金属栅格层与所述焊盘区的插栓结构和焊盘结构同时制作的步骤进行说明，其中，所述像素区的金属栅格层与暴露出的所述部分衬底和/或所述沟槽填充结构电性连接的不同情形参阅上述步骤S11至步骤S15，在此不再赘述。以图7a～7i中所示的所述金属栅格层214与所述第一开口2131暴露出的所述沟槽填充结构212的顶部侧壁外围的部分衬底20和所述沟槽填充结构212的全部的顶表面电性连接的情形为例，所述像素区21的沟槽填充结构212和金属栅格层214与所述焊盘区22的插栓结构223和焊盘结构225同时制作的步骤如下：
参阅图7a，按照步骤S21，提供一具有像素区21和焊盘区22的衬底20，所述焊盘区22位于所述像素区21的外围。所述焊盘区22的衬底20中形成有金属互连结构221。
参阅图7a～7c，按照步骤S22，同时形成沟槽填充结构212于所述像素区21的衬底20中以及形成所述插栓结构223于所述焊盘区22的衬底20中。形成步骤包括：首先，如图7a所示，覆盖垫氧化层23于所述像素区21和焊盘区22的衬底20表面，所述垫氧化层23用于在后续光刻形成第一图案化的光刻胶层24时，对所述衬底20的表面进行保护；然后，如图7a和图7b所示，形成第一图案化的光刻胶层24于所述垫氧化层23上，以所述第一图案化的光刻胶层24为掩膜，对所述垫氧化层23以及至少部分厚度的所述衬底20进行刻蚀，以在 所述像素区21的衬底20中形成沟槽211以及在所述焊盘区22的衬底20中形成通孔222，所述通孔222暴露出所述金属互连结构221的部分顶表面，且所述沟槽211的深度与所述通孔222的深度相同；接着，如图7b所示，去除所述第一图案化的光刻胶层24；接着，形成隔离氧化层于所述沟槽211、通孔222和所述垫氧化层23的表面上(为了便于对后续的步骤进行说明，所述沟槽211中的隔离氧化层为隔离氧化层2121，所述通孔222中的隔离氧化层为隔离氧化层2231，图7c中也采用了不同的填充图案进行标识)，其中，所述沟槽211中的隔离氧化层2121可以仅位于所述沟槽211的侧壁上，也可以均位于所述沟槽211的侧壁和底壁上，所述通孔222中的隔离氧化层2231仅位于所述通孔222的侧壁上；接着，在所述沟槽211和通孔222中填满第一导电金属层(为了便于对后续的步骤进行说明，所述沟槽211中的第一导电金属层为第一导电金属层2122，所述通孔222中的第一导电金属层为第一导电金属层2232，图7c中也采用了不同的填充图案进行标识)，且所述第一导电金属层还覆盖在所述沟槽211和所述通孔222外围的所述隔离氧化层上；接着，采用刻蚀或者化学机械研磨工艺去除覆盖于所述沟槽211和所述通孔222外围的所述衬底20的表面上的第一导电金属层、隔离氧化层和垫氧化层23，以在所述沟槽211中形成沟槽填充结构212以及在所述通孔222中形成插栓结构223，所述插栓结构223中的第一导电金属层2232的底部与所述金属互连结构221电性连接，如图7c所示。
参阅图7d，按照步骤S23，覆盖缓冲介质层25于所述像素区21和焊盘区22的衬底20的表面上，且所述缓冲介质层25将所述沟槽填充结构212和插栓结构223掩埋在内。
参阅图7e～7f，按照步骤S24，刻蚀所述缓冲介质层25，以在所述像素区21的缓冲介质层25中形成第一开口2131和在所述焊盘区22的缓冲介质层25中形成第二开口224，所述第一开口2131暴露出所述沟槽填充结构212的顶部侧壁外围的部分衬底20和所述沟槽填充结构212的全部的顶表面，所述第二开口224暴露出所述插栓结构223的部分的顶部表面。
形成所述第一开口2131和所述第二开口224的步骤可以包括：形成第二图案化的光刻胶层261于所述缓冲介质层25上(如图7e所示)，以所述第二图案化的光刻胶层261为掩膜，对所述缓冲介质层25进行刻蚀，以在所述像素区21的缓冲介质层25中形成所述第一开口2131以及在所述焊盘区22的缓冲介质层 25中形成第二开口224，如图7f所示，所述第一开口2131暴露出所述沟槽填充结构212的顶部侧壁外围的部分衬底20和所述沟槽填充结构212的全部的顶表面，所述第二开口224暴露出所述插栓结构223的第一导电金属层2232的部分或全部的顶部表面。
参阅图7g～7i，按照步骤S25，同时形成金属栅格层214于所述像素区21的缓冲介质层25上以及形成焊盘结构225于所述焊盘区22的所述缓冲介质层25上，所述金属栅格层214填满所述第一开口2131，以与暴露出的所述部分衬底20和所述沟槽填充结构212电性连接；所述焊盘结构225填满所述第二开口224，以与暴露出的所述插栓结构223的顶部电性连接。
同时形成所述金属栅格层214于所述像素区21的缓冲介质层25上以及形成焊盘结构225于所述焊盘区22的所述缓冲介质层25上的步骤包括：首先，如图7g所示，形成第二导电金属层27覆盖于所述缓冲介质层25上，且所述第二导电金属层27将所述第一开口2131以及所述第二开口224填满；然后，形成第三图案化的光刻胶层281于所述第二导电金属层27上(如图7h所示)，以所述第三图案化的光刻胶层281为掩膜，对所述第二导电金属层27进行刻蚀，以在所述像素区21形成金属栅格层214以及在所述焊盘区22形成焊盘结构225(如图7i所示)，所述金属栅格层214与所述第一开口2131暴露出的所述沟槽填充结构212的顶部侧壁外围的部分衬底20和所述沟槽填充结构212的全部的顶表面电性连接，所述焊盘结构225与暴露出的所述插栓结构223的第一导电金属层2232的部分或全部的顶部表面电性连接。
另外，上述的半导体器件的制造方法中的各个步骤不仅限于上述的形成顺序，各个步骤的先后顺序可适应性的进行调整。
综上所述，本发明提供的半导体器件的制造方法，包括：提供一具有像素区的衬底；形成沟槽填充结构于所述像素区的衬底中；覆盖缓冲介质层于所述像素区的衬底表面上，且所述缓冲介质层将所述沟槽填充结构掩埋在内；刻蚀所述缓冲介质层，以形成第一开口，所述第一开口至少暴露出所述沟槽填充结构的顶部侧壁外围的部分衬底和/或所述沟槽填充结构的至少部分顶部；以及，形成金属栅格层于所述缓冲介质层上，所述金属栅格层填充所述第一开口，以与暴露出的所述部分衬底和/或所述沟槽填充结构电性连接。本发明的半导体器件的制造方法使得金属栅格层与暴露出的所述部分衬底和/或所述沟槽填充结构 电性连接，进而使得能够对半导体器件进行电学性能方面的优化和改善。
本发明一实施例提供了一种半导体器件，所述半导体器件包括衬底、沟槽填充结构、缓冲介质层和金属栅格层，所述衬底具有像素区；所述沟槽填充结构形成于所述像素区的衬底中；所述缓冲介质层形成于所述像素区的衬底表面上，所述缓冲介质层具有第一开口，所述第一开口至少暴露出所述沟槽填充结构的顶部侧壁外围的部分衬底和/或所述沟槽填充结构的至少部分顶部；所述金属栅格层形成于所述缓冲介质层上，所述金属栅格层填充所述第一开口，以与暴露出的所述部分衬底和/或所述沟槽填充结构电性连接。
下面参阅图3i、图4e、图5e、图6、图7i详细描述本实施例提供的半导体器件：
所述衬底20具有像素区21。所述衬底20的材质可以为本领域技术人员熟知的任意合适的底材，具体参见步骤S11，在此不再赘述。
所述沟槽填充结构212形成于所述像素区21的衬底20中。所述沟槽填充结构212包括覆盖于所述衬底20中的沟槽211的表面上的隔离氧化层2121和填充于所述沟槽211中的填充材料，所述隔离氧化层2121至少位于所述填充材料的侧壁和所述衬底20之间，即所述隔离氧化层2121可以仅位于所述沟槽211的侧壁上，也可以均位于所述沟槽211的侧壁和底壁上。其中，所述沟槽211可以是深度为1μm～5μm的深沟槽，需要说明的是，所述沟槽211的深度不仅限于此深度范围，可以根据半导体器件的性能需求形成合适深度的所述沟槽211。
其中，所述填充材料可以包括介质材料或金属材料，或同时包括介质材料和金属材料；当所述填充材料为金属材料时，所述沟槽填充结构212包括形成于所述沟槽211的表面的隔离氧化层2121和填满所述沟槽211的第一导电金属层2122(即所述填充材料为所述第一导电金属层2122)。所述介质材料可以包括二氧化硅、氮化硅、正硅酸乙酯、硼硅玻璃、磷硅玻璃、硼磷硅玻璃、氮氧硅中的至少一种，所述金属材料可以包括钨、镍、铝、银、金、钛中的至少一种。
另外，所述沟槽填充结构212的顶表面可以与所述衬底20的顶表面齐平，或者，所述沟槽填充结构212的顶表面高于所述衬底20的顶表面，或者，仅所述沟槽填充结构212中的填充材料的顶表面高于所述衬底20的顶表面。
所述缓冲介质层25形成于所述像素区21的衬底20表面上，所述缓冲介质层25具有第一开口，所述第一开口至少暴露出所述沟槽填充结构212的顶部侧壁外围的部分衬底20或所述沟槽填充结构212的部分顶部，或者，至少暴露出所述沟槽填充结构212的顶部侧壁外围的部分衬底20和所述沟槽填充结构212的部分顶部。所述缓冲介质层25的材质可以包括二氧化硅、氮化硅、正硅酸乙酯、硼硅玻璃、磷硅玻璃、硼磷硅玻璃、氮氧硅中的至少一种。
其中，所述第一开口至少暴露出所述沟槽填充结构212的顶部侧壁外围的部分衬底20，即是指所述第一开口至少环绕所述沟槽填充结构212的顶部外围设置，以至少暴露出环绕所述沟槽填充结构212的顶部外围的部分衬底20。
所述第一开口至少暴露出所述沟槽填充结构212的部分顶部的情形包括：当所述沟槽填充结构212的顶表面高于所述衬底20的顶表面时，所述第一开口围绕所述沟槽填充结构212的顶部侧壁开设，以暴露出所述沟槽填充结构212的顶部侧壁上的隔离氧化层2121，此时，所述第一开口也暴露出所述沟槽填充结构212的顶部侧壁外围的部分衬底20；当仅所述沟槽填充结构212中的填充材料的顶表面高于所述衬底20的顶表面时，所述第一开口围绕所述沟槽填充结构212的顶部侧壁开设，以暴露出所述沟槽填充结构212的顶部侧壁上的填充材料；当所述沟槽填充结构212的顶表面高于或等于所述衬底20的顶表面时，所述第一开口也可以位于所述沟槽填充结构212的顶表面上，以暴露出所述沟槽填充结构212的部分或全部的顶表面，包括暴露出所述填充材料和/或所述隔离氧化层2121的部分或全部的顶表面；当所述沟槽填充结构212的顶表面高于所述衬底20的顶表面时，所述第一开口也可以同时暴露出所述沟槽填充结构212的顶部侧壁上的隔离氧化层2121或填充材料以及暴露出所述沟槽填充结构212的部分或全部的顶表面。
当所述填充材料包括第一导电金属层2122时，所述第一开口至少暴露出所述沟槽填充结构212的部分顶部的情形包括：所述第一开口围绕所述沟槽填充结构212的顶部侧壁开设，以暴露出所述沟槽填充结构212的顶部侧壁上的第一导电金属层2122；或者，所述第一开口位于所述沟槽填充结构212的顶表面上，以暴露出所述沟槽填充结构212的第一导电金属层2122的部分或全部的顶表面；或者，所述第一开口同时暴露出所述沟槽填充结构212的顶部侧壁上的第一导电金属层2122和所述沟槽填充结构212的第一导电金属层2122的部分 或全部的顶表面。
所述金属栅格层形成于所述缓冲介质层25上，所述金属栅格层填满所述第一开口，以与暴露出的所述部分衬底20或所述沟槽填充结构212电性连接，或者同时与暴露出的所述部分衬底20和所述沟槽填充结构212电性连接。由于所述金属栅格层能够与暴露出的所述部分衬底20和/或所述沟槽填充结构212电性连接，使得能够对半导体器件进行电学性能方面的优化和改善，例如优化和改善半导体器件的暗电流。
当所述第一开口仅暴露出所述部分衬底20时，所述金属栅格层仅与暴露出的所述部分衬底20电性连接；当所述第一开口至少暴露出所述沟槽填充结构212的部分顶部时，根据上述列出的不同情形，对应的所述金属栅格层与下方的结构电性连接的情形包括：当所述沟槽填充结构212的顶表面高于所述衬底20的顶表面，且所述第一开口围绕所述沟槽填充结构212的顶部侧壁开设(即暴露出顶部侧壁上的所述隔离氧化层2121)时，则所述金属栅格层也仅与暴露出的所述部分衬底20电性连接；当仅所述沟槽填充结构212中的填充材料的顶表面高于所述衬底20的顶表面，且所述第一开口围绕所述沟槽填充结构212的顶部侧壁开设，所述填充材料为所述第一导电金属层2122时，所述金属栅格层与所述沟槽填充结构212的顶部侧壁上的第一导电金属层2122电性连接；当所述沟槽填充结构212的顶表面高于或等于所述衬底20的顶表面，且所述第一开口位于所述沟槽填充结构212的填充材料的顶表面上，所述填充材料为所述第一导电金属层2122时，所述金属栅格层与所述沟槽填充结构212的暴露出的部分或全部的第一导电金属层2122的顶表面电性连接；当所述沟槽填充结构212的顶表面高于所述衬底20的顶表面，且所述第一开口同时暴露出所述沟槽填充结构212的顶部侧壁上的隔离氧化层2121或第一导电金属层2122以及暴露出所述第一导电金属层2122的部分或全部的顶表面时，所述金属栅格层同时与所述部分衬底20和第一导电金属层2122电性连接。
所述金属栅格层与暴露出的所述部分衬底20和/或所述沟槽填充结构212电性连接的情形举例如下：如图3i所示，所述金属栅格层214与所述第一开口暴露出的所述沟槽填充结构212的顶部侧壁外围的部分衬底20和所述沟槽填充结构212的全部的顶表面电性连接；如图4e所示，所述金属栅格层215与所述第一开口暴露出的所述沟槽填充结构212的第一导电金属层2122的部分的顶表面 电性连接；如图5e所示，所述金属栅格层216与所述第一开口暴露出的所述沟槽填充结构212的顶部侧壁外围的部分衬底20电性连接；如图6所示，所述金属栅格层217与所述第一开口暴露出的所述沟槽填充结构212的顶部侧壁外围的部分衬底20以及所述沟槽填充结构212的第一导电金属层2122的部分的顶表面电性连接。
另外，所述衬底还具有位于所述像素区外围的焊盘区，所述焊盘区的衬底中形成有金属互连结构以及位于所述金属互连结构上方的插栓结构，所述插栓结构的底部与所述金属互连结构电性连接，所述插栓结构的顶部还电性连接有焊盘结构。需要说明的是，所述焊盘区的衬底中也可以形成有所述金属互连结构之外的其它的金属结构，所述插栓结构的底部与所述金属结构电性连接；例如，所述金属结构可以为导电接触插栓，所述插栓结构的底部与所述导电接触插栓电性连接。下面均以所述金属结构为金属互连结构进行说明。
当所述沟槽填充结构中的填充材料为介质材料时，由于所述插栓结构中具有金属材料，使得所述像素区的沟槽填充结构与所述焊盘区的插栓结构需要分开制作；当所述沟槽填充结构中的填充材料为金属材料时，由于所述插栓结构中具有金属材料，因此，所述像素区的沟槽填充结构与所述焊盘区的插栓结构可以分开制作，也可以同时制作。
当所述像素区的沟槽填充结构与所述焊盘区的插栓结构分开制作时，所述插栓结构中的金属材料是与所述沟槽填充结构中的第一导电金属层不同的另一导电金属层；当所述像素区的沟槽填充结构与所述焊盘区的插栓结构同时制作时，则所述插栓结构中的金属材料也是所述沟槽填充结构中的第一导电金属层。
由于所述插栓结构的底部与所述金属互连结构电性连接，那么，当所述插栓结构中具有另一隔离氧化层时，所述另一隔离氧化层仅位于暴露出所述金属互连结构的部分顶表面的通孔的侧壁上。当所述插栓结构中的另一隔离氧化层与所述沟槽填充结构中的隔离氧化层相同，且仅所述像素区的沟槽的侧壁上具有所述隔离氧化层时，所述像素区的沟槽填充结构与所述焊盘区的插栓结构可以同时制作；当所述插栓结构中的另一隔离氧化层与所述沟槽填充结构中的隔离氧化层相同，但所述像素区的沟槽的侧壁和底壁上均具有所述隔离氧化层时，所述像素区的沟槽填充结构与所述焊盘区的插栓结构可以同时制作，只是需要增加一个步骤将所述通孔的底壁上的另一隔离氧化层去除；当所述插栓结构中 的另一隔离氧化层与所述沟槽填充结构中的隔离氧化层的材质等不相同时，所述像素区的沟槽填充结构与所述焊盘区的插栓结构需要分开制作。
当所述像素区的沟槽填充结构与所述焊盘区的插栓结构能够同时制作时，所述像素区的金属栅格层和所述焊盘区的焊盘结构也能够同时制作。
根据图1a至图1j所示的像素区的金属栅格层和焊盘区的焊盘结构的制作工艺可知，像素区的金属栅格层和焊盘区的焊盘结构先后在不同的工艺中进行制作时，导致工艺复杂、工艺整合度低，进而导致工艺成本较高。因此，若所述像素区的沟槽填充结构和金属栅格层与所述焊盘区的插栓结构和焊盘结构同时制作，能够降低工艺的复杂度、提高工艺的整合度，进而降低生产成本。
所述像素区的金属栅格层与暴露出的所述部分衬底和/或所述沟槽填充结构电性连接的不同情形参阅上述的说明，在此不再赘述。如图7i所示，以所述金属栅格层214与所述第一开口2131暴露出的所述沟槽填充结构212的顶部侧壁外围的部分衬底20和所述沟槽填充结构212的全部的顶表面电性连接的情形为例，对同时制作形成的所述像素区21的沟槽填充结构212和金属栅格层214与所述焊盘区22的插栓结构223和焊盘结构225进行说明：
所述沟槽填充结构212包括填充在所述像素区21的沟槽211中的第一导电金属层，以及位于所述沟槽211表面的隔离氧化层时，所述插栓结构223包括：位于暴露出所述金属互连结构221的部分顶表面的通孔222的侧壁上的隔离氧化层，以及填满所述通孔222的第一导电金属层。为了便于区分，所述沟槽211表面的隔离氧化层为隔离氧化层2121，所述通孔222表面的隔离氧化层为隔离氧化层2231，所述沟槽211中的第一导电金属层为第一导电金属层2122，所述通孔222中的第一导电金属层为第一导电金属层2232，图7i中也采用了不同的填充图案进行标识。其中，所述沟槽211中的隔离氧化层2121可以仅位于所述沟槽211的侧壁上，也可以均位于所述沟槽211的侧壁和底壁上，所述通孔222中的隔离氧化层2231仅位于所述通孔222的侧壁上；所述插栓结构223中的第一导电金属层2232的底部与所述金属互连结构221电性连接。
所述缓冲介质层25形成于所述像素区21和焊盘区22的衬底20的表面上，且在所述像素区21的缓冲介质层25中形成有第一开口2131以及在所述焊盘区22的缓冲介质层25中形成有第二开口224，所述第一开口2131暴露出所述沟槽填充结构212的顶部侧壁外围的部分衬底20和所述沟槽填充结构212的全部 的顶表面，所述第二开口224暴露出所述插栓结构223的部分的顶部表面，所述第二开口224可以暴露出所述插栓结构223的第一导电金属层2232的部分或全部的顶部表面。
所述像素区21的缓冲介质层25上形成有金属栅格层214，所述焊盘区22的缓冲介质层25上形成有焊盘结构225，所述金属栅格层214填满所述第一开口2131，以与暴露出的所述部分衬底20和所述沟槽填充结构212电性连接；所述焊盘结构225填满所述第二开口224，以与暴露出的所述插栓结构223的顶部电性连接。
综上所述，本发明提供的半导体器件，包括：衬底，具有像素区；沟槽填充结构，形成于所述像素区的衬底中；缓冲介质层，形成于所述像素区的衬底表面上，所述缓冲介质层具有第一开口，所述第一开口至少暴露出所述沟槽填充结构的顶部侧壁外围的部分衬底和/或所述沟槽填充结构的至少部分顶部；以及，金属栅格层，形成于所述缓冲介质层上，所述金属栅格层填充所述第一开口，以与暴露出的所述部分衬底和/或所述沟槽填充结构电性连接。本发明的半导体器件使得金属栅格层与暴露出的所述部分衬底和/或所述沟槽填充结构电性连接，进而使得能够对半导体器件进行电学性能方面的优化和改善。
上述描述仅是对本发明较佳实施例的描述，并非对本发明范围的任何限定，本发明领域的普通技术人员根据上述揭示内容做的任何变更、修饰，均属于权利要求书的保护范围。

Claims (14)

  1. 一种半导体器件的制造方法，其特征在于，包括：
    提供一具有像素区的衬底；
    形成沟槽填充结构于所述像素区的衬底中；
    覆盖缓冲介质层于所述像素区的衬底表面上，且所述缓冲介质层将所述沟槽填充结构掩埋在内；
    刻蚀所述缓冲介质层，以形成第一开口，所述第一开口至少暴露出所述沟槽填充结构的顶部侧壁外围的部分衬底和/或所述沟槽填充结构的至少部分顶部；以及，
    形成金属栅格层于所述缓冲介质层上，所述金属栅格层填充所述第一开口，以与暴露出的所述部分衬底和/或所述沟槽填充结构电性连接。
  2. 如权利要求1所述的半导体器件的制造方法，其特征在于，形成所述沟槽填充结构于所述像素区的衬底中的步骤包括：
    覆盖垫氧化层于所述像素区的衬底表面；
    形成第一图案化的光刻胶层于所述垫氧化层上，以所述第一图案化的光刻胶层为掩膜，对所述垫氧化层以及至少部分厚度的所述衬底进行刻蚀，以在所述像素区的衬底中形成沟槽；
    去除所述第一图案化的光刻胶层；
    形成隔离氧化层于所述沟槽和所述垫氧化层的表面上；
    在所述沟槽中填满填充材料，且所述填充材料还覆盖在所述沟槽外围的所述隔离氧化层上；以及，
    采用刻蚀或者化学机械研磨工艺去除覆盖于所述沟槽外围的所述衬底的表面上的填充材料、隔离氧化层和垫氧化层，以在所述沟槽中形成沟槽填充结构。
  3. 如权利要求2所述的半导体器件的制造方法，其特征在于，所述填充材料包括第一导电金属层，所述第一开口至少暴露出所述沟槽填充结构的部分顶部的情形包括：所述第一开口围绕所述沟槽填充结构的顶部侧壁开设，以暴露出所述沟槽填充结构的顶部侧壁上的第一导电金属层，和/或，所述第一开口位于所述沟槽填充结构的顶表面上，以暴露出所述沟槽填充结构的第一导电金属层的部分或全部的顶表面。
  4. 如权利要求1所述的半导体器件的制造方法，其特征在于，刻蚀所述缓 冲介质层，以形成所述第一开口的步骤包括：
    形成第二图案化的光刻胶层于所述缓冲介质层上，以所述第二图案化的光刻胶层为掩膜，对所述缓冲介质层进行刻蚀，以在所述像素区的缓冲介质层中形成所述第一开口，所述第一开口至少暴露出所述沟槽填充结构的顶部侧壁外围的部分衬底和/或所述沟槽填充结构的至少部分顶部；以及，
    去除所述第二图案化的光刻胶层。
  5. 如权利要求1所述的半导体器件的制造方法，其特征在于，形成所述金属栅格层于所述缓冲介质层上的步骤包括：
    形成第二导电金属层覆盖于所述缓冲介质层上，且所述第二导电金属层将所述第一开口填满；
    形成第三图案化的光刻胶层于所述第二导电金属层上，以所述第三图案化的光刻胶层为掩膜，对所述第二导电金属层进行刻蚀，以在所述像素区形成金属栅格层，所述金属栅格层与所述第一开口暴露出的所述部分衬底和/或所述沟槽填充结构电性连接；以及，
    去除所述第三图案化的光刻胶层。
  6. 如权利要求1至5中任一项所述的半导体器件的制造方法，其特征在于，所述衬底还具有位于所述像素区外围的焊盘区，所述焊盘区的衬底中形成有金属互连结构以及位于所述金属互连结构上方的插栓结构，所述插栓结构的底部与所述金属互连结构电性连接。
  7. 如权利要求6所述的半导体器件的制造方法，其特征在于，当所述沟槽填充结构包括填充在所述像素区的沟槽中的第一导电金属层时，在形成沟槽填充结构于所述像素区的衬底中的同时，一道形成所述插栓结构于所述焊盘区的衬底中。
  8. 如权利要求6所述的半导体器件的制造方法，其特征在于，在覆盖所述缓冲介质层于所述像素区的衬底表面上的同时，还覆盖所述缓冲介质层于所述焊盘区的衬底表面上，以使得所述缓冲介质层将所述插栓结构掩埋在内；在刻蚀所述像素区上的所述缓冲介质层，以形成所述第一开口的同时，还刻蚀所述焊盘区上的所述缓冲介质层，以形成第二开口，所述第二开口暴露出所述插栓结构的部分的顶部表面；以及，在形成所述金属栅格层于所述像素区的所述缓冲介质层上的同时，还形成焊盘结构于所述焊盘区的所述缓冲介质层上，所述 焊盘结构填满所述第二开口，以与暴露出的所述插栓结构的顶部电性连接。
  9. 一种半导体器件，其特征在于，包括：
    衬底，具有像素区；
    沟槽填充结构，形成于所述像素区的衬底中；
    缓冲介质层，形成于所述像素区的衬底表面上，所述缓冲介质层具有第一开口，所述第一开口至少暴露出所述沟槽填充结构的顶部侧壁外围的部分衬底和/或所述沟槽填充结构的至少部分顶部；以及，
    金属栅格层，形成于所述缓冲介质层上，所述金属栅格层填充所述第一开口，以与暴露出的所述部分衬底和/或所述沟槽填充结构电性连接。
  10. 如权利要求9所述的半导体器件，其特征在于，所述沟槽填充结构包括覆盖于所述衬底中的沟槽的表面上的隔离氧化层和填充于所述沟槽中的填充材料，所述隔离氧化层至少位于所述填充材料的侧壁和所述衬底之间。
  11. 如权利要求10所述的半导体器件，其特征在于，所述填充材料包括第一导电金属层，所述第一开口至少暴露出所述沟槽填充结构的部分顶部的情形包括：所述第一开口围绕所述沟槽填充结构的顶部侧壁开设，以暴露出所述沟槽填充结构的顶部侧壁上的第一导电金属层，和/或，所述第一开口位于所述沟槽填充结构的顶表面上，以暴露出所述沟槽填充结构的第一导电金属层的部分或全部的顶表面。
  12. 如权利要求9至11中任一项所述的半导体器件，其特征在于，所述衬底还具有位于所述像素区外围的焊盘区，所述焊盘区的衬底中形成有金属互连结构以及位于所述金属互连结构上方的插栓结构，所述插栓结构的底部与所述金属互连结构电性连接。
  13. 如权利要求12所述的半导体器件，其特征在于，当所述沟槽填充结构包括填充在所述像素区的沟槽中的第一导电金属层时，所述插栓结构包括：位于暴露出所述金属互连结构的部分顶表面的通孔的侧壁上的隔离氧化层，以及填满所述通孔的第一导电金属层。
  14. 如权利要求12所述的半导体器件，其特征在于，所述缓冲介质层还形成于所述焊盘区的衬底表面上，且所述缓冲介质层具有暴露出所述插栓结构的部分的顶部表面的第二开口；所述焊盘区的缓冲介质层上还形成有焊盘结构，所述焊盘结构填满所述第二开口，以与暴露出的所述插栓结构电性连接。
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