WO2021104372A1 - 像素电路与检测方法 - Google Patents

像素电路与检测方法 Download PDF

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Publication number
WO2021104372A1
WO2021104372A1 PCT/CN2020/131773 CN2020131773W WO2021104372A1 WO 2021104372 A1 WO2021104372 A1 WO 2021104372A1 CN 2020131773 W CN2020131773 W CN 2020131773W WO 2021104372 A1 WO2021104372 A1 WO 2021104372A1
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Prior art keywords
transistor
detection
pole
circuit
control terminal
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PCT/CN2020/131773
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English (en)
French (fr)
Inventor
孙世成
郭钟旭
史大为
张伟
李存智
王培�
Original Assignee
京东方科技集团股份有限公司
重庆京东方显示技术有限公司
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Application filed by 京东方科技集团股份有限公司, 重庆京东方显示技术有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US17/417,440 priority Critical patent/US11538375B2/en
Publication of WO2021104372A1 publication Critical patent/WO2021104372A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3275—Details of drivers for data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/061—Details of flat display driving waveforms for resetting or blanking
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0238—Improving the black level

Definitions

  • the present invention relates to the field of display technology, in particular to a pixel circuit and a detection method.
  • the driving part of the LTPS AMOLED display panel is composed of multiple thin film transistors (TFTs), and the performance of these TFTs directly affects the display effect of the display panel. Therefore, TFT performance testing is very important in the production and manufacturing of display panels.
  • TFTs thin film transistors
  • the purpose of the present invention is to provide a circuit and method for detecting the TFT characteristics of an LTPS AMOLED display panel that at least solve the above-mentioned problems.
  • An embodiment of the present disclosure provides a pixel circuit, including: a light-emitting element; a driving sub-circuit configured to generate a current for causing the light-emitting element to emit light; and a reset sub-circuit configured to receive a reset control signal from a reset control signal line And receiving a reset signal from the reset signal line, and under the action of the reset control signal, using the reset signal to reset the driving sub-circuit and the anode of the light-emitting element; the writing sub-circuit is configured to slave data The line receives the data signal and the scan signal from the scan signal line, and under the action of the scan signal, the data signal is provided to the driving sub-circuit; the light-emitting control sub-circuit is configured to receive the first power line from the first power line A power supply voltage and a lighting control signal received from a lighting signal line, and under the action of the lighting control signal, the first power supply voltage is provided to the driver sub-circuit and the current generated by the driver sub-circuit is provided to The an
  • the pixel circuit further includes a plurality of detection terminals, including a detection control terminal and a detection output terminal, configured to apply a detection control signal via the detection control terminal, and obtain a detection output signal via the detection output terminal, so as to The detection output signal detects elements included in the pixel circuit.
  • the detection control terminal includes a first detection control terminal connected to the reset signal line, a second detection control terminal connected to the reset control signal line, and a third detection control terminal connected to the light-emitting control signal line And a fourth detection control terminal connected to the scanning signal line;
  • the detection output terminal includes a first detection output terminal connected to the first power line and a second detection output terminal connected to the anode of the light-emitting element .
  • a plurality of detection terminals are arranged in the same layer as the layer where the anode of the light-emitting element is located.
  • the driving sub-circuit includes a driving transistor and a storage capacitor, wherein a first pole of the storage capacitor is connected to the first power line, and a second pole of the storage capacitor is connected to the gate of the driving transistor and the The second end of the detecting element, the first pole and the second pole of the driving transistor are both connected to the light emission control sub-circuit.
  • the reset sub-circuit includes a first transistor and a seventh transistor, wherein the gate of the first transistor is connected to the reset control signal line, and the first electrode of the first transistor is connected to the second transistor of the detection element.
  • the second electrode of the first transistor is connected to the reset signal line
  • the gate of the seventh transistor is connected to the scan signal line
  • the first electrode of the seventh transistor is connected to the anode of the light-emitting element
  • the second electrode of the seventh transistor is connected to the reset signal line.
  • the writing sub-circuit includes a second transistor and a fourth transistor, wherein the gates of the second transistor and the fourth transistor are both connected to the scan signal line, and the first electrode of the second transistor is connected
  • the second electrode of the driving transistor, the second electrode of the second transistor is connected to the gate of the driving transistor; the first electrode of the fourth transistor is connected to the data signal line, and the second electrode of the fourth transistor is connected to the data signal line.
  • the two poles are connected to the first pole of the driving transistor.
  • the light emission control sub-circuit includes a fifth transistor and a sixth transistor, wherein the gates of the fifth transistor and the sixth transistor are both connected to the light emission control signal line, and the first electrode of the fifth transistor Connected to the first power line, the second electrode of the fifth transistor is connected to the first electrode of the driving transistor; the first electrode of the sixth transistor is connected to the second electrode of the driving transistor, the sixth The second electrode of the transistor is connected to the anode of the light-emitting element, and the cathode of the light-emitting element is connected to the second power line.
  • the detection element includes an eighth transistor, the gate of the eighth transistor is used as the control terminal of the detection element, and the first electrode and the second electrode of the eighth transistor are respectively used as the first end of the detection element And the second end.
  • the embodiment of the present disclosure also provides a detection method of a pixel circuit, which includes: cutting a wiring at a designated position in the pixel circuit to obtain a detection path including at least one designated element of the pixel circuit; The at least one designated element is tested.
  • using the detection path to detect the at least one designated element includes: determining at least one detection control terminal and a detection control terminal from a detection control terminal and a detection output terminal according to the designated element to be tested in the at least one designated component. Output terminal; applying a detection control signal to the detection path via the determined at least one detection control terminal; and obtain a detection output signal via the determined detection output terminal, and apply a detection control signal to the designated component to be tested according to the detection output signal Perform testing.
  • the detection path includes a driving transistor, a fifth transistor, a sixth transistor, and an eighth transistor
  • the detecting the at least one designated element by using the detection path includes: when the driving transistor is detected: controlling with a first detection As the gate of the driving transistor, the first detection output terminal is used as the source of the driving transistor, and the second detection output terminal is used as the drain of the driving transistor; when the fifth transistor is detected, the third The detection control terminal is used as the gate of the fifth transistor, the first detection output terminal is used as the first pole of the fifth transistor, and the second detection output terminal is used as the second pole of the fifth transistor; In the case of six transistors, the third detection control terminal is used as the gate of the sixth transistor, the first detection output terminal is used as the first pole of the sixth transistor, and the second detection output terminal is used as the gate of the sixth transistor. The second pole.
  • the detection path includes a first transistor, an eighth transistor and a seventh transistor of an adjacent pixel row
  • the detection of the at least one designated element by the detection path includes: detecting the first transistor or the second transistor
  • the second detection control terminal is used as the gates of the first transistor and the eighth transistor
  • the first detection control terminal is used as the first pole of the first transistor and the eighth transistor.
  • the second detection output terminal of the adjacent pixel row is used as the second electrode of the first transistor and the eighth transistor; when the seventh transistor of the adjacent pixel row is detected, the fourth detection control terminal is used as the seventh transistor.
  • the first detection control terminal is used as the first pole of the seventh transistor
  • the second detection output terminal of the adjacent pixel row is used as the second pole of the seventh transistor.
  • the detection path includes a second transistor, a sixth transistor, and an eighth transistor
  • the detection of the at least one designated element using the detection path includes: when the second transistor is detected, a fourth detection control The terminal is used as the gate of the second transistor, the second detection output terminal is used as the first pole of the second transistor, and the first detection control terminal is used as the second pole of the second transistor; in the detection of the sixth transistor
  • the third detection control terminal is used as the gate of the sixth transistor
  • the first detection control terminal is used as the first pole of the sixth transistor
  • the second detection output terminal is used as the second pole of the sixth transistor.
  • the second detection control terminal is used as the gate of the eighth transistor
  • the first detection control terminal is used as the first pole of the eighth transistor
  • the second detection output terminal is used as the gate of the eighth transistor.
  • the detection path includes fourth transistors located in adjacent first pixel rows and second pixel rows, and fifth transistors located in the first pixel rows and second pixel rows, respectively.
  • the detection of the at least one designated element by the detection path includes: when the fourth transistor of the first pixel row is detected, the fourth detection control terminal of the first pixel row is used as the gate of the fourth transistor to The first detection output terminal of the second pixel row is used as the first pole of the fourth transistor, and the first detection output terminal of the first pixel row is used as the second pole of the fourth transistor;
  • the third detection control terminal of the first pixel is used as the gate of the fifth transistor, the first detection output terminal of the first pixel row is used as the first electrode of the fifth transistor, and the second The first detection output terminal of the pixel row serves as the second electrode of the fifth transistor.
  • the pixel circuit of the embodiment of the present disclosure when inspecting the components included in the pixel circuit, it is only necessary to remove the organic materials of the pixel definition layer PDL (Pixel Definition Layer). These organic materials are compared with organic and inorganic composite film layers. It is easier to remove and has a higher sample preparation success rate. At the same time, this structural design only needs to connect the probe directly to the metal detection terminal (Pad) used for testing. Compared with the FIB bonding method, it is more stable and has higher accuracy. Bad has an important role.
  • PDL Pixel Definition Layer
  • each TFT included in the pixel circuit can be tested.
  • the detection element can be used to add a path for resetting the storage capacitor to optimize the reset effect and help improve flicker and afterimages.
  • FIG. 1 is a schematic structural diagram of a pixel circuit of an embodiment of the present disclosure
  • FIG. 2 is a schematic diagram of the layout of the detection terminal of an embodiment of the present disclosure
  • FIG. 3 is a circuit diagram of a pixel circuit of an embodiment of the present disclosure.
  • FIG. 4 is a flowchart of a detection method according to an embodiment of the present disclosure.
  • Fig. 5 is a first structural diagram of a detection path of an embodiment of the present disclosure
  • Fig. 6 is a second structural diagram of a detection path of an embodiment of the present disclosure.
  • FIG. 7 is a third structural diagram of a detection path of an embodiment of the present disclosure.
  • FIG. 8 is a fourth structural diagram of the detection path of the embodiment of the present disclosure.
  • FIG. 1 is a schematic diagram of the structure of a pixel circuit of an embodiment of the present disclosure.
  • the pixel circuit 100 of the embodiment of the present disclosure is used to detect the characteristics of the TFT in the pixel area of the LTPS AMOLED display panel.
  • the pixel circuit 100 includes a driving sub-circuit 101, a reset sub-circuit 102, a writing sub-circuit 103, a light-emission control sub-circuit 104, a detection element 105, and a light-emitting element 106.
  • the driving sub-circuit 101 is configured to generate a current for causing the light emitting element 106 to emit light.
  • the reset sub-circuit 102 is configured to receive a reset control signal (Reset) from the reset control signal line and a reset signal (Vinit) from the reset signal line, and under the action of the reset control signal, use the reset signal to drive the sub-circuit 101 and emit light.
  • the anode of element 106 is reset.
  • the data signal in the subsequent stage can be stored more quickly and reliably.
  • the light-emitting element can be displayed in a black state before emitting light, and the display effect such as the contrast of the display device using the above-mentioned pixel circuit can be improved.
  • the writing sub-circuit 103 is configured to receive a data signal (Data) from the data line and a scan signal (Gate) from the scan signal line, and to provide the data signal to the driving sub-circuit 101 under the action of the scan signal.
  • the light emission control sub-circuit 104 is configured to receive a first power supply voltage (VDD) from a first power supply line and a light emission control signal (EM) from a light emission signal line, and under the action of the light emission control signal, provide the first power supply voltage to
  • VDD first power supply voltage
  • EM light emission control signal
  • the control end of the detection element 105 is connected to the reset control signal line, the first end of the detection element 105 is connected to the reset signal line, and the second end of the detection element is connected to the driving sub-circuit 101, and is configured to be a pair of elements included in the pixel circuit 100. Perform testing.
  • the anode and cathode of the light-emitting element 106 are respectively connected to the first power supply voltage VDD (for example, a high-level voltage) and the second power supply voltage VSS (for example, a low-level voltage), so that the light-emitting element is driven by the driving sub-circuit 101. Glows under the action of electric current.
  • a plurality of detection terminals are also provided in the same layer as the anode of the light-emitting element 106.
  • the multiple detection terminals include a detection control terminal and a detection output terminal.
  • the detection control signal may be applied via the detection control terminal, and the detection output signal may be acquired via the detection output terminal, so as to detect the elements included in the pixel circuit according to the detection output signal.
  • FIG. 2 is a schematic diagram of the layout of the detection terminal of an embodiment of the present disclosure.
  • the detection control terminal includes a first detection control terminal 11, which is configured to be connected to the reset signal (Vinit) line and connected to the first terminal of the detection element.
  • the second detection control terminal 12 is set to be connected to the reset signal (Reset) line, that is, to the scanning signal (Gate n-1 ) line of the previous-stage pixel circuit.
  • the third detection control terminal 13 is configured to be connected to the light emission control signal (EM) line.
  • the fourth detection control terminal 14 which is set to be connected to the scanning signal (Gate n ) line.
  • the detection output terminal includes a first detection output terminal 15 which is configured to be connected to a first power supply (VDD) line.
  • the second detection output terminal 16 which is arranged to be connected to the anode of the light-emitting element OLED.
  • the first detection control terminal 11 to the fourth detection control terminal 14 and the first detection output terminal 15 and the second detection output terminal 16 are all formed on the uppermost OLED anode layer of the substrate. More preferably, the first detection control terminals 11 of the plurality of pixel circuits are connected by a metal wire provided on the OLED anode layer at the uppermost part of the substrate. Specifically, the pattern of the metal detection terminal is designed on the anode layer, and the detection terminal and the via connection point are formed through processes such as photolithography and etching to realize the above-mentioned connection relationship.
  • the first detection control terminal 11 to the fourth detection control terminal 14 and the first detection control terminal 11, the first detection output terminal 15 and the second detection output terminal 16 can form a "4 control terminal + 3 input/output"
  • the "terminal” structure can test the characteristics of multiple transistors in the circuit through the cooperation of multiple detection terminals.
  • FIG. 3 is a circuit diagram of a pixel circuit of an embodiment of the present disclosure.
  • a 7T1C pixel driving circuit is taken as an example for description. It is easy to understand that other common pixel driving circuit structures such as 6T1C, 6T2C, 5T1C, and 4T1C can be used.
  • FIG. 3 is only an example and is not used to limit the embodiments of the present disclosure.
  • the driving sub-circuit includes a driving transistor DTFT and a storage capacitor Cst.
  • the first electrode of the storage capacitor Cst is connected to the first power supply (VDD) line
  • the second electrode of the storage capacitor Cst is connected to the gate of the driving transistor DTFT and the second end of the detection element
  • the first and second electrodes of the driving transistor DTFT are both Connect to the lighting control sub-circuit.
  • the gate of the driving transistor DTFT and the second electrode of the storage capacitor Cst can discharge electricity under the control of a reset control signal (Reset).
  • Reset reset control signal
  • the detection element may include an eighth transistor T8, the gate of the eighth transistor T8 serves as the control end of the detection element, and the first and second electrodes of the eighth transistor T8 serve as the first and second ends of the detection element, respectively.
  • the eighth transistor T8 can be formed at the same time as other transistors in the pixel circuit, but does not participate in the work when other transistors are in use. Therefore, the eighth transistor T8 will not affect the performance of the circuit.
  • the reset function of the storage capacitor Cst can be optimized, and at the same time, it can be used as the gate control terminal of the driving transistor DTFT test without affecting the working state of the circuit.
  • the first pole of the transistor T8 is connected to the reset voltage Vinit, which can better discharge the power of the storage capacitor Cst and the driving transistor DTFT.
  • the first electrode of the eighth transistor T8 is connected to the first detection control terminal 11, the second electrode is connected to the gate of the driving transistor DTFT, and the gate of the eighth transistor T8 is connected to the second detection control terminal 12.
  • the reset sub-circuit includes a first transistor T1 and a seventh transistor T7.
  • the gate of the first transistor T1 is connected to the reset control signal Reset (that is, the scanning signal Gate n-1 of the previous pixel circuit), the first electrode of the first transistor T1 is connected to the second electrode of the eighth transistor T8, and the driving transistor DTFT The gate and the first pole of the storage capacitor Cst.
  • the second electrode of the first transistor T1 is connected to the reset signal Vinit.
  • the gate of the seventh transistor T7 is connected to the scanning signal Gate n
  • the first electrode of T7 is connected to the anode of the light-emitting element OLED
  • the second electrode is connected to the reset signal Vinit.
  • the writing sub-circuit includes a second transistor T2 and a fourth transistor T4.
  • the gates of the second transistor T2 and the fourth transistor T4 are both connected to the scanning signal Gate n , the first electrode of the second transistor T2 is connected to the second electrode of the driving transistor DTFT, and the second electrode is connected to the gate of the driving transistor DTFT.
  • the first electrode of the fourth transistor T4 is connected to the data signal Data, and the second electrode is connected to the first electrode of the driving transistor DTFT.
  • the light emission control sub-circuit includes a fifth transistor T5 and a sixth transistor T6.
  • the gates of the fifth transistor T5 and the sixth transistor T6 are both connected to the light emission control signal EM, the first electrode of the fifth transistor T5 is connected to the first power supply VDD, and the second electrode is connected to the first electrode of the driving transistor DTFT.
  • the first electrode of the sixth transistor T6 is connected to the second electrode of the driving transistor DTFT, and the second electrode is connected to the anode of the light emitting element OLED.
  • the scan signal Gate n-1 of the pixel circuit of the previous stage (that is, the reset control signal of the pixel circuit of the current stage) and the scan signal Gate n of the current stage make the first transistor T1 and the seventh transistor T7 turn on,
  • the storage capacitor Cst and the anode of the light-emitting element OLED are connected to the reset signal line, and the power is released.
  • the scan signal Gate n turns on the fourth transistor T4 and the second transistor T2, and the data voltage is written into the storage capacitor Cst through the fourth transistor T4, the driving transistor DTFT, and the second transistor T2.
  • the emission control signal EM turns on the fifth transistor T5 and the sixth transistor T6, and the power supply VDD is applied to the anode of the light-emitting element OLED through the fifth transistor, the driving transistor DTFT, and the sixth transistor T6, thereby making the light-emitting element OLED Glow.
  • FIG. 4 is a flowchart of a detection method 400 according to an embodiment of the present disclosure. As shown in FIG. 4, the detection method 400 includes the following steps:
  • step S410 the wiring at a designated position in the pixel circuit is cut to obtain a detection path including at least one designated element of the pixel circuit.
  • step S420 at least one designated element is detected using the detection path.
  • using the detection path to detect at least one designated element includes: according to the designated element to be tested in the at least one designated element, determining at least one of the detection control terminal and the detection output terminal from the detection control terminal and the detection output terminal.
  • the determined at least one detection control terminal applies a detection control signal to the detection path, acquires a detection output signal through the determined detection output terminal, and detects the designated component to be tested based on the detection output signal.
  • Figures 5 to 8 respectively show the structure diagrams of the detection path of an embodiment of the present disclosure. The following describes in detail the process of detecting at least one designated element using the detection path with reference to FIGS. 5 to 8.
  • the circuit structure of the detection path shown in FIG. 5 includes a driving transistor DTFT, a fifth transistor T5, a sixth transistor T6, and an eighth transistor T8 in the detection path.
  • a low-level signal is applied to the third detection control terminal 13 connected to the emission control signal (EM) line and the second detection control terminal 12 connected to the reset control signal (Reset) line to turn on the Eight transistors T8, fifth transistor T5 and sixth transistor T6.
  • the first detection control terminal 11 can be used as the gate of the driving transistor DTFT via the eighth transistor T8, the first detection output terminal 15 can be used as the source of the driving transistor DTFT via the fifth transistor T5, and the second detection output terminal 16 serves as the drain of the driving transistor DTFT via the sixth transistor T6.
  • Conventional TFT characteristic evaluation includes, but is not limited to: TFT transfer characteristic curve Id-Vg and output characteristic curve Id-Vd, and TFT characteristic parameters (such as threshold voltage, mobility, off-state leakage current, etc.).
  • the first detection control terminal 11 and the second detection control terminal 12 are kept at a low potential to turn on the eighth transistor T8 and the driving transistor DTFT.
  • the third detection control terminal 13 can be used as the gate of the fifth transistor T5/sixth transistor T6, and the first detection output terminal 15 (or via the fifth transistor T5) can be used as the first of the fifth transistor T5 (or the sixth transistor T6).
  • the second detection output terminal 16 (or through the sixth transistor T6) serves as the second electrode, such as the drain, of the sixth transistor T6 (or the fifth transistor T5), for example, the source, thereby forming a T5/T6 characteristic test path .
  • the electrical connection between the second electrode of the seventh transistor T7 and the reset signal line forms the circuit structure of the detection path as shown in FIG. 6.
  • the detection path includes a first transistor T1, a seventh transistor T7, and an eighth transistor T8.
  • the first transistor T1 and the eighth transistor T8 are located in the same pixel row, and the seventh transistor T7 is located in the previous adjacent pixel row where the first transistor T1 and the eighth transistor T8 are located.
  • the seventh transistor T7 is located in the previous adjacent pixel row where the first transistor T1 and the eighth transistor T8 are located.
  • adjacent to the first transistor T1(n) and the eighth transistor T8(n) in the current pixel row (nth row) is the previous pixel row (nth row).
  • the seventh transistor T7(n) in the current pixel row (nth row) is located in the first pixel row (n+1th row) Near the transistor T1 (n+1) and the eighth transistor T8 (n+1).
  • the second detection control terminal 12 serves as the gate of the first transistor T1 and the eighth transistor T8, and the first detection control terminal 11 serves as the first pole of the first transistor T1 and the eighth transistor T8.
  • the second detection output terminal 16 of line n-1) serves as the second pole. The probe is connected to the corresponding detection terminal, and then the performance test of the first transistor T1 or the eighth transistor can be performed.
  • the fourth detection control terminal 14 serves as the gate of the seventh transistor T7
  • the first detection control terminal 11 serves as the first pole of the seventh transistor T7
  • the second detection output terminal 16 of the adjacent pixel row (the n-1th row) serves as the The second pole.
  • the probe is connected to the corresponding detection terminal, and then the performance test of the seventh transistor T7 can be performed.
  • the sixth transistor T6 or the eighth transistor T8 cut off part of the circuit to connect the first transistor T1, the driving transistor DTFT, the fourth transistor T4, the fifth transistor T5, the seventh transistor T7 and the storage
  • the capacitor Cst is disconnected from the circuit and cuts off the electrical connection between the second pole of the first transistor T1 and the seventh transistor T7 and the reset signal line, forming the circuit structure of the detection path as shown in FIG. 7, in the detection path, It includes a second transistor T2, a sixth transistor T6, and an eighth transistor T8.
  • test T2 the third detection control terminal 13 connected to the light emission control signal (EM) line and the second detection control terminal 12 connected to the reset signal (Reset) line apply a low-level signal, thereby turning on the eighth transistor T8 and
  • the sixth transistor T6 the first detection control terminal 11 can be used as the first pole of the second transistor T2 via the eighth transistor T8, and the second detection output terminal 16 can be used as the second pole of the second transistor T2 via the sixth transistor T6.
  • the four detection control terminal 14 serves as the gate of the second transistor T2.
  • the sixth transistor T6 can be tested in the same way.
  • the fourth detection control terminal 14 connected to the scan signal line and the second detection control terminal 12 connected to the reset signal (Reset) line maintain a low potential to turn on the eighth transistor.
  • the transistor T8 and the second transistor T2 the first detection control terminal 11 can be used as the first pole of the sixth transistor T6 via the eighth transistor T8 and the second transistor T2, and the second detection output terminal 16 can be used as the second pole of the sixth transistor T6.
  • the third detection control terminal 13 can be used as the gate of the sixth transistor T6 to form a path for characteristic testing of T6.
  • the eighth transistor T8 can be tested.
  • the low level of the third detection control terminal 13 and the fourth detection control terminal 14 turns on the second transistor T2 and the sixth transistor T6, and the second detection control terminal 12 serves as the eighth transistor T8.
  • the first detection control terminal 11 serves as the first pole of the eighth transistor T8, and the second detection output terminal 16 serves as the second pole of the eighth transistor T8 via the sixth transistor T6 and the second transistor T2.
  • the test input/output detection terminal is not designed on the data line. Therefore, in the embodiment of the present disclosure, the data line is used as two adjacent pixel rows ( Taking the n-th row and the n+1-th row as an example), the transistors in two adjacent pixel rows are combined together to form the circuit structure of the detection path as shown in FIG. 8.
  • the fourth detection control terminal 14 in the n+1th row applies a low-level signal to turn on the fifth transistor T5(n) in the nth row, the fourth transistor T4(n+1) in the n+1th row and The fifth transistor T5(n+1).
  • the first detection output terminal 15 in the n+1th row passes through the fifth transistor T5(n+1) in the n+1th row and the fourth transistor T4(n+ 1)
  • the first detection output terminal 15 in the nth row can be used as the fourth transistor in the nth row via the fifth transistor T5(n) in the nth row
  • the second pole of T4(n) and the fourth detection control terminal 14 in the nth row serve as the gate of the fourth transistor T4(n) in the nth row.
  • the probe is connected to the corresponding detection terminal, and the performance test of T4 in the nth row can be performed.
  • the fourth detection control terminal 14 in the nth row, the third detection control terminal 13 in the n+1th row, and the fourth detection control terminal 14 apply low-level signals to conduct Pass the fourth transistor T4(n) in the nth row, the fifth transistor T5(n+1) and the fourth transistor T4(n+1) in the n+1th row, and the first detection output terminal in the n+1th row 15
  • the fifth transistor T5(n+1) and the fourth transistor T4(n+1) in the n+1th row and the fourth transistor T4(n) in the nth row are used as the fifth transistor T5(n )
  • the first detection output terminal 15 in the nth row is used as the second electrode of the fifth transistor T5(n) in the nth row
  • the third detection control terminal 13 in the nth row is used as the fifth transistor in the nth row
  • the gate of T5(n) constitutes the detection path of the fifth transistor T5. In Table 1, the above-mentioned detection paths
  • the metal pad of the TFT test point is designed on the same layer as the anode layer of the metal layer on the uppermost layer of the TFT, and the metal pad is prevented from TFT or newly added TFT isolation to avoid storage capacitors, data lines, and other special locations to be tested. Coupling to form a structure for TFT testing. By cutting off part of the metal line, a test path is formed between the test pixel or the separated pixel, and a voltage is applied to the test metal Pad (Gate/EM/Reset/Vinit AND) to control the turn-on and turn-off of the pixel circuit.
  • test metal detection Terminal In the test metal detection Terminal (Vinit AND/Vdd/AND) input or detect signal changes to test the characteristics of each TFT in the pixel circuit.
  • the detection method according to the embodiment of the present disclosure can realize a more convenient, high success rate, and high accuracy test.

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Abstract

一种像素电路（100）与像素电路（100）的检测方法，像素电路（100）包括：发光元件（106）、存储电容、驱动子电路（101）、复位子电路（102）、写入子电路（103）、发光控制子电路（104）和检测元件（105），检测元件（105）的控制端与复位控制信号线（Reset）连接，检测元件（105）的第一端与复位信号线（Vinit）连接，检测元件（105）的第二端与驱动子电路（101）连接，配置为对像素电路（100）中所包括的元件进行检测。

Description

像素电路与检测方法
本申请要求于2019年11月28日提交的、申请号为201911190017.7的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明涉及显示技术领域，尤其是涉及一种像素电路与检测方法。
背景技术
LTPS AMOLED显示面板的驱动部分由多个薄膜晶体管TFT(Thin Film Transistor)构成，这些TFT的性能直接影响显示面板的显示效果。因此，TFT的性能测试在显示面板在生产制造中非常重要。
发明内容
本发明的目的在于提供一种至少解决上述问题的检测LTPS AMOLED显示面板的TFT特性的电路与方法。
本公开的实施例提供了一种像素电路，包括：发光元件；驱动子电路，配置为产生用于使所述发光元件发光的电流；复位子电路，配置为从复位控制信号线接收复位控制信号和从复位信号线接收复位信号，以及在所述复位控制信号的作用下，利用所述复位信号对所述驱动子电路和所述发光元件的阳极进行复位；写入子电路，配置为从数据线接收数据信号和从扫描信号线接收扫描信号，以及在所述扫描信号的作用下，将所述数据信号提供给所述驱动子电路；发光控制子电路，配置为从第一电源线接收第一电源电压和从发光信号线接收发光控制信号，以及在所述发光控制信号的作用下，将所述第一电源电压提供给所述驱动子电路以及将所述驱动子电路产生的电流提供给所述发光元件的阳极；以及检测元件，所述检测元件的控制端与所述复位控制信号线连接，所述检测元件的第一端与所述复位信号线连接，所述检测元件的第二端与所述驱动子电路连接，配置为对像素电路中所包括的元件进行检测。
进一步地，像素电路还包括多个检测端，包括检测控制端和检测输出端，配置为为经由所述检测控制端施加检测控制信号，并经由所述检测输出端获取检测输出信号，以 便根据所述检测输出信号对像素电路中所包括的元件进行检测。
进一步地，检测控制端包括与所述复位信号线连接的第一检测控制端、与所述复位控制信号线连接的第二检测控制端、与所述发光控制信号线连接的第三检测控制端和与所述扫描信号线连接的第四检测控制端；所述检测输出端包括与所述第一电源线连接的第一检测输出端和与所述发光元件的阳极连接的第二检测输出端。
进一步地，多个检测端设置在与所述发光元件的阳极所在的层相同的层中。
进一步地，驱动子电路包括驱动晶体管和存储电容，其中，所述存储电容的第一极连接所述第一电源线，所述存储电容的第二极连接所述驱动晶体管的栅极和所述检测元件的第二端，所述驱动晶体管的第一极和第二极均连接至所述发光控制子电路。
进一步地，复位子电路包括第一晶体管和第七晶体管,其中，所述第一晶体管的栅极连接所述复位控制信号线，所述第一晶体管的第一极连接所述检测元件的第二端；所述第一晶体管的第二极连接所述复位信号线，所述第七晶体管的栅极连接所述扫描信号线，所述第七晶体管的第一极连接所述发光元件的阳极，所述第七晶体管的第二极连接所述复位信号线。
进一步地，写入子电路包括第二晶体管和第四晶体管，其中，所述第二晶体管和所述第四晶体管的栅极均连接所述扫描信号线,所述第二晶体管的第一极连接所述驱动晶体管的第二极，所述第二晶体管的第二极连接所述驱动晶体管的栅极；所述第四晶体管的第一极连接所述数据信号线，所述第四晶体管的第二极连接所述驱动晶体管的第一极。
进一步地，发光控制子电路包括第五晶体管和第六晶体管，其中，所述第五晶体管和所述第六晶体管的栅极均连接所述发光控制信号线，所述第五晶体管的第一极连接所述第一电源线，所述第五晶体管的第二极连接所述驱动晶体管的第一极；所述第六晶体管的第一极连接所述驱动晶体管的第二极，所述第六晶体管的第二极连接所述发光元件的阳极，所述发光元件的阴极连接第二电源线。
进一步地，检测元件包括第八晶体管，所述第八晶体管的栅极作为所述检测元件的控制端，所述第八晶体管的第一极和第二极分别作为所述检测元件的第一端和第二端。
本公开的实施例还提供了像素电路的检测方法，包括：切断所述像素电路中指定位置处的布线，以得到包括所述像素电路的至少一个指定元件的检测通路；利用所述检测通路对所述至少一个指定元件进行检测。
进一步地，利用所述检测通路对所述至少一个指定元件进行检测包括：根据所述至 少一个指定元件中待测的指定元件，从检测控制端和检测输出端中确定至少一个检测控制端和检测输出端；经由所确定的至少一个检测控制端向所述检测通路施加检测控制信号；以及经由所确定的检测输出端获取检测输出信号，并根据所述检测输出信号对所述待测的指定元件进行检测。
进一步地，检测通路包括驱动晶体管、第五晶体管、第六晶体管和第八晶体管，所述利用所述检测通路对所述至少一个指定元件进行检测包括：在检测驱动晶体管时：以第一检测控制端作为所述驱动晶体管的栅极，以第一检测输出端作为所述驱动晶体管的源极，以第二检测输出端作为所述驱动晶体管的漏极；在检测第五晶体管时，以第三检测控制端作为所述第五晶体管的栅极，以第一检测输出端作为所述第五晶体管的第一极，以第二检测输出端作为所述第五晶体管的第二极；在检测第六晶体管时，以第三检测控制端作为所述第六晶体管的栅极，以第一检测输出端作为所述第六晶体管的第一极，以第二检测输出端作为所述第六晶体管的第二极。
进一步地，所述检测通路包括第一晶体管和第八晶体管以及相邻像素行的第七晶体管，所述利用所述检测通路对所述至少一个指定元件进行检测包括：在检测第一晶体管或第八晶体管时，以第二检测控制端作为所述第一晶体管和所述第八晶体管的栅极，以第一检测控制端作为所述第一晶体管和所述第八晶体管的第一极，以相邻像素行的第二检测输出端作为所述第一晶体管和所述第八晶体管的第二极；在检测相邻像素行的第七晶体管时，以第四检测控制端作为所述第七晶体管的栅极，以第一检测控制端作为所述第七晶体管的第一极，以相邻像素行的第二检测输出端作为所述第七晶体管的第二极。
进一步地，所述检测通路包括第二晶体管、第六晶体管和第八晶体管，所述利用所述检测通路对所述至少一个指定元件进行检测包括：在检测第二晶体管时，以第四检测控制端作为所述第二晶体管的栅极，以第二检测输出端作为所述第二晶体管的第一极，以第一检测控制端作为所述第二晶体管的第二极；在检测第六晶体管时，以第三检测控制端作为所述第六晶体管的栅极，以第一检测控制端作为所述第六晶体管的第一极，以第二检测输出端作为所述第六晶体管的第二极；在检测第八晶体管时，以第二检测控制端作为所述第八晶体管的栅极，以第一检测控制端作为所述第八晶体管的第一极，以第二检测输出端作为所述第八晶体管的第二极。
进一步地，所述检测通路包括分别位于相邻的第一像素行和第二像素行的第四 晶体管和分别位于所述第一像素行和所述第二像素行的第五晶体管，所述利用所述检测通路对所述至少一个指定元件进行检测包括：在检测第一像素行的第四晶体管时，以第一像素行的第四检测控制端经作为所述第四晶体管的栅极，以第二像素行的第一检测输出端作为所述第四晶体管的第一极，以第一像素行的第一检测输出端作为所述第四晶体管的第二极；在检测第一像素行的第五晶体管时，以第一像素的第三检测控制端作为所述第五晶体管的栅极，以第一像素行的第一检测输出端作为所述第五晶体管的第一极，以第二像素行的第一检测输出端作为所述第五晶体管的第二极。
根据本公开实施例的像素电路，在对像素电路中所包括的元件进行检测时，只需去除像素界定层PDL(Pixel Definition Layer)的有机材料，这些有机材料相比于有机与无机复合膜层更易去除，具有更高的制样成功率。同时这种结构设计只需要将探针直接搭接在用于测试的金属检测端(Pad)上即可，相比于FIB搭接方法更加稳定，准确率更高，对于解析与TFT特性相关的不良有重要作用。
同时，根据本公开实施例的像素电路，可以对像素电路中所包括的各个TFT进行测试。并且可以利用检测元件增加一条对存储电容进行复位的路径，优化复位效果，有利于改善闪烁与残像等。
附图说明
图1是本公开实施例的像素电路的结构示意图；
图2是本公开实施例的检测端的布局示意图；
图3是本公开实施例的像素电路的电路图；
图4是本公开实施例的检测方法的流程图；
图5是本公开实施例的检测通路的第一结构图；
图6是本公开实施例的检测通路的第二结构图；
图7是本公开实施例的检测通路的第三结构图；
图8是本公开实施例的检测通路的第四结构图。
具体实施方式
为了使本技术领域人员更好的理解本公开的实施例，下面结合附图和实施方法对本公开的实施例作进一步的详细描述，需要说明的是，在不冲突的情况下，本申请中的实 施例和实施例中的特征可以相互任意组合。
图1是本公开实施例的像素电路的结构示意图。如图1所示，本公开实施例的像素电路100用于对LTPS AMOLED显示面板的像素区中的TFT的特性进行检测。如图1所示，像素电路100包括驱动子电路101、复位子电路102、写入子电路103、发光控制子电路104、检测元件105和发光元件106。
根据实施例，驱动子电路101被配置为产生用于使发光元件106发光的电流。复位子电路102被配置为从复位控制信号线接收复位控制信号(Reset)和从复位信号线接收复位信号(Vinit)，以及在复位控制信号的作用下，利用复位信号对驱动子电路101和发光元件106的阳极进行复位。从而使得后续阶段中的数据信号可以被更迅速、更可靠地存储。同时，可以使发光元件在发光之前显示为黑态，可改善采用上述像素电路的显示装置的对比度等显示效果。写入子电路103被配置为从数据线接收数据信号(Data)和从扫描信号线接收扫描信号(Gate)，以及在扫描信号的作用下，将数据信号提供给驱动子电路101。发光控制子电路104被配置为从第一电源线接收第一电源电压(VDD)和从发光信号线接收发光控制信号(EM)，以及在发光控制信号的作用下，将第一电源电压提供给驱动子电路101以及将驱动子电路101产生的电流提供给发光元件106的阳极。检测元件105的控制端与复位控制信号线连接，检测元件105的第一端与复位信号线连接，检测元件的第二端与驱动子电路101连接，配置为对像素电路100中所包括的元件进行检测。发光元件106的阳极和阴极分别连接第一电源电压VDD(例如，高电平电压)和第二电源电压VSS(例如，低电平电压)，从而使得发光元件在驱动子电路101所产生的驱动电流的作用下发光。
根据实施例，在与发光元件106的阳极所在的层相同的层中还设置有多个检测端。多个检测端包括检测控制端和检测输出端。根据实施例，可以经由检测控制端施加检测控制信号，并经由检测输出端获取检测输出信号，以便根据检测输出信号对像素电路中所包括的元件进行检测。
图2是本公开实施例的检测端的布局示意图。如图2所示，检测控制端包括第一检测控制端11，其设置为与复位信号(Vinit)线连接，且与检测元件的第一端连接。第二检测控制端12，其设置为与复位信号(Reset)线连接，即与前一级像素电路的扫描信号(Gate n-1)线连接。第三检测控制端13，其设置为与发光控制信号(EM)线连接。以及第四检测控制端14，其设置为与扫描信号(Gate n)线连接。检测输出端包括第一 检测输出端15，其设置为与第一电源(VDD)线连接。以及第二检测输出端16，其设置为与发光元件OLED的阳极连接。
根据实施例，第一检测控制端11至第四检测控制端14以及第一检测输出端15和第二检测输出端16均形成在基板最上方的OLED阳极层。更优选地，多个像素电路的第一检测控制端11通过在基板最上方的OLED阳极层设置的金属导线连接。具体地，在阳极层上设计金属检测端的图案，通过光刻、刻蚀等工艺，形成检测端和过孔链接点，实现上述连接关系。
采用这样的结构，第一检测控制端11至第四检测控制端14与第一检测控制端11、第一检测输出端15和第二检测输出端16可以形成“4控制端+3输入/输出端”结构，可以通过多个检测端的配合实现对电路内部多个晶体管的特性的测试。
图3是本公开实施例的像素电路的电路图。在图3中，以7T1C像素驱动电路为例进行说明。容易理解的是，可以采用其他常见的如6T1C、6T2C、5T1C和4T1C等像素驱动电路的结构，图3仅为示例，并不用于限定本公开的实施例。
如图3所示，驱动子电路包括驱动晶体管DTFT和存储电容Cst。存储电容Cst的第一极连接第一电源(VDD)线，存储电容Cst的第二极连接驱动晶体管DTFT的栅极和检测元件的第二端，驱动晶体管DTFT的第一极和第二极均连接至发光控制子电路。驱动晶体管DTFT的栅极与存储电容Cst的第二极可在复位控制信号(Reset)的控制下释放电量。
如图3所示，检测元件可以包括第八晶体管T8，第八晶体管T8的栅极作为检测元件的控制端，第八晶体管T8的第一极和第二极分别作为检测元件的第一端和第二端。第八晶体管T8可以与像素电路中的其他晶体管同时形成，但是在其他晶体管使用时不参与工作，因此，第八晶体管T8不会影响电路的性能。
并且，由于采用了晶体管T8的结构，可以优化存储电容Cst的复位功能，同时在不影响电路的工作状态的前提下，可作为驱动晶体管DTFT测试的栅极控制端。尤其是晶体管T8的第一极与复位电压Vinit连接，可以更好地泄放存储电容Cst和驱动晶体管DTFT的电量。
第八晶体管T8的第一极连接第一检测控制端11，第二极连接驱动晶体管DTFT的栅极，第八晶体管T8的栅极连接第二检测控制端12。
需要说明的是，在7T1C、6T1C、6T2C、5T1C和4T1C电路中，只要是驱动晶体管 的栅极可以经由复位信号线放电的方案，均可以采用本公开的发明构思来实现，即新增一个晶体管T8，并将T8的栅极与复位控制信号线连接，且T8的第二极与该驱动晶体管栅极连接。
如图3所示，复位子电路包括第一晶体管T1和第七晶体管T7。第一晶体管T1的栅极连接复位控制信号Reset(即前一级像素电路的扫描信号Gate n-1)，第一晶体管T1的第一极连接第八晶体管T8的第二极、驱动晶体管DTFT的栅极和存储电容Cst的第一极。第一晶体管T1的第二极连接复位信号Vinit。第七晶体管T7的栅极连接扫描信号Gate n，T7的第一极连接发光元件OLED的阳极，第二极连接复位信号Vinit。
写入子电路包括第二晶体管T2和第四晶体管T4。第二晶体管T2和第四晶体管T4的栅极均连接扫描信号Gate n,第二晶体管T2的第一极连接驱动晶体管DTFT的第二极，第二极连接驱动晶体管DTFT的栅极。第四晶体管T4的第一极连接数据信号Data，第二极连接驱动晶体管DTFT的第一极。
发光控制子电路包括第五晶体管T5和第六晶体管T6。第五晶体管T5和第六晶体管T6的栅极均连接发光控制信号EM，第五晶体管T5的第一极连接第一电源VDD，第二极连接驱动晶体管DTFT的第一极。第六晶体管T6的第一极连接驱动晶体管DTFT的第二极，第二极连接发光元件OLED的阳极。
在像素电路进行正常显示工作时：
在第一时段中，前一级像素电路的扫描信号Gate n-1(即本级像素电路的复位控制信号)和本级的扫描信号Gate n使得第一晶体管T1和第七晶体管T7导通，使得存储电容Cst和发光元件OLED的阳极的与复位信号线连通，电量进行释放。
在第二时段中，扫描信号Gate n使得第四晶体管T4、第二晶体管导通T2，数据电压通过第四晶体管T4、驱动晶体管DTFT和第二晶体管T2写入存储电容Cst。
在第三时段中，发光控制信号EM使得第五晶体管T5和第六晶体管T6导通，电源VDD通过第五晶体管、驱动晶体管DTFT、第六晶体管T6施加到发光元件OLED阳极，进而使得发光元件OLED发光。
当需要对晶体管特性进行检测时，则根据需要对电路的部分进行切断，将部分晶体管从电路中断开，利用剩余电路进行检测。图4是本公开实施例的检测方法400的流程图。如图4所示，检测方法400包括以下步骤：
在步骤S410中，切断像素电路中指定位置处的布线，以得到包括像素电路的至少 一个指定元件的检测通路。
在步骤S420中，利用检测通路对至少一个指定元件进行检测。
根据实施例，利用检测通路对至少一个指定元件进行检测包括：根据至少一个指定元件中待测的指定元件，从检测控制端和检测输出端中确定至少一个检测控制端和检测输出端，经由所确定的至少一个检测控制端向检测通路施加检测控制信号，以及经由所确定的检测输出端获取检测输出信号，并根据检测输出信号对待测的指定元件进行检测。图5至图8分别示出了本公开实施例的检测通路的结构图。下面结合图5至图8详细说明利用检测通路对至少一个指定元件进行检测的过程。
1.测试驱动晶体管DTFT、第五晶体管T5、第六晶体管T6
当需要测试驱动晶体管DTFT、第五晶体管T5或第六晶体管T6时，切断部分线路，以将第一晶体管T1、第二晶体管T2、第四晶体管T4和第七晶体管T7从线路上断开，形成如图5所示的检测通路的电路结构，在该检测通路中，包括驱动晶体管DTFT、第五晶体管T5、第六晶体管T6和第八晶体管T8。
如测试驱动晶体管DTFT，在与发光控制信号(EM)线连接的第三检测控制端13和与复位控制信号(Reset)线连接的第二检测控制端12施加低电平信号，进而导通第八晶体管T8、第五晶体管T5和第六晶体管T6。如图5所示，第一检测控制端11经第八晶体管T8可作驱动晶体管DTFT的栅极，第一检测输出端15经第五晶体管T5作驱动晶体管DTFT的源极，第二检测输出端16经第六晶体管T6作驱动晶体管DTFT的漏极。将探针搭接到对应检测端上，便可以进行DTFT的性能测试。常规的TFT特性评价包括但不限于：TFT的转移特性曲线Id～Vg和输出特性曲线Id～Vd、以及TFT特性参数(如阈值电压、迁移率、关态漏电流等)。
如需要测试第五晶体管T5或第六晶体管T6，第一检测控制端11和第二检测控制端12保持低电位，以导通第八晶体管T8与驱动晶体管DTFT。第三检测控制端13可作第五晶体管T5/第六晶体管T6的栅极，第一检测输出端15(或经第五晶体管T5)作第五晶体管T5(或第六晶体管T6)的第一极，例如源极，第二检测输出端16(或经第六晶体管T6)作第六晶体管T6(或第五晶体管T5)的第二极，例如漏极，由此构成T5/T6特性测试通路。
2.测试第一晶体管T1、第七晶体管T7、第八晶体管T8
当需要测试第一晶体管T1、第七晶体管T7或第八晶体管T8时，切断部分线路， 以将第二晶体管T2至第六晶体管T6和存储电容Cst从线路上断开，并切断第一晶体管T1、第七晶体管T7的第二极与复位信号线的电连接，形成如图6所示的检测通路的电路结构，在该检测通路中，包括第一晶体管T1、第七晶体管T7和第八晶体管T8。
需要说明的是，在该检测通路中，第一晶体管T1和第八晶体管T8位于相同的像素行，而第七晶体管T7位于与第一晶体管T1和第八晶体管T8所在像素行相邻的前一像素行中，这是因为制造工艺的原因，使得与当前像素行(第n行)中的第一晶体管T1(n)和第八晶体管T8(n)邻近布置的是前一像素行(第n-1行)中的第七晶体管T7(n-1)，而当前像素行(第n行)中的第七晶体管T7(n)位于后一像素行(第n+1行)中的第一晶体管T1(n+1)和第八晶体管T8(n+1)附近。
测试时，第二检测控制端12作为第一晶体管T1和第八晶体管T8的栅极，第一检测控制端11作为第一晶体管T1和第八晶体管T8的第一极，相邻像素行(第n-1行)的第二检测输出端16作为第二极。探针搭接到对应检测端上，便可以进行第一晶体管T1或第八晶体管的性能测试。
第四检测控制端14作为第七晶体管T7的栅极，第一检测控制端11作为第七晶体管T7的第一极，相邻像素行(第n-1行)的第二检测输出端16作为第二极。探针搭接到对应检测端上，便可以进行第七晶体管T7的性能测试。
3.测试第二晶体管T2、第六晶体管T6、第八晶体管T8
当需要测试第二晶体管T2、第六晶体管T6或第八晶体管T8时，切断部分线路，以将第一晶体管T1、驱动晶体管DTFT以及第四晶体管T4、第五晶体管T5、第七晶体管T7和存储电容Cst从线路上断开，并切断第一晶体管T1、第七晶体管T7的第二极与复位信号线的电连接，形成如图7所示的检测通路的电路结构，在该检测通路中，包括第二晶体管T2、第六晶体管T6和第八晶体管T8。
如测试T2，与发光控制信号(EM)线连接的第三检测控制端13、与复位信号(Reset)线连接的第二检测控制端12施加低电平信号，进而导通第八晶体管T8和第六晶体管T6，第一检测控制端11经第八晶体管T8可作第二晶体管T2的第一极，第二检测输出端16经第六晶体管T6可作第二晶体管T2的第二极，第四检测控制端14作第二晶体管T2的栅极。
利用这个电路，同理可以测试第六晶体管T6，与扫描信号线连接的第四检测控制端14和与复位信号(Reset)线连接的第二检测控制端12保持低电位，以导通第八晶体 管T8与第二晶体管T2，第一检测控制端11经第八晶体管T8、第二晶体管T2可作第六晶体管T6的第一极，第二检测输出端16作第六晶体管T6第二极，第三检测控制端13可作第六晶体管T6栅极，构成用于对T6进行特性测试的通路。
同理可测试第八晶体管T8，第三检测控制端13和第四检测控制端14的低电平导通第二晶体管T2和第六晶体管T6，则第二检测控制端12作为第八晶体管T8的栅极，第一检测控制端11作为第八晶体管T8的第一极，第二检测输出端16经第六晶体管T6和第二晶体管T2作为第八晶体管T8的第二极。
探针搭接到对应检测端上，便可以进行T2/T6/T8的性能测试。
4.测试第四晶体管T4、第五晶体管T5
当需要测试第四晶体管T4、第五晶体管T5时，切断部分线路，将第一晶体管T1、第二晶体管T2、第六晶体管T6、第七晶体管T7、第八晶体管T8、驱动驱动晶体管DTFT和存储电容Cst从线路上断开。在本公开的实施例中，为了降低数据线上的耦合，未在数据线上设计测试输入/输出检测端，因此，在本公开的实施例中，利用数据线作两个相邻像素行(以第n行和第n+1行为例说明)的链接线，使得两个相邻像素行中的晶体管组合在一起，形成如图8所示的检测通路的电路结构。
如需测试第n行(第一像素行)的第四晶体管T4(n)，则第n行的第三检测控制端13、第n+1行(第二像素行)第三检测控制端13、第n+1行的第四检测控制端14施加低电平信号，以导通第n行的第五晶体管T5(n)、第n+1行的第四晶体管T4(n+1)和第五晶体管T5(n+1)。当检测第n行的第四晶体管T4(n)时，第n+1行的第一检测输出端15经第n+1行第五晶体管T5(n+1)和第四晶体管T4(n+1)作第n行的第四晶体管T4(n)的第一极，第n行的第一检测输出端15经第n行的第五晶体管T5(n)可作第n行的第四晶体管T4(n)的第二极，第n行的第四检测控制端14作第n行的第四晶体管T4(n)的栅极。探针搭接到对应检测端上，便可以进行第n行的T4的性能测试。
如需测试第n行的第五晶体管T5，则第n行的第四检测控制端14、第n+1行第三检测控制端13、第四检测控制端14施加低电平信号，以导通第n行的第四晶体管T4(n)、第n+1行的第五晶体管T5(n+1)和第四晶体管T4(n+1)，第n+1行的第一检测输出端15经第n+1行的第五晶体管T5(n+1)和第四晶体管T4(n+1)和第n行的第四晶体管T4(n)作第n行的第五晶体管T5(n)的第一极，第n行的第一检测输出端15作 第n行的第五晶体管T5(n)第二极，第n行的第三检测控制端13作第n行的第五晶体管T5(n)的栅极，构成第五晶体管T5的检测通路。在表1中，对于上述检测通路进行了汇总。
Figure PCTCN2020131773-appb-000001
表1
现有技术中，需要采用腐蚀、研磨等方法，将TFT基板上的有机与无机绝缘层去除，或采用聚焦离子束FIB挖孔搭接的方式，再通过探针搭接到TFT的源极、漏极、栅极来测试TFT。但由于复合膜层腐蚀精度、机械研磨精度难以掌控到微米级别，因此测试成功率极低。此外，在进行FIB搭接时，由于镀铂或搭接效果难以确认，测试结果浮动很大，准确率不足。
本公开实施例通过在TFT最上层的金属层阳极层同层设计TFT测试点的金属Pad，并使金属Pad避开TFT或新增TFT隔离，规避存储电容、数据线等特殊位置被测试金属Pad耦合，形成TFT测试的结构。通过截断部分金属线，在测试像素或与相离像素形成测试通路，并在测试金属Pad(Gate/EM/Reset/Vinit AND)上施加电压控制像素电路的导通与关断，在测试金属检测端(Vinit AND/Vdd/AND)输入或检出信号变化，来测试像素电路内各个TFT的特性。根据本公开实施例的检测方法可实现更加方便、成功率高、准确性高的测试。
以上描述仅为本申请的较佳实施例以及对所运用技术原理的说明。本领域技术人员应当理解，本申请中所涉及的公开范围，并不限于上述技术特征的特定组合而成的技术 方案，同时也应涵盖在不脱离前述公开构思的情况下，由上述技术特征或其等同特征进行任意组合而形成的其它技术方案。例如上述特征与本申请中公开的(但不限于)具有类似功能的技术特征进行互相替换而形成的技术方案。

Claims (15)

  1. 一种像素电路，包括：
    发光元件；
    驱动子电路，配置为产生用于使所述发光元件发光的电流；
    复位子电路，配置为从复位控制信号线接收复位控制信号和从复位信号线接收复位信号，以及在所述复位控制信号的作用下，利用所述复位信号对所述驱动子电路和所述发光元件的阳极进行复位；
    写入子电路，配置为从数据线接收数据信号和从扫描信号线接收扫描信号，以及在所述扫描信号的作用下，将所述数据信号提供给所述驱动子电路；
    发光控制子电路，配置为从第一电源线接收第一电源电压和从发光信号线接收发光控制信号，以及在所述发光控制信号的作用下，将所述第一电源电压提供给所述驱动子电路以及将所述驱动子电路产生的电流提供给所述发光元件的阳极；以及
    检测元件，所述检测元件的控制端与所述复位控制信号线连接，所述检测元件的第一端与所述复位信号线连接，所述检测元件的第二端与所述驱动子电路连接，配置为对像素电路中所包括的元件进行检测。
  2. 根据权利要求1所述的电路，还包括：
    多个检测端，包括检测控制端和检测输出端，配置为经由所述检测控制端施加检测控制信号，并经由所述检测输出端获取检测输出信号，以便根据所述检测输出信号对像素电路中所包括的元件进行检测。
  3. 根据权利要求2所述的电路，其中：
    所述检测控制端包括与所述复位信号线连接的第一检测控制端、与所述复位控制信号线连接的第二检测控制端、与所述发光控制信号线连接的第三检测控制端和与所述扫描信号线连接的第四检测控制端；
    所述检测输出端包括与所述第一电源线连接的第一检测输出端和与所述发光元件的阳极连接的第二检测输出端。
  4. 根据权利要求2或3所述的电路，其中：所述多个检测端设置在与所述发光元件的阳极所在的层相同的层中。
  5. 根据权利要求1至4中任一项所述的电路，其中，所述驱动子电路包括驱动 晶体管和存储电容，其中，所述存储电容的第一极连接所述第一电源线，所述存储电容的第二极连接所述驱动晶体管的栅极和所述检测元件的第二端，所述驱动晶体管的第一极和第二极均连接至所述发光控制子电路。
  6. 根据权利要求5所述的电路，其中，所述复位子电路包括第一晶体管和第七晶体管,其中，所述第一晶体管的栅极连接所述复位控制信号线，所述第一晶体管的第一极连接所述检测元件的第二端，所述第一晶体管的第二极连接所述复位信号线，所述第七晶体管的栅极连接所述扫描信号线，所述第七晶体管的第一极连接所述发光元件的阳极，所述第七晶体管的第二极连接所述复位信号线。
  7. 根据权利要求5所述的电路，其中，所述写入子电路包括第二晶体管和第四晶体管，其中，所述第二晶体管和所述第四晶体管的栅极均连接所述扫描信号线,所述第二晶体管的第一极连接所述驱动晶体管的第二极，所述第二晶体管的第二极连接所述驱动晶体管的栅极；所述第四晶体管的第一极连接所述数据信号线，所述第四晶体管的第二极连接所述驱动晶体管的第一极。
  8. 根据权利要求5所述的电路，其中，所述发光控制子电路包括第五晶体管和第六晶体管，其中，所述第五晶体管和所述第六晶体管的栅极均连接所述发光控制信号线，所述第五晶体管的第一极连接所述第一电源线，所述第五晶体管的第二极连接所述驱动晶体管的第一极；所述第六晶体管的第一极连接所述驱动晶体管的第二极，所述第六晶体管的第二极连接所述发光元件的阳极，所述发光元件的阴极连接第二电源线。
  9. 根据权利要求1所述的电路，其中，所述检测元件包括第八晶体管，所述第八晶体管的栅极作为所述检测元件的控制端，所述第八晶体管的第一极和第二极分别作为所述检测元件的第一端和第二端。
  10. 一种基于权利要求1至9中任一项所述的像素电路的检测方法，包括：
    切断所述像素电路中指定位置处的布线，以得到包括所述像素电路的至少一个指定元件的检测通路；
    利用所述检测通路对所述至少一个指定元件进行检测。
  11. 根据权利要求10所述的方法，其中，利用所述检测通路对所述至少一个指定元件进行检测包括：
    根据所述至少一个指定元件中待测的指定元件，从检测控制端和检测输出端中确定至少一个检测控制端和检测输出端；
    经由所确定的至少一个检测控制端向所述检测通路施加检测控制信号；以及
    经由所确定的检测输出端获取检测输出信号，并根据所述检测输出信号对所述待测的指定元件进行检测。
  12. 根据权利要求11所述的方法，其中，所述检测通路包括驱动晶体管、第五晶体管、第六晶体管和第八晶体管，所述利用所述检测通路对所述至少一个指定元件进行检测包括：
    在检测驱动晶体管时，以第一检测控制端作为所述驱动晶体管的栅极，以第一检测输出端作为所述驱动晶体管的源极，以第二检测输出端作为所述驱动晶体管的漏极；
    在检测第五晶体管时，以第三检测控制端作为所述第五晶体管的栅极，以第一检测输出端作为所述第五晶体管的第一极，以第二检测输出端作为所述第五晶体管的第二极；
    在检测第六晶体管时，以第三检测控制端作为所述第六晶体管的栅极，以第一检测输出端作为所述第六晶体管的第一极，以第二检测输出端作为所述第六晶体管的第二极。
  13. 根据权利要求11所述的方法，其中，所述检测通路包括第一晶体管和第八晶体管以及相邻像素行的第七晶体管，所述利用所述检测通路对所述至少一个指定元件进行检测包括：
    在检测第一晶体管或第八晶体管时，以第二检测控制端作为所述第一晶体管和所述第八晶体管的栅极，以第一检测控制端作为所述第一晶体管和所述第八晶体管的第一极，以相邻像素行的第二检测输出端作为所述第一晶体管和所述第八晶体管的第二极；
    在检测相邻像素行的第七晶体管时，以第四检测控制端作为所述第七晶体管的栅极，以第一检测控制端作为所述第七晶体管的第一极，以相邻像素行的第二检测输出端作为所述第七晶体管的第二极。
  14. 根据权利要求11所述的方法，其中，所述检测通路包括第二晶体管、第六晶体管和第八晶体管，所述利用所述检测通路对所述至少一个指定元件进行检测包括：
    在检测第二晶体管时，以第四检测控制端作为所述第二晶体管的栅极，以第二检测输出端作为所述第二晶体管的第一极，以第一检测控制端作为所述第二晶体管 的第二极；
    在检测第六晶体管时，以第三检测控制端作为所述第六晶体管的栅极，以第一检测控制端作为所述第六晶体管的第一极，以第二检测输出端作为所述第六晶体管的第二极；
    在检测第八晶体管时，以第二检测控制端作为所述第八晶体管的栅极，以第一检测控制端作为所述第八晶体管的第一极，以第二检测输出端作为所述第八晶体管的第二极。
  15. 根据权利要求11所述的方法，其中，所述检测通路包括分别位于相邻的第一像素行和第二像素行的第四晶体管和分别位于所述第一像素行和所述第二像素行的第五晶体管，所述利用所述检测通路对所述至少一个指定元件进行检测包括：
    在检测第一像素行的第四晶体管时，以第一像素行的第四检测控制端作为所述第四晶体管的栅极，以第二像素行的第一检测输出端作为所述第四晶体管的第一极，以第一像素行的第一检测输出端作为所述第四晶体管的第二极；
    在检测第一像素行的第五晶体管时，以第一像素行的第三检测控制端作为所述第五晶体管的栅极，以第一像素行的第一检测输出端作为所述第五晶体管的第一极，以第二像素行的第一检测输出端作为所述第五晶体管的第二极。
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