WO2021103853A1 - 显示基板和显示装置 - Google Patents

显示基板和显示装置 Download PDF

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Publication number
WO2021103853A1
WO2021103853A1 PCT/CN2020/122092 CN2020122092W WO2021103853A1 WO 2021103853 A1 WO2021103853 A1 WO 2021103853A1 CN 2020122092 W CN2020122092 W CN 2020122092W WO 2021103853 A1 WO2021103853 A1 WO 2021103853A1
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Prior art keywords
area
gate line
orthographic projection
base substrate
gate
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PCT/CN2020/122092
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English (en)
French (fr)
Inventor
尚庭华
周洋
罗正位
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京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Priority to US17/311,889 priority Critical patent/US11984458B2/en
Publication of WO2021103853A1 publication Critical patent/WO2021103853A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1218—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or structure of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a display substrate and a display device.
  • an embodiment of the present disclosure provides a display substrate, which is characterized by comprising a display area and a frame area located at the periphery of the display area, wherein the display area includes a first area and a second area, and the second area The number of sub-pixels connected to each gate line in a region is less than the number of sub-pixels connected to each gate line in the second region;
  • the display substrate includes signal lines arranged in the frame area, the orthographic projection of each gate line in the first area on the base substrate of the display substrate and the signal line on the substrate The orthographic projections on the substrate overlap, and a capacitance is formed between the signal line and the gate line in the first area to increase the load capacitance of the gate line in the first area.
  • the gate line in the first region includes a first gate line and a second gate line, the first gate line is located between the second region and the second gate line, and the first gate line
  • the number of line-connected sub-pixels is greater than the number of sub-pixels connected to the second gate line.
  • the overlapping area of the orthographic projection of the first grid line on the base substrate and the orthographic projection of the signal line on the base substrate is larger than that of the second grid line on the base substrate The overlapping area of the orthographic projection of the signal line and the orthographic projection of the signal line on the base substrate.
  • the frame area of the display substrate further includes a polysilicon layer disposed on a side of the gate line in the first area away from the signal line, wherein the polysilicon layer and the gate line in the first area
  • the wire is insulated and electrically connected to the signal wire.
  • the signal line and the polysilicon layer jointly form a first plate of the capacitor, and the gate line is a second plate of the capacitor.
  • the overlapping area of the orthographic projection of the first grid line on the base substrate and the orthographic projection of the signal line on the base substrate is equal to that of the fourth grid line on the base substrate The overlapping area of the orthographic projection of the signal line and the orthographic projection of the signal line on the base substrate.
  • the overlapping area of the orthographic projection of the first grid line on the base substrate and the orthographic projection of the polysilicon layer on the base substrate is larger than that of the second grid line on the base substrate.
  • the overlapping area of the orthographic projection of the polysilicon layer and the orthographic projection of the polysilicon layer on the base substrate is larger than that of the second grid line on the base substrate.
  • the overlapping area of the orthographic projection of the first grid line on the base substrate and the orthographic projection of the polysilicon layer on the base substrate is equal to that of the second grid line on the base substrate The overlapping area of the orthographic projection of the polysilicon layer and the orthographic projection of the polysilicon layer on the base substrate.
  • the display substrate further includes a first insulating layer, and the first insulating layer includes a first part located between the gate line and the signal line, and a second part located between adjacent gate lines, The first part is used to maintain insulation between the gate line and the signal line, and the second part is used to maintain insulation between adjacent gate lines.
  • a second insulating layer is further provided between the polysilicon layer and the gate line, and the second insulating layer is used to maintain insulation between the gate line and the polysilicon layer.
  • a via hole penetrating the second portion of the first insulating layer and the second insulating layer is opened in the display substrate, and the signal line is connected to the polysilicon layer through the via hole.
  • the shift register unit of the display substrate is located in the frame area and is located on the side of the signal line close to the display area.
  • the gate line in the first region includes a first part, a second part, and a third part, wherein the orthographic projection of the second part on the base substrate and the signal line on the backing The orthographic projections on the base substrate coincide, the first part connects the first end of the second part and the sub-pixel, and the third part connects the second end of the second part and the shift register unit.
  • a capacitance is formed between the second part of the gate line in the first area and the signal line to increase the load capacitance of the gate line in the first area.
  • the signal line is a low-level signal line.
  • the arrangement of the sub-pixels connected by the gate lines in the first region and the second region is the same.
  • embodiments of the present disclosure also provide a display device, including the display substrate as described above.
  • FIG. 1 is a schematic structural diagram of a display substrate provided by an embodiment of the disclosure
  • FIG. 2 is a schematic structural diagram of a display substrate provided by another embodiment of the present disclosure.
  • FIG. 3 is a schematic structural diagram of a display substrate provided by another embodiment of the present disclosure.
  • FIG. 4 is a waveform diagram of a gate scan signal in a case where a load capacitance is not added to the gate line in the display substrate according to another embodiment of the present disclosure
  • FIG. 5 is a waveform diagram of a gate scan signal when a load capacitance of the gate line in the display substrate is increased according to another embodiment of the present disclosure
  • FIG. 6 is a schematic diagram of a part of the structure of a first gate line and a second gate line in a display substrate provided by another embodiment of the present disclosure
  • FIG. 7 is a cross-sectional view of a frame area in a display substrate provided by another embodiment of the present disclosure.
  • FIG. 8 is a schematic diagram of a partial structure of a first gate line and a second gate line in a display substrate provided by another embodiment of the present disclosure.
  • FIG. 9 is a schematic diagram of a part of the structure of a display substrate provided by another embodiment of the present disclosure.
  • the number of sub-pixels connected to part of the gate lines in the special-shaped screen will be different from the number of sub-pixels connected to other gate lines. In this way, the load of some gate lines in the display screen is different from the load of other gate lines, resulting in part of the gate lines.
  • the signal delay of is different from the signal delay of other gate lines, which reduces the display effect of the display device.
  • the embodiments of the present disclosure provide a display substrate and a display device to solve the phenomenon that the load of some of the gate lines in the special-shaped screen is different from the load of other gate lines in the related art, which causes the signal delay of some traces to be different from the signal delay of other traces. , Improve the display effect of the display device.
  • An embodiment of the present disclosure provides a display substrate, as shown in FIG. 1, including a display area 110 and a frame area 120 located around the display area 110, wherein the display area 110 includes a first area 111 and a second area 112 , The number of sub-pixels connected to each gate line in the first region 111 is less than the number of sub-pixels connected to each gate line in the second region 112;
  • the display substrate includes a signal line 130 disposed in the frame area 120, and the orthographic projection of each gate line in the first area 111 on the base substrate of the display substrate is in line with the signal line 130.
  • the orthographic projection on the base substrate overlaps, and a capacitance is formed between the signal line 130 and the gate line in the first area 111 to increase the load capacitance of the gate line in the first area 111.
  • the load capacitance of the gate line in the first region 111 with a small number of connected sub-pixels is compensated by using the signal line 130, so that the load capacitance of the gate line in the first region 111 can be close to It is even equal to the load capacitance of the gate lines in the second region 112, so that the delays of the gate lines in the display substrate are close to ensure the display effect of the display device. Therefore, the technical solution provided by the present disclosure can ensure the display effect of the display device.
  • the number of sub-pixels connected to the gate line in the first area 111 is less than the number of sub-pixels connected to the gate line in the second area 112 quantity.
  • the arrangement of the sub-pixels connected by the gate lines in the first region and the second region is the same.
  • the types of pixels, the order of pixel arrangement, and the pitch are all the same.
  • the arrangement of the sub-pixels connected by the gate lines in the first region and the second region may also be different.
  • the types of pixels, the order of pixel arrangement, the pitch, etc. may be partly the same or completely different.
  • the frame area 120 described above is arranged around the outer contour of the display area 110, and the shape of the frame area 120 is the same as the shape of the outer contour of the display area 110.
  • the shape of the frame area 120 is the same as the shape of the outer contour of the display area 110.
  • a part of the outer contour of the display area 110 is arc-shaped, it surrounds the outer contour of the display area 110.
  • Part of the frame area 120 of the outline is also a circular arc with the same arc, wherein the corresponding part of the signal line 130 in the frame area 120 is also a circular arc.
  • the display area 110 includes a first area 111 and a second area 112, wherein the number of sub-pixels connected by the gate lines in the second area 112 are equal, and both are larger than those of the sub-pixels connected by the gate lines in the first area 111. Quantity.
  • the above-mentioned signal line can be an additional signal line added to the original frame area 120 to compensate for the load capacitance of the gate line in the first area 111, so that it does not affect the working mode of the original wiring in the frame area 120, and is compatible with multiple lines.
  • a special-shaped screen; the above-mentioned signal lines can also be used to compensate the load capacitance of the gate lines in the first area 111 through the signal lines originally laid out in the frame area 120, for example: the frame area 120 is originally laid out with low-level signals Lines, by using low-level signal lines as signal lines, the number of wiring in the frame area 120 can be reduced, which is conducive to narrowing the frame of the display device.
  • the number of gate line-connected sub-pixels in the first region 111 is less than the number of gate line-connected sub-pixels in the second region 112.
  • the load capacitance of the gate lines in the first region 111 is smaller than the load capacitance of the gate lines in the second region 112, which in turn causes the signal delay of the gate lines in the first region 111 to be as much as that of the gate lines in the second region 112. The signal delay is different, which affects the display effect of the display device.
  • the number of sub-pixels connected by multiple gate lines in the first region 111 may be the same, as shown in FIG. 2, that is, the length of each part of the first region 111 in the extending direction of the gate lines is equal; the first region 111
  • the number of sub-pixels connected by multiple gate lines in the gate line may also be different, as shown in FIG. 3, that is, the length of the first region 111 in the extending direction of the gate line is not equal; of course, a part of the sub-pixels in the first region 111 may also be
  • the number of gate lines connected to the sub-pixels in the region is the same, and the number of gate lines connected to the sub-pixels in another part of the first region 111 is different, as shown in FIG. 1, which is not limited here.
  • the signal line 130 and each gate line in the first region 111 form a capacitance, wherein, because in a period of time, only one of the multiple gate lines in the first region 111 will jump the voltage signal on the gate line. Therefore, the signal line 130 receives less disturbance in each time period, and the jump of the gate line will not affect the stability of the signal line 130.
  • the voltage on the gate line in the first region 111 will undergo a high-low jump.
  • the voltage that defines the gate scan signal jumps from 90%
  • the time taken to 10% is Tf.
  • the voltage jumps to ⁇ 7V, the jump range is 14V, and the time it takes for the voltage signal to jump from +5.6V to -5.6V is Tf; similarly, the voltage of the gate scan signal is changed from In the low-to-high transition, in the voltage transition range, the time it takes to define the voltage of the gate scan signal from 10% to 90% transition is Tr.
  • Tr the greater the number of sub-pixels connected by the gate line, the longer Tr and Tf are.
  • FIG 4 it is the waveform diagram of the gate scanning signal on the gate line when the load capacitance is not added to the gate line.
  • the upper two waveforms in Figure 4 are in the array substrate row drive technology (Gate Driver On Array, GOA for short) Two clock signals related to the gate line.
  • the waveform below is the waveform of the gate scan signal on the gate line.
  • the abscissa in Figure 4 is the time coordinate and the unit is s.
  • the ordinate in Figure 4 is the voltage coordinate and the unit is V.
  • Tr 0.43us
  • Tf 0.48us
  • the waveform diagram of the gate scan signal on the gate line when the load capacitance is added to the gate line As shown in Figure 5, the waveform diagram of the gate scan signal on the gate line when the load capacitance is added to the gate line.
  • the upper two waveforms in Figure 5 are the two clock signals related to the gate line in the GOA, and the lower waveform is
  • the abscissa in FIG. 5 is the time coordinate and the unit is s
  • the ordinate in FIG. 5 is the voltage coordinate and the unit is V.
  • Tr 0.56us
  • Tf 0.61us
  • the signal line 130 and the gate line in the first area 111 are used to form a capacitance to increase the load capacitance of the gate line in the first area 111, so that the overall load capacitance of the gate line in the first area 111 is equal to that of the gate line in the first area 111.
  • the overall load capacitance of the gate lines in the two regions 112 is the same or close to ensure that the signal delay of the gate lines in the first region 111 is the same as the signal delay of the gate lines in the second region 112 to ensure the display effect of the display device.
  • the gate lines in the first area 111 include a first gate line A and a second gate line B, and the first gate line A is located in the second area 112 and the first gate line A. Between the two gate lines B, the number of sub-pixels connected to the first gate line A is greater than the number of sub-pixels connected to the second gate line B.
  • the number of gate lines connected to the sub-pixels in the first region 111 is different, and the closer the gate line to the second region 112 is, the more the number of connected sub-pixels is, the farther away the gate line from the second region 112 is.
  • the capacitance value of the load capacitance added by the signal line 130 to the second gate line B is greater than the capacitance value of the load capacitance added by the signal line 130 to the first gate line A.
  • FIG. 6 it can be designed as: the orthographic projection of the first gate line A on the base substrate and the orthographic projection of the signal line on the base substrate
  • the overlapping area of the projection is larger than the overlapping area of the orthographic projection of the second gate line B on the base substrate and the orthographic projection of the signal line on the base substrate.
  • the overlap area between the gate line and the signal line 130 determines the overlap area between the gate line and the signal line 130.
  • the overlapping area of the first gate line A and the signal line 130 to be larger than the overlapping area of the second gate line B and the signal line 130, it can be achieved that the load capacitance increased for the first gate line A is greater than With respect to the increased load capacitance of the second gate line B, finally the load capacitance of the first gate line A and the load capacitance of the second gate line B can be close to or even equal.
  • the frame area of the display substrate further includes a gate line 510 disposed in the first area and a polysilicon layer 530 on a side away from the signal line 130.
  • the polysilicon layer 530 is insulated from the gate line 510 in the first region and is electrically connected to the signal line 130.
  • the display substrate further includes a first insulating layer, and the first insulating layer includes a first portion located between the gate line and the signal line, and between adjacent gate lines The second part is used to maintain insulation between the gate line and the signal line, and the second part is used to maintain insulation between adjacent gate lines.
  • the display substrate further includes a first insulating layer 540.
  • the first insulating layer 540 includes a first portion 541 located between the gate line 510 and the signal line 130, and between adjacent gate lines 510.
  • the first part 541 can ensure the insulation between the gate line 510 and the signal line 130, and the second part 542 can ensure the insulation between the adjacent gate lines 510.
  • a second insulating layer is further provided between the polysilicon layer and the gate line, and the second insulating layer is used to make the gate line and the polysilicon layer Keep it insulated.
  • a second insulating layer 550 is further provided between the polysilicon layer 530 and the gate line 510, and the second insulating layer 550 can ensure that the gate line 510 and the polysilicon layer 530 maintain insulation.
  • a via hole 560 that penetrates the second portion 542 of the first insulating layer 540 and the second insulating layer 550 is opened in the display substrate, and the signal line 130 passes through the via hole 560 and the polysilicon layer 530 connection.
  • the second insulating layer 550 may have a multi-layer structure, for example, including two insulating material layers stacked on each other.
  • the specific manufacturing process can be as follows: firstly, a polysilicon layer 530 is formed on the base substrate, and then a second insulating layer 550 covering the polysilicon layer 530 is formed, and then a gate line is formed on the side of the second insulating layer 550 away from the polysilicon layer 530 510. Then, a first insulating layer 540 is formed on the side of the gate line 510 away from the polysilicon layer 530. The first insulating layer 540 covers the gate line 510 (that is, covers the gap between the gate line 510 and the gate line 510). A via 560 penetrating through the second portion 542 and the second insulating layer 550 is opened between the gate lines 510. Finally, a signal line 130 is formed on the side of the first insulating layer 540 away from the polysilicon layer 530. At this time, the signal line 130 can pass through The hole 560 is connected to the polysilicon layer 530.
  • the overlapping area of the orthographic projection of the first gate line A on the base substrate and the orthographic projection of the signal line 130 on the base substrate is equal to the second The overlapping area of the orthographic projection of the gate line B on the base substrate and the orthographic projection of the signal line 130 on the base substrate.
  • the signal lines may be arranged at equal widths at various positions in the frame area 120, and the wiring design of the gate lines in the first area 111 in the frame area 120 may also be the same, so that the first area 111
  • the overlapping area of the orthographic projection of the inner gate line on the base substrate and the orthographic projection of the signal line on the base substrate are both equal.
  • the overlapping area of the orthographic projection of the first gate line A on the base substrate and the orthographic projection of the polysilicon layer on the base substrate is larger than that of the second gate line B on the base substrate.
  • the overlapping area of the orthographic projection on the base substrate and the orthographic projection of the polysilicon layer on the base substrate is larger than that of the second gate line B on the base substrate.
  • the signal line 130 is electrically connected to the polysilicon layer 530 through the via 560, thereby forming a signal line-gate line-polysilicon three-layer capacitor structure.
  • the signal line 130 and the polysilicon layer 530 together serve as the first plate of the capacitor
  • the gate line 510 is the second plate of the capacitor.
  • the signal line 130 is connected to the polysilicon layer 530 to provide sufficient load capacitance for the gate line in the first region, so as to avoid insufficient load capacitance provided by the two-layer capacitor structure formed by the signal line 130 and the gate line 510.
  • the overlapping area of the orthographic projection of the first gate line on the base substrate and the orthographic projection of the polysilicon layer 530 on the base substrate is larger than that of the second gate line on the base substrate.
  • the overlapping area of the orthographic projection on the base substrate and the orthographic projection of the polysilicon layer 530 on the base substrate is larger than that of the second gate line on the base substrate.
  • the overlapping area of the orthographic projection of the first gate line on the base substrate and the orthographic projection of the polysilicon layer 530 on the base substrate is equal to that of the second gate line on the base substrate.
  • the overlapping area of the orthographic projection on the base substrate and the orthographic projection of the polysilicon layer 530 on the base substrate is equal to that of the second gate line on the base substrate.
  • the shape of the signal line 130 is basically fixed, when the polysilicon layer is fabricated, the area of the polysilicon layer 530 that overlaps the gate line 510 can be designed according to how much compensation capacitance needs to be added on each gate line 510. The effect of the targeted compensation gate line 510 is achieved.
  • the shift register unit 710 of the display substrate is located in the frame area, and is located on the side of the signal line 130 close to the display area.
  • the gate scan signal after the gate scan signal is output from the shift register unit, it first flows in a direction away from the display area, and after passing through the frame area, it flows from the area where the signal line is located in the frame area to the display area.
  • the light emission control unit 720 of the display substrate may also be located in the frame area and between the signal line 130 and the shift register unit 710.
  • the gate line in the first area includes a first part A1, a second part A2, and a third part A3, wherein the orthographic projection of the second part A2 on the base substrate Coinciding with the orthographic projection of the signal line 130 on the base substrate, the first part A1 is connected to the first end of the second part A2 and the sub-pixels, and the third part A3 is connected to the second part A2 The second end and the shift register unit.
  • a capacitance is formed between the second portion A2 of the gate line and the signal line 130 to increase the load capacitance of the gate line to compensate because the number of sub-pixels connected to the gate line in the first region is less than that in the second region.
  • the gate line is connected to the load capacitance missing from the number of sub-pixels.
  • the embodiment of the present disclosure also provides a display device including the display substrate as described above.
  • the display device can be a display, a mobile phone, a tablet computer, a television, a wearable electronic device, a navigation display device, and the like.

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  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

一种显示基板和显示装置，其中，显示基板包括显示区域(110)和位于显示区域(110)周边的边框区域(120)，其中，显示区域(110)包括第一区域(111)和第二区域(112)，第一区域(111)内的每一栅线连接的子像素的数量少于第二区域(112)内每一栅线连接的子像素的数量；显示基板包括设置在边框区域(120)内的信号线(130)，第一区域内(111)的每一栅线在显示基板的衬底基板上的正投影与信号线(130)在衬底基板上的正投影部分重合，信号线(130)与第一区域(111)内的栅线之间形成电容，以增加第一区域内的栅线的负载电容。

Description

显示基板和显示装置
相关申请的交叉引用
本申请主张在2019年11月26日在中国提交的中国专利申请号No.201911171262.3的优先权，其全部内容通过引用包含于此。
技术领域
本公开涉及显示技术领域，尤其涉及一种显示基板和显示装置。
背景技术
随着科技的发展，人们日常中越来越多的设备上开始配备显示屏，例如：智能手表、智能冰箱等等，其中，由于设备形状各式各样，对应的显示屏的形状也需要相匹配，从而存在很多需要配备异形屏的情况。
发明内容
第一方面，本公开实施例提供一种显示基板，其特征在于，包括显示区域和位于所述显示区域周边的边框区域，其中，所述显示区域包括第一区域和第二区域，所述第一区域内的每一栅线连接的子像素的数量少于所述第二区域内每一栅线连接的子像素的数量；
所述显示基板包括设置在所述边框区域内的信号线，所述第一区域内的每一栅线在所述显示基板的衬底基板上的正投影与所述信号线在所述衬底基板上的正投影部分重合，所述信号线与所述第一区域内的栅线之间形成电容，以增加所述第一区域内的栅线的负载电容。
进一步地，所述第一区域内的栅线包括第一栅线和第二栅线，所述第一栅线位于所述第二区域与所述第二栅线之间，所述第一栅线连接的子像素的数量大于所述第二栅线连接的子像素的数量。
进一步地，所述第一栅线在所述衬底基板上的正投影与所述信号线在所述衬底基板上的正投影的重合面积大于所述第二栅线在所述衬底基板上的正投影与所述信号线在所述衬底基板上的正投影的重合面积。
进一步地，所述显示基板的边框区域中还包括设置于所述第一区域内的栅线远离所述信号线一侧的多晶硅层，其中，所述多晶硅层与所述第一区域内的栅线绝缘设置且与所述信号线电连接。
进一步地，所述信号线和所述多晶硅层共同形成所述电容的第一极板、所述栅线为所述电容的第二极板。
进一步地，所述第一栅线在所述衬底基板上的正投影与所述信号线在所述衬底基板上的正投影的重合面积等于所述第四栅线在所述衬底基板上的正投影与所述信号线在所述衬底基板上的正投影的重合面积。
进一步地，所述第一栅线在所述衬底基板上的正投影与所述多晶硅层在所述衬底基板上的正投影的重合面积大于所述第二栅线在所述衬底基板上的正投影与所述多晶硅层在所述衬底基板上的正投影的重合面积。
进一步地，所述第一栅线在所述衬底基板上的正投影与所述多晶硅层在所述衬底基板上的正投影的重合面积等于所述第二栅线在所述衬底基板上的正投影与所述多晶硅层在所述衬底基板上的正投影的重合面积。
进一步地，所述显示基板还包括第一绝缘层，所述第一绝缘层包括位于所述栅线与所述信号线之间的第一部分，以及位于相邻栅线之间的第二部分，所述第一部分用于使所述栅线与所述信号线之间保持绝缘，所述第二部分用于使相邻栅线之间保持绝缘。
进一步地，在所述多晶硅层和所述栅线之间还设有第二绝缘层，所述第二绝缘层用于使所述栅线与所述多晶硅层之间保持绝缘。
进一步地，在所述显示基板中开设贯穿所述第一绝缘层的第二部分和所述第二绝缘层的过孔，所述信号线通过所述过孔与所述多晶硅层连接。
进一步地，所述显示基板的移位寄存器单元位于所述边框区域内，且位于所述信号线靠近所述显示区域的一侧。
进一步地，所述第一区域内的栅线包括第一部分、第二部分和第三部分，其中，所述第二部分在所述衬底基板上的正投影与所述信号线在所述衬底基板上的正投影重合，所述第一部分连接所述第二部分的第一端和子像素，所述第三部分连接所述第二部分的第二端和移位寄存器单元。
进一步地，所述第一区域内的栅线的第二部分与所述信号线之间形成电 容，以增加所述第一区域内的栅线的负载电容。
进一步地，所述信号线为低电平信号线。
进一步地，所述第一区域和第二区域内栅线连接的子像素的排列方式相同。
第二方面，本公开实施例还提供一种显示装置，包括如上所述的显示基板。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对本公开实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。
图1为本公开一实施例提供的显示基板的结构示意图；
图2为本公开另一实施例提供的显示基板的结构示意图；
图3为本公开另一实施例提供的显示基板的结构示意图；
图4为本公开另一实施例提供的显示基板中栅线未增加负载电容的情况下栅极扫描信号的波形图；
图5为本公开另一实施例提供的显示基板中栅线增加负载电容的情况下栅极扫描信号的波形图；
图6为本公开另一实施例提供的显示基板中第一栅线和第二栅线的部分结构示意图；
图7为本公开另一实施例提供的显示基板中边框区域的剖视图；
图8为本公开另一实施例提供的显示基板中第一栅线和第二栅线的部分结构示意图；
图9为本公开另一实施例提供的显示基板的部分结构示意图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本公开一部分实施例，而不是全 部的实施例。基于本公开中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
异形屏中部分栅线连接的子像素的数量会与其他栅线连接的子像素的数量不同，这样，显示屏中存在部分栅线的负载与其他栅线的负载不同的情况，造成部分栅线的信号延迟与其他栅线的信号延迟不同，降低显示装置的显示效果。
本公开实施例提供一种显示基板和显示装置，以解决相关技术中异形屏中部分栅线的负载与其他栅线的负载不同导致部分走线的信号延迟与其他走线的信号延迟不同的现象，改善显示装置的显示效果。
本公开实施例提供一种显示基板，如图1所示，包括显示区域110和位于所述显示区域110周边的边框区域120，其中，所述显示区域110包括第一区域111和第二区域112，所述第一区域111内的每一栅线连接的子像素的数量少于所述第二区域112内每一栅线连接的子像素的数量；
所述显示基板包括设置在所述边框区域120内的信号线130，所述第一区域111内的每一栅线在所述显示基板的衬底基板上的正投影与所述信号线130在所述衬底基板上的正投影部分重合，所述信号线130与所述第一区域111内的栅线之间形成电容，以增加所述第一区域111内的栅线的负载电容。
本公开实施例中，通过利用信号线130来对连接的子像素的数量较少的第一区域111内的栅线进行负载电容的补偿，使得第一区域111内的栅线的负载电容能够接近甚至等于第二区域112内的栅线的负载电容，从而使显示基板中各栅线的延迟接近，确保显示装置的显示效果。因此，本公开提供的技术方案能够确保显示装置的显示效果。
由于显示装置需要安装摄像头、麦克风、扬声器等器件，或者由于显示装置本身形状的显示，从而导致第一区域111内栅线连接的子像素的数量少于第二区域112内栅线连接的子像素的数量。
在一些实施例中，所述第一区域和第二区域内栅线连接的子像素的排列方式相同。也就是说，像素种类，像素排列的顺序，间距等完全相同。
在一些实施例中，所述第一区域和第二区域内栅线连接的子像素的排列方式也可以不相同。也就是说，像素种类，像素排列的顺序，间距等可以部 分相同，也可以完全不同。
所述第一区域和第二区域内栅线连接的子像素的排列方式，只要没有添加本公开实施例中的位于其他区域(例如边框区域)的信号线时，第一区域内栅极的负载小于第二区域内栅极的负载即可，其他不做具体限制。
上述边框区域120环绕显示区域110的外轮廓设置，边框区域120的形状与显示区域110外轮廓的形状相同，例如：在显示区域110的部分外轮廓为圆弧形的情况下，包围该部分外轮廓的部分边框区域120也为相同弧度的圆弧形，其中，边框区域120内的信号线130中对应的部分也为圆弧形。
显示区域110中包括第一区域111和第二区域112，其中，第二区域112内的栅线连接的子像素的数量均相等，且均大于第一区域111内的栅线连接的子像素的数量。
上述信号线可以是在原本边框区域120额外增加一根信号线，专用于补偿第一区域111内的栅线的负载电容，这样能够不影响边框区域120内原有走线的工作方式，能够兼容多种异形屏；上述信号线也可以是通过原本布局在边框区域120内的信号线，来用于补偿第一区域111内的栅线的负载电容，例如：边框区域120原本布局有低电平信号线，通过将低电平信号线作为信号线，这样能够降低边框区域120的布线数量，有利于显示装置的窄边框化。
由于第一区域111在栅线延伸方向上的长度小于第二区域112，因此，第一区域111内的栅线连接子像素的数量少于第二区域112内的栅线连接子像素的数量。这样，导致第一区域111内的栅线的负载电容小于第二区域112内的栅线的负载电容，进而造成第一区域111内的栅线的信号延迟与第二区域112内的栅线的信号延迟不同，影响显示装置的显示效果。
其中，第一区域111内的多根栅线连接子像素的数量可以是相同的，如图2所示，即第一区域111各部分在栅线延伸方向上的长度均相等；第一区域111内的多根栅线连接子像素的数量也可以是不同的，如图3所示，即第一区域111在栅线延伸方向上的长度不等；当然，还可以第一区域111中一部分子区域内的栅线连接子像素的数量相同，第一区域111中另一部分子区域内的栅线连接子像素的数量不同，如图1所示，此处不作限定。
信号线130与第一区域111内的每一根栅线均形成电容，其中，因为在 一个时间段内第一区域111内的多根栅线中只会有一根栅线上的电压信号发生跳变，因此信号线130在每个时间段内受到的扰动较小，栅线的跳变不会对信号线130的稳定性造成影响。
第一区域111内的栅线上的电压会发生高低跳变，栅极扫描信号的电压由高至低跳变时，在电压跳变范围内，定义栅极扫描信号的电压由90％跳变至10％所用时长为Tf，例如电压跳变为±7V，跳变范围为14V，电压信号由+5.6V跳变至-5.6V所用时间即为Tf；同样的，栅极扫描信号的电压由低至高跳变时，在电压跳变范围内，定义栅极扫描信号的电压由10％跳变至90％所用时间为Tr。其中，栅线连接的子像素的数量越多，Tr和Tf越长。
如图4所示，为未对栅线增加负载电容时栅线上栅极扫描信号的波形图，图4中上方的两个波形为阵列基板行驱动技术(Gate Driver On Array，简称GOA)中与栅线相关的两个时钟信号，下方的波形为栅线上栅极扫描信号的波形，图4中的横坐标为时间坐标，单位为s，图4中的纵坐标为电压坐标，单位为V。
根据图4中的参数计算可得：Tr＝0.43us，Tf＝0.48us。
如图5所示，为对栅线增加负载电容时栅线上栅极扫描信号的波形图，图5中上方的两个波形为GOA中与栅线相关的两个时钟信号，下方的波形为栅线上栅极扫描信号的波形，图5中的横坐标为时间坐标，单位为s，图5中的纵坐标为电压坐标，单位为V。
根据图5中的参数计算可得：Tr＝0.56us，Tf＝0.61us，即增加栅线的负载电容后，增加了栅线上栅极扫描信号的Tr和Tf，使得栅线上栅极扫描信号的波形更接近于其他连接的子像素更多的栅线上的栅极扫描信号的波形。
本公开实施例中，利用信号线130与第一区域111内的栅线形成电容，来增加第一区域111内的栅线的负载电容，使得第一区域111内栅线的整体负载电容与第二区域112内栅线的整体负载电容相同或接近，进而确保第一区域111内栅线的信号延迟与第二区域112内栅线的信号延迟相同，确保显示装置的显示效果。
进一步地，如图3所示，所述第一区域111内的栅线包括第一栅线A和第二栅线B，所述第一栅线A位于所述第二区域112与所述第二栅线B之 间，所述第一栅线A连接的子像素的数量大于所述第二栅线B连接的子像素的数量。
本实施例中，第一区域111内的多根栅线连接子像素的数量是不同的，且越靠近第二区域112的栅线连接子像素的数量越多，越远离第二区域112的栅线连接子像素的数量越少，如图3所示。
由于第二栅线B连接的子像素的数量少于第一栅线A连接的子像素的数量，因此，为了使第一栅线A的负载电容和第二栅线B的负载电容接近第二区域112内的栅线的负载电容，信号线130对第二栅线B增加的负载电容的电容值要大于信号线130对第一栅线A增加的负载电容的电容值。
在一可选的实施方式中，如图6所示，可以设计为：所述第一栅线A在所述衬底基板上的正投影与所述信号线在所述衬底基板上的正投影的重合面积大于所述第二栅线B在所述衬底基板上的正投影与所述信号线在所述衬底基板上的正投影的重合面积。
栅线与信号线130之间的交叠面积(栅线在所述衬底基板上的正投影与所述信号线130在所述衬底基板上的正投影的重合面积)决定了栅线与信号线130之间形成的电容的大小，交叠面积越大栅线与信号线130之间形成的电容就越大，从而对栅线增加的负载电容就越大。
本实施方式中，通过将第一栅线A与信号线130的交叠面积设计为大于第二栅线B与信号线130的交叠面积，能够实现针对第一栅线A增加的负载电容大于针对第二栅线B增加的负载电容，使得最后第一栅线A的负载电容和第二栅线B的负载电容能够接近甚至相等。
在另一可选的实施方式中，如图7所示，所述显示基板的边框区域中还包括设置于所述第一区域内的栅线510远离所述信号线130一侧的多晶硅层530，其中，所述多晶硅层530与所述第一区域内的栅线510绝缘设置且与所述信号线130电连接。
在另一可选的实施方式中，显示基板还包括第一绝缘层，所述第一绝缘层包括位于所述栅线与所述信号线之间的第一部分，以及位于相邻栅线之间的第二部分，所述第一部分用于使所述栅线与所述信号线之间保持绝缘，所述第二部分用于使相邻栅线之间保持绝缘。
本实施例中，如图7所示，显示基板还包括第一绝缘层540，第一绝缘层540包括位于栅线510与信号线130之间的第一部分541，以及位于相邻栅线510之间的第二部分542，第一部分541能够确保栅线510与信号线130之间保持绝缘，第二部分542能够确保相邻栅线510之间保持绝缘。
在另一可选的实施方式中，在所述多晶硅层和所述栅线之间还设有第二绝缘层，所述第二绝缘层用于使所述栅线与所述多晶硅层之间保持绝缘。另外，如图7所示，在所述多晶硅层530和所述栅线510之间还设有第二绝缘层550，第二绝缘层550能够确保栅线510与多晶硅层530之间保持绝缘。
在所述显示基板中开设贯穿所述第一绝缘层540的第二部分542和所述第二绝缘层550的过孔560，所述信号线130通过所述过孔560与所述多晶硅层530连接。
其中，第二绝缘层550可以为多层结构，例如包括两层相互叠设的绝缘材料层。
具体的制作流程，可以是：首先在衬底基板上形成多晶硅层530，再形成覆盖多晶硅层530的第二绝缘层550，然后，在第二绝缘层550远离多晶硅层530的一侧形成栅线510，然后，在栅线510远离多晶硅层530的一侧形成第一绝缘层540，第一绝缘层540覆盖栅线510(即覆盖栅线510和栅线510之间的间隙)，然后，在栅线510之间开设贯穿第二部分542和第二绝缘层550的过孔560，最后，在第一绝缘层540远离多晶硅层530的一侧形成信号线130，此时信号线130能够通过过孔560与多晶硅层530连接。
进一步的，如图8所示，所述第一栅线A在所述衬底基板上的正投影与所述信号线130在所述衬底基板上的正投影的重合面积等于所述第二栅线B在所述衬底基板上的正投影与所述信号线130在所述衬底基板上的正投影的重合面积。
本实施例中，信号线可以是在边框区域120的各个位置等宽度设置的，且第一区域111内各栅线在边框区域120内的布线设计也可以均相同，这样，使得第一区域111内的栅线在所述衬底基板上的正投影与所述信号线在所述衬底基板上的正投影的重合面积均相等。
进一步地，所述第一栅线A在所述衬底基板上的正投影与所述多晶硅层 在所述衬底基板上的正投影的重合面积大于所述第二栅线B在所述衬底基板上的正投影与所述多晶硅层在所述衬底基板上的正投影的重合面积。
结合图7，通过过孔560，使得信号线130与多晶硅层530电连接，从而形成信号线-栅线-多晶硅的三层电容结构，信号线130和多晶硅层530共同作为电容的第一极板、栅线510为电容的第二极板。
信号线130与多晶硅层530连接，可以为第一区域中的栅线提供足够的负载电容，以避免信号线130与栅线510形成的两层电容结构提供的负载电容不够。
在一些实施例中，所述第一栅线在所述衬底基板上的正投影与所述多晶硅层530在所述衬底基板上的正投影的重合面积大于所述第二栅线在所述衬底基板上的正投影与所述多晶硅层530在所述衬底基板上的正投影的重合面积。
在一些实施例中，所述第一栅线在所述衬底基板上的正投影与所述多晶硅层530在所述衬底基板上的正投影的重合面积等于所述第二栅线在所述衬底基板上的正投影与所述多晶硅层530在所述衬底基板上的正投影的重合面积。
本实施例中，由于信号线130形状基本固定，在制作多晶硅层时，可根据每根栅线510上需要增加的补偿电容的多少来设计与栅线510交叠的多晶硅层530面积的大小，达到针对性的补偿栅线510的效果。
进一步地，如图9所示，所述显示基板的移位寄存器单元710位于所述边框区域内，且位于所述信号线130靠近所述显示区域的一侧。
这样，栅极扫描信号从移位寄存器单元输出后，先向远离显示区域的方向流动，经过边框区域后，再从边框区域中信号线所在的区域向显示区域流动。
另外，如图9所示，显示基板的发光控制单元720也可以位于所述边框区域内，且位于所述信号线130与移位寄存器单元710之间。
其中，如图9所示，所述第一区域内的栅线包括第一部分A1、第二部分A2和第三部分A3，其中，所述第二部分A2在所述衬底基板上的正投影与所述信号线130在所述衬底基板上的正投影重合，所述第一部分A1连接所述 第二部分A2的第一端和子像素，所述第三部分A3连接所述第二部分A2的第二端和移位寄存器单元。
具体的，栅线的第二部分A2与所述信号线130之间形成电容，以增加栅线的负载电容，以补偿因为第一区域内的栅线连接子像素的数量少于第二区域内的栅线连接子像素的数量所缺失的负载电容。
栅线的第二部分A2作为电容的第二极板的面积越大，栅线增加的负载电容就越大，栅线的第二部分A2作为电容的第二极板的面积越小，栅线增加的负载电容就越小。
本公开实施例还提供了一种显示装置，包括如上所述的显示基板。
显示装置可以是显示器、手机、平板电脑、电视机、可穿戴电子设备、导航显示设备等。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
可以理解，当诸如层、膜、区域或基板之类的元件被称作位于另一元件“上”或“下”时，该元件可以“直接”位于另一元件“上”或“下”，或者可以存在中间元件。
上面结合附图对本公开的实施例进行了描述，但是本公开并不局限于上述的具体实施方式，上述的具体实施方式仅仅是示意性的，而不是限制性的，本领域的普通技术人员在本公开的启示下，在不脱离本公开宗旨和权利要求所保护的范围情况下，还可做出很多形式，均属于本公开的保护之内。

Claims (17)

  1. 一种显示基板，包括显示区域和位于所述显示区域周边的边框区域，其中，所述显示区域包括第一区域和第二区域，所述第一区域内的每一栅线连接的子像素的数量少于所述第二区域内每一栅线连接的子像素的数量；
    所述显示基板包括设置在所述边框区域内的信号线，所述第一区域内的每一栅线在所述显示基板的衬底基板上的正投影与所述信号线在所述衬底基板上的正投影部分重合，所述信号线与所述第一区域内的栅线之间形成电容，以增加所述第一区域内的栅线的负载电容。
  2. 根据权利要求1所述的显示基板，其中，所述第一区域内的栅线包括第一栅线和第二栅线，所述第一栅线位于所述第二区域与所述第二栅线之间，所述第一栅线连接的子像素的数量大于所述第二栅线连接的子像素的数量。
  3. 根据权利要求2所述的显示基板，其中，所述第一栅线在所述衬底基板上的正投影与所述信号线在所述衬底基板上的正投影的重合面积大于所述第二栅线在所述衬底基板上的正投影与所述信号线在所述衬底基板上的正投影的重合面积。
  4. 根据权利要求2所述的显示基板，其中，所述第一栅线在所述衬底基板上的正投影与所述信号线在所述衬底基板上的正投影的重合面积等于所述第二栅线在所述衬底基板上的正投影与所述信号线在所述衬底基板上的正投影的重合面积。
  5. 根据权利要求2所述的显示基板，其中，所述显示基板的边框区域中还包括设置于所述第一区域内的栅线远离所述信号线一侧的多晶硅层，其中，所述多晶硅层与所述第一区域内的栅线绝缘设置且与所述信号线电连接。
  6. 根据权利要求5所述的显示基板，其中，所述信号线和所述多晶硅层共同形成所述电容的第一极板、所述栅线为所述电容的第二极板。
  7. 根据权利要求5所述的显示基板，其中，所述第一栅线在所述衬底基板上的正投影与所述多晶硅层在所述衬底基板上的正投影的重合面积大于所述第二栅线在所述衬底基板上的正投影与所述多晶硅层在所述衬底基板上的正投影的重合面积。
  8. 根据权利要求5所述的显示基板，其中，所述第一栅线在所述衬底基板上的正投影与所述多晶硅层在所述衬底基板上的正投影的重合面积等于所述第二栅线在所述衬底基板上的正投影与所述多晶硅层在所述衬底基板上的正投影的重合面积。
  9. 根据权利要求5所述的显示基板，还包括第一绝缘层，所述第一绝缘层包括位于所述栅线与所述信号线之间的第一部分，以及位于相邻栅线之间的第二部分，所述第一部分用于使所述栅线与所述信号线之间保持绝缘，所述第二部分用于使相邻栅线之间保持绝缘。
  10. 根据权利要求9所述的显示基板，其中，在所述多晶硅层和所述栅线之间还设有第二绝缘层，所述第二绝缘层用于使所述栅线与所述多晶硅层之间保持绝缘。
  11. 根据权利要求10所述的显示基板，其中，在所述显示基板中开设贯穿所述第一绝缘层的第二部分和所述第二绝缘层的过孔，所述信号线通过所述过孔与所述多晶硅层连接。
  12. 根据权利要求1所述的显示基板，其中，所述显示基板的移位寄存器单元位于所述边框区域内，且位于所述信号线靠近所述显示区域的一侧。
  13. 根据权利要求12所述的显示基板，其中，所述第一区域内的栅线包括第一部分、第二部分和第三部分，其中，所述第二部分在所述衬底基板上的正投影与所述信号线在所述衬底基板上的正投影重合，所述第一部分连接所述第二部分的第一端和子像素，所述第三部分连接所述第二部分的第二端和移位寄存器单元。
  14. 根据权利要求13中所述的显示基板，其中，所述第一区域内的栅线的第二部分与所述信号线之间形成电容，以增加所述第一区域内的栅线的负载电容。
  15. 根据权利要求1-14中任一项所述的显示基板，其中，所述信号线为低电平信号线。
  16. 根据权利要求1-15中任一项所述的显示基板，其中，所述第一区域和第二区域内栅线连接的子像素的排列方式相同。
  17. 一种显示装置，包括如权利要求1-16中任一项所述的显示基板。
PCT/CN2020/122092 2019-11-26 2020-10-20 显示基板和显示装置 WO2021103853A1 (zh)

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