WO2021103853A1 - 显示基板和显示装置 - Google Patents
显示基板和显示装置 Download PDFInfo
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- WO2021103853A1 WO2021103853A1 PCT/CN2020/122092 CN2020122092W WO2021103853A1 WO 2021103853 A1 WO2021103853 A1 WO 2021103853A1 CN 2020122092 W CN2020122092 W CN 2020122092W WO 2021103853 A1 WO2021103853 A1 WO 2021103853A1
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- orthographic projection
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- 239000000758 substrate Substances 0.000 title claims abstract description 137
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 47
- 229920005591 polysilicon Polymers 0.000 claims description 47
- 238000009413 insulation Methods 0.000 claims description 11
- 239000003990 capacitor Substances 0.000 claims description 10
- 230000000149 penetrating effect Effects 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 10
- 230000000694 effects Effects 0.000 description 7
- 238000005516 engineering process Methods 0.000 description 3
- 230000007704 transition Effects 0.000 description 3
- 238000004364 calculation method Methods 0.000 description 2
- 230000001934 delay Effects 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
- G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1218—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or structure of the substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
Definitions
- the present disclosure relates to the field of display technology, and in particular to a display substrate and a display device.
- an embodiment of the present disclosure provides a display substrate, which is characterized by comprising a display area and a frame area located at the periphery of the display area, wherein the display area includes a first area and a second area, and the second area The number of sub-pixels connected to each gate line in a region is less than the number of sub-pixels connected to each gate line in the second region;
- the display substrate includes signal lines arranged in the frame area, the orthographic projection of each gate line in the first area on the base substrate of the display substrate and the signal line on the substrate The orthographic projections on the substrate overlap, and a capacitance is formed between the signal line and the gate line in the first area to increase the load capacitance of the gate line in the first area.
- the gate line in the first region includes a first gate line and a second gate line, the first gate line is located between the second region and the second gate line, and the first gate line
- the number of line-connected sub-pixels is greater than the number of sub-pixels connected to the second gate line.
- the overlapping area of the orthographic projection of the first grid line on the base substrate and the orthographic projection of the signal line on the base substrate is larger than that of the second grid line on the base substrate The overlapping area of the orthographic projection of the signal line and the orthographic projection of the signal line on the base substrate.
- the frame area of the display substrate further includes a polysilicon layer disposed on a side of the gate line in the first area away from the signal line, wherein the polysilicon layer and the gate line in the first area
- the wire is insulated and electrically connected to the signal wire.
- the signal line and the polysilicon layer jointly form a first plate of the capacitor, and the gate line is a second plate of the capacitor.
- the overlapping area of the orthographic projection of the first grid line on the base substrate and the orthographic projection of the signal line on the base substrate is equal to that of the fourth grid line on the base substrate The overlapping area of the orthographic projection of the signal line and the orthographic projection of the signal line on the base substrate.
- the overlapping area of the orthographic projection of the first grid line on the base substrate and the orthographic projection of the polysilicon layer on the base substrate is larger than that of the second grid line on the base substrate.
- the overlapping area of the orthographic projection of the polysilicon layer and the orthographic projection of the polysilicon layer on the base substrate is larger than that of the second grid line on the base substrate.
- the overlapping area of the orthographic projection of the first grid line on the base substrate and the orthographic projection of the polysilicon layer on the base substrate is equal to that of the second grid line on the base substrate The overlapping area of the orthographic projection of the polysilicon layer and the orthographic projection of the polysilicon layer on the base substrate.
- the display substrate further includes a first insulating layer, and the first insulating layer includes a first part located between the gate line and the signal line, and a second part located between adjacent gate lines, The first part is used to maintain insulation between the gate line and the signal line, and the second part is used to maintain insulation between adjacent gate lines.
- a second insulating layer is further provided between the polysilicon layer and the gate line, and the second insulating layer is used to maintain insulation between the gate line and the polysilicon layer.
- a via hole penetrating the second portion of the first insulating layer and the second insulating layer is opened in the display substrate, and the signal line is connected to the polysilicon layer through the via hole.
- the shift register unit of the display substrate is located in the frame area and is located on the side of the signal line close to the display area.
- the gate line in the first region includes a first part, a second part, and a third part, wherein the orthographic projection of the second part on the base substrate and the signal line on the backing The orthographic projections on the base substrate coincide, the first part connects the first end of the second part and the sub-pixel, and the third part connects the second end of the second part and the shift register unit.
- a capacitance is formed between the second part of the gate line in the first area and the signal line to increase the load capacitance of the gate line in the first area.
- the signal line is a low-level signal line.
- the arrangement of the sub-pixels connected by the gate lines in the first region and the second region is the same.
- embodiments of the present disclosure also provide a display device, including the display substrate as described above.
- FIG. 1 is a schematic structural diagram of a display substrate provided by an embodiment of the disclosure
- FIG. 2 is a schematic structural diagram of a display substrate provided by another embodiment of the present disclosure.
- FIG. 3 is a schematic structural diagram of a display substrate provided by another embodiment of the present disclosure.
- FIG. 4 is a waveform diagram of a gate scan signal in a case where a load capacitance is not added to the gate line in the display substrate according to another embodiment of the present disclosure
- FIG. 5 is a waveform diagram of a gate scan signal when a load capacitance of the gate line in the display substrate is increased according to another embodiment of the present disclosure
- FIG. 6 is a schematic diagram of a part of the structure of a first gate line and a second gate line in a display substrate provided by another embodiment of the present disclosure
- FIG. 7 is a cross-sectional view of a frame area in a display substrate provided by another embodiment of the present disclosure.
- FIG. 8 is a schematic diagram of a partial structure of a first gate line and a second gate line in a display substrate provided by another embodiment of the present disclosure.
- FIG. 9 is a schematic diagram of a part of the structure of a display substrate provided by another embodiment of the present disclosure.
- the number of sub-pixels connected to part of the gate lines in the special-shaped screen will be different from the number of sub-pixels connected to other gate lines. In this way, the load of some gate lines in the display screen is different from the load of other gate lines, resulting in part of the gate lines.
- the signal delay of is different from the signal delay of other gate lines, which reduces the display effect of the display device.
- the embodiments of the present disclosure provide a display substrate and a display device to solve the phenomenon that the load of some of the gate lines in the special-shaped screen is different from the load of other gate lines in the related art, which causes the signal delay of some traces to be different from the signal delay of other traces. , Improve the display effect of the display device.
- An embodiment of the present disclosure provides a display substrate, as shown in FIG. 1, including a display area 110 and a frame area 120 located around the display area 110, wherein the display area 110 includes a first area 111 and a second area 112 , The number of sub-pixels connected to each gate line in the first region 111 is less than the number of sub-pixels connected to each gate line in the second region 112;
- the display substrate includes a signal line 130 disposed in the frame area 120, and the orthographic projection of each gate line in the first area 111 on the base substrate of the display substrate is in line with the signal line 130.
- the orthographic projection on the base substrate overlaps, and a capacitance is formed between the signal line 130 and the gate line in the first area 111 to increase the load capacitance of the gate line in the first area 111.
- the load capacitance of the gate line in the first region 111 with a small number of connected sub-pixels is compensated by using the signal line 130, so that the load capacitance of the gate line in the first region 111 can be close to It is even equal to the load capacitance of the gate lines in the second region 112, so that the delays of the gate lines in the display substrate are close to ensure the display effect of the display device. Therefore, the technical solution provided by the present disclosure can ensure the display effect of the display device.
- the number of sub-pixels connected to the gate line in the first area 111 is less than the number of sub-pixels connected to the gate line in the second area 112 quantity.
- the arrangement of the sub-pixels connected by the gate lines in the first region and the second region is the same.
- the types of pixels, the order of pixel arrangement, and the pitch are all the same.
- the arrangement of the sub-pixels connected by the gate lines in the first region and the second region may also be different.
- the types of pixels, the order of pixel arrangement, the pitch, etc. may be partly the same or completely different.
- the frame area 120 described above is arranged around the outer contour of the display area 110, and the shape of the frame area 120 is the same as the shape of the outer contour of the display area 110.
- the shape of the frame area 120 is the same as the shape of the outer contour of the display area 110.
- a part of the outer contour of the display area 110 is arc-shaped, it surrounds the outer contour of the display area 110.
- Part of the frame area 120 of the outline is also a circular arc with the same arc, wherein the corresponding part of the signal line 130 in the frame area 120 is also a circular arc.
- the display area 110 includes a first area 111 and a second area 112, wherein the number of sub-pixels connected by the gate lines in the second area 112 are equal, and both are larger than those of the sub-pixels connected by the gate lines in the first area 111. Quantity.
- the above-mentioned signal line can be an additional signal line added to the original frame area 120 to compensate for the load capacitance of the gate line in the first area 111, so that it does not affect the working mode of the original wiring in the frame area 120, and is compatible with multiple lines.
- a special-shaped screen; the above-mentioned signal lines can also be used to compensate the load capacitance of the gate lines in the first area 111 through the signal lines originally laid out in the frame area 120, for example: the frame area 120 is originally laid out with low-level signals Lines, by using low-level signal lines as signal lines, the number of wiring in the frame area 120 can be reduced, which is conducive to narrowing the frame of the display device.
- the number of gate line-connected sub-pixels in the first region 111 is less than the number of gate line-connected sub-pixels in the second region 112.
- the load capacitance of the gate lines in the first region 111 is smaller than the load capacitance of the gate lines in the second region 112, which in turn causes the signal delay of the gate lines in the first region 111 to be as much as that of the gate lines in the second region 112. The signal delay is different, which affects the display effect of the display device.
- the number of sub-pixels connected by multiple gate lines in the first region 111 may be the same, as shown in FIG. 2, that is, the length of each part of the first region 111 in the extending direction of the gate lines is equal; the first region 111
- the number of sub-pixels connected by multiple gate lines in the gate line may also be different, as shown in FIG. 3, that is, the length of the first region 111 in the extending direction of the gate line is not equal; of course, a part of the sub-pixels in the first region 111 may also be
- the number of gate lines connected to the sub-pixels in the region is the same, and the number of gate lines connected to the sub-pixels in another part of the first region 111 is different, as shown in FIG. 1, which is not limited here.
- the signal line 130 and each gate line in the first region 111 form a capacitance, wherein, because in a period of time, only one of the multiple gate lines in the first region 111 will jump the voltage signal on the gate line. Therefore, the signal line 130 receives less disturbance in each time period, and the jump of the gate line will not affect the stability of the signal line 130.
- the voltage on the gate line in the first region 111 will undergo a high-low jump.
- the voltage that defines the gate scan signal jumps from 90%
- the time taken to 10% is Tf.
- the voltage jumps to ⁇ 7V, the jump range is 14V, and the time it takes for the voltage signal to jump from +5.6V to -5.6V is Tf; similarly, the voltage of the gate scan signal is changed from In the low-to-high transition, in the voltage transition range, the time it takes to define the voltage of the gate scan signal from 10% to 90% transition is Tr.
- Tr the greater the number of sub-pixels connected by the gate line, the longer Tr and Tf are.
- FIG 4 it is the waveform diagram of the gate scanning signal on the gate line when the load capacitance is not added to the gate line.
- the upper two waveforms in Figure 4 are in the array substrate row drive technology (Gate Driver On Array, GOA for short) Two clock signals related to the gate line.
- the waveform below is the waveform of the gate scan signal on the gate line.
- the abscissa in Figure 4 is the time coordinate and the unit is s.
- the ordinate in Figure 4 is the voltage coordinate and the unit is V.
- Tr 0.43us
- Tf 0.48us
- the waveform diagram of the gate scan signal on the gate line when the load capacitance is added to the gate line As shown in Figure 5, the waveform diagram of the gate scan signal on the gate line when the load capacitance is added to the gate line.
- the upper two waveforms in Figure 5 are the two clock signals related to the gate line in the GOA, and the lower waveform is
- the abscissa in FIG. 5 is the time coordinate and the unit is s
- the ordinate in FIG. 5 is the voltage coordinate and the unit is V.
- Tr 0.56us
- Tf 0.61us
- the signal line 130 and the gate line in the first area 111 are used to form a capacitance to increase the load capacitance of the gate line in the first area 111, so that the overall load capacitance of the gate line in the first area 111 is equal to that of the gate line in the first area 111.
- the overall load capacitance of the gate lines in the two regions 112 is the same or close to ensure that the signal delay of the gate lines in the first region 111 is the same as the signal delay of the gate lines in the second region 112 to ensure the display effect of the display device.
- the gate lines in the first area 111 include a first gate line A and a second gate line B, and the first gate line A is located in the second area 112 and the first gate line A. Between the two gate lines B, the number of sub-pixels connected to the first gate line A is greater than the number of sub-pixels connected to the second gate line B.
- the number of gate lines connected to the sub-pixels in the first region 111 is different, and the closer the gate line to the second region 112 is, the more the number of connected sub-pixels is, the farther away the gate line from the second region 112 is.
- the capacitance value of the load capacitance added by the signal line 130 to the second gate line B is greater than the capacitance value of the load capacitance added by the signal line 130 to the first gate line A.
- FIG. 6 it can be designed as: the orthographic projection of the first gate line A on the base substrate and the orthographic projection of the signal line on the base substrate
- the overlapping area of the projection is larger than the overlapping area of the orthographic projection of the second gate line B on the base substrate and the orthographic projection of the signal line on the base substrate.
- the overlap area between the gate line and the signal line 130 determines the overlap area between the gate line and the signal line 130.
- the overlapping area of the first gate line A and the signal line 130 to be larger than the overlapping area of the second gate line B and the signal line 130, it can be achieved that the load capacitance increased for the first gate line A is greater than With respect to the increased load capacitance of the second gate line B, finally the load capacitance of the first gate line A and the load capacitance of the second gate line B can be close to or even equal.
- the frame area of the display substrate further includes a gate line 510 disposed in the first area and a polysilicon layer 530 on a side away from the signal line 130.
- the polysilicon layer 530 is insulated from the gate line 510 in the first region and is electrically connected to the signal line 130.
- the display substrate further includes a first insulating layer, and the first insulating layer includes a first portion located between the gate line and the signal line, and between adjacent gate lines The second part is used to maintain insulation between the gate line and the signal line, and the second part is used to maintain insulation between adjacent gate lines.
- the display substrate further includes a first insulating layer 540.
- the first insulating layer 540 includes a first portion 541 located between the gate line 510 and the signal line 130, and between adjacent gate lines 510.
- the first part 541 can ensure the insulation between the gate line 510 and the signal line 130, and the second part 542 can ensure the insulation between the adjacent gate lines 510.
- a second insulating layer is further provided between the polysilicon layer and the gate line, and the second insulating layer is used to make the gate line and the polysilicon layer Keep it insulated.
- a second insulating layer 550 is further provided between the polysilicon layer 530 and the gate line 510, and the second insulating layer 550 can ensure that the gate line 510 and the polysilicon layer 530 maintain insulation.
- a via hole 560 that penetrates the second portion 542 of the first insulating layer 540 and the second insulating layer 550 is opened in the display substrate, and the signal line 130 passes through the via hole 560 and the polysilicon layer 530 connection.
- the second insulating layer 550 may have a multi-layer structure, for example, including two insulating material layers stacked on each other.
- the specific manufacturing process can be as follows: firstly, a polysilicon layer 530 is formed on the base substrate, and then a second insulating layer 550 covering the polysilicon layer 530 is formed, and then a gate line is formed on the side of the second insulating layer 550 away from the polysilicon layer 530 510. Then, a first insulating layer 540 is formed on the side of the gate line 510 away from the polysilicon layer 530. The first insulating layer 540 covers the gate line 510 (that is, covers the gap between the gate line 510 and the gate line 510). A via 560 penetrating through the second portion 542 and the second insulating layer 550 is opened between the gate lines 510. Finally, a signal line 130 is formed on the side of the first insulating layer 540 away from the polysilicon layer 530. At this time, the signal line 130 can pass through The hole 560 is connected to the polysilicon layer 530.
- the overlapping area of the orthographic projection of the first gate line A on the base substrate and the orthographic projection of the signal line 130 on the base substrate is equal to the second The overlapping area of the orthographic projection of the gate line B on the base substrate and the orthographic projection of the signal line 130 on the base substrate.
- the signal lines may be arranged at equal widths at various positions in the frame area 120, and the wiring design of the gate lines in the first area 111 in the frame area 120 may also be the same, so that the first area 111
- the overlapping area of the orthographic projection of the inner gate line on the base substrate and the orthographic projection of the signal line on the base substrate are both equal.
- the overlapping area of the orthographic projection of the first gate line A on the base substrate and the orthographic projection of the polysilicon layer on the base substrate is larger than that of the second gate line B on the base substrate.
- the overlapping area of the orthographic projection on the base substrate and the orthographic projection of the polysilicon layer on the base substrate is larger than that of the second gate line B on the base substrate.
- the signal line 130 is electrically connected to the polysilicon layer 530 through the via 560, thereby forming a signal line-gate line-polysilicon three-layer capacitor structure.
- the signal line 130 and the polysilicon layer 530 together serve as the first plate of the capacitor
- the gate line 510 is the second plate of the capacitor.
- the signal line 130 is connected to the polysilicon layer 530 to provide sufficient load capacitance for the gate line in the first region, so as to avoid insufficient load capacitance provided by the two-layer capacitor structure formed by the signal line 130 and the gate line 510.
- the overlapping area of the orthographic projection of the first gate line on the base substrate and the orthographic projection of the polysilicon layer 530 on the base substrate is larger than that of the second gate line on the base substrate.
- the overlapping area of the orthographic projection on the base substrate and the orthographic projection of the polysilicon layer 530 on the base substrate is larger than that of the second gate line on the base substrate.
- the overlapping area of the orthographic projection of the first gate line on the base substrate and the orthographic projection of the polysilicon layer 530 on the base substrate is equal to that of the second gate line on the base substrate.
- the overlapping area of the orthographic projection on the base substrate and the orthographic projection of the polysilicon layer 530 on the base substrate is equal to that of the second gate line on the base substrate.
- the shape of the signal line 130 is basically fixed, when the polysilicon layer is fabricated, the area of the polysilicon layer 530 that overlaps the gate line 510 can be designed according to how much compensation capacitance needs to be added on each gate line 510. The effect of the targeted compensation gate line 510 is achieved.
- the shift register unit 710 of the display substrate is located in the frame area, and is located on the side of the signal line 130 close to the display area.
- the gate scan signal after the gate scan signal is output from the shift register unit, it first flows in a direction away from the display area, and after passing through the frame area, it flows from the area where the signal line is located in the frame area to the display area.
- the light emission control unit 720 of the display substrate may also be located in the frame area and between the signal line 130 and the shift register unit 710.
- the gate line in the first area includes a first part A1, a second part A2, and a third part A3, wherein the orthographic projection of the second part A2 on the base substrate Coinciding with the orthographic projection of the signal line 130 on the base substrate, the first part A1 is connected to the first end of the second part A2 and the sub-pixels, and the third part A3 is connected to the second part A2 The second end and the shift register unit.
- a capacitance is formed between the second portion A2 of the gate line and the signal line 130 to increase the load capacitance of the gate line to compensate because the number of sub-pixels connected to the gate line in the first region is less than that in the second region.
- the gate line is connected to the load capacitance missing from the number of sub-pixels.
- the embodiment of the present disclosure also provides a display device including the display substrate as described above.
- the display device can be a display, a mobile phone, a tablet computer, a television, a wearable electronic device, a navigation display device, and the like.
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Abstract
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Claims (17)
- 一种显示基板,包括显示区域和位于所述显示区域周边的边框区域,其中,所述显示区域包括第一区域和第二区域,所述第一区域内的每一栅线连接的子像素的数量少于所述第二区域内每一栅线连接的子像素的数量;所述显示基板包括设置在所述边框区域内的信号线,所述第一区域内的每一栅线在所述显示基板的衬底基板上的正投影与所述信号线在所述衬底基板上的正投影部分重合,所述信号线与所述第一区域内的栅线之间形成电容,以增加所述第一区域内的栅线的负载电容。
- 根据权利要求1所述的显示基板,其中,所述第一区域内的栅线包括第一栅线和第二栅线,所述第一栅线位于所述第二区域与所述第二栅线之间,所述第一栅线连接的子像素的数量大于所述第二栅线连接的子像素的数量。
- 根据权利要求2所述的显示基板,其中,所述第一栅线在所述衬底基板上的正投影与所述信号线在所述衬底基板上的正投影的重合面积大于所述第二栅线在所述衬底基板上的正投影与所述信号线在所述衬底基板上的正投影的重合面积。
- 根据权利要求2所述的显示基板,其中,所述第一栅线在所述衬底基板上的正投影与所述信号线在所述衬底基板上的正投影的重合面积等于所述第二栅线在所述衬底基板上的正投影与所述信号线在所述衬底基板上的正投影的重合面积。
- 根据权利要求2所述的显示基板,其中,所述显示基板的边框区域中还包括设置于所述第一区域内的栅线远离所述信号线一侧的多晶硅层,其中,所述多晶硅层与所述第一区域内的栅线绝缘设置且与所述信号线电连接。
- 根据权利要求5所述的显示基板,其中,所述信号线和所述多晶硅层共同形成所述电容的第一极板、所述栅线为所述电容的第二极板。
- 根据权利要求5所述的显示基板,其中,所述第一栅线在所述衬底基板上的正投影与所述多晶硅层在所述衬底基板上的正投影的重合面积大于所述第二栅线在所述衬底基板上的正投影与所述多晶硅层在所述衬底基板上的正投影的重合面积。
- 根据权利要求5所述的显示基板,其中,所述第一栅线在所述衬底基板上的正投影与所述多晶硅层在所述衬底基板上的正投影的重合面积等于所述第二栅线在所述衬底基板上的正投影与所述多晶硅层在所述衬底基板上的正投影的重合面积。
- 根据权利要求5所述的显示基板,还包括第一绝缘层,所述第一绝缘层包括位于所述栅线与所述信号线之间的第一部分,以及位于相邻栅线之间的第二部分,所述第一部分用于使所述栅线与所述信号线之间保持绝缘,所述第二部分用于使相邻栅线之间保持绝缘。
- 根据权利要求9所述的显示基板,其中,在所述多晶硅层和所述栅线之间还设有第二绝缘层,所述第二绝缘层用于使所述栅线与所述多晶硅层之间保持绝缘。
- 根据权利要求10所述的显示基板,其中,在所述显示基板中开设贯穿所述第一绝缘层的第二部分和所述第二绝缘层的过孔,所述信号线通过所述过孔与所述多晶硅层连接。
- 根据权利要求1所述的显示基板,其中,所述显示基板的移位寄存器单元位于所述边框区域内,且位于所述信号线靠近所述显示区域的一侧。
- 根据权利要求12所述的显示基板,其中,所述第一区域内的栅线包括第一部分、第二部分和第三部分,其中,所述第二部分在所述衬底基板上的正投影与所述信号线在所述衬底基板上的正投影重合,所述第一部分连接所述第二部分的第一端和子像素,所述第三部分连接所述第二部分的第二端和移位寄存器单元。
- 根据权利要求13中所述的显示基板,其中,所述第一区域内的栅线的第二部分与所述信号线之间形成电容,以增加所述第一区域内的栅线的负载电容。
- 根据权利要求1-14中任一项所述的显示基板,其中,所述信号线为低电平信号线。
- 根据权利要求1-15中任一项所述的显示基板,其中,所述第一区域和第二区域内栅线连接的子像素的排列方式相同。
- 一种显示装置,包括如权利要求1-16中任一项所述的显示基板。
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Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN105895002A (zh) * | 2015-02-12 | 2016-08-24 | 三星显示有限公司 | 非四边形的显示器 |
CN107919090A (zh) * | 2017-11-30 | 2018-04-17 | 武汉天马微电子有限公司 | 显示面板及显示装置 |
JP2018063348A (ja) * | 2016-10-13 | 2018-04-19 | 三菱電機株式会社 | 液晶表示パネルおよび液晶表示装置 |
CN108646477A (zh) * | 2018-03-27 | 2018-10-12 | 上海中航光电子有限公司 | 阵列基板、显示面板和显示装置 |
CN109633971A (zh) * | 2019-01-31 | 2019-04-16 | 厦门天马微电子有限公司 | 一种显示面板及显示装置 |
CN109683751A (zh) * | 2019-01-04 | 2019-04-26 | 合肥鑫晟光电科技有限公司 | 触控基板及其制作方法、显示装置 |
KR20190062948A (ko) * | 2017-11-29 | 2019-06-07 | 엘지디스플레이 주식회사 | 표시 장치 |
CN209103062U (zh) * | 2017-10-10 | 2019-07-12 | 三菱电机株式会社 | 液晶显示装置 |
CN110827673A (zh) * | 2019-11-26 | 2020-02-21 | 京东方科技集团股份有限公司 | 显示基板和显示装置 |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN105469764B (zh) * | 2015-12-31 | 2018-11-27 | 上海天马微电子有限公司 | 一种阵列基板、液晶显示面板及电子设备 |
CN106098010B (zh) * | 2016-08-17 | 2018-06-05 | 京东方科技集团股份有限公司 | 一种阵列基板及显示面板 |
CN106483728B (zh) | 2017-01-04 | 2019-05-21 | 京东方科技集团股份有限公司 | 像素结构、阵列基板和显示装置 |
WO2018212100A1 (ja) * | 2017-05-18 | 2018-11-22 | シャープ株式会社 | アクティブマトリクス基板およびその製造方法 |
CN108037626A (zh) * | 2017-11-29 | 2018-05-15 | 武汉天马微电子有限公司 | 一种显示面板及显示装置 |
CN112419904B (zh) * | 2017-11-30 | 2022-03-29 | 武汉天马微电子有限公司 | 一种显示面板及其制作方法、显示装置 |
CN108831387B (zh) * | 2018-06-29 | 2020-10-16 | 上海天马微电子有限公司 | 阵列基板、显示面板、显示装置及显示面板的驱动方法 |
CN109065550B (zh) * | 2018-07-25 | 2020-12-22 | 武汉华星光电技术有限公司 | 薄膜晶体管阵列面板及显示装置 |
CN109712995B (zh) * | 2019-01-30 | 2021-03-09 | 上海天马有机发光显示技术有限公司 | 显示面板及显示装置 |
CN109728005B (zh) * | 2019-02-13 | 2021-05-11 | 厦门天马微电子有限公司 | 一种阵列基板、显示面板以及显示装置 |
JP7240921B2 (ja) * | 2019-03-26 | 2023-03-16 | 株式会社ジャパンディスプレイ | 表示装置 |
JP7446774B2 (ja) * | 2019-11-07 | 2024-03-11 | 株式会社ジャパンディスプレイ | 半導体基板及び表示装置 |
-
2019
- 2019-11-26 CN CN201911171262.3A patent/CN110827673A/zh active Pending
-
2020
- 2020-10-20 WO PCT/CN2020/122092 patent/WO2021103853A1/zh active Application Filing
- 2020-10-20 US US17/311,889 patent/US11984458B2/en active Active
Patent Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN105895002A (zh) * | 2015-02-12 | 2016-08-24 | 三星显示有限公司 | 非四边形的显示器 |
JP2018063348A (ja) * | 2016-10-13 | 2018-04-19 | 三菱電機株式会社 | 液晶表示パネルおよび液晶表示装置 |
CN209103062U (zh) * | 2017-10-10 | 2019-07-12 | 三菱电机株式会社 | 液晶显示装置 |
KR20190062948A (ko) * | 2017-11-29 | 2019-06-07 | 엘지디스플레이 주식회사 | 표시 장치 |
CN107919090A (zh) * | 2017-11-30 | 2018-04-17 | 武汉天马微电子有限公司 | 显示面板及显示装置 |
CN108646477A (zh) * | 2018-03-27 | 2018-10-12 | 上海中航光电子有限公司 | 阵列基板、显示面板和显示装置 |
CN109683751A (zh) * | 2019-01-04 | 2019-04-26 | 合肥鑫晟光电科技有限公司 | 触控基板及其制作方法、显示装置 |
CN109633971A (zh) * | 2019-01-31 | 2019-04-16 | 厦门天马微电子有限公司 | 一种显示面板及显示装置 |
CN110827673A (zh) * | 2019-11-26 | 2020-02-21 | 京东方科技集团股份有限公司 | 显示基板和显示装置 |
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