WO2021218625A1 - 显示基板及其制作方法和显示装置 - Google Patents

显示基板及其制作方法和显示装置 Download PDF

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Publication number
WO2021218625A1
WO2021218625A1 PCT/CN2021/086859 CN2021086859W WO2021218625A1 WO 2021218625 A1 WO2021218625 A1 WO 2021218625A1 CN 2021086859 W CN2021086859 W CN 2021086859W WO 2021218625 A1 WO2021218625 A1 WO 2021218625A1
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WIPO (PCT)
Prior art keywords
layer
electrode
display
display area
gate metal
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PCT/CN2021/086859
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English (en)
French (fr)
Inventor
邱远游
黄耀
刘聪
王彬艳
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京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Priority to US17/626,770 priority Critical patent/US11778863B2/en
Publication of WO2021218625A1 publication Critical patent/WO2021218625A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/60—OLEDs integrated with inorganic light-sensitive elements, e.g. with inorganic solar cells or inorganic photodiodes
    • H10K59/65—OLEDs integrated with inorganic image sensors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1216—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission
    • H01L27/153—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars
    • H01L27/156—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars two-dimensional arrays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/35—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels
    • H10K59/353—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels characterised by the geometrical arrangement of the RGB subpixels

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a display substrate, a manufacturing method thereof, and a display device.
  • an implementation of the under-screen camera technology is to set an aperture area on the screen to set the camera. This arrangement causes the pixel density of a small area around the aperture area (called the L area) to be lower than other normal areas (called the H area).
  • some pixels in the H area and the pixels in the same row and in the L area provide Gate signals through the same signal line (Gate).
  • the other signal lines are only electrically connected to the pixels in the H zone and provide Gtae signals.
  • there will be a certain difference in the gate signal of the pixel resulting in a difference in the charging time of the pixel, which may affect the brightness uniformity of the screen. , Affect the display quality.
  • an embodiment of the present disclosure provides a display substrate, including a base substrate, a driving circuit layer on the base substrate, and a light-emitting unit, the light-emitting unit including a first electrode and a second electrode that are stacked , And a light-emitting layer located between the first electrode and the second electrode, the display substrate includes a first display area, a second display area and an opening area, the second display area is located in the first Between the display area and the opening area, the pixel density of the first display area is greater than the pixel density of the second display area;
  • the display substrate further includes a compensation capacitor for compensating the sub-pixels in the second display area.
  • the compensation capacitor includes a first electrode plate and a second electrode plate, and the first electrode plate and the second display area The gates of the sub-pixels are electrically connected, and the second electrode plate is electrically connected to the first electrode.
  • the driving circuit layer includes a source and drain electrode layer, and one of the first electrode plate and the second electrode plate and the source and drain electrode layer are provided with the same layer and the same material.
  • the second electrode plate and the source and drain electrode layers are arranged in the same layer and the same material
  • the drive circuit layer further includes a third insulating layer located on the side of the source and drain electrode layers away from the base substrate
  • the light-emitting unit is located on a side of the third insulating layer away from the base substrate, the third insulating layer, the second electrode and the light-emitting unit are provided with via holes, and the second The electrode plate is electrically connected with the first electrode through the via hole.
  • the display substrate includes a gate layer, and at least one of the first electrode plate and the second electrode plate is provided in the same layer and the same material as the gate layer.
  • the gate layer of the driving circuit layer includes a first gate metal layer and a second gate metal layer, and the first electrode plate of the compensation capacitor is connected to the first gate metal layer.
  • the gate metal layer is arranged in the same layer and the same material, and the second electrode plate of the compensation capacitor and the second gate metal layer are arranged in the same layer and the same material.
  • the first electrode plate is electrically connected to the first gate metal layer through a connecting wire, and the connecting wire and the first gate metal layer are provided in the same layer and the same material;
  • the driving circuit layer includes the first gate metal layer, the first insulating layer, the second gate metal layer, the second insulating layer, the source and drain electrode layers, and the third insulating layer, which are arranged in a direction away from the base substrate.
  • the light emitting unit is located on the side of the third insulating layer away from the base substrate, and the display substrate is provided with penetrating through the second insulating layer, the source and drain electrode layer, and the third insulating layer.
  • the insulating layer, the second electrode and the via hole of the light-emitting layer, and the second electrode is electrically connected to the first electrode through the via hole.
  • one electrode plate of the compensation capacitor and the second electrode are provided in the same layer and the same material.
  • the display substrate further includes a gate layer, wherein the driving circuit layer includes a source and drain electrode layer, the first electrode plate and the gate electrode layer are provided in the same layer and the same material, and the second electrode The plate and the source and drain electrode layers are arranged in the same layer and the same material.
  • the driving circuit layer includes a source and drain electrode layer
  • the first electrode plate and the gate electrode layer are provided in the same layer and the same material
  • the second electrode The plate and the source and drain electrode layers are arranged in the same layer and the same material.
  • the driving circuit layer further includes a third insulating layer located on a side of the source and drain electrode layer away from the base substrate, and the light-emitting unit is located at a side of the third insulating layer away from the base substrate.
  • the third insulating layer, the second electrode and the light-emitting unit are provided with via holes, and the second electrode plate is electrically connected to the first electrode through the via holes.
  • the display substrate further includes a gate layer, wherein the second electrode plate and the gate layer are provided in the same layer and the same material.
  • the gate layer of the driving circuit layer includes a first gate metal layer and a second gate metal layer, and the first electrode plate of the compensation capacitor is connected to the first gate metal layer.
  • the gate metal layer is arranged in the same layer and the same material, and the second electrode plate of the compensation capacitor and the second gate metal layer are arranged in the same layer and the same material.
  • the first electrode plate is electrically connected to the first gate metal layer through a connecting wire, and the connecting wire and the first gate metal layer are provided in the same layer and the same material;
  • the driving circuit layer includes the first gate metal layer, the first insulating layer, the second gate metal layer, the second insulating layer, the source and drain electrode layers, and the third insulating layer, which are arranged in a direction away from the base substrate.
  • the light emitting unit is located on the side of the third insulating layer away from the base substrate, and the display substrate is provided with penetrating through the second insulating layer, the source and drain electrode layer, and the third insulating layer.
  • the insulating layer, the second electrode and the via hole of the light-emitting layer, and the second electrode is electrically connected to the first electrode through the via hole.
  • embodiments of the present disclosure also provide a display device, including the display substrate described in any one of the above.
  • embodiments of the present disclosure also provide a method for manufacturing a display substrate, including the step of forming a compensation capacitor;
  • the display substrate includes a base substrate, a driving circuit layer on the base substrate, and a light-emitting unit, and the light-emitting unit includes a first electrode, a second electrode, and a first electrode and a second electrode.
  • the light-emitting layer between the two electrodes, the display substrate includes a first display area, a second display area and an open area, the second display area is located between the first display area and the open area, so The pixel density of the first display area is greater than the pixel density of the second display area, the compensation capacitor is used to compensate the sub-pixels in the second display area, and one plate of the compensation capacitor is connected to the second display area.
  • the gates of the sub-pixels in the display area are electrically connected, and the other plate is electrically connected to the first electrode.
  • FIG. 1 is a schematic diagram of the structure of a display substrate in some embodiments of the present disclosure
  • FIG. 2 is another schematic diagram of the structure of the display substrate in some embodiments of the present disclosure.
  • 3A is another schematic diagram of the structure of the display substrate in some embodiments of the present disclosure.
  • 3B is another schematic diagram of the structure of the display substrate in some embodiments of the present disclosure.
  • 4A is a simulation result of sub-pixel charging of a display substrate in the related art
  • FIG. 4B is a simulation result of sub-pixel charging of the display substrate in some embodiments of the present disclosure.
  • Some embodiments of the present disclosure provide a display substrate.
  • the display substrate includes a first display area A1, a second display area A2, and an opening area A3.
  • the first display area A1 refers to a conventional display area in the display panel.
  • the pixel density of the first display area A1 is usually higher, and it is also referred to as the H area in this embodiment.
  • the opening area A3 refers to an area where no sub-pixels are provided, and the opening area A3 is usually used to provide components including but not limited to cameras and the like.
  • the second display area A2 is usually located around the aperture area A3. It should be understood that, in order to adapt to the existence of the aperture area A3, some adaptive adjustments may be needed to the structure of the display substrate, which results in an area near the aperture area A3. The area will be affected to a certain extent. Therefore, the pixel density of the second display area A2 is generally lower than that of the first display area A1, which is also referred to as the L area in this embodiment.
  • the opening area A3 is circular, and the outer contour of the second display area A2 is rectangular, and is arranged around the opening area A3.
  • the shape and position of the second display area A2 and the aperture area A3 are not fixed.
  • the perforated area A3 can be moved to the edge of the effective display area of the display substrate, so that the second display area A2 only surrounds the portion of the perforated area A3; for another example, the second display area A2 can be combined with the perforated area Make certain adjustments to the shape of A3.
  • the shapes and positions of the second display area A2 and the aperture area A3 can be adjusted as required, and there is no further limitation here.
  • the display substrate includes a base substrate, a driving circuit layer located on the base substrate, and a light-emitting unit located on the base substrate.
  • the light-emitting unit includes a first electrode, a second electrode, and a light-emitting layer located between the first electrode and the second electrode, which are stacked.
  • the specific structure of the driving circuit layer and the light-emitting unit may refer to the related technology to a certain extent, which is not further limited and described here.
  • the display substrate further includes a compensation capacitor 110 for compensating the sub-pixels in the second display area A2.
  • the compensation capacitor 110 includes a first electrode plate and a second electrode plate, and the first electrode plate and the gates of the sub-pixels in the second display area A2 130 is electrically connected, the second electrode plate is electrically connected to the first electrode, and the first electrode is a common electrode of the light-emitting unit to provide a stable signal source through the first electrode.
  • the compensation capacitor 110 electrically connected to the gates of the sub-pixels in the second display area A2 is provided to compensate the gate signal lines of the sub-pixels in the second display area A2, thereby realizing the adjustment of the second display area A2.
  • the charging time of the sub-pixels connected to the same gate signal line in the second display area A2 is used to improve the consistency of the charging time of the sub-pixels in the first display area A1, which helps to improve The consistency of the screen brightness, thereby improving the display effect.
  • the first plate and the second plate of the compensation capacitor 110 can be manufactured separately, for example, a conductive layer is deposited at different positions to form the first plate and the second plate of the compensation capacitor 110, And correspondingly, conductive wires are made to realize electrical connection between the first electrode plate and the gate of the sub-pixel in the L area, and the second electrode plate is electrically connected to the first electrode.
  • the production of the plates of the compensation capacitor 110 is completed while other film structures in the display substrate are produced.
  • the driving circuit layer includes a source and drain electrode layer, and one of the first electrode plate and the second electrode plate and the source and drain electrode layer are provided with the same layer and the same material.
  • the source and drain electrode layers and the plates of the compensation capacitor 110 can be manufactured at the same time without adding process steps, which helps to save costs.
  • the manufacturing process is basically the same, and the main difference lies in the adjustment of the connection relationship and the connection structure of the electrical connection.
  • the production of the plates of the compensation capacitor 110 can also be completed while other film structures are made.
  • the layer, the second electrode of the light-emitting unit, and other film layer structures are arranged in the same layer and the same material.
  • a certain amount of material can be reserved through a patterning process to form the electrode plate of the compensation capacitor 110.
  • a via hole or a connecting wire can be set as required to realize electrical connection between the first electrode plate and the grid, and the second electrode plate is electrically connected with the first electrode.
  • the driving circuit layer of the display substrate includes a first gate metal layer, a first insulating layer (second gate insulating layer), a second gate metal layer, and a first gate metal layer arranged in a direction away from the base substrate.
  • the second insulating layer (interlayer dielectric layer), the source and drain electrode layer, the third insulating layer (flat layer), the light-emitting unit is located on the side of the third insulating layer away from the base substrate, and the second electrode, light-emitting layer,
  • the fourth insulating layer (pixel defining layer) and the first electrode are sequentially stacked in a direction away from the base substrate. Via holes can penetrate through different film layers as needed to achieve electrical connection.
  • a via hole that penetrates the first insulating layer and the second insulating layer can be opened. It is necessary to penetrate the second gate metal layer or avoid the second gate metal layer, so that the first electrode plate can be electrically connected to the first gate metal layer through the via hole.
  • a via hole penetrating the third insulating layer, the second electrode and the light-emitting layer can be opened to pass through the The via hole realizes the electrical connection between the source and drain electrode layer and the first electrode.
  • the first electrode plate of the compensation capacitor 110 and the first gate metal layer are arranged in the same layer and the same material. Since the first electrode plate is electrically connected to the first gate metal layer, it is possible to directly retain a part of the material.
  • the connecting line is formed, that is, the connecting line, the first gate metal layer, and the first electrode plate are simultaneously fabricated through a patterning process.
  • the second electrode plate and the second gate metal layer are arranged in the same layer and the same material. In this way, it is necessary to open the second insulating layer, the source and drain electrode layer, the third insulating layer, the second electrode and the light emitting layer. Layer via holes to realize electrical connection between the second electrode plate and the first electrode. Obviously, a conductive structure with the same layer and the same material as the source and drain electrode layers can also be reserved, and the second electrode plate is electrically connected to the conductive structure through the via hole, and further, the conductive structure is electrically connected to the first electrode through the via hole.
  • first electrode plate and the second electrode plate are not fixed.
  • first electrode plate may be located between the second electrode plate and the base substrate, or the second electrode plate may be located on the first plate.
  • the electrode plate and the base substrate only need to be electrically connected by opening corresponding via holes.
  • the first electrode plate and the second gate metal layer are arranged in the same layer and the same material and are electrically connected to the first gate metal layer through via holes, and the second electrode plate and the source and drain electrode layers are arranged in the same layer and the same material, and are connected to the The first electrode is electrically connected; in another specific embodiment, the first electrode plate and the source and drain electrode layers are arranged in the same layer and the same material, and are electrically connected to the first gate metal layer through the via hole, and the second electrode plate is connected to the The two gate metal layers are arranged in the same layer and the same material, and are electrically connected with the first electrode through the via hole.
  • the first electrode plate 3101 and the first gate metal layer 3102 are arranged in the same layer and the same material, and the two are electrically connected.
  • the first gate metal layer 3102, the first insulating layer ( (Or called the second gate insulating layer) 3013 and the second gate metal layer 3104 are stacked in sequence.
  • the second electrode plate 3105 and the second gate metal layer 3104 are arranged in the same layer and the same material and insulated from each other.
  • the first electrode plate 3101 and the second plate 3105 together form a compensation capacitor 110.
  • the second electrode plate 3105 is electrically connected to the first reserved structure 3017 through the via hole penetrating the second insulating layer 3106, wherein the first reserved structure 3107 and the source and drain electrode layers are arranged in the same layer and the same material, and the source and drain electrodes are fabricated.
  • the layer remains as a conductive structure.
  • the first reserved structure 3107 is electrically connected to the second reserved structure 3109 through a via hole penetrating the third insulating layer 3108, wherein the second reserved structure 3109 and the second electrode of the light-emitting unit are arranged in the same layer and material, and are fabricated
  • the second electrode remains as a conductive structure
  • the second reserved structure 3109 is electrically connected to the first electrode 3111 of the light-emitting unit through a via hole penetrating the fourth insulating layer 3110.
  • the first electrode plate 3201 and the second gate metal layer are provided with the same layer and the same material and are insulated from each other, and the second electrode plate 3202 and the source and drain electrode layers are provided with the same layer material. .
  • the first electrode plate 3201 is electrically connected to the first gate metal layer 3204 through a via hole penetrating the first insulating layer 3203, the first electrode plate 3201 and the second electrode plate 3202 are insulated by the second insulating layer 3205, The diode 3202 is electrically connected to the third reserved structure 3207 through the via hole penetrating the third insulating layer 3206.
  • the third reserved structure 3207 and the second electrode of the light-emitting unit are arranged in the same layer and the same material, and when the second electrode is made Remaining as a conductive structure, the third reserved structure 3207 is electrically connected to the first electrode 3209 of the light-emitting unit through a via hole penetrating the fourth insulating layer 3208.
  • the arrangement positions of the first electrode plate and the second electrode plate and the arrangement manner of the via holes can be further adjusted adaptively, which is not further limited here.
  • the compensation capacitor 110 is disposed in the second display area A2, that is, the aforementioned L area. It should be understood that the pixel density of the H area is relatively high, so there is no more area for making the compensation capacitor 110, and the aperture area A3 may need to be used for setting up devices such as a camera. Therefore, it is necessary to ensure its light transmittance. Therefore, arranging the compensation capacitor 110 in the L zone helps to reduce the possible influence on the display effect.
  • electrical simulations are performed on the pixel circuit provided with the compensation capacitor 110 and the pixel circuit without the compensation capacitor 110 to verify the effect of the compensation capacitor on the pixel.
  • the full charging time (fall time) of the Gate signal of two adjacent pixel rows is compared.
  • the larger the fall time the shorter the charging time and the higher the brightness.
  • the upper image in FIG. 4A is a simulation result of a first sub-pixel in a display substrate without a compensation capacitor.
  • the first sub-pixel is a sub-pixel located in the H area and in the same row as the L area.
  • the bottom figure in 4A is a simulation result of a second sub-pixel in a display substrate without a compensation capacitor.
  • the second sub-pixel is a sub-pixel located in the H area and located in the same column as the first sub-pixel.
  • the horizontal axis in the figure represents the charging time
  • the vertical axis represents the charging rate
  • the line between the two circles in the figure represents the pixel charging process.
  • Fig. 4B Please refer to Fig. 4B.
  • the upper picture in Fig. 4B is the simulation result of the first sub-pixel in the display substrate with the compensation capacitor
  • the lower picture in Fig. 4B is the simulation result of the second sub-pixel in the display substrate with the compensation capacitor.
  • the charging time of the sub-pixels in the H area located in the same row as the L area can be reduced from the charging time of other H areas, thereby reducing the display of the H area.
  • the embodiment of the present disclosure also provides a display device, which includes the display substrate of any one of the above.
  • a compensation capacitor electrically connected to the gate of the sub-pixel in the second display area is provided to compensate the gate signal line of the sub-pixel in the second display area, thereby realizing the adjustment of the second display area.
  • the charging time of the sub-pixels connected to the same gate signal line as the sub-pixels in the second display area is used to improve the consistency of the charging time of the sub-pixels in the first display area, which helps to improve the brightness of the screen. Consistency, thereby improving the display effect.
  • Display devices may include, but are not limited to, display devices such as mobile phones, tablet computers, digital cameras, laptop computers, vehicle-mounted computers, desktop computers, smart TVs, wearable devices, etc., because the technical solution of this embodiment includes the above-mentioned display substrate All the technical solutions of the embodiment can at least achieve all the technical effects mentioned above, which will not be repeated here.
  • the embodiment of the present disclosure also provides a manufacturing method of the display substrate, including the step of forming the compensation capacitor 110.
  • the electrode plate of the compensation capacitor 110 may be separately manufactured at a specific position, or may be manufactured simultaneously with other film layers through a patterning process as described in the above display substrate embodiment.
  • the structure of the manufactured compensation capacitor 110 please refer to the above-mentioned display substrate embodiment, and the involved process itself can also refer to the related technology, which will not be repeated here.
  • a compensation capacitor electrically connected to the gate of the sub-pixel in the second display area is provided to compensate the gate signal line of the sub-pixel in the second display area, thereby Adjust the charging time of the sub-pixels connected to the same gate signal line as the sub-pixels in the second display area in the first display area, so as to improve the consistency of the charging time of the sub-pixels in the first display area, which helps to improve The consistency of the screen brightness, thereby improving the display effect.

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Abstract

本公开提供一种显示基板及其制作方法和显示装置。显示基板包括衬底基板、位于衬底基板上的驱动电路层和发光单元，发光单元包括层叠设置的第一电极、第二电极、以及位于第一电极和第二电极之间的发光层，显示基板包括第一显示区、第二显示区和开孔区域，第二显示区位于第一显示区和开孔区域之间，第一显示区的像素密度大于第二显示区的像素密度；显示基板还包括用于补偿第二显示区内子像素的补偿电容，补偿电容包括第一极板和第二极板，第一极板与第二显示区内的子像素的栅极电连接，第二极板与第一电极电连接。

Description

显示基板及其制作方法和显示装置
相关申请的交叉引用
本申请主张在2020年4月29日在中国提交的中国专利申请号No.202010354537.3的优先权，其全部内容通过引用包含于此。
技术领域
本公开涉及显示技术领域，尤其涉及一种显示基板及其制作方法和显示装置。
背景技术
由于不同的使用需求，一些元器件需要占用显示屏的屏下空间。例如，一种屏下摄像头技术的实现方式是在屏幕上设置开孔区域以设置摄像头。这种设置方式导致开孔区域周围的一小部分区域(称作L区)的像素密度低于其他正常区域(称作H区)。
然而H区中的某些像素与位于同一行且处于L区的像素通过同一信号线(栅线，Gate)提供Gate信号。而另外一些信号线则仅与H区的像素电连接并提供Gtae信号，这两种情况下，像素的Gate信号会存在一定的差异，导致像素的充电时间也存在差异，可能影响画面亮度均一性，影响显示质量。
发明内容
第一方面，本公开实施例提供了一种显示基板，包括衬底基板、位于所述衬底基板上的驱动电路层和发光单元，所述发光单元包括层叠设置的第一电极、第二电极、以及位于所述第一电极和所述第二电极之间的发光层，所述显示基板包括第一显示区、第二显示区和开孔区域，所述第二显示区位于所述第一显示区和所述开孔区域之间，所述第一显示区的像素密度大于所述第二显示区的像素密度；
所述显示基板还包括用于补偿所述第二显示区内子像素的补偿电容，所 述补偿电容包括第一极板和第二极板，所述第一极板与所述第二显示区内的子像素的栅极电连接，所述第二极板与所述第一电极电连接。
可选的，所述驱动电路层包括源漏电极层，所述第一极板和所述第二极板中的一个与所述源漏电极层同层同材料设置。
可选的，所述第二极板与所述源漏电极层同层同材料设置，所述驱动电路层还包括位于所述源漏电极层远离所述衬底基板一侧的第三绝缘层，所述发光单元位于所述第三绝缘层远离所述衬底基板的一侧，所述第三绝缘层、所述第二电极和所述发光单元上开设有过孔，且所述第二极板通过所述过孔与所述第一电极电连接。
可选的，所述显示基板包括栅极层，所述第一极板和所述第二极板中的至少一个与所述栅极层同层同材料设置。
可选的，沿远离所述衬底基板的方向，所述驱动电路层的栅极层包括第一栅金属层和第二栅金属层，所述补偿电容的第一极板与所述第一栅金属层同层同材料设置，所述补偿电容的第二极板与所述第二栅金属层同层同材料设置。
可选的，所述第一极板通过连接线与所述第一栅金属层电连接，所述连接线与所述第一栅金属层同层同材料设置；
所述驱动电路层包括沿远离所述衬底基板的方向设置的所述第一栅金属层、第一绝缘层、所述第二栅金属层、第二绝缘层、源漏电极层、第三绝缘层，所述发光单元位于所述第三绝缘层远离所述衬底基板的一侧，所述显示基板上开设有贯穿所述第二绝缘层、所述源漏电极层、所述第三绝缘层、所述第二电极和所述发光层的过孔，所述第二电极通过所述过孔与所述第一电极电连接。
可选的，所述补偿电容的一个极板与所述第二电极同层同材料设置。
可选的，所述显示基板还包括栅极层，其中，所述驱动电路层包括源漏电极层，所述第一极板与所述栅极层同层同材料设置，所述第二极板与所述源漏电极层同层同材料设置。
可选的，所述驱动电路层还包括位于所述源漏电极层远离所述衬底基板一侧的第三绝缘层，所述发光单元位于所述第三绝缘层远离所述衬底基板的 一侧，所述第三绝缘层、所述第二电极和所述发光单元上开设有过孔，且所述第二极板通过所述过孔与所述第一电极电连接。
可选的，所述显示基板还包括栅极层，其中，所述第二极板与所述栅极层同层同材料设置。
可选的，沿远离所述衬底基板的方向，所述驱动电路层的栅极层包括第一栅金属层和第二栅金属层，所述补偿电容的第一极板与所述第一栅金属层同层同材料设置，所述补偿电容的第二极板与所述第二栅金属层同层同材料设置。
可选的，所述第一极板通过连接线与所述第一栅金属层电连接，所述连接线与所述第一栅金属层同层同材料设置；
所述驱动电路层包括沿远离所述衬底基板的方向设置的所述第一栅金属层、第一绝缘层、所述第二栅金属层、第二绝缘层、源漏电极层、第三绝缘层，所述发光单元位于所述第三绝缘层远离所述衬底基板的一侧，所述显示基板上开设有贯穿所述第二绝缘层、所述源漏电极层、所述第三绝缘层、所述第二电极和所述发光层的过孔，所述第二电极通过所述过孔与所述第一电极电连接。
第二方面，本公开实施例还提供了一种显示装置，包括以上任一项所述的显示基板。
第三方面，本公开实施例还提供了一种显示基板的制作方法，包括形成补偿电容的步骤；
其中，所述显示基板包括衬底基板、位于所述衬底基板上的驱动电路层和发光单元，所述发光单元包括第一电极、第二电极、以及位于所述第一电极和所述第二电极之间的发光层，所述显示基板包括第一显示区、第二显示区和开孔区域，所述第二显示区位于所述第一显示区和所述开孔区域之间，所述第一显示区的像素密度大于所述第二显示区的像素密度，所述补偿电容用于补偿所述第二显示区内的子像素，所述补偿电容的一个极板与所述第二显示区内的子像素的栅极电连接，另一个极板与所述第一电极电连接。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对本公开实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获取其他的附图。
图1是本公开一些实施例中显示基板的结构示意图；
图2是本公开一些实施例中显示基板的又一结构示意图；
图3A是本公开一些实施例中显示基板的又一结构示意图；
图3B是本公开一些实施例中显示基板的又一结构示意图；
图4A是相关技术中显示基板的子像素充电仿真结果；
图4B是本公开一些实施例中显示基板的子像素充电仿真结果。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获取的所有其他实施例，都属于本公开保护的范围。
本公开的一些实施例提供了一种显示基板。
如图1所示，在本公开的一些实施例中，显示基板包括第一显示区A1、第二显示区A2和开孔区域A3。
本实施例中，第一显示区A1指的是显示面板中常规的显示区，该第一显示区A1像素密度通常较高，本实施例中又将其称作H区。
开孔区域A3指的是未设置子像素的区域，该开孔区域A3通常用于设置包括但不限于摄像头等元器件等。
第二显示区A2通常位于开孔区域A3的周围，应当理解的是，为了适应开孔区域A3的存在，可能需要对显示基板的结构作出一些适应性调整，这导致开孔区域A3的附近的区域会受到一定的影响，因此，该第二显示区A2的像素密度通常小于第一显示区A1，本实施例中又将其称作L区。
如图1所示，在本公开的一些实施例，开孔区域A3呈圆形，第二显示区A2的外部轮廓呈矩形，且环绕开孔区域A3设置。
显然，该第二显示区A2和开孔区域A3的形状和位置均不是固定不变的。例如，可以将开孔区域A3移动至显示基板的有效显示区的边缘处，这样，第二显示区A2仅环绕开孔区域A3的部分；又如，可以将第二显示区A2和开孔区域A3的形状作出一定的调整。具体地，可以根据需要对于第二显示区A2和开孔区域A3的形状和位置作出调整，此处不做进一步限定。
本实施例中，显示基板包括衬底基板、位于衬底基板上的驱动电路层和位于衬底基板上的发光单元。其中，发光单元包括层叠设置的第一电极、第二电极、以及位于第一电极和第二电极之间的发光层。驱动电路层和发光单元的具体结构可以一定程度上参考相关技术，此处不作进一步限定和描述。
显示基板还包括用于补偿第二显示区A2内子像素的补偿电容110，补偿电容110包括第一极板和第二极板，第一极板与第二显示区A2内的子像素的栅极130电连接，第二极板与第一电极电连接，该第一电极为发光单元的公共电极，以通过该第一电极提供稳定的信号源。
这样，本公开实施例通过设置与第二显示区A2内的子像素的栅极电连接的补偿电容110，以对第二显示区A2中的子像素的栅信号线进行补偿，从而实现调整第一显示区A1中，与第二显示区A2中子像素连接至同一栅信号线的子像素的充电时间，以提高第一显示区A1中的子像素的充电时间的一致性，有助于提高画面亮度的一致性，从而提高显示效果。
在本公开一些实施例中，补偿电容110的第一极板和第二极板可以单独制作，例如，分别在不同的位置沉积导电层形成补偿电容110的第一极板和第二极板，并相应的制作导电线实现第一极板与L区的子像素的栅极电连接，第二极板与第一电极电连接。
在本公开其它一些实施例中，则是在制作显示基板中其他膜层结构的同时，完成了补偿电容110的极板的制作。
具体的，驱动电路层包括源漏电极层，第一极板和第二极板中的一个与源漏电极层同层同材料设置。
以第二极板与源漏电极层同层同材料设置为例说明，在制作源漏电极层时，首先形成金属材料层，然后通过一次构图工艺完成源漏电极层和第二极板的制作。
这一过程中，通过调整mask(掩膜版)的结构，即可在不增加工艺步骤的情况下，同时完成源漏电极层和补偿电容110的极板的制作，有助于节约成本。
显然，如果第一极板与源漏电极层同层同材料设置，其制作工艺也基本相同，主要区别在于调整电连接的连接关系和连接结构。
在本公开其它一些实施例中，也可以在制作其他一些膜层结构的同时完成补偿电容110的极板的制作，例如补偿电容110的极板还可以与包括但不限于驱动电路层的栅极层、发光单元的第二电极等膜层结构同层同材料设置。
也就是说，可以在制作其他导电膜层的同时，通过一次构图工艺保留一定的材料形成补偿电容110的极板。
进一步的，还可以根据需要开设过孔或设置连接线以实现第一极板与栅极电连接，第二极板与第一电极电连接。
在本公开一些实施例中，显示基板的驱动电路层包括沿远离衬底基板的方向设置的第一栅金属层、第一绝缘层(第二栅极绝缘层)、第二栅金属层、第二绝缘层(层间介质层)、源漏电极层、第三绝缘层(平坦层)，发光单元位于第三绝缘层远离衬底基板的一侧，且发光单元的第二电极、发光层、第四绝缘层(像素界定层)和第一电极沿着远离衬底基板的方向依次层叠设置。过孔则可以根据需要贯穿不同的膜层，以实现电连接。
在本公开一些实施例中，补偿电容110的第一极板与源漏电极层同层同材料设置，则可以开设贯穿第一绝缘层、第二绝缘层的过孔，该过孔还可以根据需要贯穿第二栅金属层或避让第二栅金属层，这样，第一极板可以通过该过孔与第一栅金属层电连接。
在本公开其它一些实施例中，补偿电容110的第二极板与源漏电极层同层同材料设置，则可以开设贯穿第三绝缘层、第二电极和发光层的过孔，以通过该过孔实现源漏电极层与第一电极的电连接。
在本公开其它一些实施例中，补偿电容110的第一极板与第一栅金属层同层同材料设置，由于第一极板与第一栅金属层电连接，所以可以直接通过保留一部分材料形成连接线，也就是说，连接线、第一栅金属层、第一极板通过一次构图工艺同时制作。
在本公开其它一些实施例中，第二极板与第二栅金属层同层同材料设置，这样，需要开设贯穿第二绝缘层、源漏电极层、第三绝缘层、第二电极和发光层的过孔以实现第二极板与第一电极电连接。显然，也可以预留与源漏电极层同层同材料设置的导电结构，第二极板通过过孔与该导电结构电连接，进一步的，该导电结构通过过孔与第一电极电连接。
应当理解的是，第一极板和第二极板的位置并非固定的，例如，可以是第一极板位于第二极板和衬底基板之间，也可以是第二极板位于第一极板和衬底基板之间，只要通过开设相应的过孔实现电连接即可。
例如，第一极板与第二栅金属层同层同材料设置且通过过孔与第一栅金属层电连接，第二极板与源漏电极层同层同材料设置，且通过过孔与第一电极电连接；在另外一个具体实施方式中，则是第一极板与源漏电极层同层同材料设置，且通过过孔与第一栅金属层电连接，第二极板与第二栅金属层同层同材料设置，且通过过孔与第一电极电连接。
下面，请参阅图3A和图3B所示的实施例做进一步说明。
如图3A所示，在本公开一些实施例中，第一极板3101与第一栅金属层3102同层同材料设置，且两者电连接，第一栅金属层3102、第一绝缘层(或称第二栅极绝缘层)3013、第二栅金属层3104依次层叠设置，第二极板3105与第二栅金属层3104同层同材料设置且两者之间相互绝缘，第一极板3101和第二极板3105共同组成了补偿电容110。
第二极板3105通过贯穿第二绝缘层3106的过孔与第一预留结构3017电连接，其中，第一预留结构3107与源漏电极层同层同材料设置，并在制作源漏电极层时保留下来作为导电结构。第一预留结构3107通过贯穿第三绝缘层3108的过孔与第二预留结构3109电连接，其中，第二预留结构3109与发光单元的第二电极同层同材料设置，并在制作第二电极时保留下来作为导电结构，第二预留结构3109通过贯穿第四绝缘层3110的过孔与发光单元的第一电极3111电连接。
如图3B所示，在本公开其它一些实施例中，第一极板3201与第二栅金属层同层同材料设置且相互绝缘设置，第二极板3202与源漏电极层同层材料设置。
进一步的，第一极板3201通过贯穿第一绝缘层3203的过孔与第一栅金属层3204电连接，第一极板3201和第二极板3202之间通过第二绝缘层3205绝缘，第二极板3202通过贯穿第三绝缘层3206的过孔与第三预留结构3207电连接，第三预留结构3207与发光单元的第二电极同层同材料设置，并在制作第二电极时保留下来作为导电结构，第三预留结构3207通过贯穿第四绝缘层3208的过孔与发光单元的第一电极3209电连接。
显然，第一极板和第二极板的设置位置和过孔的设置方式可以进一步作出适应性调整，此处不做进一步限定。
本公开的一些实施例中，将补偿电容110设置于第二显示区A2，也就是上述L区。应当理解的是，H区的像素密度相对较高，因此没有更多的区域用于制作补偿电容110，而开孔区域A3可能需要用于设置摄像头等装置，因此，需要保证其透光率，因此，将补偿电容110设置在L区，有助于降低对于显示效果可能产生的影响。
进一步的，本实施例中还对设置有上述补偿电容110和未设置上述补偿电容110的像素电路进行了电学仿真，以验证补偿电容对于像素带来的影响效果。
仿真过程中，比较了相邻两行像素行的Gate信号的完全充电时间(fall time)，通常情况下，fall time越大，充电时间越少，亮度越高。
请参阅图4A，图4A中的上图为未设置补偿电容的显示基板中第一子像素的仿真结果，该第一子像素为一个位于H区且与L区位于同一行的子像素，图4A中下图为未设置补偿电容的显示基板中第二子像素的仿真结果，该第二子像素为位于H区，且与第一子像素位于同一列的子像素。
图中横轴代表充电时间，纵轴代表充电率，图中两个圆圈之间的线条代表像素充电过程。可见，电容补偿前，第一子像素和第二子像素的栅信号)Gate信号的fall time相差较大，约为15.7ns(纳秒)左右。
请参阅图4B，图4B中的上图为设置补偿电容的显示基板中第一子像素的仿真结果，图4B中下图为设置补偿电容的显示基板中第二子像素的仿真结果，可见，设置电容补偿后，第一子像素和第二子像素的Gate信号的fall time显著减小，约减小为2ns左右，说明此案例中的电容补偿方式是有效的。
也就是说，本实施例中通过在L区设置补偿电容，能够使与L区位于同一行的H区的子像素的充电时间与其他H区的充电时间差距减小，从而降低对于H区显示效果一致性的影响。
本公开实施例还提供了一种显示装置，包括以上任一项的显示基板。
根据本发明实施例的显示装置，通过设置与第二显示区内的子像素的栅极电连接的补偿电容，以对第二显示区中的子像素的栅信号线进行补偿，从而实现调整第一显示区中，与第二显示区中子像素连接至同一栅信号线的子像素的充电时间，以提高第一显示区中的子像素的充电时间的一致性，有助于提高画面亮度的一致性，从而提高显示效果。
显示装置可以包括但不限于手机、平板电脑、数码相机、膝上型便携计算机、车载电脑、台式计算机、智能电视机、可穿戴设备等显示装置，由于本实施例的技术方案包括了上述显示基板实施例的全部技术方案，因此至少能实现上述全部技术效果，此处不再赘述。
本公开实施例还提供了一种显示基板的制作方法，包括形成补偿电容110的步骤。
制作过程中，可以在特定的位置单独制作补偿电容110的极板，也可以如上述显示基板实施例中描述通过一次构图工艺与其他膜层同时制作。所制作的补偿电容110的结构具体可参考上述显示基板实施例，而所涉及的工艺本身也可以参考相关技术，此处不再赘述。
根据本发明实施例的显示基板的制作方法，通过设置与第二显示区内的子像素的栅极电连接的补偿电容，以对第二显示区中的子像素的栅信号线进行补偿，从而实现调整第一显示区中，与第二显示区中子像素连接至同一栅信号线的子像素的充电时间，以提高第一显示区中的子像素的充电时间的一致性，有助于提高画面亮度的一致性，从而提高显示效果。
以上，仅为本公开的一些实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以权利要求的保护范围为准。

Claims (14)

  1. 一种显示基板，包括衬底基板、位于所述衬底基板上的驱动电路层和发光单元，所述发光单元包括层叠设置的第一电极、第二电极、以及位于所述第一电极和所述第二电极之间的发光层，所述显示基板包括第一显示区、第二显示区和开孔区域，所述第二显示区位于所述第一显示区和所述开孔区域之间，所述第一显示区的像素密度大于所述第二显示区的像素密度；
    所述显示基板还包括用于补偿所述第二显示区内子像素的补偿电容，所述补偿电容包括第一极板和第二极板，所述第一极板与所述第二显示区内的子像素的栅极电连接，所述第二极板与所述第一电极电连接。
  2. 如权利要求1所述的显示基板，其中，所述驱动电路层包括源漏电极层，所述第一极板和所述第二极板中的一个与所述源漏电极层同层同材料设置。
  3. 如权利要求2所述的显示基板，其特征在于，所述第二极板与所述源漏电极层同层同材料设置，所述驱动电路层还包括位于所述源漏电极层远离所述衬底基板一侧的第三绝缘层，所述发光单元位于所述第三绝缘层远离所述衬底基板的一侧，所述第三绝缘层、所述第二电极和所述发光单元上开设有过孔，且所述第二极板通过所述过孔与所述第一电极电连接。
  4. 如权利要求1所述的显示基板，还包括栅极层，其中，所述第一极板与所述栅极层同层同材料设置。
  5. 如权利要求4所述的显示基板，其中，沿远离所述衬底基板的方向，所述驱动电路层的栅极层包括第一栅金属层和第二栅金属层，所述补偿电容的第一极板与所述第一栅金属层同层同材料设置，所述补偿电容的第二极板与所述第二栅金属层同层同材料设置。
  6. 如权利要求5所述的显示基板，其中，所述第一极板通过连接线与所述第一栅金属层电连接，所述连接线与所述第一栅金属层同层同材料设置；
    所述驱动电路层包括沿远离所述衬底基板的方向设置的所述第一栅金属层、第一绝缘层、所述第二栅金属层、第二绝缘层、源漏电极层、第三绝缘层，所述发光单元位于所述第三绝缘层远离所述衬底基板的一侧，所述显示 基板上开设有贯穿所述第二绝缘层、所述源漏电极层、所述第三绝缘层、所述第二电极和所述发光层的过孔，所述第二电极通过所述过孔与所述第一电极电连接。
  7. 如权利要求1所述的显示基板，其中，所述补偿电容的一个极板与所述第二电极同层同材料设置。
  8. 如权利要求1所述的显示基板，还包括栅极层，其中，所述驱动电路层包括源漏电极层，所述第一极板与所述栅极层同层同材料设置，所述第二极板与所述源漏电极层同层同材料设置。
  9. 如权利要求8所述的显示基板，其中，所述驱动电路层还包括位于所述源漏电极层远离所述衬底基板一侧的第三绝缘层，所述发光单元位于所述第三绝缘层远离所述衬底基板的一侧，所述第三绝缘层、所述第二电极和所述发光单元上开设有过孔，且所述第二极板通过所述过孔与所述第一电极电连接。
  10. 如权利要求1所述的显示基板，还包括栅极层，其中，所述第二极板与所述栅极层同层同材料设置。
  11. 如权利要求10所述的显示基板，其中，沿远离所述衬底基板的方向，所述驱动电路层的栅极层包括第一栅金属层和第二栅金属层，所述补偿电容的第一极板与所述第一栅金属层同层同材料设置，所述补偿电容的第二极板与所述第二栅金属层同层同材料设置。
  12. 如权利要求11所述的显示基板，其中，所述第一极板通过连接线与所述第一栅金属层电连接，所述连接线与所述第一栅金属层同层同材料设置；
    所述驱动电路层包括沿远离所述衬底基板的方向设置的所述第一栅金属层、第一绝缘层、所述第二栅金属层、第二绝缘层、源漏电极层、第三绝缘层，所述发光单元位于所述第三绝缘层远离所述衬底基板的一侧，所述显示基板上开设有贯穿所述第二绝缘层、所述源漏电极层、所述第三绝缘层、所述第二电极和所述发光层的过孔，所述第二电极通过所述过孔与所述第一电极电连接。
  13. 一种显示装置，包括权利要求1至12中任一项所述的显示基板。
  14. 一种显示基板的制作方法，包括形成补偿电容的步骤；
    其中，所述显示基板包括衬底基板、位于所述衬底基板上的驱动电路层和发光单元，所述发光单元包括第一电极、第二电极、以及位于所述第一电极和所述第二电极之间的发光层，所述显示基板包括第一显示区、第二显示区和开孔区域，所述第二显示区位于所述第一显示区和所述开孔区域之间，所述第一显示区的像素密度大于所述第二显示区的像素密度，所述补偿电容用于补偿所述第二显示区内的子像素，所述补偿电容的一个极板与所述第二显示区内的子像素的栅极电连接，另一个极板与所述第一电极电连接。
PCT/CN2021/086859 2020-04-29 2021-04-13 显示基板及其制作方法和显示装置 WO2021218625A1 (zh)

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