WO2021088792A1 - 像素驱动电路、显示设备和像素驱动电路驱动方法 - Google Patents

像素驱动电路、显示设备和像素驱动电路驱动方法 Download PDF

Info

Publication number
WO2021088792A1
WO2021088792A1 PCT/CN2020/126116 CN2020126116W WO2021088792A1 WO 2021088792 A1 WO2021088792 A1 WO 2021088792A1 CN 2020126116 W CN2020126116 W CN 2020126116W WO 2021088792 A1 WO2021088792 A1 WO 2021088792A1
Authority
WO
WIPO (PCT)
Prior art keywords
circuit
sub
duration
driving
control
Prior art date
Application number
PCT/CN2020/126116
Other languages
English (en)
French (fr)
Inventor
刘冬妮
玄明花
Original Assignee
京东方科技集团股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US17/417,238 priority Critical patent/US11398184B2/en
Publication of WO2021088792A1 publication Critical patent/WO2021088792A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2007—Display of intermediate tones
    • G09G3/2077—Display of intermediate tones by a combination of two or more gradation control methods
    • G09G3/2081—Display of intermediate tones by a combination of two or more gradation control methods with combination of amplitude modulation and time modulation
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3258—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the voltage across the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0833—Several active elements per pixel in active matrix panels forming a linear amplifier or follower
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0852—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor being a dynamic memory with more than one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0259—Details of the generation of driving signals with use of an analog or digital ramp generator in the column driver or in the pixel circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0275—Details of drivers for data electrodes, other than drivers for liquid crystal, plasma or OLED displays, not related to handling digital grey scale data or to communication of data to the pixels by means of a current
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/061—Details of flat display driving waveforms for resetting or blanking
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/066—Waveforms comprising a gently increasing or decreasing portion, e.g. ramp

Definitions

  • the present application relates to the display field, and in particular to a pixel driving circuit, a display device, and a pixel driving circuit driving method.
  • Miniature inorganic light-emitting diodes have broad development prospects in the display field because of their high brightness and high reliability.
  • the present application provides an improved pixel driving circuit, a display device, and a pixel driving circuit driving method.
  • the present application provides a pixel driving circuit for providing signals to elements to be driven, including a driving sub-circuit, a time length control sub-circuit, and a data writing sub-circuit, wherein the driving sub-circuits are electrically connected to the time length control sub-circuits respectively And the data writing sub-circuit, the data writing sub-circuit is used to transmit a data signal to the driving sub-circuit, the duration control sub-circuit is used to control the on-duration of the driving sub-circuit, the driving The sub-circuit is used for controlling the current of the component to be driven according to the data signal during the on-time.
  • the duration control sub-circuit includes a comparator connected to a reference voltage signal line, the driving sub-circuit, and a duration signal line respectively, and the comparator is used to compare the duration signal line input
  • the duration signal and the reference voltage signal provided by the reference voltage signal line output a comparison signal to control the conduction duration of the driving sub-circuit.
  • the positive input terminal of the comparator is connected to the duration signal line
  • the negative input terminal of the comparator is connected to the reference voltage signal line
  • the output terminal of the comparator is connected to the driving sub-circuit .
  • the reference voltage signal is a triangular wave signal, a sawtooth wave signal, or a sine wave signal.
  • the duration control sub-circuit further includes a duration control transistor, the gate of the duration control transistor is connected to the output terminal of the comparator, and the first pole is connected to a duration control for providing a duration control signal.
  • the second pole of the signal line is connected to the driving sub-circuit, and the duration control transistor is used for outputting the duration control signal according to the comparison signal to control the on-duration of the driving sub-circuit.
  • the duration control sub-circuit further includes a duration writing sub-circuit, the input terminal of the duration writing sub-circuit is connected to the duration signal line, and the output terminal is connected to the first input of the comparator Terminal, and the control terminal of the time length writing sub-circuit is connected to the data writing control signal line, and the time length writing sub-circuit is used to receive the data writing control signal output by the data writing control signal line, according to the The data writing control signal connects the duration signal line and the comparator.
  • the duration control sub-circuit further includes a duration storage capacitor, the first terminal of the duration storage capacitor is connected to the first input terminal of the comparator and the output terminal of the duration writing sub-circuit.
  • the driving sub-circuit includes a driving transistor, the gate of the driving transistor is connected to the second pole of the duration control transistor of the duration control sub-circuit, and the first pole of the driving transistor is connected to the second pole of the duration control transistor of the duration control sub-circuit.
  • the data writing sub-circuit is connected, and the second pole of the driving transistor is connected to the component to be driven.
  • the data writing sub-circuit includes a data writing transistor, and a first pole of the data writing transistor is electrically connected to a data line to receive a data signal input from the data line.
  • the second pole of the input transistor is electrically connected to the driving sub-circuit, and the gate of the data writing transistor is electrically connected to the data writing control signal line to receive the data writing control signal.
  • the pixel driving circuit further includes at least one of the following: a reset sub-circuit, which is connected to the driving sub-circuit and the to-be-driven element, respectively, and is used to control the driving sub-circuit and the to-be-driven element.
  • the driving element is reset;
  • the compensation sub-circuit is connected to the data writing sub-circuit through the driving sub-circuit, and is used to store the data signal input by the data writing sub-circuit; the work control sub-circuit, and the driver
  • the circuit connection is used to control the driving sub-circuit to drive the component to be driven to emit light.
  • the present application provides a display device, including an element to be driven and the aforementioned pixel driving circuit, and the pixel driving circuit is connected to the element to be driven.
  • the display device includes a plurality of sub-pixels, and each of the sub-pixels is provided with a corresponding pixel driving circuit for driving the elements to be driven of the sub-pixels to emit light.
  • the display device further includes: multiple duration signal lines for transmitting duration signals; multiple data signal lines for transmitting the data signals; multiple duration control signal lines for transmitting time duration signals; The duration control signal; wherein each of the pixel drive circuits corresponding to the sub-pixels in the same row is electrically connected to the same duration control signal line; each of the pixel drive circuits corresponding to the sub-pixels in the same column is connected to the same The duration signal line is electrically connected to the same data signal line.
  • the present application provides a pixel driving circuit driving method applied to the aforementioned pixel driving circuit, including: writing a data signal to the driving sub-circuit; writing a work control signal to control the driving sub-circuit to conduct , To drive the element to be driven to emit light according to the data signal; to control the on-duration of the driving sub-circuit to control the light-emitting duration of the element to be driven.
  • the controlling the conduction duration of the driving sub-circuit includes: writing a duration signal; comparing the duration signal and a reference voltage signal to generate a comparison signal to control the conduction duration of the driving sub-circuit.
  • FIG. 1 is a block diagram of a pixel driving circuit of an embodiment provided by the present application
  • FIG. 2 is a specific circuit structure diagram of the pixel driving circuit shown in FIG. 1;
  • FIG. 3 is an input and output waveform diagram of the comparator of the embodiment of the present application in two frame periods
  • FIG. 4 is a diagram of a specific circuit structure of the comparator shown in FIG. 2;
  • FIG. 5 is a timing diagram of the pixel driving circuit shown in FIG. 2;
  • FIG. 6 is a pixel matrix diagram of an embodiment of the display device provided by this application.
  • FIG. 7 is a block diagram of a pixel driving circuit according to an embodiment provided by this application.
  • the working time length of the components to be driven described in the text can be understood as the light-emitting time length of the light-emitting diode.
  • inorganic light-emitting diodes such as micro LEDs and mini LEDs
  • their luminous efficiency, brightness of emitted light, and color coordinates will change with the current density at low current densities, leading to display quality problem. Since a current with a high current density can drive the element to be driven to emit stable light, in order to ensure luminous efficiency, it can be considered to use a current with a high current density to drive the element to be driven to emit light to display an image.
  • FIG. 1 and FIG. 7 are block diagrams of the pixel driving circuit 100 according to the embodiment provided in the present application.
  • the pixel driving circuit 100 is disposed in the display device 800, and the display device 800 includes an element 70 to be driven.
  • the pixel driving circuit 100 is connected to the element 70 to be driven, and is used to drive the element 70 to be driven to emit light.
  • the pixel driving circuit 100 includes a driving sub-circuit 40, a duration control sub-circuit 10 and a data writing sub-circuit 30, wherein the driving sub-circuit 40 is electrically connected to the duration control sub-circuit 10 and the data writing sub-circuit 30, respectively.
  • the data writing sub-circuit 30 is used to transmit the data signal Data_I.
  • the duration control sub-circuit 10 is used to control the on duration of the driving sub-circuit 40.
  • the driving sub-circuit 40 is used for controlling the current of the component 70 to be driven according to the data signal Data_I during the on-time.
  • the pixel driving circuit 100 can control the current and the light-emitting duration of the element 70 to be driven, and can control the current to be large, so that the emitted light has high stability, and can individually control the current to achieve high-gray-scale image display. It can also control the current and light-emitting Time length, to achieve accurate display of low grayscale images under high current.
  • the light-emitting duration can be controlled according to the size of the current and the grayscale of the image to be displayed. The lower the image grayscale, the shorter the light-emitting duration. By adjusting the current and the light-emitting duration, the emitted light is stable and the grayscale of the image is accurate, which improves the display The accuracy of the image.
  • the component to be driven 70 includes a light emitting diode.
  • the data signal Data_I transmitted by the data writing sub-circuit 30 can be a fixed high-level signal that enables the miniature inorganic light-emitting diode to have higher luminous efficiency.
  • the pixel driving circuit mainly controls the gray scale through the duration control sub-circuit 10.
  • the potential of the data signal Data_I can take a value within a certain voltage interval, and the data signal within the voltage interval can ensure that the miniature inorganic light-emitting diode has a higher luminous efficiency.
  • the pixel drive circuit passes the data The signal Data_I and the time control circuit 10 jointly control the light-emitting brightness of the miniature inorganic light-emitting diode.
  • the pixel driving circuit 100 receives the time-length signal Data_T and the data signal Data_I that are input according to the time sequence in one frame period, and controls the light-emitting time of the element 70 to be driven in one frame period according to the time-length signal Data_T, and according to the data signal Data_I controls the current density flowing through the component 70 to be driven in the current frame period. In this way, independent control of the driving current and the light-emitting duration of the drive element 70 to be driven is achieved.
  • the duration control sub-circuit 10 of the pixel driving circuit 100 is used to receive the duration signal Data_T
  • the data writing sub-circuit 30 is used to receive the data signal Data_I.
  • the driving sub-circuit 40 of the pixel driving circuit 100 includes a control terminal 401, a first terminal 402, and a second terminal 403.
  • the driving sub-circuit 40 is connected to the data writing sub-circuit 30 through the first terminal 402, and is connected to the data writing sub-circuit 30 through the control terminal 401 and the duration control sub-circuit.
  • the circuit 10 is connected, and is connected to the component 70 to be driven through the second terminal 403.
  • the data writing sub-circuit 30 writes the data signal Data_I to the driving sub-circuit 40 through the first terminal 402; the driving sub-circuit 40 generates a driving current according to the data signal Data_I, and outputs the current from the second terminal 403 to the component to be driven 70;
  • the duration control sub-circuit 10 controls the conduction duration of the driving sub-circuit 40 through the control terminal 401.
  • the duration control sub-circuit 10 controls the driving sub-circuit 40 to turn off when the component 70 to be driven emits light for a set duration, so that the component 70 to be driven stops emitting light, thereby controlling the luminous duration of the component 70 to be driven.
  • the pixel driving circuit 100 receives the data write control signal Gate_A.
  • the data write control signal Gate_A can control the duration control sub-circuit 10 to communicate with the duration signal line 31 (see Figure 2), the data write sub-circuit 30 and the data signal line 32 (see Figure 2) are connected, and the duration control sub-circuit 10 receives the duration.
  • the data writing sub-circuit 30 receives the data signal Data_I.
  • FIG. 7 shows an example in which the second end 403 of the driving sub-circuit 40 is directly connected to the element to be driven 70, the present application is not limited to this.
  • the driving sub-circuit 40 may be connected to the to-be-driven element 70 when there is an intermediate element (for example, the work control sub-circuit 20 shown in FIG. 1) therebetween.
  • the pixel driving circuit 100 further includes a reset sub-circuit 60, a compensation sub-circuit 50 and a work control sub-circuit 20, and a power supply terminal VDD.
  • the reset sub-circuit 60 is respectively connected to the driving sub-circuit 40 and the to-be-driven element 70 for resetting the driving sub-circuit 40 and the to-be-driven element 70.
  • the reset sub-circuit 60 is respectively connected to the control terminal 401 of the driving sub-circuit 40 and the positive voltage terminal of the component 70 to be driven.
  • the reset sub-circuit 60 inputs the reset voltage Vinit to the control terminal 401 of the driving sub-circuit 40 and the component to be driven 70 under the control of the reset control signal RST to control the driving sub-circuit 40
  • the voltage on the terminal 401 and the component to be driven 70 is reset to eliminate the influence of the remaining data signal Data_I or the duration signal Data_T from the previous frame period on the current frame period.
  • the compensation sub-circuit 50 is connected to the data writing sub-circuit 30 through the driving sub-circuit 40, and is used to store the data signal input by the data writing sub-circuit 30. In some embodiments, the compensation sub-circuit 50 is also used to store the threshold voltage of the driving sub-circuit 40. In some embodiments, the compensation sub-circuit 50 is connected between the control terminal 401 and the second terminal 403 of the driving sub-circuit 40. The compensation sub-circuit 50 stores the threshold voltage of the driving sub-circuit 40 under the control of the data writing control signal Gate_A. The signal and data are written into the data signal Data_I input by the drive circuit 20.
  • the threshold voltage signal compensates the driving sub-circuit 40, so that the driving current output by the driving sub-circuit 40 is only related to the data signal Data_I, and is not affected by the The threshold voltage of the driving sub-circuit 40 itself is affected, thereby improving the accuracy of the output driving current.
  • the work control sub-circuit 20 and the driving sub-circuit 40 are connected to control the driving sub-circuit 40 to drive the element 70 to be driven to emit light.
  • the work control sub-circuit 20 controls the on-off between the power supply terminal VDD and the driving sub-circuit 40, as well as the on-off between the driving sub-circuit 40 and the component to be driven 70, Furthermore, the time point at which the driving sub-circuit 40 drives the element 70 to be driven to emit light is controlled.
  • the pixel driving circuit 100 receives the duration signal Data_T, the data signal Data_I, the reset voltage Vinit, the data write control signal Gate_A, and the work control signal EM involved in the above description according to the time sequence within one frame period.
  • the display device 800 includes at least one signal output circuit (not shown) for outputting the duration signal Data_T, the data signal Data_I, the reset voltage Vinit, the data writing control signal Gate_A, and the work sequence according to the time sequence in one frame period. Control signal EM.
  • the pixel driving circuit 100 is connected to the signal output circuit to receive corresponding signals according to time sequence.
  • FIG. 2 is a specific circuit structure diagram of the pixel driving circuit 100 shown in FIG. 1. It should be noted that the specific circuit structures of the duration control sub-circuit 10, the driving sub-circuit 40 and the data writing sub-circuit 30 shown in FIG. 2 can also be applied to the pixel driving circuit 100 shown in FIG. 7.
  • the component to be driven 70 may include a miniature light emitting diode D1;
  • the duration control sub-circuit 10 includes a comparator U1, the comparator U1 is connected to the driving sub-circuit 40 and the duration signal line 31, and the comparator U1 is used to compare the duration signal line 31 input
  • the duration signal Data_T and the reference voltage signal Vref output the comparison signal V_out to control the conduction duration of the driving sub-circuit 40.
  • the comparator U1 compares the duration signal Data_T with the reference voltage signal Vref to generate the comparison signal V_out, and the circuit structure is simple.
  • the duration control sub-circuit 10 includes a duration write sub-circuit 102, the duration write sub-circuit 102 is connected between the duration signal line 31 and the comparator U1, and the duration write sub-circuit 102 and the data write control signal The line 33 is connected, and the duration writing sub-circuit 102 is used to receive the data write control signal Gate_A output by the data write control signal line 33, and connect the duration signal line 31 and the comparator U1 according to the data write control signal Gate_A.
  • the time length writing sub-circuit 102 controls the on and off between the time length signal line 31 and the comparator U1, and after the comparator U1 receives the time length signal Data_T input from the time length signal line 31, the time length signal line 31 and the comparator U1 are interrupted.
  • the connection can prevent the duration signal line 31 from inputting the duration signal Data_T of the next frame before the end of the current frame period, which will affect the image display in the current frame period.
  • the duration write sub-circuit 102 includes a duration write transistor T8, the gate of the duration write transistor T8 is connected to the data write control signal line 33, the first pole is connected to the duration signal line 31, and the second pole is connected to the comparator. U1, the data write control signal Gate_A passes on the duration write transistor T8, and then connects the duration signal line 31 and the comparator U1.
  • the duration control sub-circuit 10 includes a duration storage capacitor C2.
  • the duration storage capacitor C2 is connected between the comparator U1 and the duration writing sub-circuit 102.
  • the duration storage capacitor C2 is used to store the duration signal Data_T so that the duration When the writing sub-circuit 102 is disconnected, the duration storage capacitor C2 can provide a duration signal Data_T for the comparator U1 to compare the duration signal Data_T with the reference voltage signal Vref and generate a comparison signal V_out.
  • the reference voltage signal Vref is a time-varying voltage signal.
  • the reference voltage signal Vref is a triangular wave signal, a sawtooth wave signal, or a sine wave signal.
  • the reference voltage signal Vref is a triangular wave signal.
  • the comparison signal V_out output by the comparator U1 includes a low level; when the reference voltage signal Vref is less than the duration signal Data_T, the comparison signal V_out output by the comparator U1 includes a high level.
  • the size of the duration signal Data_T can control the duty ratio of the comparison signal V_out output by the comparator U1 in each frame period.
  • FIG. 3 is an input and output waveform diagram of the comparator U1 in two frame periods of an embodiment of the present application.
  • the size of the duration signal Data_T is Data_T1
  • the reference voltage signal Vref is greater than Data_T1
  • the comparator U1 outputs a low level
  • the duration signal Data_T is The size is Data_T2.
  • the reference voltage signal Vref is greater than Data_T1
  • the comparator U1 outputs a low level. Since the sizes of Data_T1 and Data_T2 are different, the duty ratios of the output comparison signal V_out in the frame periods T11 and T12 are different.
  • FIG. 4 is a specific circuit structure diagram of the comparator U1 shown in FIG. 2.
  • Va represents the positive input terminal of the comparator U1
  • Vb represents the negative input terminal of the comparator U1
  • Vo represents the output terminal of the comparator U1.
  • the positive input terminal of the comparator U1 is connected to the duration signal line 31 for receiving the duration signal Data_T, the negative input terminal of the comparator U1 receives the reference voltage signal Vref, and the output terminal of the comparator U1 Connect the driving sub-circuit 40.
  • the comparator U1 outputs a comparison signal V_out corresponding to the duty cycle according to the duration signal Data_T, and controls the conduction duration of the driving sub-circuit 40 through the comparison signal V_out.
  • the duration control sub-circuit 10 includes a duration control transistor T9.
  • the duration control transistor T9 is connected to the comparator U1 and the driving sub-circuit 40 respectively.
  • the duration control transistor T9 is used to output the duration control signal CTL according to the comparison signal V_out to control The turn-on duration of the driving sub-circuit 40.
  • the gate of the duration control transistor T9 is connected to the output terminal of the comparator U1
  • the first pole of the duration control transistor T9 is connected to the duration control signal line 36
  • the second pole of the duration control transistor T9 is connected to the driving sub-circuit 40.
  • the duration control transistor T9 When the duration control transistor T9 is turned on under the control of the comparison signal V_out, it outputs a duration control signal CTL to control the turn-on duration of the driving sub-circuit 40. In some embodiments, when the comparison signal V_out is at a low level, the duration control transistor T9 is turned on.
  • the duration control signal CTL controls the driving sub-circuit 40 to be turned off, and the component to be driven 70 stops emitting light, thereby controlling the luminous duration of the component to be driven 70 in one frame period.
  • the driving sub-circuit 40 includes a driving transistor T4, the gate of the driving transistor T4 is connected to the second electrode of the time-length control transistor T9 of the time-length control sub-circuit 10, and the first electrode of the driving transistor T4 is connected to the data writing sub-circuit.
  • the circuit 30 is connected, and the second pole of the driving transistor T4 is connected to the component 70 to be driven.
  • the driving transistor T4 receives the data signal Data_I input by the data writing sub-circuit 30 through the first pole, generates a corresponding driving current according to the data signal Data_I, and inputs the driving current to the component to be driven 70 through the second pole.
  • the duration control signal CTL controls the driving transistor T4 to turn off through the gate of the driving transistor T4, so that the first pole and the second pole of the driving transistor T4 are disconnected, and the driving element 70 stops emitting light.
  • the data writing sub-circuit 30 includes a data writing transistor T2.
  • the first pole of the data writing transistor T2 is electrically connected to the data line 32 to receive the data signal Data_I input by the data line 32.
  • the data writing transistor T2 The second pole of the data writing transistor T2 is electrically connected to the driving sub-circuit 40, and the gate of the data writing transistor T2 is electrically connected to the data writing control signal line 33 to receive the data writing control signal Gate_A.
  • the data writing control signal Gate_A controls the data writing transistor T2 to turn on, the data writing transistor T2 writes the data signal Data_I to the driving transistor T4, and the driving transistor T4 generates a corresponding drive current according to the data signal Data_I .
  • the pixel driving circuit 100 realizes that within one frame period, the light-emitting duration of the element to be driven 70 is controllable, and the driving current is controllable. By controlling the light-emitting duration and the size of the driving current, low grayscale display of the displayed image can be realized, and the display can be improved. The accuracy of the image.
  • the reset sub-circuit 60 includes a first reset transistor T1 and a second reset transistor T7.
  • the gates of the first reset transistor T1 and the second reset transistor T7 are respectively connected to the reset control line 35, and the first poles are respectively connected to the reset signal.
  • Terminal 37 wherein the reset signal terminal 37 generates a reset voltage Vint.
  • the second electrode of the first reset transistor T1 is connected to the gate of the driving transistor T4, and the second electrode of the second reset transistor T2 is connected to the positive voltage terminal of the component 70 to be driven.
  • the first reset transistor T1 and the second reset transistor T7 are turned on by the reset control signal RST input by the reset control line 35, and then the reset voltage Vint generated by the reset signal terminal 37 is applied to the gate of the driving transistor T4 and the gate of the element to be driven 70
  • the positive voltage terminal resets the gate of the driving transistor T4 and the positive voltage terminal of the element to be driven 70 to eliminate the influence of the remaining data signal Data_I in the previous frame period on the current frame.
  • the compensation sub-circuit 50 includes a compensation transistor T3 and a data signal storage capacitor C1.
  • the gate of the compensation transistor T3 is connected to the data writing control signal line 33, the first pole is connected to the gate of the driving transistor T4, and the second pole is connected to The second pole of the driving transistor T4.
  • the data writing control signal Gate_A controls the compensation transistor T3 to be turned on, and then the data writing transistor T2 is written to the data signal Data_I of the first pole of the driving transistor T4, and the data signal Data_I is written to the gate of the driving transistor T4 through the compensation transistor T3.
  • the data signal storage capacitor C1 is connected to the gate of the driving transistor T4 and the first pole of the compensation transistor T3, and stores the data signal Data_I written to the gate of the driving transistor T4, so that when the compensation transistor T3 is turned off, the data signal Data_I is stored
  • the capacitor C1 can provide a data signal Data_I, so that the driving transistor T4 generates a driving current according to the data signal Data_I.
  • the data signal Data_I is transmitted through the first pole and the second pole of the driving transistor T4, and there will be a fixed voltage drop difference.
  • the compensation transistor T3 and the driving transistor T4 can choose the same structure transistors, so that The compensation transistor T3 compensates the data signal Data_I lost on the driving transistor T4 to ensure the accuracy of image display.
  • the pixel driving circuit 100 includes a power supply terminal VDD.
  • the work control sub-circuit 20 includes a first light-emission control transistor T5 and a second light-emission control transistor T6. The gates of the first light-emission control transistor T5 and the second light-emission control transistor T6 are connected to the work control signal line 34.
  • the first electrode is connected to the power supply terminal VDD, the second electrode is connected to the driving transistor T4; the first electrode of the second light-emitting control transistor T5 is connected to the component to be driven 70, and the second electrode is connected to the driving transistor T4.
  • the first light emission control transistor T5 controls the on and off between the power supply terminal VDD and the driving transistor T4, and the second light emission control transistor T5 controls the on and off between the driving transistor T4 and the component 70 to be driven.
  • the work control signal EM controls the first light emission control transistors T5 and T6 to turn on, and then the power supply terminal VDD, the driving transistor T4 and the element 70 to be driven are turned on. A current path is formed therebetween, and the component 70 to be driven emits light.
  • the conduction of the first light emission control transistors T5 and T6 is controlled by different control signals.
  • the driving transistor T4 since the gate of the driving transistor T4 has written the data signal Data_I generated according to the image gray scale, and the data signal Data_I is generally a voltage signal, at the power supply terminal VDD, the driving transistor T4 and When the circuit between the driving elements 70 is turned on, the voltage of the power supply terminal VDD is applied to the first electrode of the driving transistor T4, and the first electrode and the gate of the driving transistor T4 form a voltage difference, and the driving can be controlled according to the voltage difference.
  • the magnitude of the current makes the component 70 to be driven emit light according to the gray scale of the image to be displayed.
  • the component 70 to be driven in this embodiment may include a miniature light emitting diode D1.
  • the transistors of the pixel driving circuit 100 include N-type transistors, and in other embodiments, the transistors of the pixel driving circuit 100 include P-type transistors.
  • the transistors involved in this application except the constituent elements of the comparator U1 are all P-type transistors.
  • the element to be driven 70 is described as a light-emitting element, and the driving sub-circuit 70 is described as driving the element 70 to be driven to emit light, the present disclosure is not limited thereto.
  • the component 70 to be driven may be other types of components, as long as it needs to be driven and its driving duration needs to be changed in a controlled manner.
  • FIG. 5 is a timing diagram of a pixel driving circuit 100 shown in FIG. 2, including a signal timing diagram of the pixel driving circuit 100 in one frame period.
  • the pixel driving circuit 100 includes a reset phase S1, a data writing phase S2-1, and a work control phase S3 in one frame period.
  • the first reset transistor T1 and the second reset transistor T7 are turned on by the low-level reset control signal RST output by the reset control line 35, and at the same time, the first light emission control transistors T5 and T6 are output by the work control signal line 34
  • the high-level duration control signal CTL is turned off
  • the compensation transistor T3 is turned off by the high-level output of the control signal line Gate_A(1)
  • the duration write transistor T8 and the data write transistor T2 are output by the data write control signal line 33.
  • the reset voltage Vint can be a low potential voltage, such as grounding.
  • the data signal storage capacitor C1 and the anode of the micro light emitting diode D1 are discharged through the first reset transistor T1 and the second reset transistor T7, respectively, and the gate voltage of the driving transistor T4 and the anode voltage of the micro light emitting diode D1 are the reset voltages. Vint, in this way, the remaining data signal Data_I of the previous frame period on the gate of the driving transistor T4 and the anode of the micro light emitting diode D1 is cleared, thereby improving the display accuracy of the current frame period.
  • the first reset transistor T1 and the second reset transistor T7 are turned off by the high-level reset control signal RST output by the reset control line 35, and the reset voltage Vint is stored by the data signal storage capacitor C1.
  • the data writing transistor T2, the duration writing transistor T8, and the compensation transistor T3 are turned on by the low level output from the control signal line Gate_A(1), and the first light emission control transistors T5 and T6 are output by the work control signal line 34 by the work control signal
  • the high-level duration control signal CTL is turned off.
  • the data signal Data_I is written into the first electrode of the driving transistor T4 through the data writing transistor T2.
  • the driving transistor T4 is turned on and the data signal Data_I is driven.
  • the transistor T4 and the compensation transistor T3 charge the data signal storage capacitor C1
  • the voltage on the gate of the driving transistor T4 increases, and the voltage on the first pole of the driving transistor T4 remains at Vdata.
  • Vdata represents the voltage of the data signal Data_I
  • Vth represents the threshold voltage of the driving transistor T4.
  • the duration signal Data_T is stored in the duration storage capacitor C2 through the duration write transistor T8.
  • the voltage of the duration signal Data_T is different in different frame periods.
  • the reference voltage signal Vref is less than the duration signal Data_T
  • the comparison signal V_out output by the comparator U1 is at a high level
  • the duration control transistor T9 is turned off.
  • an array substrate or a display panel that includes a plurality of pixel drive circuits arranged in an array
  • the pixel drive circuits located in the same row are connected to the same control signal line Gate_A
  • the pixel drive circuits that are not in the same row are connected to different pixel drive circuits.
  • the control signal line Gate_A, and the control signal line Gate_A connecting adjacent rows are connected in a cascade manner; the entire array substrate or the display panel is written in a progressive scan manner.
  • a data writing stage S2 is included in one frame period, and S2 includes a plurality of data writing sub-stages, S2-1, S2-2, S2-3 and so on.
  • the working phase S3 may further include a light-emitting sub-phase S3-1 and a light-emitting stop sub-phase S3-2.
  • the first reset transistor T1 and the second reset transistor T7 are turned off by the high level output by the reset control line 35, and the data writing transistor T2, the duration writing transistor T8 and the compensation transistor T3 are controlled by the control signal line Gate_A (1)
  • the output high level is cut off, the reference voltage signal Vref is less than the duration signal Data_T, the comparison signal V_out output by the comparator U1 is at high level, the duration control transistor T9 is cut off, and the first light emitting control transistors T5 and T6 are controlled by the work control signal
  • the low level output from line 34 is turned on, the data signal Data_I (low level potential) stored at one end of the data signal storage capacitor C1 (ie, point N(1)) and the voltage applied to the power supply terminal VDD form a voltage difference, and the driving transistor T4 According to the voltage difference, a driving current for driving the micro light emitting diode D1 to emit light in the current frame period is generated, and is transmitted to the micro light emitting dio
  • Stop light emission sub-phase S3-2 the first reset transistor T1 and the second reset transistor T7 are turned off by the high level output of the reset control line 35, and the data writing transistor T2, the duration writing transistor T8 and the compensation transistor T3 are controlled by the control signal line.
  • the high level output of Gate_A(1) is cut off, the reference voltage signal Vref is greater than the duration signal Data_T (Va(Data_T) in Figure 6, for different pixel circuits, the value of Va can be the same or different), the output of the comparator U1
  • the comparison signal V_out is low level, the duration control transistor T9 is turned on, and the duration control transistor T9 outputs the duration control signal CTL (high level potential) to the gate of the driving transistor T4, so that the potential at point N(1) becomes high, so that The driving transistor T4 is turned off, so that the micro light emitting diode D1 stops emitting light.
  • each pixel driving circuit can be written with effective work control signals at the same time to realize the display of grayscale images. This is because each pixel driving circuit is written with a different Data_T signal in the data writing sub-phase. Therefore, each pixel driving circuit can control the micro light emitting diode D1 to emit light for a different length of time in the work control phase.
  • the data writing phase and the work control phase can also be performed row by row, that is, the pixel driving circuit of the first row first completes the data writing phase and the working control phase, and then the pixel driving circuit of the second row enters the data The writing phase and the work control phase until the pixel drive circuit of the nth row enters the work control phase.
  • the effective duration of the working control signal EM corresponding to each row of pixel driving circuits in the working phase is the same.
  • the data writing phase and the work control phase can also be performed row by row, that is, the pixel driving circuit of the first row completes the data writing phase first, and then the pixel driving circuit of the second row enters the data writing phase , Until the pixel drive circuit of the nth row completes the data writing stage; then the pixel drive circuit of the first row first completes the work control stage, and then the pixel drive circuit of the second row enters the work control stage, until the pixel drive circuit of the nth row completes the work control stage .
  • the pixel driving circuit 100 of the present application separately controls the driving current and the light-emitting time of the driving element 70 to realize the display of low-gray-scale images and improve the accuracy of the displayed images.
  • FIG. 6 is a pixel matrix diagram of an embodiment of the display device 800 provided by this application.
  • the display device 800 provided in the present application includes the to-be-driven element 70 and the aforementioned pixel driving circuit 100.
  • the display device 800 includes a plurality of sub-pixels 801, and each sub-pixel 801 is correspondingly provided with a pixel driving circuit 100 for driving the to-be-driven element 70 of the sub-pixel 801 to emit light.
  • the component to be driven 70 includes a micro LED or a mini LED or an organic electroluminescent diode OLED.
  • the display device 800 includes multiple duration signal lines 31, multiple data signal lines 32 and multiple duration control signal lines 36.
  • the duration signal line 31 is used to transmit the duration signal Data_T; the data signal line 32 is used to transmit the data signal Data_I; the duration control signal line 36 is used to transmit the duration control signal CTL.
  • each pixel driving circuit 100 corresponding to the same row of sub-pixels 801 is electrically connected to the same time length control signal line 36; each pixel driving circuit 100 corresponding to the same column of sub-pixels 801 is connected to the same time length signal line 31 and the same data signal line 32 Electric connection.
  • the display device 800 further includes a plurality of data writing control signal lines 33, a plurality of work control signal lines 34, and a plurality of reset control lines 35.
  • the write control signal line 33 is used to transmit the write control signal Gate_A
  • the work control signal line 34 is used to transmit the work control signal EM
  • the reset control line 35 is used to transmit the reset control signal RST.
  • each pixel driving circuit 100 corresponding to the same row of sub-pixels 801 is electrically connected to the same data writing control signal line 33, the same reset control line 35, and the same work control signal line 34.
  • a control signal is sent to each pixel driving circuit 100 in time sequence through the control line of each row, and each pixel driving circuit 100 is controlled; a data signal is sent to each pixel driving circuit according to the time sequence through the data line of each column
  • the circuit 100 controls the displayed image.
  • the display device 800 may further include other components, such as a signal decoding circuit, a voltage conversion circuit, etc. These components may use existing conventional components, which will not be described in detail here.
  • the display device 800 of the present application can be applied to any products or components with display functions, such as electronic paper, mobile phones, tablet computers, televisions, monitors, notebook computers, digital photo frames, and navigators.
  • display device 800 reference may be made to the technical effects of the pixel driving circuit 100 provided in the embodiments of the present application, which will not be repeated here.
  • the present application also provides at least one pixel drive circuit driving method for driving the pixel drive circuit 100 provided in the present application.
  • the pixel driving method includes steps S1-S2.
  • step S1 a data signal is written to the driving sub-circuit.
  • step S2 a work control signal is written to control the driving sub-circuit to be turned on to drive the element to be driven to emit light according to the data signal; at the same time, to control the conduction time of the driving sub-circuit to control The light-emitting duration of the component to be driven.
  • the step S2 of controlling the on-duration of the driving sub-circuit includes sub-steps S21 and S22.
  • the duration signal is compared with the reference voltage signal to generate a comparison signal to control the on-duration of the driving sub-circuit.
  • the pixel driving circuit driving method provided in the present application can independently control the driving current and light-emitting duration of the pixel driving circuit 100 to drive the element 70 to be driven, and further realize the display of low-gray-scale images by controlling the light-emitting duration, and improve the display accuracy.
  • the relevant part can refer to the part of the description of the device embodiment.
  • the method embodiment and the device embodiment are complementary to each other.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Control Of El Displays (AREA)

Abstract

一种像素驱动电路（100）、显示设备（800）和像素驱动电路驱动方法。像素驱动电路（100）包括驱动子电路（40）、时长控制子电路（10）和数据写入子电路（30），其中，驱动子电路（40）分别电连接时长控制子电路（10）和数据写入子电路（30），数据写入子电路（30）用于向驱动子电路（40）传输数据信号，时长控制子电路（10）用于控制驱动子电路（40）的导通时长，驱动子电路（40）用于在导通时长内根据数据信号控制待驱动元件（70）的电流。显示设备（800）包括像素驱动电路（100）。像素驱动电路驱动方法应用于像素驱动电路（100）。

Description

像素驱动电路、显示设备和像素驱动电路驱动方法
相关申请的交叉引用
本申请要求于2019年11月5日提交至中国知识产权局的中国专利申请No.201911071491.8的优先权，所述公开的内容通过引用其全部合并于此。
技术领域
本申请涉及显示领域，尤其涉及一种像素驱动电路、显示设备和像素驱动电路驱动方法。
背景技术
微型无机发光二极管因为其高亮度和高信赖性，在显示领域具有广阔的发展前景。
发明内容
本申请提供一种改进的像素驱动电路、显示设备以及像素驱动电路驱动方法。
本申请提供一种像素驱动电路，用于向待驱动元件提供信号，包括驱动子电路、时长控制子电路和数据写入子电路，其中，所述驱动子电路分别电连接所述时长控制子电路和所述数据写入子电路，所述数据写入子电路用于向所述驱动子电路传输数据信号，所述时长控制子电路用于控制所述驱动子电路的导通时长，所述驱动子电路用于在导通时长内根据所述数据信号控制所述待驱动元件的电流。
在一些实施例中，所述时长控制子电路包括比较器，所述比较器分别连接 基准电压信号线、所述驱动子电路以及时长信号线，所述比较器用于比较所述时长信号线输入的时长信号和所述基准电压信号线提供的基准电压信号，输出比较信号以控制所述驱动子电路的导通时长。
在一些实施例中，所述比较器的正输入端连接所述时长信号线，所述比较器的负输入端连接所述基准电压信号线，所述比较器的输出端连接所述驱动子电路。
在一些实施例中，所述基准电压信号为三角波信号、锯齿波信号或正弦波信号。
在一些实施例中，所述时长控制子电路还包括时长控制晶体管，所述时长控制晶体管的栅极连接至所述比较器的输出端，第一极连接至用于提供时长控制信号的时长控制信号线，第二极连接至所述驱动子电路，所述时长控制晶体管用于根据所述比较信号，输出所述时长控制信号，控制所述驱动子电路的导通时长。
在一些实施例中，所述时长控制子电路还包括时长写入子电路，所述时长写入子电路的输入端连接于所述时长信号线，输出端连接至所述比较器的第一输入端，并且所述时长写入子电路的控制端和数据写入控制信号线连接，所述时长写入子电路用于接收所述数据写入控制信号线输出的数据写入控制信号，根据所述数据写入控制信号连通所述时长信号线和所述比较器。
在一些实施例中，所述时长控制子电路还包括时长存储电容，所述时长存储电容的第一端连接至所述比较器的第一输入端和所述时长写入子电路的输出端。
在一些实施例中，所述驱动子电路包括驱动晶体管，所述驱动晶体管的栅极和所述时长控制子电路的时长控制晶体管的第二极连接，所述驱动晶体管的第一极和所述数据写入子电路连接，所述驱动晶体管的第二极和所述待驱动元件连接。
在一些实施例中，所述数据写入子电路包括数据写入晶体管，所述数据写入晶体管的第一极与数据线电连接，以接收所述数据线输入的数据信号，所述 数据写入晶体管的第二极与所述驱动子电路电连接，所述数据写入晶体管的栅极与所述数据写入控制信号线电连接，以接收所述数据写入控制信号。
在一些实施例中，所述像素驱动电路还包括以下中的至少一者：复位子电路，分别连接所述驱动子电路和所述待驱动元件，用于对所述驱动子电路和所述待驱动元件进行复位；补偿子电路，通过所述驱动子电路连接至所述数据写入子电路，用于存储所述数据写入子电路输入的数据信号；工作控制子电路，和所述驱动子电路连接，用于控制所述驱动子电路驱动所述待驱动元件发光。
本申请提供一种显示设备，包括待驱动元件和如前所述的像素驱动电路，所述像素驱动电路与所述待驱动元件连接。
在一些实施例中，所述显示设备包括多个亚像素，每个所述亚像素对应设置一个所述像素驱动电路，用于驱动所述亚像素的待驱动元件发光。
在一些实施例中，所述显示设备还包括：多条时长信号线，用于传输时长信号；多条数据信号线，用于传输所述数据信号；多条时长控制信号线，用于传输所述时长控制信号；其中，同一行所述亚像素对应的各所述像素驱动电路电连接同一条所述时长控制信号线；同一列所述亚像素对应的各所述像素驱动电路与同一条所述时长信号线和同一条所述数据信号线电连接。
本申请提供一种应用于如前所述的像素驱动电路的像素驱动电路驱动方法，包括：向所述驱动子电路写入数据信号；写入工作控制信号，以控制所述驱动子电路导通，来根据所述数据信号驱动所述待驱动元件发光；控制所述驱动子电路的导通时长，来控制所述待驱动元件的发光时长。
在一些实施例中，所述控制所述驱动子电路的导通时长，包括：写入时长信号；比较时长信号和基准电压信号，产生比较信号，以控制所述驱动子电路的导通时长。
附图说明
图1是本申请提供的实施例的像素驱动电路的模块框图；
图2为图1所示的像素驱动电路的具体电路结构图；
图3是本申请实施例的比较器在两个帧周期的输入输出波形图；
图4是图2所示的比较器的一种具体电路结构图；
图5为图2所示的像素驱动电路的一个时序图；
图6为本申请提供的显示设备的实施例的像素矩阵图；
图7为本申请提供的实施例的像素驱动电路的模块框图。
具体实施方式
这里将详细地对示例性实施例进行说明，其示例表示在附图中。下面的描述涉及附图时，除非另有表示，不同附图中的相同数字表示相同或相似的要素。以下示例性实施例中所描述的实施方式并不代表与本申请相一致的所有实施方式。相反，它们仅是与如所附权利要求书中所详述的、本申请的一些方面相一致的装置的例子。
在本申请使用的术语是仅仅出于描述特定实施例的目的，而非旨在限制本申请。除非另作定义，本申请使用的技术术语或者科学术语应当为本申请所属领域内具有一般技能的人士所理解的通常意义。本申请说明书以及权利要求书中使用的“一个”或者“一”等类似词语也不表示数量限制，而是表示存在至少一个。“多个”表示至少两个。“包括”或者“包含”等类似词语意指出现在“包括”或者“包含”前面的元件或者物件涵盖出现在“包括”或者“包含”后面列举的元件或者物件及其等同，并不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而且可以包括电性的连接，不管是直接的还是间接的。在本申请说明书和所附权利要求书中所使用的单数形式的“一种”、“所述”和“该”也旨在包括多数形式，除非上下文清楚地表示其他含义。还应当理解，本文中使用的术语“和/或”是指并包含一个或多个相关联的列出项目的任何或所有可能组合。
通过驱动显示设备中每个像素的待驱动元件发光来显示图像，其中待驱动元件为电流驱动型器件，如微型发光二极管(micro LED)或者迷你发光二极管(mini LED)或者有机电致发光二极管OLED。在这种情况下，文中 所述的待驱动元件的工作时长可以被理解为发光二极管的发光时长。
对于无机发光二极管，如微型发光二极管(micro LED)和迷你发光二极管(mini LED)，其发光效率、发射光线的亮度以及色坐标在低电流密度下会随着电流密度变化而变化，进而导致显示品质问题。由于大电流密度的电流能驱动待驱动元件发出稳定的光线，为了保证发光效率，可以考虑使用大电流密度的电流驱动待驱动元件发光来显示图像。
图1和图7是本申请提供的实施例的像素驱动电路100的模块框图。像素驱动电路100设置于显示设备800内，显示设备800包括待驱动元件70。像素驱动电路100与待驱动元件70连接，用于驱动待驱动元件70发光。像素驱动电路100包括驱动子电路40、时长控制子电路10和数据写入子电路30，其中，驱动子电路40分别电连接时长控制子电路10和数据写入子电路30。数据写入子电路30用于传输数据信号Data_I。时长控制子电路10用于控制驱动子电路40的导通时长。驱动子电路40用于在导通时长内根据数据信号Data_I控制待驱动元件70的电流。
像素驱动电路100可以控制待驱动元件70的电流大小和发光时长，可以控制电流较大，使发出的光线稳定性高，可以单独控制电流实现高灰阶的图像显示，也可以通过控制电流和发光时长，实现大电流下的低灰阶图像的准确显示。可以根据电流的大小和待显示的图像的灰阶，控制发光时长，图像灰阶越低，发光时长越短，通过调节电流和发光时长，使得发出的光线稳定且图像的灰阶准确，提高显示图像的准确性。
可以理解的是，待驱动元件70包括发光二极管。尤其是在待驱动元件70是微型无机发光二极管的情况下，数据写入子电路30传输的数据信号Data_I可以为使微型无机发光二极管能够具有较高的发光效率的固定高电平信号，在此情况下，像素驱动电路主要通过时长控制子电路10来控制灰阶。或者，数据信号Data_I的电位可以在一定的电压区间范围内取值，在该电压区间范围内的数据信号能够保证微型无机发光二极管具有较高的发光效率，在此情况下，像素驱动电路通过数据信号Data_I和时间控制电路10的共同控制微型无机发光二 极管的发光亮度。
一些实施例中，像素驱动电路100在一个帧周期内，接收按照时序输入的时长信号Data_T和数据信号Data_I，并根据时长信号Data_T控制待驱动元件70在一帧周期内的发光时长，根据数据信号Data_I控制当前一帧周期内流过待驱动元件70的电流密度大小。如此，实现对待驱动元件70的驱动电流大小和发光时长的独立控制。
一些实施例中，像素驱动电路100的时长控制子电路10用于接收时长信号Data_T，数据写入子电路30用于接收数据信号Data_I。像素驱动电路100的驱动子电路40包括控制端401，第一端402和第二端403，驱动子电路40通过第一端402和数据写入子电路30连接，通过控制端401和时长控制子电路10连接，通过第二端403和待驱动元件70连接。数据写入子电路30通过第一端402将数据信号Data_I写入到驱动子电路40；驱动子电路40根据数据信号Data_I产生驱动电流，并从第二端403将电流输出给待驱动元件70；时长控制子电路10通过控制端401控制驱动子电路40的导通时长。
一些实施例中，时长控制子电路10在待驱动元件70发光达到设定时长时，控制驱动子电路40截止，使得待驱动元件70停止发光，从而控制待驱动元件70的发光时长。
一些实施例中，像素驱动电路100接收数据写入控制信号Gate_A。数据写入控制信号Gate_A可以控制时长控制子电路10和时长信号线31(见图2)连通，数据写入子电路30和数据信号线32(见图2)连通，时长控制子电路10接收时长信号Data_T，数据写入子电路30接收数据信号Data_I。
需要说明的是，尽管图7中示出了驱动子电路40的第二端403直接与待驱动元件70连接的示例，但是本申请不限于此。一些实施例中，驱动子电路40可以在其间存在中间元件(例如，图1所示的工作控制子电路20)的情况下与待驱动元件70连接。
一些实施例中，参照图1，像素驱动电路100还包括复位子电路60、补偿子电路50和工作控制子电路20以及电源端VDD。一些实施例中，复位子电路 60分别连接驱动子电路40和待驱动元件70，用于对驱动子电路40和待驱动元件70进行复位。一些实施例中，复位子电路60分别连接驱动子电路40的控制端401和待驱动元件70的正电压端。在每帧周期进行图像显示之前，复位子电路60在复位控制信号RST的控制下，将复位电压Vinit输入到驱动子电路40的控制端401和待驱动元件70上，对驱动子电路40的控制端401和待驱动元件70上的电压进行复位，以消除上一帧周期残留的数据信号Data_I或时长信号Data_T对当前帧周期的影响。
一些实施例中，补偿子电路50通过驱动子电路40和数据写入子电路30连接，用于存储数据写入子电路30输入的数据信号。一些实施例中，补偿子电路50还用于存储驱动子电路40的阈值电压。一些实施例中，补偿子电路50连接于驱动子电路40的控制端401和第二端403之间，补偿子电路50在数据写入控制信号Gate_A的控制下，存储驱动子电路40的阈值电压信号和数据写入驱动电路20输入的数据信号Data_I。一些实施例中，在一个帧周期的发光阶段，所述阈值电压信号对所述驱动子电路40进行补偿，使得所述驱动子电路40输出的驱动电流只和数据信号Data_I相关，不受所述驱动子电路40本身的阈值电压影响，从而提高了输出的驱动电流的准确性。
一些实施例中，工作控制子电路20和驱动子电路40连接，用于控制驱动子电路40驱动待驱动元件70发光。一些实施例中，工作控制子电路20在工作控制信号EM的控制下，控制电源端VDD和驱动子电路40之间的通断，以及驱动子电路40和待驱动元件70之间的通断，进而控制驱动子电路40驱动待驱动元件70发光的时间点。
一些实施例中，像素驱动电路100在一个帧周期内按照时序接收以上描述中涉及到的时长信号Data_T、数据信号Data_I、复位电压Vinit、数据写入控制信号Gate_A以及工作控制信号EM。一些实施例中，显示设备800包括至少一个信号输出电路(未示出)，用以在一个帧周期内按照时序输出时长信号Data_T、数据信号Data_I、复位电压Vinit、数据写入控制信号Gate_A以及工作控制信号EM。像素驱动电路100和所述信号输出电路连接，以按照时序接收对应的信号。
图2为图1所示的像素驱动电路100的具体电路结构图。需要说明的是，图2所示的时长控制子电路10、驱动子电路40和数据写入子电路30的具体电路结构也可应用于图7所示的像素驱动电路100。
参照图2，待驱动元件70可以包括微型发光二极管D1；时长控制子电路10包括比较器U1，比较器U1连接驱动子电路40以及时长信号线31，比较器U1用于比较时长信号线31输入的时长信号Data_T和基准电压信号Vref，输出比较信号V_out以控制驱动子电路40的导通时长。比较器U1比较时长信号Data_T和基准电压信号Vref以产生比较信号V_out，电路结构简单。
一些实施例中，时长控制子电路10包括时长写入子电路102，时长写入子电路102连接于时长信号线31和比较器U1之间，并且时长写入子电路102和数据写入控制信号线33连接，时长写入子电路102用于接收数据写入控制信号线33输出的数据写入控制信号Gate_A，根据数据写入控制信号Gate_A连通时长信号线31和比较器U1。通过时长写入子电路102控制时长信号线31和比较器U1之间通断，并且在比较器U1接收到时长信号线31输入的时长信号Data_T后，中断时长信号线31和比较器U1之间的连接，可防止在本帧周期未结束时，时长信号线31输入下一帧的时长信号Data_T，影响本帧周期内的图像显示。
一些实施例中，时长写入子电路102包括时长写入晶体管T8，时长写入晶体管T8的栅极连接数据写入控制信号线33，第一极连接时长信号线31，第二极连接比较器U1，数据写入控制信号Gate_A通过导通时长写入晶体管T8，进而连通时长信号线31和比较器U1。
在一些实施例中，时长控制子电路10包括时长存储电容C2，时长存储电容C2连接于比较器U1和时长写入子电路102之间，时长存储电容C2用于存储时长信号Data_T，使得在时长写入子电路102断开时，时长存储电容C2可以提供时长信号Data_T，用于比较器U1将时长信号Data_T和基准电压信号Vref进行比较并产生比较信号V_out。在一些实施例中，基准电压信号Vref为随时间变化的电压信号。在一些实施例中，基准电压信号Vref为三角波信号、锯齿波信号或正弦波信号。在本实施例中，基准电压信号Vref为三角波信号。基准电压 信号Vref大于时长信号Data_T时，比较器U1输出的比较信号V_out包括低电平；基准电压信号Vref小于时长信号Data_T时，比较器U1输出的比较信号V_out包括高电平。通过时长信号Data_T的大小可控制每个帧周期内比较器U1输出的比较信号V_out的占空比。
图3是本申请一个实施例的比较器U1在两个帧周期的输入输出波形图。根据图3，在帧周期T11内，时长信号Data_T的大小为Data_T1，在时间段t2-t3，基准电压信号Vref大于Data_T1，比较器U1输出低电平；在帧周期T12内，时长信号Data_T的大小为Data_T2，在时间段t4-t5，基准电压信号Vref大于Data_T1，比较器U1输出低电平。由于Data_T1和Data_T2的大小不同，因此输出的比较信号V_out在帧周期T11和T12内的占空比不同。
图4是图2所示的比较器U1的一种具体电路结构图。图4中，Va表示比较器U1的正输入端，Vb表示比较器U1的负输入端，Vo表示比较器U1的输出端。当Va处输入的电压高于Vb处输入的电压时，Vo输出高电平，当Va处输入的电压低于Vb处输入的电压时，Vo输出低电平。
继续参见图2，在一些实施例中，比较器U1的正输入端连接时长信号线31，用于接收时长信号Data_T，比较器U1的负输入端接收基准电压信号Vref，比较器U1的输出端连接驱动子电路40。比较器U1在每个帧周期内，根据时长信号Data_T输出对应占空比的比较信号V_out，通过比较信号V_out控制驱动子电路40的导通时长。
在一些实施例中，时长控制子电路10包括时长控制晶体管T9，时长控制晶体管T9分别连接比较器U1和驱动子电路40，时长控制晶体管T9用于根据比较信号V_out，输出时长控制信号CTL，控制驱动子电路40的导通时长。一些实施例中，时长控制晶体管T9的栅极连接比较器U1的输出端，时长控制晶体管T9的第一极连接时长控制信号线36，时长控制晶体管T9的第二极连接驱动子电路40。时长控制晶体管T9在比较信号V_out的控制下导通时，输出时长控制信号CTL，以控制驱动子电路40的导通时长。一些实施例中，当比较信号V_out为低电平时，时长控制晶体管T9导通。
在一些实施例中，时长控制信号CTL控制驱动子电路40断开，待驱动元件70停止发光，进而控制待驱动元件70在一个帧周期内的发光时长。在一些实施例中，驱动子电路40包括驱动晶体管T4，驱动晶体管T4的栅极和时长控制子电路10的时长控制晶体管T9的第二极连接，驱动晶体管T4的第一极和数据写入子电路30连接，驱动晶体管T4的第二极和待驱动元件70连接。驱动晶体管T4通过第一极接收数据写入子电路30输入的数据信号Data_I，并根据数据信号Data_I产生对应的驱动电流，通过第二极将驱动电流输入到待驱动元件70。一些实施例中，时长控制信号CTL通过驱动晶体管T4的栅极控制驱动晶体管T4断开，从而使得驱动晶体管T4的第一极和第二极断开，待驱动元件70停止发光。
一些实施例中，数据写入子电路30包括数据写入晶体管T2，数据写入晶体管T2的第一极与数据线32电连接，以接收数据线32输入的数据信号Data_I，数据写入晶体管T2的第二极与驱动子电路40电连接，数据写入晶体管T2的栅极与数据写入控制信号线33电连接，以接收数据写入控制信号Gate_A。一些实施例中，数据写入控制信号Gate_A控制数据写入晶体管T2导通，数据写入晶体管T2将数据信号Data_I写入到驱动晶体管T4，由驱动晶体管T4根据数据信号Data_I产生对应大小的驱动电流。在不同帧周期中，数据信号Data_I的大小不同，进而待驱动元件70接收到的驱动电流大小不同。由此，像素驱动电路100实现一个帧周期内，待驱动元件70的发光时长可控，且驱动电流可控，通过控制发光时长和驱动电流大小，可实现显示图像的低灰阶显示，提高显示图像的准确性。
本实施例中，复位子电路60包括第一复位晶体管T1和第二复位晶体管T7，第一复位晶体管T1和第二复位晶体管T7的栅极分别连接复位控制线35，第一极分别连接复位信号端37，其中，复位信号端37产生复位电压Vint。第一复位晶体管T1的第二极连接驱动晶体管T4的栅极，第二复位晶体管T2的第二极连接待驱动元件70的正电压端。第一复位晶体管T1和第二复位晶体管T7由复位控制线35输入的复位控制信号RST导通，进而将复位信号端37产生的复位电 压Vint施加到驱动晶体管T4的栅极和待驱动元件70的正电压端，对驱动晶体管T4的栅极和待驱动元件70的正电压端进行复位，以消除上一帧周期中残留的数据信号Data_I对当前帧的影响。
本实施例中，补偿子电路50包括补偿晶体管T3和数据信号存储电容C1，补偿晶体管T3的栅极连接数据写入控制信号线33，第一极连接驱动晶体管T4的栅极，第二极连接驱动晶体管T4的第二极。数据写入控制信号Gate_A控制补偿晶体管T3导通，进而将数据写入晶体管T2写入到驱动晶体管T4第一极的数据信号Data_I，通过补偿晶体管T3写入驱动晶体管T4的栅极。数据信号存储电容C1连接驱动晶体管T4的栅极和补偿晶体管T3的第一极，对写入到驱动晶体管T4的栅极的数据信号Data_I进行存储，使得补偿晶体管T3断开时，数据信号Data_I存储电容C1可提供数据信号Data_I，使的驱动晶体管T4根据数据信号Data_I产生驱动电流。同时，数据信号Data_I经过驱动晶体管T4的第一极和第二极的传输，会存在一个固定的压降差，在具体电路设计时，补偿晶体管T3和驱动晶体管T4可选择相同结构的晶体管，使得补偿晶体管T3对驱动晶体管T4上损失的数据信号Data_I进行补偿，保证图像显示的准确性。
本实施例中，像素驱动电路100包括电源端VDD。工作控制子电路20包括第一发光控制晶体管T5和第二发光控制晶体管T6，第一发光控制晶体管T5和第二发光控制晶体管T6的栅极连接工作控制信号线34，第一发光控制晶体管T5的第一极连接电源端VDD，第二极连接驱动晶体管T4；第二发光控制晶体管T5的第一极连接待驱动元件70，第二极连接驱动晶体管T4。第一发光控制晶体管T5控制电源端VDD和驱动晶体管T4之间的通断，第二发光控制晶体管T5控制驱动晶体管T4和待驱动元件70之间的通断。在一个帧周期内，进入图像显示阶段，即待驱动元件70发光阶段时，工作控制信号EM控制第一发光控制晶体管T5和T6导通，进而电源端VDD、驱动晶体管T4和待驱动元件70之间形成电流通路，待驱动元件70发光。其他一些实施例中，第一发光控制晶体管T5和T6的导通由不同的控制信号控制。在本申请一个帧周期的发光阶段，由于在驱动晶体管T4的栅极已经写入根据图像灰阶生成的数据信号Data_I，而 数据信号Data_I一般为一个电压信号，在电源端VDD、驱动晶体管T4和待驱动元件70之间的电路导通时，电源端VDD的电压施加到驱动晶体管T4的第一极，驱动晶体管T4的第一极和栅极形成一个电压差，根据该电压差即可控制驱动电流的大小，使得待驱动元件70按照待显示图像的灰阶发光。本实施例中的待驱动元件70可以包括微型发光二极管D1。
本申请的一些实施例中，像素驱动电路100的晶体管包括N型晶体管，另外一些实施例中，像素驱动电路100中的晶体管包括P型晶体管。为方便描述，本申请中涉及到的除比较器U1的构成元件之外的晶体管均为P型晶体管。
需要说明的是，尽管在上文的示例中，将待驱动元件70描述为发光元件，并将驱动子电路70描述为驱动待驱动元件70发光，但是本公开不限于此。待驱动元件70可以是其他类型的元件，只要其需要驱动并且对其的驱动时长需要受控变化即可。
图5为图2所示的一个像素驱动电路100的时序图，包括像素驱动电路100在一个帧周期内的信号时序图。根据图5，像素驱动电路100在一个帧周期内，包括复位阶段S1、数据写入阶段S2-1、工作控制阶段S3。
复位阶段S1，第一复位晶体管T1和第二复位晶体管T7由复位控制线35输出的低电平的复位控制信号RST导通，同时，第一发光控制晶体管T5和T6由工作控制信号线34输出的高电平的时长控制信号CTL截止，补偿晶体管T3由控制信号线Gate_A(1)输出的高电平截止，时长写入晶体管T8和数据写入晶体管T2由数据写入控制信号线33输出的高电平截止，比较器U1输出的比较信号V_out为高电平，时长控制晶体管T9截止，复位信号端37输出的复位电压Vint施加到驱动晶体管T4的栅极和微型发光二极管D1的阳极，其中，复位电压Vint可以为低电位的电压，例如接地。在复位阶段S1，数据信号存储电容C1和微型发光二极管D1的阳极分别通过第一复位晶体管T1和第二复位晶体管T7放电，驱动晶体管T4的栅极电压和微型发光二极管D1的阳极电压为复位电压Vint，如此，驱动晶体管T4的栅极和微型发光二极管D1的阳极残留的上一帧周期的数据信号Data_I被清除，进而提高了当前帧周期的显示准确度。
可以理解的是，对于包括阵列排布的多个像素驱动电路的阵列基板或者显示面板而言，所有像素驱动电路可以同时执行复位阶段S1。
数据写入阶段S2-1，第一复位晶体管T1和第二复位晶体管T7由复位控制线35输出的高电平的复位控制信号RST截止，复位电压Vint由数据信号存储电容C1进行存储。数据写入晶体管T2、时长写入晶体管T8和补偿晶体管T3由控制信号线Gate_A(1)输出的低电平导通，第一发光控制晶体管T5和T6由工作控制信号由工作控制信号线34输出的高电平的时长控制信号CTL截止。数据信号Data_I通过数据写入晶体管T2写入驱动晶体管T4的第一极，通过驱动晶体管T4的自身特性，例如栅极电位低于第一极电位时，驱动晶体管T4导通，数据信号Data_I经过驱动晶体管T4和补偿晶体管T3对数据信号存储电容C1进行充电，驱动晶体管T4栅极上的电压增大，驱动晶体管T4的第一极上的电压保持为Vdata，当驱动晶体管T4栅极上的电压为Vdata+Vth时，驱动晶体管T4截止。其中，Vdata表示数据信号Data_I的电压，Vth表示驱动晶体管T4的阈值电压。同时，时长信号Data_T通过时长写入晶体管T8存储到时长存储电容C2。在一些实施例中，时长信号Data_T在不同帧周期的电压大小不同。该阶段，基准电压信号Vref小于时长信号Data_T，比较器U1输出的比较信号V_out为高电平，时长控制晶体管T9截止。
可以理解的是：对于包括阵列排布的多个像素驱动电路的阵列基板或者显示面板而言，位于同一行的像素驱动电路连接同一根控制信号线Gate_A，而不同行的像素驱动电路连接不同的控制信号线Gate_A，且连接相邻行的控制信号线Gate_A以级联的方式连接；整个阵列基板或显示面板以逐行扫描的方式写入。对于整个阵列基板或显示面板而言，在一个帧周期内包括一个数据写入阶段S2，而S2包括多个数据写入子阶段，S2-1,S2-2，S2-3等。
工作控制阶段S3，写入有效的工作控制信号EM，使第一发光控制晶体管T5和第二发光控制晶体管T6开启导通。工作阶段S3可以进一步包括发光子阶段S3-1和停止发光子阶段S3-2。
发光子阶段S3-1，第一复位晶体管T1和第二复位晶体管T7由复位控制线 35输出的高电平截止，数据写入晶体管T2、时长写入晶体管T8和补偿晶体管T3由控制信号线Gate_A(1)输出的高电平截止，基准电压信号Vref小于时长信号Data_T，比较器U1输出的比较信号V_out为高电平，时长控制晶体管T9截止，第一发光控制晶体管T5和T6由工作控制信号线34输出的低电平导通，数据信号存储电容C1的一端(即N(1)点)存储的数据信号Data_I(低电平电位)和电源端VDD施加的电压形成电压差，驱动晶体管T4根据该电压差产生当前帧周期内驱动微型发光二极管D1发光的驱动电流，并通过第二发光控制晶体管T5传输到微型发光二极管D1，微型发光二极管D1发光。
停止发光子阶段S3-2，第一复位晶体管T1和第二复位晶体管T7由复位控制线35输出的高电平截止，数据写入晶体管T2、时长写入晶体管T8和补偿晶体管T3由控制信号线Gate_A(1)输出的高电平截止，基准电压信号Vref大于时长信号Data_T(如图6中的Va(Data_T)，对于不同的像素电路，Va的数值可以相同可以不同)，比较器U1输出的比较信号V_out为低电平，时长控制晶体管T9导通，时长控制晶体管T9输出时长控制信号CTL(高电平电位)到驱动晶体管T4的栅极，使得N(1)点的电位变高，让驱动晶体管T4截止，从而微型发光二极管D1停止发光。
可以理解的是：对于包括阵列排布的多个像素驱动电路的阵列基板或者显示面板而言，所有像素驱动电路可以被同时写入有效的工作控制信号，来实现灰阶画面的显示。这是由于每个像素驱动电路在数据写入子阶段都被写入了不同的Data_T信号，因此，每个像素驱动电路能够控制微型发光二极管D1在工作控制阶段发光的时间长短不同。
在一些实施例中，也可以按照逐行依次进行数据写入阶段和工作控制阶段，也即第一行像素驱动电路首先完成数据写入阶段和工作控制阶段，之后第二行像素驱动电路进入数据写入阶段和工作控制阶段，直至第n行像素驱动电路进入工作控制阶段。其中，每一行像素驱动电路在工作阶段对应的工作控制信号EM的有效时长相同。在另一些实施例中，亦可以逐行依次分别进行数据写入阶段和工作控制阶段，也即第一行像素驱动电路首先完成数据写入阶段，之后第 二行像素驱动电路进入数据写入阶段，直至第n行像素驱动电路完成数据写入阶段；之后第一行像素驱动电路首先完成工作控制阶段，之后第二行像素驱动电路进入工作控制阶段，直至第n行像素驱动电路完成工作控制阶段。
本申请的像素驱动电路100通过对待驱动元件70的驱动电流和发光时间分别进行控制，实现低灰阶图像的显示，提高了显示图像的准确性。
图6为本申请提供的显示设备800的一个实施例的像素矩阵图。本申请提供的显示设备800包括待驱动元件70和前面所述的像素驱动电路100。在一些实施例中，显示设备800包括多个亚像素801，每个亚像素801对应设置一个像素驱动电路100，用于驱动亚像素801的待驱动元件70发光。待驱动元件70包括微型发光二极管(micro LED)或者迷你发光二极管(mini LED)或者有机电致发光二极管OLED。在一些实施例中，显示设备800包括多条时长信号线31、多条数据信号线32和多条时长控制信号线36。时长信号线31用于传输时长信号Data_T；数据信号线32用于传输所述数据信号Data_I；时长控制信号线36用于传输时长控制信号CTL。其中，同一行亚像素801对应的各像素驱动电路100电连接同一条时长控制信号线36；同一列亚像素801对应的各像素驱动电路100与同一条时长信号线31和同一条数据信号线32电连接。
一些实施例中，显示设备800还包括多条数据写入控制信号线33、多条工作控制信号线34和多条复位控制线35。写入控制信号线33用于传输写入控制信号Gate_A，工作控制信号线34用于传输工作控制信号EM，复位控制线35用于传输复位控制信号RST。其中，同一行亚像素801对应的各像素驱动电路100电连接同一条数据写入控制信号线33和同一条复位控制线35以及同一条工作控制信号线34。显示设备800显示图像过程中，通过每一行的控制线按照时序发送控制信号给各像素驱动电路100，对各像素驱动电路100进行控制；通过每一列的数据线按照时序发送数据信号给各像素驱动电路100，对显示图像进行控制。
一些实施例中，显示设备800还可以包括其他部件，例如信号解码电路、 电压转换电路等，这些部件可以采用已有的常规部件，这里不再详述。在一些实施例中，本申请的显示设备800可以应用于电子纸、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件中。关于显示设备800的技术效果可以参考本申请的实施例中提供的像素驱动电路100的技术效果，这里不再赘述。
本申请至少还提供一种像素驱动电路驱动方法，用于驱动本申请提供的像素驱动电路100。
像素驱动方法包括步骤S1-S2。
在步骤S1中，向所述驱动子电路写入数据信号。
在步骤S2中，写入工作控制信号，以控制所述驱动子电路导通，来根据所述数据信号驱动所述待驱动元件发光；同时，控制所述驱动子电路的导通时长，来控制所述待驱动元件的发光时长。
在一些实施例中，控制所述驱动子电路的导通时长的步骤S2包括子步骤S21和S22。
子步骤S21中，写入时长信号。
子步骤S22中，比较时长信号和基准电压信号，产生比较信号，以控制所述驱动子电路的导通时长。
本申请提供的像素驱动电路驱动方法可以独立控制像素驱动电路100驱动待驱动元件70的驱动电流和发光时长，进而通过控制发光时长实现低灰阶图像的显示，提高显示准确度。
对于方法实施例而言，由于其基本对应于装置实施例，所以相关之处参见装置实施例的部分说明即可。方法实施例和装置实施例互为补充。
以上所述仅为本申请的较佳实施例而已，并不用以限制本申请，凡在本申请的精神和原则之内，所做的任何修改、等同替换、改进等，均应包含在本申请保护的范围之内。

Claims (14)

  1. 一种像素驱动电路，用于向待驱动元件提供信号，包括：驱动子电路、时长控制子电路和数据写入子电路，
    其中，所述驱动子电路分别电连接所述时长控制子电路和所述数据写入子电路，所述数据写入子电路用于向所述驱动子电路传输数据信号，所述时长控制子电路用于控制所述驱动子电路的导通时长，所述驱动子电路用于在导通时长内根据所述数据信号控制所述待驱动元件的电流。
  2. 根据权利要求1所述的像素驱动电路，其中，所述时长控制子电路包括比较器，所述比较器连接基准电压信号线、所述驱动子电路以及时长信号线，所述比较器用于比较所述时长信号线输入的时长信号和所述基准电压信号线提供的基准电压信号，输出比较信号以控制所述驱动子电路的导通时长。
  3. 根据权利要求2所述的像素驱动电路，其中，所述基准电压信号为三角波信号、锯齿波信号或正弦波信号。
  4. 根据权利要求2所述的像素驱动电路，其中，所述时长控制子电路还包括时长控制晶体管，所述时长控制晶体管的栅极连接至所述比较器的输出端，第一极连接至用于提供时长控制信号的时长控制信号线，第二极连接至所述驱动子电路，所述时长控制晶体管用于根据所述比较信号，输出所述时长控制信号，控制所述驱动子电路的导通时长。
  5. 根据权利要求2所述的像素驱动电路，其中，所述时长控制子电路还包括时长写入子电路，所述时长写入子电路的输入端连接于所述时长信号线，输出端连接至所述比较器的第一输入端，并且所述时长写入子电路的控制端和数据写入控制信号线连接，所述时长写入子电路用于接收所述数据写入控制信号线输出的数据写入控制信号，根据所述数据写入控制信号连通所述时长信号线 和所述比较器。
  6. 根据权利要求5所述的像素驱动电路，其中，所述时长控制子电路还包括时长存储电容，所述时长存储电容的第一端连接至所述比较器的第一输入端和所述时长写入子电路的输出端。
  7. 根据权利要求1所述的像素驱动电路，其中，所述驱动子电路包括驱动晶体管，所述驱动晶体管的栅极和所述时长控制子电路的时长控制晶体管的第二极连接，所述驱动晶体管的第一极和所述数据写入子电路连接，所述驱动晶体管的第二极和所述待驱动元件连接。
  8. 根据权利要求1所述的像素驱动电路，其中，所述数据写入子电路包括数据写入晶体管，所述数据写入晶体管的第一极与数据线电连接，以接收所述数据线输入的数据信号，所述数据写入晶体管的第二极与所述驱动子电路电连接，所述数据写入晶体管的栅极与所述数据写入控制信号线电连接，以接收所述数据写入控制信号。
  9. 根据权利要求1所述的像素驱动电路，其中，所述像素驱动电路还包括以下中的至少一者：
    复位子电路，分别连接所述驱动子电路和所述待驱动元件，用于对所述驱动子电路和所述待驱动元件进行复位；
    补偿子电路，通过所述驱动子电路连接至所述数据写入子电路，用于存储所述数据写入子电路输入的数据信号；
    工作控制子电路，和所述驱动子电路连接，用于控制所述驱动子电路驱动所述待驱动元件发光。
  10. 一种显示设备，包括待驱动元件和根据权利要求1-9任一项所述的像 素驱动电路，所述像素驱动电路与所述待驱动元件连接，所述待驱动元件为电流驱动型发光二极管。
  11. 根据权利要求10所述的显示设备，其中，所述显示设备包括多个亚像素，每个所述亚像素对应设置一个所述像素驱动电路，用于驱动所述亚像素的所述待驱动元件发光。
  12. 根据权利要求11所述的显示设备，其中，所述显示设备还包括：
    多条时长信号线，用于传输时长信号；
    多条数据信号线，用于传输所述数据信号；
    多条时长控制信号线，用于传输时长控制信号；
    其中，同一行所述亚像素对应的各所述像素驱动电路电连接同一条所述时长控制信号线；
    同一列所述亚像素对应的各所述像素驱动电路与同一条所述时长信号线和同一条所述数据信号线电连接。
  13. 一种像素驱动电路的驱动方法，所述像素驱动电路是权利要求1-9中任一项所述的驱动电路，所述方法包括：
    向所述驱动子电路写入数据信号；
    写入工作控制信号，以控制所述驱动子电路导通，来根据所述数据信号驱动所述待驱动元件发光；
    控制所述驱动子电路的导通时长，来控制所述待驱动元件的发光时长。
  14. 根据权利要求13所述的驱动方法，其中，所述控制所述驱动子电路的导通时长，包括：
    写入时长信号；
    比较时长信号和基准电压信号，产生比较信号，以控制所述驱动子电路的 导通时长。
PCT/CN2020/126116 2019-11-05 2020-11-03 像素驱动电路、显示设备和像素驱动电路驱动方法 WO2021088792A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US17/417,238 US11398184B2 (en) 2019-11-05 2020-11-03 Pixel driving circuit, display apparatus, and method for driving pixel driving circuit

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201911071491.8A CN110782831B (zh) 2019-11-05 2019-11-05 像素驱动电路、显示设备和像素驱动电路驱动方法
CN201911071491.8 2019-11-05

Publications (1)

Publication Number Publication Date
WO2021088792A1 true WO2021088792A1 (zh) 2021-05-14

Family

ID=69389172

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2020/126116 WO2021088792A1 (zh) 2019-11-05 2020-11-03 像素驱动电路、显示设备和像素驱动电路驱动方法

Country Status (3)

Country Link
US (1) US11398184B2 (zh)
CN (1) CN110782831B (zh)
WO (1) WO2021088792A1 (zh)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112837649B (zh) * 2019-11-01 2022-10-11 京东方科技集团股份有限公司 像素驱动电路及其驱动方法、显示面板、显示装置
CN110782831B (zh) 2019-11-05 2021-02-26 京东方科技集团股份有限公司 像素驱动电路、显示设备和像素驱动电路驱动方法
CN111261098B (zh) * 2020-03-17 2021-11-12 京东方科技集团股份有限公司 像素驱动电路及驱动方法、显示装置
CN111223443B (zh) * 2020-03-17 2021-02-09 京东方科技集团股份有限公司 像素电路及其驱动方法、显示基板、显示装置
CN111243499B (zh) 2020-03-24 2021-10-15 京东方科技集团股份有限公司 像素驱动电路和显示设备
CN111243521B (zh) * 2020-03-31 2021-04-30 厦门天马微电子有限公司 像素驱动电路、驱动方法及显示面板
CN111477163B (zh) * 2020-04-21 2021-09-28 京东方科技集团股份有限公司 像素驱动电路及其驱动方法、显示面板
US11100849B1 (en) 2020-05-13 2021-08-24 Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd. Display device and driving method thereof
CN111477165A (zh) * 2020-05-13 2020-07-31 深圳市华星光电半导体显示技术有限公司 显示装置及其驱动方法
CN111477164B (zh) 2020-05-13 2022-04-05 深圳市华星光电半导体显示技术有限公司 一种显示器的驱动电路
CN111785201B (zh) * 2020-07-02 2021-09-24 深圳市华星光电半导体显示技术有限公司 一种像素驱动电路及其驱动方法、显示面板以及显示装置
CN113450700B (zh) * 2020-07-10 2022-07-22 重庆康佳光电技术研究院有限公司 一种显示控制方法、装置、显示设备和电子设备
CN111785209B (zh) * 2020-07-16 2022-04-19 京东方科技集团股份有限公司 显示面板及其驱动方法、显示装置
CN114333685B (zh) * 2020-09-25 2023-08-08 京东方科技集团股份有限公司 像素驱动结构及显示面板
US11557246B2 (en) * 2020-09-30 2023-01-17 Boe Technology Group Co., Ltd. Pixel circuit and method for controlling the same, and display device
CN112992041A (zh) * 2021-02-26 2021-06-18 合肥维信诺科技有限公司 显示面板及其驱动方法和显示装置
CN113129845B (zh) * 2021-04-12 2022-07-29 Tcl华星光电技术有限公司 一种背光驱动方法及显示面板
CN113345366B (zh) * 2021-06-10 2022-09-23 成都辰显光电有限公司 像素驱动电路及其驱动方法、显示面板

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107735832A (zh) * 2015-06-05 2018-02-23 苹果公司 显示面板的发光控制装置和方法
CN108735160A (zh) * 2018-04-08 2018-11-02 信利（惠州）智能显示有限公司 有机发光显示驱动装置和有机发光显示器
CN109872686A (zh) * 2019-04-19 2019-06-11 京东方科技集团股份有限公司 一种驱动电路、显示面板及显示面板的制作方法
US20190251904A1 (en) * 2018-02-12 2019-08-15 Samsung Display Co., Ltd. Display device
CN110136642A (zh) * 2019-05-30 2019-08-16 上海天马微电子有限公司 一种像素电路及其驱动方法和显示面板
CN110782831A (zh) * 2019-11-05 2020-02-11 京东方科技集团股份有限公司 像素驱动电路、显示设备和像素驱动电路驱动方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100409290C (zh) * 2001-12-14 2008-08-06 三洋电机株式会社 数字驱动型显示装置
JP3854161B2 (ja) * 2002-01-31 2006-12-06 株式会社日立製作所 表示装置
CN1755778A (zh) * 2004-09-30 2006-04-05 精工爱普生株式会社 像素电路、像素驱动方法以及电子机器
JP2015004945A (ja) * 2013-02-04 2015-01-08 ソニー株式会社 表示装置及びその駆動方法、並びに、制御パルス生成装置
CN110010057B (zh) * 2019-04-25 2021-01-22 京东方科技集团股份有限公司 像素驱动电路、像素驱动方法和显示装置
US11100849B1 (en) * 2020-05-13 2021-08-24 Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd. Display device and driving method thereof

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107735832A (zh) * 2015-06-05 2018-02-23 苹果公司 显示面板的发光控制装置和方法
US20190251904A1 (en) * 2018-02-12 2019-08-15 Samsung Display Co., Ltd. Display device
CN108735160A (zh) * 2018-04-08 2018-11-02 信利（惠州）智能显示有限公司 有机发光显示驱动装置和有机发光显示器
CN109872686A (zh) * 2019-04-19 2019-06-11 京东方科技集团股份有限公司 一种驱动电路、显示面板及显示面板的制作方法
CN110136642A (zh) * 2019-05-30 2019-08-16 上海天马微电子有限公司 一种像素电路及其驱动方法和显示面板
CN110782831A (zh) * 2019-11-05 2020-02-11 京东方科技集团股份有限公司 像素驱动电路、显示设备和像素驱动电路驱动方法

Also Published As

Publication number Publication date
CN110782831A (zh) 2020-02-11
US20220076616A1 (en) 2022-03-10
US11398184B2 (en) 2022-07-26
CN110782831B (zh) 2021-02-26

Similar Documents

Publication Publication Date Title
WO2021088792A1 (zh) 像素驱动电路、显示设备和像素驱动电路驱动方法
CN109872680B (zh) 像素电路及驱动方法、显示面板及驱动方法、显示装置
CN110021264B (zh) 像素电路及其驱动方法、显示面板
WO2020211509A1 (zh) 驱动电路、显示面板及显示面板的制作方法
JP7094300B2 (ja) 画素の駆動回路、画素の駆動方法及び表示装置
KR102579142B1 (ko) 화소와 이를 이용한 유기전계발광 표시장치 및 그의 구동방법
US9595228B2 (en) Pixel array and organic light emitting display device including the same
WO2017080379A1 (zh) 像素补偿电路及其驱动方法、阵列基板以及显示装置
WO2018032899A1 (zh) 像素电路及其驱动方法、显示面板和显示装置
US20080158114A1 (en) Organic electroluminescent display device and method of driving the same
CN113838421A (zh) 像素电路及其驱动方法、显示面板
TWI406227B (zh) 顯示裝置及驅動顯示裝置之方法
US20110254883A1 (en) Pixel circuit relating to organic light emitting diode and display using the same and driving method thereof
CN111276097B (zh) 像素驱动电路及其驱动方法、显示基板
TWI464725B (zh) 像素電路，顯示裝置，顯示裝置之驅動方法及電子單元
KR20120094734A (ko) 유기전계발광 표시장치 및 그의 구동방법
US10997920B2 (en) Pixel drive circuit and drive method, and display apparatus
CN106057126A (zh) 一种像素电路及其驱动方法
US20220084456A1 (en) Pixel driving circuit, driving method thereof, and display device
WO2020187158A1 (zh) 像素驱动电路和显示面板及其驱动方法、显示装置
KR102653575B1 (ko) 표시 장치
KR20170132598A (ko) 유기발광다이오드를 포함하는 화소 회로 및 이를 포함하는 표시장치
WO2021047562A1 (zh) 像素驱动电路、像素单元及驱动方法、阵列基板、显示装置
CN112820236B (zh) 像素驱动电路及其驱动方法、显示面板、显示装置
KR20150141368A (ko) 유기발광 표시장치의 휘도 편차 보상장치 및 보상방법

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 20884327

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 20884327

Country of ref document: EP

Kind code of ref document: A1

122 Ep: pct application non-entry in european phase

Ref document number: 20884327

Country of ref document: EP

Kind code of ref document: A1

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205A DATED 14.02.2023)

122 Ep: pct application non-entry in european phase

Ref document number: 20884327

Country of ref document: EP

Kind code of ref document: A1