WO2021082867A1 - 偏差驱动的总线感知总体布线方法 - Google Patents

偏差驱动的总线感知总体布线方法 Download PDF

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WO2021082867A1
WO2021082867A1 PCT/CN2020/119321 CN2020119321W WO2021082867A1 WO 2021082867 A1 WO2021082867 A1 WO 2021082867A1 CN 2020119321 W CN2020119321 W CN 2020119321W WO 2021082867 A1 WO2021082867 A1 WO 2021082867A1
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wiring
bus
edge
congestion
area
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PCT/CN2020/119321
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French (fr)
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刘耿耿
朱伟大
郭文忠
黄兴
陈国龙
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福州大学
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/392—Floor-planning or layout, e.g. partitioning or placement

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  • the invention belongs to the technical field of integrated circuit computer-aided design, and specifically relates to a deviation-driven bus-sensing overall wiring method.
  • the wiring is usually divided into overall wiring and detailed wiring.
  • the overall wiring is an extremely important stage in the entire physical design.
  • the result of the overall wiring will determine the quality of the detailed wiring later, thereby affecting the result of the entire physical design.
  • the bus plays an increasingly important role in some memory-intensive and computationally intensive chip designs.
  • the purpose of the present invention is to provide a deviation-driven bus-sensing overall wiring method, which takes into account the length matching of the bus, can obtain a high-quality wiring result, and effectively improve the performance of the chip.
  • a deviation-driven bus-sensing overall wiring method includes the following steps:
  • Step S1 Project multi-layer wiring information and resources onto a 2D plane
  • Step S2 Use the FLUTE algorithm to construct the rectangular Steiner minimum tree of all wire nets, and then decompose it to obtain a series of pin pairs;
  • Step S3 According to the positions of the two pins in the pin pair, a congestion cost map is generated according to the following rules;
  • Step S4 According to the congestion cost map, a deviation-driven edge transfer method is adopted to obtain a high-quality topological structure
  • Step S5 Use bus-aware L-shaped wiring to obtain the initial wiring result
  • Step S6 Identify the congested area according to the initial wiring result, and generate a congested area in the congested area;
  • Step S7 Re-lay out the bus wire net and non-bus pin pairs, and judge whether there is overflow, if there is no overflow, enter the post-wiring stage, if there is overflow, go to step S8;
  • Step S8 Re-layout all pin pairs, and judge whether it reaches the user preset value or whether there is overflow, if it reaches or does not overflow, enter the post-wiring stage, otherwise skip to step S6;
  • Step S9 Determine whether there is an overflow according to the structure obtained during the removal and redistribution phase. If there is an overflow, use the labyrinth wiring to redistribute these overflow edges in the entire area; otherwise, proceed to step S10;
  • Step S10 Use length-limited hybrid unidirectional monotonic wiring to redistribute all bus pin pairs.
  • the length of the new path after redistribution is equal to the half circumference of the bounding box formed by the pin pair, the new path replaces the original path, otherwise the path No change; get the final wiring result.
  • the edge on the grid graph through which this edge passes is assigned a weight of 1; otherwise, the pair of pins
  • the edge on the grid where the bounding box is formed is assigned a weight of 0.5.
  • the cost function is set as follows:
  • b eij is based on the basic side of the Sigmoid function of the cost; d c bus line length is a measure of the deviation of the price.
  • Their definitions are as follows:
  • h and k are user-defined parameters; c(e ij ) is the number of wiring tracks available between adjacent wiring units; d(e ij ) is the number of wiring tracks actually used between adjacent wiring units; d is the distance moved by the side; Seg 0 is the side before the movement; Seg e is the side after the movement; It is the j-th pin group in the i-th bus. Further, the L-shaped wiring sensed by the bus is specifically:
  • Step S51 If one of the two L-shaped paths other than the bus line network passes through the area where the bus line network is located, select the other path that does not pass through the area where the bus line network is located;
  • Step S52 If neither of the two L-shaped paths of the non-bus line network passes through the area where the bus line network is located, a path with a smaller cost is selected according to the cost function;
  • Step S53 If the two L-shaped paths of the non-bus line network both pass through the area where the bus line network is located, the path with a smaller number of bus bits is selected.
  • step S6 is specifically:
  • Step S61 Calculate the congestion levels of all sides; then divide the maximum congestion value and 1 into several intervals with different congestion levels according to the congestion level;
  • Step S62 Insert it into the corresponding congestion interval according to the congestion value of the overflow edge
  • Step S62 Starting from the interval with the highest degree of congestion, a congested area is generated for each congested edge in this congested interval;
  • Step S63 Keep expanding the congested area until the average congestion degree of all edges in the area is less than or equal to the smallest congestion value in the congestion interval.
  • step S8 is specifically: for all pin pairs in the entire wiring area, hybrid unidirectional monotonic wiring and adaptive multi-source multi-sink labyrinth wiring are applied to bus pin pairs and non-bus pin pairs, respectively. , Using a historical-based cost function:
  • Is the basic price of the edge Is the historical price
  • d c is the deviation cost
  • v c is the through-hole cost.
  • the present invention has the following beneficial effects:
  • the present invention considers the length matching problem of the bus, can obtain a high-quality wiring result, and effectively improves the performance of the chip.
  • Figure 1 is a wiring area, wiring unit and overall wiring grid diagram in an embodiment of the present invention, where (a) is the wiring area and wiring unit, (b) is the overall wiring grid diagram;
  • Figure 2 is a 2-bit bus with three pin groups in an embodiment of the present invention
  • FIG. 3 is the overall wiring result of the wire net with 3 pins in an embodiment of the present invention.
  • Figure 4 is a flow chart of the method of the present invention.
  • Figure 5 is a wiring topology diagram in an embodiment of the present invention, where (a) is the wiring topology before moving, (b) is the wiring topology moving toward the source pin group, (c) is the wiring topology far away from the source pin Wiring topology moving in the group direction;
  • Figure 6 is a bus area diagram of an embodiment of the present invention, where (a) is a path of L-shaped wiring passing through the bus area, (b) is that two L-shaped wiring paths do not pass through the bus area, (c) is two All L-shaped paths pass through the bus area.
  • the overall wiring model is specifically: in the VLSI physical design and wiring stage, the wiring area of the chip is distributed in multiple metal layers, and the overall wiring of the wiring usually divides each layer into several Rectangles of the same size, each rectangle is called G-Cell, as shown in Figure 1(a).
  • Figure 1(b) shows an overall wiring model including 3 metal layers, and each metal layer is divided into 4 ⁇ 4 G-Cells.
  • each wiring layer has only one direction, and adjacent metal layers are connected through vias (Via).
  • the capacity of the grid side represents the number of routing tracks available between adjacent G-Cell i and G-Cell j
  • d(e ij ) represents the number of routing tracks actually used.
  • bus line network For the bus line network, it has r-bit signals and q bus pin groups (PG). Among them, 1 bus pin group is the source pin group (PG i 0 ), and q-1 is the summary line pin group. In order to meet the consistency of the timing, it is necessary to make the time for each bit signal at the source pin to be transmitted to the sink pin group as much as possible, that is, the length of all pin pairs between the source pin group and the sink pin group equal. When the lengths of all the pin pairs between the two bus pin groups are inconsistent, the line length deviation occurs.
  • the bus line length deviation calculation is defined as follows:
  • FIG. 1 shows a 2-bit bus line network with 3 PGs.
  • the bus wiring target :
  • a bus line network set B ⁇ B 1 ,B 2 ,...,B n ⁇
  • N ⁇ N 1 ,N 2 ,...,N m ⁇ .
  • P ⁇ p 1 , p 2 ,..., p k ⁇ .
  • the number of overflows and the line length deviation are important indicators to measure the level of routing. Therefore, the overall bus-aware router considers congestion and deviation at each stage to optimize the total overflow, total line length deviation, and total line length when considering the shortage of wiring resources and congestion, so as to obtain A high-quality overall wiring result.
  • a deviation-driven bus-sensing overall wiring method includes the following steps:
  • the multi-layer wiring information and resources are projected onto the 2D plane, and then the FLUTE algorithm is used to construct the rectangular Steiner minimum tree of all the wire nets, and then it is decomposed to obtain a series of pin pairs. Finally, according to the positions of the two pins in the pin pair, a congestion cost map is generated according to the following rules:
  • the edge on the grid graph that this edge passes through is assigned a weight of 1; otherwise, the pair of pins is The edge on the grid where the bounding box is formed is assigned a weight of 0.5.
  • a deviation-driven edge transfer technique is used.
  • the core idea of this technology is to transfer some edges in crowded areas to non-crowded areas based on the congestion cost map without increasing the minimum tree line length of the rectangular Steiner and minimizing the line length deviation as much as possible.
  • both pins of a pair of pins are Steiner points, then this edge can use the deviation-driven edge transfer technology within a "safe range".
  • the first case is that we move the edge of signal 2 closer to the source pin group by d distances, as shown in Figure 5(b), (1) For the pin group whose ordinate is smaller than the ordinate of the end edge, it is away from The distance of the source pin group is reduced by 2d lengths, but for the bus, its line length deviation has increased by 2d lengths; (2) For the ordinates that are smaller than the ordinate of the original side and greater than the ordinate of the final side Pin group, its line length deviation has increased (3) For a pin group whose ordinate is greater than that of the original side, its length to the source pin group does not change, so its line length deviation is 0.
  • the second case is that we move the edge of signal 2 away from the source pin group by d distances, as shown in Figure 5(c), (1) For the pin group whose ordinate is smaller than the original ordinate, it is away from The distance of the source pin group has increased by 2d lengths, so its line length deviation has increased by 2d lengths; (2) For the pin group whose ordinate is smaller than the ordinate of the final side and greater than the ordinate of the original side, it The line length deviation has increased (3) For the pin group whose ordinate is greater than the ordinate of the end edge, the length from the source pin group does not change, so its line length deviation is 0.
  • the best position for movement needs to be determined.
  • the total cost of the bus is calculated according to the cost function, and the best position is the edge with the least cost.
  • the cost function is set as follows:
  • beij is the basic cost of the edge based on the Sigmoid function.
  • d c is the cost of measuring the deviation of the bus line length.
  • the bus-aware L-type wiring is used to quickly obtain an initial solution of the overall wiring.
  • the method is as follows: (1) If one of the two L-shaped paths of the non-bus line network passes through the area where the bus line network is located, then we choose the other path that does not pass through the area where the bus line network is located, as shown in Figure 6(a) ); (2) If the two L-shaped paths of the non-bus line network have not passed through the area where the bus line network is located, then we will select the path with a smaller cost according to the cost function, as shown in Figure 6(b) Show; (3) If the two L-shaped paths of the non-bus line network both pass through the area where the bus line network is located, then we choose the path with fewer bus bits, as shown in Figure 6(c).
  • a multi-stage double maze strategy is adopted, which is a relocation strategy based on a combination of resource adjustment based on the congestion interval and overall resource adjustment, so as to avoid prematurely falling into a local optimal solution.
  • a congested area is generated for each congested edge in this congested interval.
  • the size of the congested area is determined by the degree of congestion near the edge, and it continues to expand until the average congestion degree of all edges in the area is less than or equal to the smallest congestion value in the congestion interval.
  • the average congestion is calculated as follows:
  • n is the number of sides of the wiring diagram in the congested area.
  • the re-distribution area is an area slightly larger than the bounding box size of the pin pair to improve the wiring time efficiency and the line length will not increase too much. This redistribution area will become larger as the number of iterations increases, so that the amount of overflow can be reduced.
  • the purpose is to allow bus pin pairs to prioritize the wiring resources that are not occupied in the congested area.
  • mixed unidirectional monotonic wiring For all non-bus pin pairs that overflow in the congested area, use mixed unidirectional monotonic wiring first to avoid excessive increase in line length. If the path of mixed unidirectional monotonic wiring still overflows, then adaptive multi-source multi-sink maze wiring will be used to help the non-bus network to bypass and find a path without overflow. The purpose is to adjust the wiring resources in the congested area, and at the same time reserve the resources in the congested area to the bus pin pairs to prevent the bus pin pairs from detouring, thereby causing excessive line length deviation.
  • hybrid unidirectional monotonic wiring and adaptive multi-source multi-sink labyrinth wiring are respectively applied to bus pin pairs and non-bus pin pairs.
  • This stage uses a historical-based cost function:
  • Is the basic price of the edge Is the historical price
  • d c is the deviation cost
  • v c is the through-hole cost.
  • v c is an adaptive cost function, and its value decreases as the number of costs increases. The purpose of this is to weaken the influence of line length and through holes, thereby encouraging pin pairs to obtain paths with smaller overflow, and It is not a path with a shorter line length and fewer vias.
  • Their definitions are as follows:
  • ⁇ and ⁇ are user-defined parameters.
  • ⁇ and ⁇ are user-defined parameters.
  • Historical item Will increase as the number of overflows of the edge increases, and at the same time It is related to the number of iterations and magnifies the historical cost. Their definitions are as follows:
  • i is the number of iterations
  • k is a user-defined parameter
  • f is a function related to the history item and the number of iterations.
  • the termination condition of this stage is that the overflow count of all edges is 0 or the iteration count reaches the user preset value.
  • the purpose of the post-processing stage is to avoid excessive resource relaxation caused by the third stage, and to further reduce overflow and improve the quality of wiring.
  • the first case is that the removal and re-distribution phase did not solve the overflow of all edges. Then we will first use the labyrinth wiring to re-distribute these overflow edges in the entire area. The wiring result does not allow more overflows.
  • the second case is that all the lines and networks have not overflowed.
  • the cost function used in this stage is as follows:
  • C is a user-defined parameter, it is a very large constant to ensure that the overflow edge will not increase.

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Abstract

一种偏差驱动的总线感知总体布线方法，首先将多层的布线信息和资源投影到2D平面上，在预布线阶段采用偏差驱动的边转移方法得到一个优质的拓扑结构，并使用总线感知的L型布线，得到一个初始布线结果；在拆线重布阶段采用多阶段的双迷宫策略，用来减少溢出和控制偏差的产生；在后布线阶段进行精炼，进一步减少偏差，最终能获得一个高质量的布线结果。该方法考虑总线的长度匹配问题，能够得到一个高质量的布线结果，有效的提高芯片的性能。

Description

偏差驱动的总线感知总体布线方法 技术领域
本发明属于集成电路计算机辅助设计技术领域，具体涉及一种偏差驱动的总线感知总体布线方法。
背景技术
随着超大集成电路制作工艺技术的迅速发展，其设计尺寸越来越小，但规模却不断增大，使得布线难度也越来越高。由于布线问题的高复杂性，布线通常分成总体布线和详细布线。而总体布线是整个物理设计中极其重要的阶段，总体布线的结果将决定后面详细布线的质量，从而影响到整个物理设计的结果。另外，总线在一些存储密集型和计算密集型的芯片设计中地位愈发重要。
技术问题
IP核的广泛使用使得总线的数量也迅猛增多。如果一个总体布线器对有总线的芯片进行总体布线而不考虑总线的长度匹配问题，它的结果会对总线造成严重的时序不匹配，这将大大地影响到芯片的性能。
技术解决方案
有鉴于此，本发明的目的在于提供一种偏差驱动的总线感知总体布线方法，考虑总线的长度匹配问题，能够得到一个高质量的布线结果，有效的提高芯片的性能。
为实现上述目的，本发明采用如下技术方案：
一种偏差驱动的总线感知总体布线方法，包括以下步骤：
(1)准备阶段：
步骤S1:将多层的布线信息和资源投影到2D平面上；
步骤S2:使用FLUTE算法构造出所有线网的直角斯坦纳最小树，紧接着将其分解，得到一系列的引脚对；
步骤S3:根据引脚对中两个引脚的位置，按照以下规则生成拥塞代价图；
(2)预布线阶段：
步骤S4:根据拥塞代价图，采用偏差驱动的边转移方法，得到一个优质的拓扑结构；
步骤S5:采用总线感知的L型布线，得到初始布线结果；
(3)拆线重布阶段：
步骤S6:根据初始布线结果，识别拥塞区间，并在拥塞区间内产生拥塞区域；
步骤S7:重布总线线网和非总线引脚对，并判断是否有溢出，若无溢出则进入后布线阶段，若有溢出则进行步骤S8；
步骤S8:重布所有引脚对，并判断是否达到用户预设值或者有无溢出，若达到或者没有溢出，则进入后布线阶段，否则跳转至步骤S6；
(1)后布线阶段
步骤S9:根据拆线重布阶段得到的结构，判断是否有溢出,若有溢出，则对这些溢出边使用迷宫布线在整个区域进行重布；否则进行步骤S10；
步骤S10:使用长度限制的混合单向单调布线重布所有的总线引脚对，当重布以后的新路径长度等于引脚对所形成边界框的半周长，则新路径替换原路径，否则路径不变；得到最终的布线结果。
进一步的，若引脚对的两个引脚可以直接通过一条水平边或者垂直边相连，则对这条边所经过网格图上的边赋上1的权值；否则，这对引脚对所形成的边界框所在网格图上的边赋上0.5的权值。
进一步的，所述偏差驱动的边转移方法移动的最佳位置的确定方法如下：
对于每个可能的位置，根据代价函数计算总线的总代价，最佳的位置即代价最小的边，代价函数设置如下：
Figure PCTCN2020119321-appb-000001
其中，b eij是基于Sigmoid函数的边的基本代价；d c是衡量总线线长偏差的代价。它们的定义如下：
Figure PCTCN2020119321-appb-000002
Figure PCTCN2020119321-appb-000003
其中，h和k是用户自定义的参数；c(e ij)是相邻布线单元之间可用的布线轨道的数量；d(e ij)是相邻布线单元之间实际使用的布线轨道数量；d是边移动的距离；Seg 0是移动前的边；Seg e是移动后的边；
Figure PCTCN2020119321-appb-000004
是第i个总线中第j个引脚组。进一步的，所述总线感知的L型布线具体为：
步骤S51:若非总线线网的两条L型路径中的其中一条路径经过总线线网所在区域，则选择另一条没有经过的总线线网所在区域的路径；
步骤S52:若非总线线网的两条L型路径都没有经过了总线线网所在的区域，则根据代价函数选择具有较小代价的路径；
步骤S53:若非总线线网的两条L型路径都经过总线线网所在的区域，则选择经过总线位数较少的路径。
进一步的，所述步骤S6具体为：
步骤S61:计算所有边的拥塞程度；然后根据拥塞程度，将最大拥塞值与1之间分成若干个不同拥塞程度的区间；
步骤S62:根据溢出边的拥塞值将其插入到相应拥塞区间内；
步骤S62:从拥塞程度最高的区间开始，在这个拥塞区间内每一条拥塞边生成一个拥塞区域；
步骤S63:不断扩大拥塞区域直到该区域内所有边的平均拥塞程度小于等于拥塞区间内最小的拥塞值。
进一步的，所述步骤S8具体为：对于整个布线区域中所有的引脚对，混合单向单调布线和自适应的多源多汇的迷宫布线分别应用在总线引脚对和非总线引脚对，采用的是基于历史的代价函数：
Figure PCTCN2020119321-appb-000005
其中，
Figure PCTCN2020119321-appb-000006
是边的基本代价，
Figure PCTCN2020119321-appb-000007
是历史代价，
Figure PCTCN2020119321-appb-000008
是惩罚代价，d c是偏差代价，v c是通孔代价。
有益效果
本发明与现有技术相比具有以下有益效果：
1、本发明考虑总线的长度匹配问题，能够得到一个高质量的布线结果，有效的提高芯片的性能。
附图说明
图1是本发明一实施例中布线区域和布线单元以及总体布线网格图，其中(a)为布线区域和布线单元，(b)为总体布线网格图；
图2是本发明一实施例中有三个引脚组的2位总线；
图3是本发明一实施例中有3个引脚的线网的总体布线结果；
图4是本发明方法流程图；
图5是本发明一实施例中布线拓扑图，其中(a)为未移动前的布线拓扑,(b)为往靠近源引脚组方向移动的布线拓扑，(c)为往远离源引脚组方向移动的布线拓扑；
图6是本发明一实施例中总线区域图，其中(a)为一条L型布线的路径经过总线区域，(b)为两条L型布线的路径都没有经过总线区域，(c)为两条L型的路径都经过总线区域。
本发明的实施方式
下面结合附图及实施例对本发明做进一步说明。
请参照图1，本实施例中，总体布线模型具体为：在超大规模集成电路物理设计布线阶段中，芯片的布线区域分布在多个金属层，布线总体布线通常将每个层被分成若干个大小相同的矩形，每个矩形被称为G-Cell，如图1(a)所示。因此，在总体布线阶段，布线区域通常用网格图G＝(V,E)表示，其中节点v i∈V代表布线网格单元，e ij∈E代表相邻网格单元对(v i，v j)的连接边。图1(b)给出 了一个包括3层的金属层，且每层金属层被划分为4×4个G-Cell的总体布线模型。除此之外，每个布线层只有一个方向，相邻金属层通过通孔(Via)连接。
在本实施例中，线网溢出计算：
网格边的容量即c(e ij)代表相邻G-Cell i和G-Cell j之间可用的布线轨道的数量，而d(e ij)则表示实际使用的布线轨道数量。当实际使用的轨道数量超过可用的轨道数量时，则发生溢出。因此，根据d(e ij)和c(e ij)可得到边的溢出量，溢出计算如下所示:
Figure PCTCN2020119321-appb-000009
在本实施例中，总线偏差计算：
对于总线线网而言，它有r位信号和q个总线引脚组(PG)。其中，1个总线引脚组为源引脚组(PG i 0)，q-1个为汇总线引脚组
Figure PCTCN2020119321-appb-000010
为了满足时序的一致，必须尽可能使在源引脚的每一个位信号传输到汇引脚组的时间尽可能相同，即源引脚组和汇引脚组之间的所有引脚对的长度相等。当两个总线引脚组之间的所有引脚对的长度不一致时，则发生了线长偏差。总线线长偏差计算定义如下：
Figure PCTCN2020119321-appb-000011
其中
Figure PCTCN2020119321-appb-000012
是第i个总线线网的源引脚组(PG i 0)和第j个汇引脚组
Figure PCTCN2020119321-appb-000013
之间第k对引脚组的线长，
Figure PCTCN2020119321-appb-000014
是第i个总线线网的PG i 0和
Figure PCTCN2020119321-appb-000015
之间所有引脚组中的最大线长。图2给出了一个有3个PG的2位总线线网。
在本实施例中，总线布线目标：
总线感知的总体布线问题可以描述为：给定一个总体布线图G＝(V,E),每条边的通道容量c(e ij),以及一个总线线网集合B＝{B 1,B 2,…,B n}和一个非总线线网集合N＝{N 1,N 2,…,N m}。对于每个非总线线网NB j∈NB,1≤j≤m，都有一组引脚P＝{p 1,p 2,…,p k}。对于总线线网B i∈B,1≤i≤n,给出信号的位数q和一组总线引脚组PG i＝{PG i 0,PG i 1,…,PG i q-1},0≤j≤q-1，其中PG i 0定义为源引脚组，
Figure PCTCN2020119321-appb-000016
定义为汇引脚组。
根据引脚所在G-Cell的位置，将所有的引脚映射到网格图G＝(V,E)中对应的顶点上。考虑总线的总体布线的目标是为每条线网在G＝(V,E)上找到一条合 法路径将该线网的所有引脚连接起来。例如，图3是一个3引脚的线网的总体布线结果的一个简单示例。
溢出数目和线长偏差是衡量可布线性高低的重要指标。因此，总线感知的总体布线器在考虑布线资源紧张和拥塞的情况下，通过在每个阶段对拥塞和偏差进行考虑，以优化总的溢出、总的线长偏差和总的线长，从而得到一个高质量的总体布线结果。
参考图4，在本实施例中，一种偏差驱动的总线感知总体布线方法，包括以下步骤：
(1)准备阶段：
首先，将多层的布线信息和资源投影到2D平面上，然后使用FLUTE算法构造出所有线网的直角斯坦纳最小树，紧接着将其分解，得到一系列的引脚对。最后，根据引脚对中两个引脚的位置，按照以下规则生成拥塞代价图：
如果引脚对的两个引脚可以直接通过一条水平边(或者垂直边)相连，则对这条边所经过网格图上的边赋上1的权值；否则，这对引脚对所形成的边界框所在网格图上的边赋上0.5的权值。
(2)预布线阶段：
在生成拥塞代价图之后，为了避免过度拥塞，获得更好的拓扑结构，使用一种偏差驱动的边转移技术。该技术的核心思想是在不增加直角斯坦纳最小树线长且尽可能最小化线长偏差的前提下，根据拥塞代价图，将一些处于拥挤区域的边转移到不拥挤的区域。
如果一对引脚对的两个引脚都是斯坦纳点，那么这条边可以在一个“安全范围”内使用偏差驱动的边转移技术。
但是对于总线而言，它的位数比较多，每个位经过FLUTE算法生成的拓扑结构都是一样，移动某些位的边会造成较大的线长偏差。然而，如果不移动，则会出现线长过长或者边大量溢出的情况。下述的例子用来解释偏差驱动的边转移技术。
在本实施例中，对于一个信号数是两位的总线来说，如图5(a)所示，以水平边举例，我们分两种情况考虑。其中，移动前的边称为原边(Seg o)，移动后的边称为终边(Seg e)，移动后会有三类引脚组。第一种情况是我们移动信号2的边 往靠近源引脚组的方向d个距离，如图5(b)所示，(1)对于纵坐标小于终边纵坐标的引脚组，它离源引脚组的距离减少了2d个长度，但是，对于总线而言，它的线长偏差却增大了2d个长度；(2)对于纵坐标小于原边纵坐标且大于终边纵坐标的引脚组，它的线长偏差增大了
Figure PCTCN2020119321-appb-000017
(3)对于纵坐标大于原边纵坐标的引脚组，它到源引脚组的长度没有变化，因此它的线长偏差为0。第二种情况是我们移动信号2的边往远离源引脚组的方向d个距离，如图5(c)所示，(1)对于纵坐标小于原边纵坐标的引脚组，它离源引脚组的距离增加了2d个长度，因此，它的线长偏差却增大了2d个长度；(2)对于纵坐标小于终边纵坐标且大于原边纵坐标的引脚组，它的线长偏差增大了
Figure PCTCN2020119321-appb-000018
(3)对于纵坐标大于终边纵坐标的引脚组，它到源引脚组的长度没有变化，因此它的线长偏差为0。
本实施例中，需要确定移动的最佳位置，对于每个可能的位置，根据代价函数计算总线的总代价，最佳的位置即代价最小的边。代价函数设置如下：
Figure PCTCN2020119321-appb-000019
其中，b eij是基于Sigmoid函数的边的基本代价。d c是衡量总线线长偏差的代价。它们的定义如下：
Figure PCTCN2020119321-appb-000020
Figure PCTCN2020119321-appb-000021
本实施例中，为了给所有的引脚对快速布线，同时避免非总线线网过多的占用总线线网的资源，采用总线感知的L型布线以快速得到一个总体布线的初始解，具体的做法如下：(1)如果非总线线网的两条L型路径中的其中一条路径经过总线线网所在区域，那么我们选择另一条没有经过的总线线网所在区域的路径，如图6(a)所示；(2)如果非总线线网的两条L型路径都没有经过了总线线网所在的区域，那么我们会根据代价函数选择具有较小代价的路径，如图 6(b)所示；(3)如果非总线线网的两条L型路径都经过总线线网所在的区域，那么我们选择经过总线位数较少的路径,如图6(c)所示。
这个阶段采用的代价函数如下：
Figure PCTCN2020119321-appb-000022
(3)拆线重步阶段：
由于L型布线仅考虑两条路径，在许多情况下，每个引脚对都无法找到合适的路径来避免拥塞。因此，拆线重步阶段的主要任务是为每个引脚对找到一条没有溢出的路径。
本实施例中，采用一种多阶段的双迷宫策略，该策略是基于拥塞区间的资源调整和基于整体资源调整相结合的重布策略，这样避免了过早陷入局部最优解。
本阶段的拆线重布的具体操作如下：
拥塞区间的识别：
首先，先计算所有边的拥塞程度；然后根据拥塞程度，将最大拥塞值与1之间分成若干个不同拥塞程度的区间I＝{I 1,I 2,…,I m}；最后，根据溢出边的拥塞值将其插入到相应拥塞区间内。
拥塞区域的产生：
从最拥塞的区间开始，为在这个拥塞区间内每一条拥塞边生成一个拥塞区域。拥塞区域的大小是由该边附近的拥塞程度决定的，不断扩大直到该区域内所有边的平均拥塞程度小于等于拥塞区间内最小的拥塞值。平均拥塞的计算方式如下：
Figure PCTCN2020119321-appb-000023
其中，n是拥塞区域内布线图的边数。
引脚对的标记：
对于一个拥塞区间内所有的拥塞区域，标记拥塞区域内的所有引脚对，同时也将里面的总线引脚对进行特别标记。只要引脚对的一个引脚位于拥塞区域内，则它就被标记。
拥塞区域的重布：
对于位于拥塞区间的总线引脚对，使用混合单向单调布线。重布区域是一个稍大于引脚对的边界框大小的区域，以提高布线时间效率和线长不会过多增大。这个重布区域会随着迭代次数的增加而变大，使得溢出量能够减少。同时，对于总线引脚对的线长会有一个重布长度的限制，它发生一次溢出，长度限制的范围就扩大一个单位。因此，线长偏差的增加将受到限制。目的是让总线引脚对优先占用拥塞区域没被占用的布线资源。
对于位于拥塞区间的所有发生溢出的非总线引脚对，首先使用混合单向单调布线，可以避免线长过多的增加。如果混合单向单调布线的路径还有溢出，那么将使用自适应的多源多汇迷宫布线来帮助非总线线网去绕行找到一条无溢出的路径。目的是调整拥塞区域的布线资源，同时将拥塞区域内的资源预留给总线引脚对，避免总线引脚对去绕行，从而产生过多的线长偏差。
整个布线区域的重布：
对于整个布线区域中所有的引脚对，混合单向单调布线和自适应的多源多汇的迷宫布线分别应用在总线引脚对和非总线引脚对。
这是为了进一步协调整个布线区域内的布线资源，避免了过早陷入局部最优解。
本阶段采用的是基于历史的代价函数：
Figure PCTCN2020119321-appb-000024
其中，
Figure PCTCN2020119321-appb-000025
是边的基本代价，
Figure PCTCN2020119321-appb-000026
是历史代价，
Figure PCTCN2020119321-appb-000027
是惩罚代价，d c是偏差代价，v c是通孔代价。
Figure PCTCN2020119321-appb-000028
和v c是自适应的代价函数，其值随着代价次数的增加而较少，这样做的目的是削弱线长和通孔的影响，从而鼓励引脚对获得具有较小溢出的路径，而不是具有较短线长和较少通孔的路径。它们的定义如下：
Figure PCTCN2020119321-appb-000029
Figure PCTCN2020119321-appb-000030
其中，α和β是用户自定义的参数。
但是，在某种程度上，线长因素的逐渐弱化会造成偏差的增大。因此，为了抵消这种影响，在代价函数中加入偏差代价。它的定义如下：
Figure PCTCN2020119321-appb-000031
其中，α和β是用户自定义的参数。
历史项
Figure PCTCN2020119321-appb-000032
会随着边的溢出次数的增加而变大，同时
Figure PCTCN2020119321-appb-000033
与迭代次数有关，对历史代价起放大作用。它们的定义如下：
Figure PCTCN2020119321-appb-000034
Figure PCTCN2020119321-appb-000035
其中，i是迭代的次数，k是用户自定义的参数，f是与历史项和迭代次数相关的函数。
本阶段终止条件是所有的边的溢出数为0或者迭代次数达到用户预设值。
(4)后布线阶段：
后处理阶段的提出的目的是为了避免第三阶段造成资源过度松弛的情况，并进一步减少溢出，提高布线的质量。
经过拆线重布阶段后，后布线阶段会有两种情况。第一种情况是拆线重布阶段没有解决所有边的溢出，那么我们首先会对这些溢出边使用迷宫布线在整个区域进行重布，布线结果不允许产生更多的溢出数。第二种情况是所有的线网都已经没有发生溢出了，在不增加溢出数的前提下，那么我们只关注于最小化线长偏差。具体的说，使用长度限制的混合单向单调布线重布所有的总线引脚对，只有重布以后的新路径长度等于引脚对所形成边界框的半周长，新路径才会替换原路径，否则路径不变。
本阶段采用的代价函数如下：
Figure PCTCN2020119321-appb-000036
其中C是用户自定义的参数，它是一个非常大的常数，以保证溢出边不会增加。
以上所述仅为本发明的较佳实施例，凡依本发明申请专利范围所做的均等变化与修饰，皆应属本发明的涵盖范围。

Claims (6)

  1. 一种偏差驱动的总线感知总体布线方法，其特征在于，包括以下步骤：
    (1)准备阶段：
    步骤S1:将多层的布线信息和资源投影到2D平面上；
    步骤S2:使用FLUTE算法构造出所有线网的直角斯坦纳最小树，紧接着将其分解，得到一系列的引脚对；
    步骤S3:根据引脚对中两个引脚的位置，按照以下规则生成拥塞代价图；
    (2)预布线阶段：
    步骤S4:根据拥塞代价图，采用偏差驱动的边转移方法，得到一个优质的拓扑结构；
    步骤S5:采用总线感知的L型布线，得到初始布线结果；
    (3)拆线重布阶段：
    步骤S6:根据初始布线结果，识别拥塞区间，并在拥塞区间内产生拥塞区域；
    步骤S7:重布总线线网和非总线引脚对，并判断是否有溢出，若无溢出则进入后布线阶段，若有溢出则进行步骤S8；
    步骤S8:重布所有引脚对，并判断是否达到用户预设值或者有无溢出，若达到或者没有溢出，则进入后布线阶段，否则跳转至步骤S6；
    (3)后布线阶段
    步骤S9:根据拆线重布阶段得到的结构，判断是否有溢出,若有溢出，则对这些溢出边使用迷宫布线在整个区域进行重布；否则进行步骤S10；
    步骤S10:使用长度限制的混合单向单调布线重布所有的总线引脚对，当重布以后的新路径长度等于引脚对所形成边界框的半周长，则新路径替换原路径，否则路径不变；得到最终的布线结果。
  2. 根据权利要求1所述的一种偏差驱动的总线感知总体布线方法，其特征在于，所述预设规则具体为：若引脚对的两个引脚可以直接通过一条水平边或者垂直边相连，则对这条边所经过网格图上的边赋上1的权值；否则，这对引脚对所形成的边界框所在网格图上的边赋上0.5的权值。
  3. 根据权利要求1所述的一种偏差驱动的总线感知总体布线方法，其特征在于，所述偏差驱动的边转移方法移动的最佳位置的确定方法如下：
    对于每个可能的位置，根据代价函数计算总线的总代价，最佳的位置即代价最小的边，代价函数设置如下：
    Figure PCTCN2020119321-appb-100001
    其中，b eij是基于Sigmoid函数的边的基本代价；d c是衡量总线线长偏差的代价。它们的定义如下：
    Figure PCTCN2020119321-appb-100002
    Figure PCTCN2020119321-appb-100003
    其中，h和k是预设值；c(e ij)是布线区域中相邻布线单元之间可用的布线轨道的数量；d(e ij)则表示实际使用的布线轨道数量；d是边移动的距离；Seg 0是移动前的边，seg e是移动后的边；
    Figure PCTCN2020119321-appb-100004
    是第i个总线中第j个引脚组。
  4. 根据权利要求1所述的一种偏差驱动的总线感知总体布线方法，其特征在于，所述总线感知的L型布线具体为：
    步骤S51:若非总线线网的两条L型路径中的其中一条路径经过总线线网所在区域，则选择另一条没有经过的总线线网所在区域的路径；
    步骤S52:若非总线线网的两条L型路径都没有经过了总线线网所在的区域，则根据代价函数选择具有较小代价的路径；
    步骤S53:若非总线线网的两条L型路径都经过总线线网所在的区域，则选择经过总线位数较少的路径。
  5. 根据权利要求1所述的一种偏差驱动的总线感知总体布线方法，其特征在于，所述步骤S6具体为：
    步骤S61:计算所有边的拥塞程度；然后根据拥塞程度，将最大拥塞值与1之间分成若干个不同拥塞程度的区间；
    步骤S62:根据溢出边的拥塞值将其插入到相应拥塞区间内；
    步骤S62:从拥塞程度最高的区间开始，在这个拥塞区间内每一条拥塞边生成一个拥塞区域；
    步骤S63:不断扩大拥塞区域直到该区域内所有边的平均拥塞程度小于等于拥塞区间内最小的拥塞值。
  6. 根据权利要求1所述的一种偏差驱动的总线感知总体布线方法，其特征在于，所述步骤S8具体为：对于整个布线区域中所有的引脚对，混合单向单调布线和自适应的多源多汇的迷宫布线分别应用在总线引脚对和非总线引脚对，采用的是基于历史的代价函数：
    Figure PCTCN2020119321-appb-100005
    其中，
    Figure PCTCN2020119321-appb-100006
    是边的基本代价，
    Figure PCTCN2020119321-appb-100007
    是历史代价，
    Figure PCTCN2020119321-appb-100008
    是惩罚代价，d c是偏差代价，v c是通孔代价。
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