WO2021079563A1 - Boucle à verrouillage de phase fractionnelle et dispositif à boucle à verrouillage de phase - Google Patents

Boucle à verrouillage de phase fractionnelle et dispositif à boucle à verrouillage de phase Download PDF

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WO2021079563A1
WO2021079563A1 PCT/JP2020/026776 JP2020026776W WO2021079563A1 WO 2021079563 A1 WO2021079563 A1 WO 2021079563A1 JP 2020026776 W JP2020026776 W JP 2020026776W WO 2021079563 A1 WO2021079563 A1 WO 2021079563A1
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frequency
phase
locked loop
signal
fractional
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PCT/JP2020/026776
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English (en)
Japanese (ja)
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飯塚　哲也
祖楽 徐
将 長田
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国立大学法人東京大学
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H03L7/197—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division

Definitions

  • the present invention relates to a fractional phase-locked loop and a phase-locked loop device.
  • phase-locked loop PLL: Phase Locked Loop
  • PFD Phase Frequency Detector
  • CP Charge Pump
  • LF Loop Filter
  • VCO Voltage Controlled Oscillator
  • variable divider variable DIV: Divider
  • the phase detector 822 compares the reference signal from the oscillator 812 with the reference signal from the variable frequency divider 830 and outputs a signal corresponding to the phase difference.
  • the charge pump 824 converts the signal from the phase detector 822 into an electric current.
  • the loop filter 826 removes the high frequency component of the current from the charge pump 824 and converts it into the control voltage of the voltage controlled oscillator 828.
  • the voltage controlled oscillator 828 controls the frequency of the output signal based on the control voltage from the loop filter 826.
  • the variable frequency divider 830 divides the signal from the voltage controlled oscillator 828 by a variable frequency division ratio and outputs it to the phase detector 822 as a reference signal.
  • the frequency Fout of the signal from the voltage controlled oscillator 828 is ideally a desired value (non-integer) of the frequency division ratio of the variable frequency divider 830 to the frequency Fref of the reference signal from the oscillator 812. ) Is multiplied.
  • the division ratio of the variable frequency divider 830 is set. It should be 39 at a rate of 25% and 40 at a rate of 75%. Therefore, a phase error occurs in the signal from the variable frequency divider 830 due to the deviation between the actual value (39 or 40) and the desired value (39.25) of the frequency division ratio of the variable frequency divider 830, which is caused by this. Phase noise appears in the final output signal of the fractional phase-locked loop 820. Further, due to the non-linearity of the components such as PFD822 and LPF824, noise at a specific frequency called Fractional Spur also appears in the final output signal as the output of the variable divider 830 fluctuates.
  • FIG. 16 is an explanatory diagram showing a linear model of the above-mentioned fractional phase-locked loop 820.
  • Kpd “F (s)”, “Kvco / s”, and “ ⁇ Nfd” are the phase detector 822, the charge pump 824, the loop filter 828, the voltage controlled oscillator 828, and the variable divider 830, respectively. Is expressed by a transfer function.
  • ⁇ ref is a reference signal.
  • ⁇ out is an output signal that is finally output.
  • In, cp is phase noise due to disturbance of the current from the charge pump 824.
  • ⁇ n, vco is the phase noise generated in the voltage controlled oscillator 828.
  • ⁇ n, div is the phase noise that appears in the signal from the variable divider 830.
  • the output signal ⁇ out can be expressed as in equation (2). From this equation (2), it can be seen that the phase noises ⁇ n and div are amplified by approximately Nfd times (for example, approximately 39.25 times) and appear in the output signal ⁇ out. Therefore, it is required to devise a fractional phase-locked loop that can avoid the phase noise ⁇ n and div being greatly amplified.
  • the main object of the fractional phase-locked loop and the phase-locked loop device of the present invention is to provide a configuration capable of avoiding a large amplification of phase noise appearing in a signal from a variable frequency divider.
  • the fractional phase-locked loop and the phase-locked loop device of the present invention have adopted the following means in order to achieve the above-mentioned main object.
  • the fractional phase-locked loop of the present invention A fractional phase-locked loop that multiplies the frequency of the reference signal by a non-integer and outputs it to the output section.
  • a first frequency adjusting unit that controls the frequency of the signal output to the output unit based on the phase difference between the two input signals.
  • a variable frequency divider that divides the frequency of the reference signal or the signal from the first frequency adjustment unit by a variable division ratio and outputs it to the first frequency adjustment unit.
  • a second that outputs a signal of the second related frequency of the difference between the frequency of the signal from the first frequency adjusting unit and the first related frequency based on the frequency of the reference signal or the multiplication of the difference to the first frequency adjusting unit.
  • Frequency control unit and The gist is to prepare.
  • the first frequency adjusting unit that controls the frequency of the signal output to the output unit based on the phase difference between the two input signals, and the reference signal or the signal from the first frequency adjusting unit
  • the second frequency adjusting unit includes the frequency of the signal from the first frequency adjusting unit and the frequency obtained by multiplying the frequency of the reference signal or the frequency of the related signal based on the reference signal. It may have a harmonic mixer that generates a signal including the frequency component of each difference of the above, and a low-pass filter that extracts and outputs a frequency component of a predetermined frequency or less from each frequency component included in the signal from the harmonic mixer. .. In this case, the low-pass filter may extract and output only the minimum frequency component from each of the frequency components.
  • the second frequency adjusting unit may further include an integer phase-locked loop that multiplies and outputs the frequency of the signal from the low-pass filter. In this way, it is possible to more sufficiently avoid that the phase noise appearing in the signal from the variable frequency divider is greatly amplified.
  • the inventors confirmed this by a linear model of the fractional phase-locked loop of the present invention in this embodiment.
  • the fractional phase-locked loop of the present invention may include a fixed frequency divider that divides the reference signal by a fixed frequency division ratio and outputs it to the second frequency adjustment unit. In this way, injection pulling can be avoided.
  • a fixed frequency divider that divides the reference signal by a fixed frequency division ratio and outputs it to the second frequency adjustment unit.
  • the first frequency adjusting unit compares two input signals and outputs a signal corresponding to the phase difference, and converts a signal from the phase detector into a current.
  • the phase-locked loop loop device of the present invention is the fractional phase-locked loop of the present invention of any of the above-described aspects, and a second inserter that multiplies the frequency of the initial reference signal and outputs it as the reference signal to the fractional phase-locked loop.
  • the gist is to provide a phase-locked loop.
  • the phase-locked loop device of the present invention includes the fractional phase-locked loop of the present invention in any of the above aspects, the effect exerted by the fractional phase-locked loop of the present invention, for example, appears in the signal from the variable frequency divider. It is possible to obtain the same effect as the effect of avoiding the large amplification of the phase noise.
  • variable frequency divider may divide the frequency of the signal from the first frequency control unit by a variable division ratio and output it to the first frequency control unit. .. In this way, in order to increase the input frequency of the variable frequency divider, it is not necessary to increase the frequency of the reference signal from the integer phase-locked loop, so that the power consumption of the integer phase-locked loop can be suppressed. ..
  • FIG. 1 is a configuration diagram showing an outline of the configuration of the phase-locked loop device 20 as the first embodiment of the present invention.
  • the phase-locked loop loop device 20 of the first embodiment includes an integer phase-locked loop 21 connected to the oscillator 12, and a fractional phase-locked loop circuit 21 connected to the integral phase-locked loop 21 and the output unit 14. 40 and.
  • the oscillator 12 for example, a crystal oscillator that oscillates a signal having a frequency of about 20 MHz to 100 MHz is used.
  • the injector phase-locked loop 21 is configured as a circuit that multiplies the frequency Fref of the first reference signal from the oscillator 12 and outputs it as a second reference signal (frequency Fit signal) to the fractional phase-locked loop 40. It includes a detector (PFD) 22, a charge pump (CP) 24, a loop filter (LF) 26, a voltage controlled oscillator (VCO) 28, and a fixed frequency divider (fixed DIV) 30.
  • PFD detector
  • CP charge pump
  • LF loop filter
  • VCO voltage controlled oscillator
  • fixed DIV fixed frequency divider
  • the phase detector 22 compares the first reference signal from the oscillator 12 with the signal from the fixed frequency divider 30 and outputs a signal corresponding to the phase difference.
  • the charge pump 24 converts the signal from the phase detector 22 into an electric current.
  • the phase detector 22 and the charge pump 24 are used to match the frequency Fref of the first reference signal from the oscillator 12 with the frequency Fid1 of the signal from the fixed frequency divider 30.
  • the loop filter 26 removes high frequency components (frequency components higher than the predetermined frequency F0) of the current from the charge pump 24 and converts them into the control voltage of the voltage controlled oscillator 28.
  • the voltage controlled oscillator 28 controls the frequency Fit of the second reference signal output to the fractional phase-locked loop 40 based on the control voltage from the loop filter 26.
  • the fixed frequency divider 30 divides the signal from the voltage controlled oscillator 28 by a fixed frequency division ratio Nid1 and outputs the signal to the phase detector 22. Therefore, the frequency Fid1 of the signal from the fixed frequency divider 30 becomes the frequency (Fint / Nid1).
  • the fractional phase-locked loop 40 is configured as a circuit that multiplies the frequency Fit of the second reference signal from the integer phase-locked loop 21 by a non-integral and outputs the final output signal (frequency Fout signal) to the output unit 14.
  • Phase detector (PFD) 42 charge pump (CP) 44, loop filter (LF) 46, voltage controlled oscillator (VCO) 48, variable frequency divider (variable DIV) 50, fixed frequency divider It includes a (fixed DIV) 52, a harmonic mixer (HM) 54, and a low-pass filter (LPF) 56.
  • the phase detector 42 compares the signal from the variable frequency divider 50 with the signal from the low-pass filter 56, and outputs a signal corresponding to the phase difference.
  • the charge pump 44 converts the signal from the phase detector 42 into an electric current.
  • the phase detector 42 and the charge pump 44 are used to match the frequency Ffd of the signal from the variable frequency divider 50 with the frequency Flpf of the signal from the lowpass filter 56.
  • the loop filter 46 removes high frequency components (frequency components higher than the predetermined frequency F1) of the current from the charge pump 44 and converts them into the control voltage of the voltage controlled oscillator 48.
  • the predetermined frequency F1 may be the same frequency as the predetermined frequency F0, or may be a different frequency.
  • the voltage controlled oscillator 48 controls the frequency Fout of the final output signal output to the output unit 14 based on the control voltage from the loop filter 46.
  • the variable frequency divider 50 includes, for example, a multi-module divider (MMD: Multi-Modulus Divider) capable of changing the frequency division ratio, and a delta-sigma modulator (MMD: Multi-Modulus Divider) that controls the frequency division ratio using the multi-module divider. It is configured as a well-known variable frequency divider with DSM: Delta-Sigma Modulator).
  • the variable frequency divider 50 divides the second reference signal from the integer phase-locked loop 21 by a variable frequency division ratio Nfd and outputs it to the phase detector 42. Therefore, the frequency Ffd of the signal from the variable frequency divider 50 is the frequency (Fint / Nfd). In the variable frequency divider 50, for example, when the desired value of the variable frequency division ratio Nfd is 39.25, the variable frequency division ratio Nfd becomes 39 at a rate of 25% and 40 at a rate of 75%. Operate.
  • the fixed frequency divider 52 divides the second reference signal from the integer phase-locked loop 21 by a fixed frequency division ratio Nid2 and outputs it to the harmonic mixer 54. Therefore, the frequency Fid2 of the signal from the fixed frequency divider 52 becomes the frequency (Fint / Nid2).
  • the low-pass filter 56 extracts a low frequency component (frequency component having a predetermined frequency F2 or less) from the signal from the harmonic mixer 54 and outputs it to the phase detector 42.
  • the predetermined frequency F2 is set so that only the minimum frequency component of each frequency component included in the signal from the harmonic mixer 54 is extracted in the first embodiment.
  • the frequency Flpf of the signal output from the low-pass filter 56 to the phase detector 42 is a multiplication (1x, 2) of the frequency Fout of the signal from the voltage control oscillator 48 and the frequency Fid2 of the signal from the fixed divider 52. It is the minimum frequency among the frequencies of each difference from the double, ).
  • the multiplication for example, 3 times
  • the frequency Flpf of the signal output from the low-pass filter 56 to the phase detector 42 can be expressed as in the equation (4).
  • the relationship between the frequency Fit of the second reference signal from the integer phase-locked loop 21 and the frequency Fout of the final output signal output to the output unit 14 is determined. It can be expressed as in equation (5).
  • the frequency division ratio Nid1 of the fixed frequency divider 30, the desired value of the frequency division ratio Nfd of the variable frequency divider 50, and the frequency division ratio Nid2 of the fixed frequency divider 52 are the final output signals. It is appropriately set based on the desired value of the frequency Fout of.
  • FIG. 2 is an explanatory diagram showing a linear model of the fractional phase-locked loop 40 included in the phase-locked loop device 20 of the first embodiment.
  • Kpd “F (s)”, “Kvco / s”, “ ⁇ Nfd”, and “ ⁇ Nid2” are the phase detector 42, the charge pump 44, the loop filter 46, and the voltage controlled oscillator 48, respectively.
  • the variable frequency divider 50 and the fixed frequency divider 52 are represented by a transfer function.
  • “ ⁇ Nhm” and the symbol for calculating the difference between the two represent the harmonic mixer 54 and the low-pass filter 56 as a transfer function.
  • ⁇ int is a second reference signal from the integer phase-locked loop 21.
  • ⁇ out is the final output signal output to the output unit 14.
  • the final output signal ⁇ out output to the output unit 14 can be expressed as in the equation (6).
  • the Laplace operator s is sufficiently small, that is, when the value Hol (s) is sufficiently large, the phase noises ⁇ n and div are not amplified and are finally (approximately 1 times). It can be seen that it appears in the output signal ⁇ out. Therefore, it can be said that it is possible to prevent the phase noises ⁇ n and div from being greatly amplified and appearing in the final output signal ⁇ out.
  • the fractional phase-locked loop 40 since the fractional phase-locked loop 40 includes the fixed frequency divider 52, the division ratio Nid2 of the fixed frequency divider 52 and the multiplication Nhm for extraction of the harmonic mixer 54 and the low-pass filter 56 are appropriately obtained. If it is determined (for example, if the division ratio Nid2 is 2 and the multiplication multiplication Nhm for extraction is 3), the second term "Nhm / Nid2" on the right side of the equation (4) or the equation (5) should not be an integer. can do. As a result, injection pulling can be avoided. The details are described in, for example, the above-mentioned document A.
  • FIG. 3 is an explanatory diagram showing an example of the analysis result when the conventional fractional phase-locked loop 820 shown in FIG. 15 is used
  • FIG. 4 is a phase-locked loop of the first embodiment shown in FIG. It is explanatory drawing which shows an example of the analysis result when the apparatus 20 (fractional phase-locked loop 40) is used.
  • the frequency Fref of the first reference signal from the oscillator 12 is 30 MHz
  • the frequency division ratio Nid1 of the fixed frequency divider 30 is 74
  • the variable frequency divider 50 As analysis conditions, for the phase-locked loop device 20 of FIG. 1, the frequency Fref of the first reference signal from the oscillator 12 is 30 MHz, the frequency division ratio Nid1 of the fixed frequency divider 30 is 74, and the variable frequency divider 50.
  • the desired value of the frequency division ratio Nfd was 32.029
  • the frequency division ratio Nid2 of the fixed frequency divider 52 was 2
  • the multiplication factor Nhm for extraction of the harmonic mixer 54 and the low-pass filter 56 was 3.
  • the frequency Fref of the reference signal from the oscillator 812 was set to 69.31 MHz
  • the desired value of the division ratio Nfd of the variable frequency divider 830 was set to 32.029.
  • the reason why the frequency Fref of the reference signal of the conventional example is set to 69.31 MHz (non-integer) is that the desired value of the frequency division ratio Nfd of the variable frequency dividers 50 and 830 is the same in the first embodiment and the conventional example.
  • the input frequencies of the fractional phase-locked loops 40 and 820 (in the first embodiment, the frequency Fit of the second reference signal from the inverter phase-locked loop 21 and in the conventional example, the frequency Ref of the reference signal from the oscillator 812). ) are the same.
  • the horizontal axis is the amount of offset from the desired value of the frequency fout of the final output signal (see equation (5)), and the vertical axis is the phase noise level.
  • a phase noise of about ⁇ 42 dBc appears.
  • a phase noise of about ⁇ 72 dBc appears. Therefore, it can be seen that in the first embodiment, the phase noise can be improved by about 30 dBc as compared with the comparative example.
  • the phase detector 42, the charge pump 44, the loop filter 46, the voltage controlled oscillator 48, the variable divider 50, and the fixed divider 50 are included.
  • a 52, a harmonic mixer 54, and a low-pass filter 56 are provided.
  • the variable frequency divider 50 divides the second reference signal from the integer phase-locked loop 21 by the variable frequency division ratio Nfd and outputs it to the phase detector 42.
  • the fixed frequency divider 52 divides the second reference signal from the integer phase-locked loop 21 by a fixed frequency division ratio Nid2 and outputs it to the harmonic mixer 54.
  • the harmonic mixer 54 generates a signal including a frequency component of each difference between the frequency Fout of the signal from the voltage controlled oscillator 48 and each multiplication of the frequency Fid2 of the signal from the fixed frequency divider 52.
  • the low-pass filter 56 extracts low-frequency components from the signal from the harmonic mixer 54.
  • FIG. 5 is a configuration diagram showing an outline of the configuration of the phase-locked loop device 120 of the second embodiment.
  • the phase-locked loop device 120 of the second embodiment is the first shown in FIG. 1, except that the variable frequency divider 50 of the fractional phase-locked loop 40 is replaced with the variable frequency divider 150 of the fractional phase-locked loop 140. It is the same as the phase-locked loop device 20 of the embodiment. Therefore, among the phase-locked loop devices 120 of the second embodiment, the same configurations as those of the phase-locked loop device 20 of the first embodiment are designated by the same reference numerals, and detailed description thereof will be omitted.
  • variable frequency divider 150 divides the signal from the voltage controlled oscillator 48 by the variable frequency division ratio Nfd2 and outputs it to the phase detector 42. Therefore, the frequency Ffd2 of the signal from the variable frequency divider 150 becomes the frequency (Fout / Nfd2).
  • the relationship between the frequency Fit of the second reference signal from the integer phase-locked loop 21 and the frequency Fout of the final output signal output to the output unit 14 is determined. It can be expressed as in equation (7).
  • the frequency division ratio Nid1 of the fixed frequency divider 30, the desired value of the frequency division ratio Nfd2 of the variable frequency divider 150, and the frequency division ratio Nid2 of the fixed frequency divider 52 are the final output signals. It is appropriately set based on the desired value of the frequency Fout of.
  • FIG. 6 is an explanatory diagram showing a linear model of the fractional phase-locked loop 140 included in the phase-locked loop device 120 of the second embodiment.
  • the part related to the variable frequency divider 50 (“ ⁇ Nfd” and the input source) is replaced with the part related to the variable frequency divider 150 (“ ⁇ Nfd2” and the input source). Except for, it is the same as the linear model of the fractional phase-locked loop 40 of FIG.
  • the definition is as shown in the equation (8)
  • the final output signal ⁇ out output to the output unit 14 can be expressed as the equation (9).
  • the variable frequency divider 50 when the signal from the voltage controlled oscillator 48 is input to the variable frequency divider 150, the variable frequency divider 50 is connected to the variable frequency divider 50 as in the first embodiment, and the second from the inter-counter phase-locked loop 21. 2 Compared to the one to which the reference signal is input, the following effects are obtained. Generally, in the fractional phase-locked loops 40 and 140, the phase noise appearing in the final output signal ⁇ out can be reduced by increasing the variable division ratios Nfd and Nfd2 of the variable dividers 50 and 150.
  • variable division ratios Nfd and Nfd2 are set to 5.25 and the variable division ratios Nfd and Nfd2 are set to 5 or 6, the variable division ratios Nfd and Nfd2 are about 20% in each cycle of the signal.
  • the desired values are 50.25 and the variable division ratios Nfd and Nfd2 are 50 or 51, the variable division ratios Nfd and Nfd2 are only about 2% in each cycle of the signal. ..
  • in order to increase the variable division ratio Nfd of the variable frequency divider 50 it is necessary to increase the frequency Fit of the second reference signal ⁇ int from the integer phase-locked loop 21, but the second reference.
  • the power consumption of the integer phase-locked loop 21 becomes large.
  • the inventors of the second embodiment In the phase-locked loop loop device 120, it was confirmed that the frequency Fit of the second reference signal ⁇ int from the inverter phase-locked loop circuit 21 can be set to about two-thirds or less of that of the phase-locked loop loop device 20 of the first embodiment.
  • the fractional phase-locked loop 140 included in the phase-locked loop device 120 of the second embodiment described above includes a variable frequency divider 150 instead of the variable divider 50 of the fractional phase-locked loop 40 of the first embodiment.
  • the variable frequency divider 150 divides the signal from the voltage controlled oscillator 48 by the variable frequency dividing ratio Nfd2 and outputs it to the phase detector 42.
  • Nfd2 variable frequency dividing ratio
  • the power consumption of the integrated phase-locked loop 21 can be suppressed as compared with the phase-locked loop device 20 of the first embodiment.
  • the fractional spar in addition to reducing the phase noise in the final output signal ⁇ out, the fractional spar can also be reduced as in the fractional phase-locked loop 40 of the first embodiment. it can.
  • FIG. 7 is a configuration diagram showing an outline of the configuration of the phase-locked loop device 120B of the third embodiment.
  • the phase-locked loop device 120B of the third embodiment is the same as the phase-locked loop device 120 of the second embodiment shown in FIG. 5, except that the fractional phase-locked loop circuit 140 is replaced with the fractional phase-locked loop circuit 140B. is there.
  • the fractional phase-locked loop 140B of the third embodiment is the same as the fractional phase-locked loop 140 of the second embodiment except that the integer phase-locked loop 158 is added. Therefore, among the phase-locked loop devices 120B of the third embodiment, the same configurations as those of the phase-locked loop device 120 of the second embodiment are designated by the same reference numerals, and detailed description thereof will be omitted.
  • the integer phase-locked loop 158 is configured in the same manner as the integer phase-locked loop 21, and includes a phase detector, a charge pump, a loop filter, a voltage controlled oscillator, and a fixed frequency divider (all of them). Not shown).
  • the integer phase-locked loop 158 multiplies the frequency Flpf of the signal from the low-pass filter 56 and outputs it to the phase detector 42 as a signal of frequency Fit2.
  • the phase detector 42 compares the signal from the variable frequency divider 150 with the signal from the indicator phase-locked loop 158, and outputs a signal corresponding to the phase difference.
  • the relationship between the frequency Fit of the second reference signal from the integer phase-locked loop 21 and the frequency Fout of the final output signal output to the output unit 14 is determined. It can be expressed as in equation (10).
  • the multiplication ratio Nint of the circuit 158 that is, the frequency Flpf of the signal input to the inter-counter phase-locked loop 158 (the signal output from the low-pass filter 56) and the frequency Fint2 of the signal output from the inter-counter phase-locked loop 158.
  • the relationship (Fint2 / Flpf) is appropriately set based on the desired value of the frequency Fout of the final output signal.
  • FIG. 8 is an explanatory diagram showing a linear model of the fractional phase-locked loop 140B included in the phase-locked loop device 120B of the third embodiment.
  • the linear model of the fractional phase-locked loop 140B of the third embodiment of FIG. 8 is the second embodiment of FIG. 6 except that the transfer function (Nint ⁇ Gint (s)) of the integer phase-locked loop 158 is added. It is the same as the linear model of the example fractional phase-locked loop 140. Therefore, the difference between the linear model of the fractional phase-locked loop 140 of the third embodiment and the linear model of the fractional phase-locked loop 140 of the second embodiment will be described. With reference to FIG.
  • the final output signal ⁇ out output to the output unit 14 can be expressed as the equation (12).
  • the Laplace operator s is sufficiently small, that is, when the value Hol (s) is sufficiently large and is within the band of the value Gint (s)
  • the phase noise ⁇ n, div is large. It can be seen that it is reduced to about 1 / Nint and appears in the final output signal ⁇ out. Therefore, it can be said that it is possible to more sufficiently avoid the phase noises ⁇ n and div being greatly amplified and appearing in the final output signal ⁇ out.
  • phase noise appearing in the final output signal ⁇ out of the fractional phase-locked loop 140B of the third embodiment is simply Nint with respect to the phase noise appearing in the final output signal ⁇ out of the fractional phase-locked loop 140 of the second embodiment. It does not mean that it becomes one of. The reason for this will be described below.
  • the signal from the low pass filter 56 (the signal of frequency Flpf) is input to the phase detector 42, whereas the fractional phase of the third embodiment is input.
  • a signal (a signal of frequency Flpf ⁇ Nint) from the inverter phase-locked loop 158 is input to the phase detector 42.
  • the variable frequency divider of the fractional phase-locked loop 140B of the third embodiment is used. It is necessary to multiply the desired value of the frequency Ffd2 of the signal from 150 by Nint with respect to the desired value of the frequency Ffd2 of the signal from the variable frequency divider 150 of the fractional phase-locked loop 140 of the second embodiment.
  • the desired value of the variable division ratio Nfd2 of the variable frequency divider 150 of the third embodiment is set to the desired value of the variable division ratio Nfd2 of the variable frequency divider 150 of the second embodiment by Nint. Must be 1.
  • the third embodiment is performed. It is necessary to set the desired value of the variable division ratio Nfd2 of the variable frequency divider 150 of the example to 5.023.
  • the variable frequency division ratio Nfd2 is set to 50 or 51
  • the variable frequency division ratio Nfd2 is 5 or It should be 6.
  • phase noise appearing in the final output signal ⁇ out of the fractional phase-locked loop 140B of the third embodiment is simply the phase noise appearing in the final output signal ⁇ out of the fractional phase-locked loop 140 of the second embodiment. It is not 1 / Nint.
  • FIG. 9 is an explanatory diagram of the fractional phase-locked loop 140 of the second embodiment
  • FIG. 10 is an explanatory diagram of the fractional phase-locked loop 140B of the third embodiment.
  • the figure on the left side is an explanatory view showing an example of the frequency characteristics of the phase noise ⁇ n, div, and the center figure shows the output of the variable frequency divider 150 as an input and the output unit 14 as an input.
  • the first predetermined circuit which became an output
  • the figure on the right side is an example of the frequency characteristic of the phase of the phase noise included in the final output signal.
  • “Fbw” in FIGS. 9 and 10 is the bandwidth of the first predetermined circuit in the fractional phase-locked loops 140 and 140B. In FIGS. 9 and 10, the bandwidths Fbw of the first predetermined circuit in the fractional phase-locked loops 140 and 140B are the same.
  • “Flpf” in FIG. 9 is the frequency of the signal output from the low-pass filter 56 to the phase detector 42
  • FIG. 10 “Fint2” is the frequency of the signal output from the indicator phase-locked loop 158 to the phase detector 42. The frequency, that is, the frequency of Nint times the frequency Flpf.
  • variable frequency divider 150 of the fractional phase-locked loop 140B when the frequency Fout of the final output signal is the same, the variable frequency divider 150 of the fractional phase-locked loop 140B This is because it is necessary to multiply the desired value of the frequency Ffd2 of the signal from Ffd2 by Nint with respect to the desired value of the frequency Ffd2 of the signal from the variable frequency divider 150 of the fractional phase-locked loop 140.
  • the phase noise ⁇ n div spreads to the higher frequency side as compared with the fractional phase-locked loop 140, so that when the bandwidth Fbw of the first predetermined circuit is the same, the phase noise ⁇ n, It can be seen that the div is further reduced, that is, the phase noise appearing in the final output signal ⁇ out is smaller. From this, it is assumed that in the fractional phase-locked loop 140B, the phase noise appearing in the final output signal ⁇ out is smaller than that in the fractional phase-locked loop 140 even when the bandwidth Fbw of the first predetermined circuit is large to some extent.
  • FIG. 11 is an explanatory diagram when the bandwidth Fbw2 of the second predetermined circuit of the fractional phase-locked loop 140B is a relatively small value Fbwlo, and FIG.
  • FIGS. 11 and 12 are explanatory diagram of the bandwidth Fbw2 of the second predetermined circuit of the fractional phase-locked loop 140B. It is explanatory drawing when is a value Fbwhi larger than a value Fbwlo.
  • the figure on the left is an explanatory diagram showing an example of the frequency characteristics of the phase noises ⁇ n and vco
  • the figure in the center is an explanatory diagram showing an example of the frequency characteristics of the transfer function of the second predetermined circuit.
  • the figure on the right is an explanatory diagram showing an example of the frequency characteristics of the phase noise included in the final output signal ⁇ out. Comparing FIGS.
  • phase noises ⁇ n and vco are reduced as the bandwidth Fbw2 of the second predetermined circuit is widened, that is, the phase noises appearing in the final output signal ⁇ out are smaller. .. Then, if the bandwidth Fbw2 of the second predetermined circuit can be increased, the voltage controlled oscillator 48 having a slightly larger phase noise can be selected. As a result, as the voltage controlled oscillator 48, a voltage controlled oscillator with a small power consumption and an area can be used although the phase noises ⁇ n and vco are slightly large.
  • the fractional phase-locked loop 140B included in the phase-locked loop device 120B of the third embodiment described above includes an integer phase-locked loop 158 in addition to the configuration of the fractional phase-locked loop 140 of the second embodiment.
  • the integer phase-locked loop 158 multiplies the frequency Flpf of the signal from the low-pass filter 56 and outputs it to the phase detector 42 as a signal of frequency Fit2.
  • the phase detector 42 of the fractional phase-locked loop 140B compares the signal from the variable frequency divider 150 with the signal from the indicator phase-locked loop 158 and outputs a signal corresponding to the phase difference.
  • the phase noise appearing in the signal from the variable frequency divider 150 is greatly amplified and appears in the final output signal ⁇ out more sufficiently than in the phase-locked loop device 120B of the second embodiment. It can be avoided. Further, in the fractional phase-locked loop 140B of the third embodiment, in addition to reducing the phase noise in the final output signal ⁇ out, similarly to the fractional phase-locked loops 40 and 140 of the first embodiment and the second embodiment, Fractional spar can also be reduced.
  • FIG. 13 is a configuration diagram showing an outline of the configuration of the phase-locked loop device 20B of the fourth embodiment.
  • the phase-locked loop device 20B of the third embodiment is the same as the phase-locked loop device 20 of the first embodiment shown in FIG. 1, except that the fractional phase-locked loop circuit 40 is replaced with the fractional phase-locked loop circuit 40B. is there.
  • the fractional phase-locked loop 40B of the fourth embodiment is the same as the fractional phase-locked loop 40 of the first embodiment except that the integer phase-locked loop 58 is added. Therefore, among the phase-locked loop devices 20B of the fourth embodiment, the same configurations as those of the phase-locked loop device 20 of the first embodiment are designated by the same reference numerals, and detailed description thereof will be omitted.
  • the integrator phase-locked loop 58 is configured in the same manner as the integrator phase-locked loop 158 of the fractional phase-locked loop 140B of the third embodiment, and the frequency Flpf of the signal from the low-pass filter 56 is multiplied to obtain a signal of frequency Fit2. Is output to the phase detector 42.
  • the phase detector 42 compares the signal from the variable frequency divider 50 with the signal from the indicator phase-locked loop 58, and outputs a signal corresponding to the phase difference.
  • the relationship between the frequency Fit of the second reference signal from the integer phase-locked loop 21 and the frequency Fout of the final output signal output to the output unit 14 is determined. It can be expressed as in equation (13).
  • the multiplication ratio Nint of the circuit 58 that is, the frequency Flpf of the signal input to the intercounter phase-locked loop 58 (the signal output from the low-pass filter 56) and the frequency Fint2 of the signal output from the intercounter phase-locked loop 58.
  • the relationship (Fint2 / Flpf) is appropriately set based on the desired value of the frequency Fout of the final output signal.
  • FIG. 14 is an explanatory diagram showing a linear model of the fractional phase-locked loop 40B included in the phase-locked loop device 20B of the fourth embodiment.
  • the linear model of the fractional phase-locked loop 40B of the fourth embodiment of FIG. 14 is the first embodiment of FIG. 2 except that the transfer function (Nint ⁇ Gint (s)) of the integral phase-locked loop 58 is added. It is the same as the linear model of the fractional phase-locked loop 40 of. Therefore, the difference between the linear model of the fractional phase-locked loop 40B of the fourth embodiment and the linear model of the fractional phase-locked loop 40 of the first embodiment will be described. With reference to FIG.
  • the final output signal ⁇ out output to the output unit 14 can be expressed as the equation (15).
  • the Laplace operator s is sufficiently small, that is, when the value Hol (s) is sufficiently large and is within the band of the value Gint (s)
  • the phase noise ⁇ n, div is large. It can be seen that it is reduced to about 1 / Nint and appears in the final output signal ⁇ out. Therefore, it can be said that it is possible to more sufficiently avoid the phase noises ⁇ n and div being greatly amplified and appearing in the final output signal ⁇ out.
  • fractional phase-locked loop 40B of the fourth embodiment has the same effect as that of the fractional phase-locked loop 140B of the third embodiment described with reference to FIGS. 9 to 12.
  • the fractional phase-locked loop 40B included in the phase-locked loop device 20B of the fourth embodiment described above includes an integer phase-locked loop 58 in addition to the configuration of the fractional phase-locked loop 40 of the first embodiment.
  • the integer phase-locked loop 58 multiplies the frequency Flpf of the signal from the low-pass filter 56 and outputs it to the phase detector 42 as a signal of frequency Fit2.
  • the phase detector 42 of the fractional phase-locked loop 40B compares the signal from the variable frequency divider 50 with the signal from the indicator phase-locked loop 58 and outputs a signal corresponding to the phase difference.
  • the phase noise appearing in the signal from the variable frequency divider 50 is greatly amplified and appears in the final output signal ⁇ out more sufficiently than the phase-locked loop device 20B of the first embodiment. It can be avoided. Further, in the fractional phase-locked loop 40B of the fourth embodiment, in addition to reducing the phase noise in the final output signal ⁇ out, the fractional phase-locked loop 40 of the first embodiment, the second embodiment, and the third embodiment, Similar to 140 and 140B, the fractional spar can be reduced.
  • the second reference signal from the integer phase-locked loop 21 has a fixed frequency division ratio.
  • a fixed frequency divider 52 that divides the frequency with Nid2 and outputs the frequency to the harmonic mixer 54 is provided.
  • the second reference signal from the integer phase-locked loop 21 may be directly input to the harmonic mixer 54 without the fixed frequency divider 52.
  • phase-locked loop circuit 21 connected to the oscillator 12 and the inverter phase
  • the fractional phase-locked loop 40 may be connected to the oscillator 12 and the output unit 14 without the integer phase-locked loop 21.
  • the oscillator 12 instead of the crystal oscillator that oscillates a signal having a frequency of about 20 MHz to 100 MHz as described above, an oscillator that oscillates a signal having a frequency of about several hundred MHz to 1 GHz is used. preferable.
  • the phase detector 42, the charge pump 44, the loop filter 46, and the voltage controlled oscillator 48 correspond to the "first frequency adjusting unit", and the variable frequency divider 50 or the variable frequency divider 50 or the variable frequency divider 40.
  • the device 150 corresponds to the "variable frequency divider”
  • the harmonic mixer 54 and the low-pass filter 56 correspond to the "second frequency adjusting unit”.
  • the fixed frequency divider 52 corresponds to the “fixed frequency divider”.
  • the invention described in the column of the means for solving the problem in the examples is carried out. Since it is an example for specifically explaining the form for solving the problem, the elements of the invention described in the column of means for solving the problem are not limited. That is, the interpretation of the invention described in the column of means for solving the problem should be performed based on the description in the column, and the examples are the inventions described in the column of means for solving the problem. It is just a concrete example.
  • the present invention can be used in the manufacturing industry of fractional phase-locked loops and phase-locked loop devices.

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Abstract

La présente invention concerne une boucle à verrouillage de phase fractionnelle qui multiplie la fréquence d'un signal de référence par un nombre non entier et délivre un signal résultant à une unité de sortie, comprenant : une première unité de réglage de fréquence qui commande la fréquence d'un signal à délivrer à l'unité de sortie, sur la base d'une différence de phase entre deux signaux d'entrée; un diviseur de fréquence variable qui divise la fréquence du signal de référence ou le signal provenant de la première unité de réglage de fréquence par un rapport de division variable, et délivre un signal résultant à la première unité de réglage de fréquence; et une seconde unité de réglage de fréquence qui délivre en sortie, à la première unité de réglage de fréquence, un signal d'une seconde fréquence associée sur la base d'une différence entre la fréquence du signal provenant de la première unité de réglage de fréquence et une première fréquence associée sur la base de la fréquence du signal de référence.
PCT/JP2020/026776 2019-10-23 2020-07-09 Boucle à verrouillage de phase fractionnelle et dispositif à boucle à verrouillage de phase WO2021079563A1 (fr)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04371024A (ja) * 1991-06-19 1992-12-24 Sony Corp Ｐｌｌ周波数シンセサイザ
JPH07122999A (ja) * 1993-10-21 1995-05-12 Murata Mfg Co Ltd Ｐｌｌ回路
JP2006311489A (ja) * 2005-03-29 2006-11-09 Renesas Technology Corp 位相同期ループ回路、オフセットｐｌｌ送信機、通信用高周波集積回路及び無線通信システム
JP2016006950A (ja) * 2014-05-26 2016-01-14 三菱電機株式会社 周波数シンセサイザ

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04371024A (ja) * 1991-06-19 1992-12-24 Sony Corp Ｐｌｌ周波数シンセサイザ
JPH07122999A (ja) * 1993-10-21 1995-05-12 Murata Mfg Co Ltd Ｐｌｌ回路
JP2006311489A (ja) * 2005-03-29 2006-11-09 Renesas Technology Corp 位相同期ループ回路、オフセットｐｌｌ送信機、通信用高周波集積回路及び無線通信システム
JP2016006950A (ja) * 2014-05-26 2016-01-14 三菱電機株式会社 周波数シンセサイザ

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