WO2021079563A1

WO2021079563A1 - Fractional phase-locked loop and phase-locked loop device

Info

Publication number: WO2021079563A1
Application number: PCT/JP2020/026776
Authority: WO
Inventors: 飯塚　哲也; 祖楽徐; 将長田
Original assignee: 国立大学法人東京大学
Priority date: 2019-10-23
Filing date: 2020-07-09
Publication date: 2021-04-29

Abstract

A fractional phase-locked loop that multiplies the frequency of a reference signal by a non-integer and outputs a resultant signal to an output unit, comprises: a first frequency adjusting unit which controls the frequency of a signal to be output to the output unit, on the basis of a phase difference between two input signals; a variable frequency divider which divides the frequency of the reference signal or the signal from the first frequency adjusting unit by a variable division ratio, and outputs a resultant signal to the first frequency adjusting unit; and a second frequency adjusting unit which outputs, to the first frequency adjusting unit, a signal of a second related frequency based on a difference between the frequency of the signal from the first frequency adjusting unit and a first related frequency based on the frequency of the reference signal.

Description

Fractional phase-locked loop and phase-locked loop device

The present invention relates to a fractional phase-locked loop and a phase-locked loop device.

Conventionally, as a fractional phase-locked loop (PLL: Phase Locked Loop) of this type, one that outputs the frequency of a reference signal multiplied by a non-integer has been proposed (see, for example, Patent Document 1 and Non-Patent Document 1). .. As shown in FIG. 15, in these fractional phase-locked loops 820, a phase detector (PFD: Phase Frequency Detector) 822, a charge pump (CP: Charge Pump) 824, and a loop filter (LF: Loop Filter) 626 are used. , A voltage controlled oscillator (VCO: Voltage Controlled Oscillator) 828 and a variable divider (variable DIV: Divider) 830 are provided. Here, the phase detector 822 compares the reference signal from the oscillator 812 with the reference signal from the variable frequency divider 830 and outputs a signal corresponding to the phase difference. The charge pump 824 converts the signal from the phase detector 822 into an electric current. The loop filter 826 removes the high frequency component of the current from the charge pump 824 and converts it into the control voltage of the voltage controlled oscillator 828. The voltage controlled oscillator 828 controls the frequency of the output signal based on the control voltage from the loop filter 826. The variable frequency divider 830 divides the signal from the voltage controlled oscillator 828 by a variable frequency division ratio and outputs it to the phase detector 822 as a reference signal. In such a fractional phase-locked loop 820, the frequency Fout of the signal from the voltage controlled oscillator 828 is ideally a desired value (non-integer) of the frequency division ratio of the variable frequency divider 830 to the frequency Fref of the reference signal from the oscillator 812. ) Is multiplied.

Japanese Unexamined Patent Publication No. 2006-303554

In the above-mentioned fractional phase-locked loop 820, for example, when it is desired to make the frequency Fout of the signal from the voltage controlled oscillator 828 39.25 times the frequency Fref of the reference signal from the oscillator 812, the division ratio of the variable frequency divider 830 is set. It should be 39 at a rate of 25% and 40 at a rate of 75%. Therefore, a phase error occurs in the signal from the variable frequency divider 830 due to the deviation between the actual value (39 or 40) and the desired value (39.25) of the frequency division ratio of the variable frequency divider 830, which is caused by this. Phase noise appears in the final output signal of the fractional phase-locked loop 820. Further, due to the non-linearity of the components such as PFD822 and LPF824, noise at a specific frequency called Fractional Spur also appears in the final output signal as the output of the variable divider 830 fluctuates.

FIG. 16 is an explanatory diagram showing a linear model of the above-mentioned fractional phase-locked loop 820. In the figure, “Kpd”, “F (s)”, “Kvco / s”, and “÷ Nfd” are the phase detector 822, the charge pump 824, the loop filter 828, the voltage controlled oscillator 828, and the variable divider 830, respectively. Is expressed by a transfer function. “Φref” is a reference signal. “Φout” is an output signal that is finally output. “In, cp” is phase noise due to disturbance of the current from the charge pump 824. “Φn, vco” is the phase noise generated in the voltage controlled oscillator 828. “Φn, div” is the phase noise that appears in the signal from the variable divider 830. With reference to FIG. 16, if defined as in equation (1), the output signal φout can be expressed as in equation (2). From this equation (2), it can be seen that the phase noises φn and div are amplified by approximately Nfd times (for example, approximately 39.25 times) and appear in the output signal φout. Therefore, it is required to devise a fractional phase-locked loop that can avoid the phase noise φn and div being greatly amplified.

The main object of the fractional phase-locked loop and the phase-locked loop device of the present invention is to provide a configuration capable of avoiding a large amplification of phase noise appearing in a signal from a variable frequency divider.

The fractional phase-locked loop and the phase-locked loop device of the present invention have adopted the following means in order to achieve the above-mentioned main object.

The fractional phase-locked loop of the present invention
A fractional phase-locked loop that multiplies the frequency of the reference signal by a non-integer and outputs it to the output section.
A first frequency adjusting unit that controls the frequency of the signal output to the output unit based on the phase difference between the two input signals.
A variable frequency divider that divides the frequency of the reference signal or the signal from the first frequency adjustment unit by a variable division ratio and outputs it to the first frequency adjustment unit.
A second that outputs a signal of the second related frequency of the difference between the frequency of the signal from the first frequency adjusting unit and the first related frequency based on the frequency of the reference signal or the multiplication of the difference to the first frequency adjusting unit. Frequency control unit and
The gist is to prepare.

In the fractional phase synchronization circuit of the present invention, the first frequency adjusting unit that controls the frequency of the signal output to the output unit based on the phase difference between the two input signals, and the reference signal or the signal from the first frequency adjusting unit The difference between the variable frequency divider that divides the frequency by the variable frequency division ratio and outputs it to the first frequency control unit, and the first related frequency based on the frequency of the signal from the first frequency control unit and the frequency of the reference signal. It is provided with a second frequency adjusting unit that outputs a signal of the second related frequency obtained by multiplying the difference to the first frequency adjusting unit. With such a configuration, it is possible to prevent the phase noise appearing in the signal from the variable divider from being greatly amplified. The inventors confirmed this by the linear model of the fractional phase-locked loop of the present invention.

In the fractional phase synchronization circuit of the present invention, the second frequency adjusting unit includes the frequency of the signal from the first frequency adjusting unit and the frequency obtained by multiplying the frequency of the reference signal or the frequency of the related signal based on the reference signal. It may have a harmonic mixer that generates a signal including the frequency component of each difference of the above, and a low-pass filter that extracts and outputs a frequency component of a predetermined frequency or less from each frequency component included in the signal from the harmonic mixer. .. In this case, the low-pass filter may extract and output only the minimum frequency component from each of the frequency components.

In the fractional phase-locked loop of the present invention, the second frequency adjusting unit may further include an integer phase-locked loop that multiplies and outputs the frequency of the signal from the low-pass filter. In this way, it is possible to more sufficiently avoid that the phase noise appearing in the signal from the variable frequency divider is greatly amplified. The inventors confirmed this by a linear model of the fractional phase-locked loop of the present invention in this embodiment.

The fractional phase-locked loop of the present invention may include a fixed frequency divider that divides the reference signal by a fixed frequency division ratio and outputs it to the second frequency adjustment unit. In this way, injection pulling can be avoided. The details are described in, for example, Document A.

Reference A: D Yang et al., “A Calibration Free Triple Loop Bang Bang PLL Achieving 131fsrms Jitter and 70dBc Fractional Spurs”, ISSCC, Feb. 2019

In the fractional phase synchronization circuit of the present invention, the first frequency adjusting unit compares two input signals and outputs a signal corresponding to the phase difference, and converts a signal from the phase detector into a current. Charge pump, a loop filter that removes frequency components higher than a predetermined frequency of the current from the charge pump and converts it into a voltage, and a frequency of a signal output to the output unit based on the voltage from the loop filter. It may have a voltage controlled oscillator for controlling the above.

The phase-locked loop loop device of the present invention is the fractional phase-locked loop of the present invention of any of the above-described aspects, and a second inserter that multiplies the frequency of the initial reference signal and outputs it as the reference signal to the fractional phase-locked loop. The gist is to provide a phase-locked loop.

Since the phase-locked loop device of the present invention includes the fractional phase-locked loop of the present invention in any of the above aspects, the effect exerted by the fractional phase-locked loop of the present invention, for example, appears in the signal from the variable frequency divider. It is possible to obtain the same effect as the effect of avoiding the large amplification of the phase noise.

In the phase-locked loop device of the present invention, the variable frequency divider may divide the frequency of the signal from the first frequency control unit by a variable division ratio and output it to the first frequency control unit. .. In this way, in order to increase the input frequency of the variable frequency divider, it is not necessary to increase the frequency of the reference signal from the integer phase-locked loop, so that the power consumption of the integer phase-locked loop can be suppressed. ..

It is a block diagram which shows the outline of the structure of the phase-locked loop device 20 as the 1st Example of this invention. It is explanatory drawing which shows the linear model of the fractional phase-locked loop 40 which the phase-locked loop apparatus 20 of 1st Example includes. It is explanatory drawing which shows an example of the analysis result at the time of using the fractional phase-locked loop 820 of the conventional example. It is explanatory drawing which shows an example of the analysis result at the time of using the phase-locked loop apparatus 20 (fractional phase-locked loop 40) of 1st Example. It is a block diagram which shows the outline of the structure of the phase-locked loop device 120 of 2nd Example. It is explanatory drawing which shows the linear model of the fractional phase-locked loop 140 included in the phase-locked loop apparatus 120 of 2nd Example. It is a block diagram which shows the outline of the structure of the phase-locked loop device 120B of 3rd Example. It is explanatory drawing which shows the linear model of the fractional phase-locked loop 140B included in the phase-locked loop apparatus 120B of 3rd Example. It is explanatory drawing about the fractional phase-locked loop 140 of 2nd Example. It is explanatory drawing about the fractional phase-locked loop 140B of 3rd Example. It is explanatory drawing when the bandwidth Fbw of a fractional phase-locked loop 140B is a value Fbw1 which is relatively small. It is explanatory drawing when the bandwidth Fbw of a fractional phase-locked loop 140B is a value Fbw2 which is larger than a value Fbw1. It is a block diagram which shows the outline of the structure of the phase-locked loop device 20B of 4th Example. It is explanatory drawing which shows the linear model of the fractional phase-locked loop 40B included in the phase-locked loop apparatus 20B of 4th Example. It is a block diagram which shows the outline of the structure of the fractional phase-locked loop 820 of the conventional example. It is explanatory drawing which shows the linear model of the fractional phase-locked loop 820 of the conventional example.

Next, a mode for carrying out the present invention will be described with reference to examples.

FIG. 1 is a configuration diagram showing an outline of the configuration of the phase-locked loop device 20 as the first embodiment of the present invention. As shown in the figure, the phase-locked loop loop device 20 of the first embodiment includes an integer phase-locked loop 21 connected to the oscillator 12, and a fractional phase-locked loop circuit 21 connected to the integral phase-locked loop 21 and the output unit 14. 40 and. Here, as the oscillator 12, for example, a crystal oscillator that oscillates a signal having a frequency of about 20 MHz to 100 MHz is used.

The injector phase-locked loop 21 is configured as a circuit that multiplies the frequency Fref of the first reference signal from the oscillator 12 and outputs it as a second reference signal (frequency Fit signal) to the fractional phase-locked loop 40. It includes a detector (PFD) 22, a charge pump (CP) 24, a loop filter (LF) 26, a voltage controlled oscillator (VCO) 28, and a fixed frequency divider (fixed DIV) 30.

The phase detector 22 compares the first reference signal from the oscillator 12 with the signal from the fixed frequency divider 30 and outputs a signal corresponding to the phase difference. The charge pump 24 converts the signal from the phase detector 22 into an electric current. The phase detector 22 and the charge pump 24 are used to match the frequency Fref of the first reference signal from the oscillator 12 with the frequency Fid1 of the signal from the fixed frequency divider 30.

The loop filter 26 removes high frequency components (frequency components higher than the predetermined frequency F0) of the current from the charge pump 24 and converts them into the control voltage of the voltage controlled oscillator 28. The voltage controlled oscillator 28 controls the frequency Fit of the second reference signal output to the fractional phase-locked loop 40 based on the control voltage from the loop filter 26. The fixed frequency divider 30 divides the signal from the voltage controlled oscillator 28 by a fixed frequency division ratio Nid1 and outputs the signal to the phase detector 22. Therefore, the frequency Fid1 of the signal from the fixed frequency divider 30 becomes the frequency (Fint / Nid1).

In the integrated phase-locked loop 21 configured in this way, the relationship between the frequency Fref of the first reference signal from the oscillator 12 and the frequency Fit of the second reference signal output to the fractional phase-locked loop 40 is as shown in equation (3). Can be expressed in.

Fint = Fref Fid1 (3)

The fractional phase-locked loop 40 is configured as a circuit that multiplies the frequency Fit of the second reference signal from the integer phase-locked loop 21 by a non-integral and outputs the final output signal (frequency Fout signal) to the output unit 14. , Phase detector (PFD) 42, charge pump (CP) 44, loop filter (LF) 46, voltage controlled oscillator (VCO) 48, variable frequency divider (variable DIV) 50, fixed frequency divider It includes a (fixed DIV) 52, a harmonic mixer (HM) 54, and a low-pass filter (LPF) 56.

The phase detector 42 compares the signal from the variable frequency divider 50 with the signal from the low-pass filter 56, and outputs a signal corresponding to the phase difference. The charge pump 44 converts the signal from the phase detector 42 into an electric current. The phase detector 42 and the charge pump 44 are used to match the frequency Ffd of the signal from the variable frequency divider 50 with the frequency Flpf of the signal from the lowpass filter 56.

The loop filter 46 removes high frequency components (frequency components higher than the predetermined frequency F1) of the current from the charge pump 44 and converts them into the control voltage of the voltage controlled oscillator 48. The predetermined frequency F1 may be the same frequency as the predetermined frequency F0, or may be a different frequency. The voltage controlled oscillator 48 controls the frequency Fout of the final output signal output to the output unit 14 based on the control voltage from the loop filter 46.

The variable frequency divider 50 includes, for example, a multi-module divider (MMD: Multi-Modulus Divider) capable of changing the frequency division ratio, and a delta-sigma modulator (MMD: Multi-Modulus Divider) that controls the frequency division ratio using the multi-module divider. It is configured as a well-known variable frequency divider with DSM: Delta-Sigma Modulator). The variable frequency divider 50 divides the second reference signal from the integer phase-locked loop 21 by a variable frequency division ratio Nfd and outputs it to the phase detector 42. Therefore, the frequency Ffd of the signal from the variable frequency divider 50 is the frequency (Fint / Nfd). In the variable frequency divider 50, for example, when the desired value of the variable frequency division ratio Nfd is 39.25, the variable frequency division ratio Nfd becomes 39 at a rate of 25% and 40 at a rate of 75%. Operate.

The fixed frequency divider 52 divides the second reference signal from the integer phase-locked loop 21 by a fixed frequency division ratio Nid2 and outputs it to the harmonic mixer 54. Therefore, the frequency Fid2 of the signal from the fixed frequency divider 52 becomes the frequency (Fint / Nid2).

The harmonic mixer 54 is configured by using a well-known sample hold circuit (SHC: Sample and Hold Circuit) or the like, and has a frequency Fout of a signal from a voltage controlled oscillator 48 and a frequency Fid2 of a signal from a fixed frequency divider 52 (SHC). = Fit / Nid2) Generates a signal containing the frequency component of each difference from the frequency of each multiplication (1x, 2x, ...). The low-pass filter 56 extracts a low frequency component (frequency component having a predetermined frequency F2 or less) from the signal from the harmonic mixer 54 and outputs it to the phase detector 42. Here, the predetermined frequency F2 is set so that only the minimum frequency component of each frequency component included in the signal from the harmonic mixer 54 is extracted in the first embodiment. Therefore, the frequency Flpf of the signal output from the low-pass filter 56 to the phase detector 42 is a multiplication (1x, 2) of the frequency Fout of the signal from the voltage control oscillator 48 and the frequency Fid2 of the signal from the fixed divider 52. It is the minimum frequency among the frequencies of each difference from the double, ...). Hereinafter, the multiplication (for example, 3 times) corresponding to the minimum frequency extracted by the low-pass filter 56 among the multiplications is referred to as "extraction multiplication Nhm". Then, the frequency Flpf of the signal output from the low-pass filter 56 to the phase detector 42 can be expressed as in the equation (4).

Flpf ＝ Fout－ (Nhm / Nid2) ・ Fint (4)

In the fractional phase-locked loop 40 of the first embodiment configured in this way, the relationship between the frequency Fit of the second reference signal from the integer phase-locked loop 21 and the frequency Fout of the final output signal output to the output unit 14 is determined. It can be expressed as in equation (5).

Fout ＝ Fint / Nfd ＋ (Nhm / Nid2) ・ Fint (5)

In the phase-locked loop device 20, the frequency division ratio Nid1 of the fixed frequency divider 30, the desired value of the frequency division ratio Nfd of the variable frequency divider 50, and the frequency division ratio Nid2 of the fixed frequency divider 52 are the final output signals. It is appropriately set based on the desired value of the frequency Fout of.

FIG. 2 is an explanatory diagram showing a linear model of the fractional phase-locked loop 40 included in the phase-locked loop device 20 of the first embodiment. In the figure, “Kpd”, “F (s)”, “Kvco / s”, “÷ Nfd”, and “÷ Nid2” are the phase detector 42, the charge pump 44, the loop filter 46, and the voltage controlled oscillator 48, respectively. The variable frequency divider 50 and the fixed frequency divider 52 are represented by a transfer function. “× Nhm” and the symbol for calculating the difference between the two represent the harmonic mixer 54 and the low-pass filter 56 as a transfer function. “Φint” is a second reference signal from the integer phase-locked loop 21. “Φout” is the final output signal output to the output unit 14. “In, cp” is phase noise due to disturbance of the current from the charge pump 44. “Φn, vco” is the phase noise generated in the voltage controlled oscillator 48. “Φn, div” is the phase noise that appears in the signal from the variable divider 50. With reference to FIG. 2, if defined as in the above equation (1), the final output signal φout output to the output unit 14 can be expressed as in the equation (6). In this equation (6), when the Laplace operator s is sufficiently small, that is, when the value Hol (s) is sufficiently large, the phase noises φn and div are not amplified and are finally (approximately 1 times). It can be seen that it appears in the output signal φout. Therefore, it can be said that it is possible to prevent the phase noises φn and div from being greatly amplified and appearing in the final output signal φout.

Further, in the first embodiment, since the fractional phase-locked loop 40 includes the fixed frequency divider 52, the division ratio Nid2 of the fixed frequency divider 52 and the multiplication Nhm for extraction of the harmonic mixer 54 and the low-pass filter 56 are appropriately obtained. If it is determined (for example, if the division ratio Nid2 is 2 and the multiplication multiplication Nhm for extraction is 3), the second term "Nhm / Nid2" on the right side of the equation (4) or the equation (5) should not be an integer. can do. As a result, injection pulling can be avoided. The details are described in, for example, the above-mentioned document A.

FIG. 3 is an explanatory diagram showing an example of the analysis result when the conventional fractional phase-locked loop 820 shown in FIG. 15 is used, and FIG. 4 is a phase-locked loop of the first embodiment shown in FIG. It is explanatory drawing which shows an example of the analysis result when the apparatus 20 (fractional phase-locked loop 40) is used. As analysis conditions, for the phase-locked loop device 20 of FIG. 1, the frequency Fref of the first reference signal from the oscillator 12 is 30 MHz, the frequency division ratio Nid1 of the fixed frequency divider 30 is 74, and the variable frequency divider 50. The desired value of the frequency division ratio Nfd was 32.029, the frequency division ratio Nid2 of the fixed frequency divider 52 was 2, and the multiplication factor Nhm for extraction of the harmonic mixer 54 and the low-pass filter 56 was 3. Regarding the fractional phase-locked loop 820 of FIG. 15, the frequency Fref of the reference signal from the oscillator 812 was set to 69.31 MHz, and the desired value of the division ratio Nfd of the variable frequency divider 830 was set to 32.029. The reason why the frequency Fref of the reference signal of the conventional example is set to 69.31 MHz (non-integer) is that the desired value of the frequency division ratio Nfd of the

variable frequency dividers

50 and 830 is the same in the first embodiment and the conventional example. The input frequencies of the fractional phase-locked loops 40 and 820 (in the first embodiment, the frequency Fit of the second reference signal from the inverter phase-locked loop 21 and in the conventional example, the frequency Ref of the reference signal from the oscillator 812). ) Are the same.

In FIGS. 3 and 4, the horizontal axis is the amount of offset from the desired value of the frequency fout of the final output signal (see equation (5)), and the vertical axis is the phase noise level. In the comparative example, as shown in FIG. 3, a phase noise of about −42 dBc appears. On the other hand, in the first embodiment, as shown in FIG. 4, a phase noise of about −72 dBc appears. Therefore, it can be seen that in the first embodiment, the phase noise can be improved by about 30 dBc as compared with the comparative example.

In the fractional phase-locked loop 40 included in the phase-locked loop device 20 of the first embodiment described above, the phase detector 42, the charge pump 44, the loop filter 46, the voltage controlled oscillator 48, the variable divider 50, and the fixed divider 50 are included. A 52, a harmonic mixer 54, and a low-pass filter 56 are provided. Here, the variable frequency divider 50 divides the second reference signal from the integer phase-locked loop 21 by the variable frequency division ratio Nfd and outputs it to the phase detector 42. The fixed frequency divider 52 divides the second reference signal from the integer phase-locked loop 21 by a fixed frequency division ratio Nid2 and outputs it to the harmonic mixer 54. The harmonic mixer 54 generates a signal including a frequency component of each difference between the frequency Fout of the signal from the voltage controlled oscillator 48 and each multiplication of the frequency Fid2 of the signal from the fixed frequency divider 52. The low-pass filter 56 extracts low-frequency components from the signal from the harmonic mixer 54. With such a configuration, it is possible to prevent the phase noise appearing in the signal from the variable divider 50 from being greatly amplified and appearing in the final output signal φout. Further, in addition to reducing the phase noise in the final output signal φout by the configuration of the fractional phase-locked loop 40 of the first embodiment, the variable component due to the non-linearity of the components such as PFD42 and LPF56. Noise at a specific frequency (so-called fractional spar) generated in the final output signal φout due to the output fluctuation of the peripheral device 50 can also be reduced.

FIG. 5 is a configuration diagram showing an outline of the configuration of the phase-locked loop device 120 of the second embodiment. The phase-locked loop device 120 of the second embodiment is the first shown in FIG. 1, except that the variable frequency divider 50 of the fractional phase-locked loop 40 is replaced with the variable frequency divider 150 of the fractional phase-locked loop 140. It is the same as the phase-locked loop device 20 of the embodiment. Therefore, among the phase-locked loop devices 120 of the second embodiment, the same configurations as those of the phase-locked loop device 20 of the first embodiment are designated by the same reference numerals, and detailed description thereof will be omitted.

The variable frequency divider 150 divides the signal from the voltage controlled oscillator 48 by the variable frequency division ratio Nfd2 and outputs it to the phase detector 42. Therefore, the frequency Ffd2 of the signal from the variable frequency divider 150 becomes the frequency (Fout / Nfd2).

In the fractional phase-locked loop 140 of the second embodiment configured in this way, the relationship between the frequency Fit of the second reference signal from the integer phase-locked loop 21 and the frequency Fout of the final output signal output to the output unit 14 is determined. It can be expressed as in equation (7).

Fout = (Nfd2 / (Nfd2-1)) ・ (Nhm / Nid2) ・ Fint (7)

In the phase-locked loop device 120, the frequency division ratio Nid1 of the fixed frequency divider 30, the desired value of the frequency division ratio Nfd2 of the variable frequency divider 150, and the frequency division ratio Nid2 of the fixed frequency divider 52 are the final output signals. It is appropriately set based on the desired value of the frequency Fout of.

FIG. 6 is an explanatory diagram showing a linear model of the fractional phase-locked loop 140 included in the phase-locked loop device 120 of the second embodiment. In the linear model of the fractional phase-locked loop 140 of FIG. 6, the part related to the variable frequency divider 50 (“÷ Nfd” and the input source) is replaced with the part related to the variable frequency divider 150 (“÷ Nfd2” and the input source). Except for, it is the same as the linear model of the fractional phase-locked loop 40 of FIG. With reference to FIG. 6, if the definition is as shown in the equation (8), the final output signal φout output to the output unit 14 can be expressed as the equation (9). In this equation (9), considering when the Laplace operator s is sufficiently small, that is, when the value Hol (s) is sufficiently large, the phase noises φn and div are amplified by Nfd2 / (Nfd2-1) times. It can be seen that it appears in the final output signal φout. Therefore, it can be said that it is possible to prevent the phase noises φn and div from being greatly amplified and appearing in the final output signal φout.

Further, in the second embodiment, when the signal from the voltage controlled oscillator 48 is input to the variable frequency divider 150, the variable frequency divider 50 is connected to the variable frequency divider 50 as in the first embodiment, and the second from the inter-counter phase-locked loop 21. 2 Compared to the one to which the reference signal is input, the following effects are obtained. Generally, in the fractional phase-locked

loops

40 and 140, the phase noise appearing in the final output signal φout can be reduced by increasing the variable division ratios Nfd and Nfd2 of the

variable dividers

50 and 150. This is because when the desired values of the variable division ratios Nfd and Nfd2 are set to 5.25 and the variable division ratios Nfd and Nfd2 are set to 5 or 6, the variable division ratios Nfd and Nfd2 are about 20% in each cycle of the signal. On the other hand, when the desired values are 50.25 and the variable division ratios Nfd and Nfd2 are 50 or 51, the variable division ratios Nfd and Nfd2 are only about 2% in each cycle of the signal. .. In the first embodiment, in order to increase the variable division ratio Nfd of the variable frequency divider 50, it is necessary to increase the frequency Fit of the second reference signal φint from the integer phase-locked loop 21, but the second reference. When the frequency Fit of the signal φint is increased, the power consumption of the integer phase-locked loop 21 becomes large. On the other hand, in the second embodiment, it is not necessary to increase the frequency Fit of the second reference signal φint in order to increase the input frequency of the variable frequency divider 150. As a result, the power consumption of the integer phase-locked loop 21 can be reduced. According to the analysis, when the phase-locked loop device 20 of the first embodiment and the phase-locked loop device 120 of the second embodiment have the same phase noise appearing in the final output signal φout, the inventors of the second embodiment In the phase-locked loop loop device 120, it was confirmed that the frequency Fit of the second reference signal φint from the inverter phase-locked loop circuit 21 can be set to about two-thirds or less of that of the phase-locked loop loop device 20 of the first embodiment.

The fractional phase-locked loop 140 included in the phase-locked loop device 120 of the second embodiment described above includes a variable frequency divider 150 instead of the variable divider 50 of the fractional phase-locked loop 40 of the first embodiment. Here, the variable frequency divider 150 divides the signal from the voltage controlled oscillator 48 by the variable frequency dividing ratio Nfd2 and outputs it to the phase detector 42. With such a configuration, it is possible to prevent the phase noise appearing in the signal from the variable frequency divider 150 from being greatly amplified and appearing in the final output signal φout, as in the phase-locked loop device 20 of the first embodiment. In addition to being able to do so, the power consumption of the integrated phase-locked loop 21 can be suppressed as compared with the phase-locked loop device 20 of the first embodiment. Further, in the fractional phase-locked loop 140 of the second embodiment, in addition to reducing the phase noise in the final output signal φout, the fractional spar can also be reduced as in the fractional phase-locked loop 40 of the first embodiment. it can.

FIG. 7 is a configuration diagram showing an outline of the configuration of the phase-locked loop device 120B of the third embodiment. The phase-locked loop device 120B of the third embodiment is the same as the phase-locked loop device 120 of the second embodiment shown in FIG. 5, except that the fractional phase-locked loop circuit 140 is replaced with the fractional phase-locked loop circuit 140B. is there. The fractional phase-locked loop 140B of the third embodiment is the same as the fractional phase-locked loop 140 of the second embodiment except that the integer phase-locked loop 158 is added. Therefore, among the phase-locked loop devices 120B of the third embodiment, the same configurations as those of the phase-locked loop device 120 of the second embodiment are designated by the same reference numerals, and detailed description thereof will be omitted.

The integer phase-locked loop 158 is configured in the same manner as the integer phase-locked loop 21, and includes a phase detector, a charge pump, a loop filter, a voltage controlled oscillator, and a fixed frequency divider (all of them). Not shown). The integer phase-locked loop 158 multiplies the frequency Flpf of the signal from the low-pass filter 56 and outputs it to the phase detector 42 as a signal of frequency Fit2. In the fractional phase-locked loop 140B, the phase detector 42 compares the signal from the variable frequency divider 150 with the signal from the indicator phase-locked loop 158, and outputs a signal corresponding to the phase difference.

In the fractional phase-locked loop 140B of the third embodiment configured in this way, the relationship between the frequency Fit of the second reference signal from the integer phase-locked loop 21 and the frequency Fout of the final output signal output to the output unit 14 is determined. It can be expressed as in equation (10).

Fout = (Nhm ・ Nfd2) / (Nhm ・ Nfd2-1) ・ (Nhm / Nid2) ・ Fint (10)

In the phase-locked loop device 120B, the frequency division ratio Nid1 of the fixed frequency divider 30, the desired value of the frequency division ratio Nfd2 of the variable frequency divider 150, the frequency division ratio Nid2 of the fixed frequency divider 52, and the indicator phase synchronization. The multiplication ratio Nint of the circuit 158, that is, the frequency Flpf of the signal input to the inter-counter phase-locked loop 158 (the signal output from the low-pass filter 56) and the frequency Fint2 of the signal output from the inter-counter phase-locked loop 158. The relationship (Fint2 / Flpf) is appropriately set based on the desired value of the frequency Fout of the final output signal.

FIG. 8 is an explanatory diagram showing a linear model of the fractional phase-locked loop 140B included in the phase-locked loop device 120B of the third embodiment. The linear model of the fractional phase-locked loop 140B of the third embodiment of FIG. 8 is the second embodiment of FIG. 6 except that the transfer function (Nint × Gint (s)) of the integer phase-locked loop 158 is added. It is the same as the linear model of the example fractional phase-locked loop 140. Therefore, the difference between the linear model of the fractional phase-locked loop 140 of the third embodiment and the linear model of the fractional phase-locked loop 140 of the second embodiment will be described. With reference to FIG. 8, if the definition is as shown in the equation (11), the final output signal φout output to the output unit 14 can be expressed as the equation (12). In this equation (12), when the Laplace operator s is sufficiently small, that is, when the value Hol (s) is sufficiently large and is within the band of the value Gint (s), the phase noise φn, div is large. It can be seen that it is reduced to about 1 / Nint and appears in the final output signal φout. Therefore, it can be said that it is possible to more sufficiently avoid the phase noises φn and div being greatly amplified and appearing in the final output signal φout.

However, the phase noise appearing in the final output signal φout of the fractional phase-locked loop 140B of the third embodiment is simply Nint with respect to the phase noise appearing in the final output signal φout of the fractional phase-locked loop 140 of the second embodiment. It does not mean that it becomes one of. The reason for this will be described below. As described above, in the fractional phase-locked loop 140B of the second embodiment, the signal from the low pass filter 56 (the signal of frequency Flpf) is input to the phase detector 42, whereas the fractional phase of the third embodiment is input. In the synchronous circuit 140B, a signal (a signal of frequency Flpf · Nint) from the inverter phase-locked loop 158 is input to the phase detector 42. Therefore, in the fractional phase-locked

loops

140 and 140B of the second embodiment and the third embodiment, when the frequency Fout of the final output signal φout is the same, the variable frequency divider of the fractional phase-locked loop 140B of the third embodiment is used. It is necessary to multiply the desired value of the frequency Ffd2 of the signal from 150 by Nint with respect to the desired value of the frequency Ffd2 of the signal from the variable frequency divider 150 of the fractional phase-locked loop 140 of the second embodiment. For that purpose, the desired value of the variable division ratio Nfd2 of the variable frequency divider 150 of the third embodiment is set to the desired value of the variable division ratio Nfd2 of the variable frequency divider 150 of the second embodiment by Nint. Must be 1. For example, when the desired value of the variable division ratio Nfd2 of the variable frequency divider 150 of the second embodiment is 50.23 and the multiplication ratio Nint of the integer phase-locked loop 158 of the third embodiment is 10, the third embodiment is performed. It is necessary to set the desired value of the variable division ratio Nfd2 of the variable frequency divider 150 of the example to 5.023. In this case, in the variable frequency divider 150 of the second embodiment, the variable frequency division ratio Nfd2 is set to 50 or 51, whereas in the variable frequency divider 150 of the third embodiment, the variable frequency division ratio Nfd2 is 5 or It should be 6. When the desired value of the variable division ratio Nfd2 of the variable frequency divider 150 becomes small, the phase noises φn and div tend to increase. For this reason, the phase noise appearing in the final output signal φout of the fractional phase-locked loop 140B of the third embodiment is simply the phase noise appearing in the final output signal φout of the fractional phase-locked loop 140 of the second embodiment. It is not 1 / Nint.

Next, a comparison of the effect of reducing the phase noise appearing in the final output signal φout with respect to the phase noises φn and div in the fractional phase-locked

loops

140 and 140B of the second embodiment and the third embodiment will be described. FIG. 9 is an explanatory diagram of the fractional phase-locked loop 140 of the second embodiment, and FIG. 10 is an explanatory diagram of the fractional phase-locked loop 140B of the third embodiment. In FIGS. 9 and 10, the figure on the left side is an explanatory view showing an example of the frequency characteristics of the phase noise φn, div, and the center figure shows the output of the variable frequency divider 150 as an input and the output unit 14 as an input. It is explanatory drawing which shows an example of the frequency characteristic of the transfer function of the circuit (hereinafter referred to as "the first predetermined circuit") which became an output, and the figure on the right side is an example of the frequency characteristic of the phase of the phase noise included in the final output signal. It is explanatory drawing which shows. “Fbw” in FIGS. 9 and 10 is the bandwidth of the first predetermined circuit in the fractional phase-locked

loops

140 and 140B. In FIGS. 9 and 10, the bandwidths Fbw of the first predetermined circuit in the fractional phase-locked

loops

140 and 140B are the same. “Flpf” in FIG. 9 is the frequency of the signal output from the low-pass filter 56 to the phase detector 42, and FIG. 10 “Fint2” is the frequency of the signal output from the indicator phase-locked loop 158 to the phase detector 42. The frequency, that is, the frequency of Nint times the frequency Flpf.

Comparing FIGS. 9 and 10, since the frequency Fit2 (= Nint × Flpf) is larger than the frequency Flpf, the phase noise φn of the fractional phase-locked loop 140B and the div are the phase noise φn of the fractional phase-locked loop 140. It can be seen that it spreads to the high frequency side compared to the div (the maximum value becomes the high frequency side). As described above, in the fractional phase-locked

loops

140 and 140B of the second embodiment and the third embodiment, when the frequency Fout of the final output signal is the same, the variable frequency divider 150 of the fractional phase-locked loop 140B This is because it is necessary to multiply the desired value of the frequency Ffd2 of the signal from Ffd2 by Nint with respect to the desired value of the frequency Ffd2 of the signal from the variable frequency divider 150 of the fractional phase-locked loop 140. Then, in the fractional phase-locked loop 140B, the phase noise φn, div spreads to the higher frequency side as compared with the fractional phase-locked loop 140, so that when the bandwidth Fbw of the first predetermined circuit is the same, the phase noise φn, It can be seen that the div is further reduced, that is, the phase noise appearing in the final output signal φout is smaller. From this, it is assumed that in the fractional phase-locked loop 140B, the phase noise appearing in the final output signal φout is smaller than that in the fractional phase-locked loop 140 even when the bandwidth Fbw of the first predetermined circuit is large to some extent.

Next, in the fractional phase-locked loop 140B, the voltage when the bandwidth Fbw2 of the circuit (hereinafter referred to as “second predetermined circuit”) that outputs the output unit 14 while inputting the output of the voltage controlled oscillator 48 is changed. A comparison of the effect of reducing the phase noise appearing in the final output signal φout (specifically, the phase noise caused by the phase noise φn, vco) with respect to the phase noise φn, vco generated in the controlled oscillator 48 will be described. FIG. 11 is an explanatory diagram when the bandwidth Fbw2 of the second predetermined circuit of the fractional phase-locked loop 140B is a relatively small value Fbwlo, and FIG. 12 is an explanatory diagram of the bandwidth Fbw2 of the second predetermined circuit of the fractional phase-locked loop 140B. It is explanatory drawing when is a value Fbwhi larger than a value Fbwlo. In FIGS. 11 and 12, the figure on the left is an explanatory diagram showing an example of the frequency characteristics of the phase noises φn and vco, and the figure in the center is an explanatory diagram showing an example of the frequency characteristics of the transfer function of the second predetermined circuit. The figure on the right is an explanatory diagram showing an example of the frequency characteristics of the phase noise included in the final output signal φout. Comparing FIGS. 11 and 12, it can be seen that the phase noises φn and vco are reduced as the bandwidth Fbw2 of the second predetermined circuit is widened, that is, the phase noises appearing in the final output signal φout are smaller. .. Then, if the bandwidth Fbw2 of the second predetermined circuit can be increased, the voltage controlled oscillator 48 having a slightly larger phase noise can be selected. As a result, as the voltage controlled oscillator 48, a voltage controlled oscillator with a small power consumption and an area can be used although the phase noises φn and vco are slightly large.

The fractional phase-locked loop 140B included in the phase-locked loop device 120B of the third embodiment described above includes an integer phase-locked loop 158 in addition to the configuration of the fractional phase-locked loop 140 of the second embodiment. Here, the integer phase-locked loop 158 multiplies the frequency Flpf of the signal from the low-pass filter 56 and outputs it to the phase detector 42 as a signal of frequency Fit2. Then, the phase detector 42 of the fractional phase-locked loop 140B compares the signal from the variable frequency divider 150 with the signal from the indicator phase-locked loop 158 and outputs a signal corresponding to the phase difference. With such a configuration, the phase noise appearing in the signal from the variable frequency divider 150 is greatly amplified and appears in the final output signal φout more sufficiently than in the phase-locked loop device 120B of the second embodiment. It can be avoided. Further, in the fractional phase-locked loop 140B of the third embodiment, in addition to reducing the phase noise in the final output signal φout, similarly to the fractional phase-locked

loops

40 and 140 of the first embodiment and the second embodiment, Fractional spar can also be reduced.

FIG. 13 is a configuration diagram showing an outline of the configuration of the phase-locked loop device 20B of the fourth embodiment. The phase-locked loop device 20B of the third embodiment is the same as the phase-locked loop device 20 of the first embodiment shown in FIG. 1, except that the fractional phase-locked loop circuit 40 is replaced with the fractional phase-locked loop circuit 40B. is there. The fractional phase-locked loop 40B of the fourth embodiment is the same as the fractional phase-locked loop 40 of the first embodiment except that the integer phase-locked loop 58 is added. Therefore, among the phase-locked loop devices 20B of the fourth embodiment, the same configurations as those of the phase-locked loop device 20 of the first embodiment are designated by the same reference numerals, and detailed description thereof will be omitted.

The integrator phase-locked loop 58 is configured in the same manner as the integrator phase-locked loop 158 of the fractional phase-locked loop 140B of the third embodiment, and the frequency Flpf of the signal from the low-pass filter 56 is multiplied to obtain a signal of frequency Fit2. Is output to the phase detector 42. In the fractional phase-locked loop 40B, the phase detector 42 compares the signal from the variable frequency divider 50 with the signal from the indicator phase-locked loop 58, and outputs a signal corresponding to the phase difference.

In the fractional phase-locked loop 40B of the fourth embodiment configured in this way, the relationship between the frequency Fit of the second reference signal from the integer phase-locked loop 21 and the frequency Fout of the final output signal output to the output unit 14 is determined. It can be expressed as in equation (13).

Fout = (Nhm / Nid2 + 1 / (Nfd ・ Nint)) ・ Fint (13)

In the phase-locked loop device 20B, the frequency division ratio Nid1 of the fixed frequency divider 30, the desired value of the frequency division ratio Nfd of the variable frequency divider 50, the frequency division ratio Nid2 of the fixed frequency divider 52, and the indicator phase synchronization. The multiplication ratio Nint of the circuit 58, that is, the frequency Flpf of the signal input to the intercounter phase-locked loop 58 (the signal output from the low-pass filter 56) and the frequency Fint2 of the signal output from the intercounter phase-locked loop 58. The relationship (Fint2 / Flpf) is appropriately set based on the desired value of the frequency Fout of the final output signal.

FIG. 14 is an explanatory diagram showing a linear model of the fractional phase-locked loop 40B included in the phase-locked loop device 20B of the fourth embodiment. The linear model of the fractional phase-locked loop 40B of the fourth embodiment of FIG. 14 is the first embodiment of FIG. 2 except that the transfer function (Nint × Gint (s)) of the integral phase-locked loop 58 is added. It is the same as the linear model of the fractional phase-locked loop 40 of. Therefore, the difference between the linear model of the fractional phase-locked loop 40B of the fourth embodiment and the linear model of the fractional phase-locked loop 40 of the first embodiment will be described. With reference to FIG. 14, if the definition is as shown in the equation (14), the final output signal φout output to the output unit 14 can be expressed as the equation (15). In this equation (15), when the Laplace operator s is sufficiently small, that is, when the value Hol (s) is sufficiently large and is within the band of the value Gint (s), the phase noise φn, div is large. It can be seen that it is reduced to about 1 / Nint and appears in the final output signal φout. Therefore, it can be said that it is possible to more sufficiently avoid the phase noises φn and div being greatly amplified and appearing in the final output signal φout.

Further, the fractional phase-locked loop 40B of the fourth embodiment has the same effect as that of the fractional phase-locked loop 140B of the third embodiment described with reference to FIGS. 9 to 12.

The fractional phase-locked loop 40B included in the phase-locked loop device 20B of the fourth embodiment described above includes an integer phase-locked loop 58 in addition to the configuration of the fractional phase-locked loop 40 of the first embodiment. Here, the integer phase-locked loop 58 multiplies the frequency Flpf of the signal from the low-pass filter 56 and outputs it to the phase detector 42 as a signal of frequency Fit2. Then, the phase detector 42 of the fractional phase-locked loop 40B compares the signal from the variable frequency divider 50 with the signal from the indicator phase-locked loop 58 and outputs a signal corresponding to the phase difference. With such a configuration, the phase noise appearing in the signal from the variable frequency divider 50 is greatly amplified and appears in the final output signal φout more sufficiently than the phase-locked loop device 20B of the first embodiment. It can be avoided. Further, in the fractional phase-locked loop 40B of the fourth embodiment, in addition to reducing the phase noise in the final output signal φout, the fractional phase-locked loop 40 of the first embodiment, the second embodiment, and the third embodiment, Similar to 140 and 140B, the fractional spar can be reduced.

In the phase-locked

loop devices

20, 120, 120B, and 20B of the first embodiment, the second embodiment, the third embodiment, and the fourth embodiment, the second reference signal from the integer phase-locked loop 21 has a fixed frequency division ratio. A fixed frequency divider 52 that divides the frequency with Nid2 and outputs the frequency to the harmonic mixer 54 is provided. However, the second reference signal from the integer phase-locked loop 21 may be directly input to the harmonic mixer 54 without the fixed frequency divider 52.

In the phase-locked

loop devices

20, 120, 120B, and 20B of the first embodiment, the second embodiment, the third embodiment, and the fourth embodiment, the phase-locked loop circuit 21 connected to the oscillator 12 and the inverter phase A fractional phase-locked loop 40 connected to the synchronization circuit 21 and the output unit 14 is provided. However, the fractional phase-locked loop 40 may be connected to the oscillator 12 and the output unit 14 without the integer phase-locked loop 21. In this case, as the oscillator 12, instead of the crystal oscillator that oscillates a signal having a frequency of about 20 MHz to 100 MHz as described above, an oscillator that oscillates a signal having a frequency of about several hundred MHz to 1 GHz is used. preferable.

The correspondence between the main elements of the examples and the main elements of the invention described in the column of means for solving the problem will be described. In the first embodiment and the second embodiment, the phase detector 42, the charge pump 44, the loop filter 46, and the voltage controlled oscillator 48 correspond to the "first frequency adjusting unit", and the variable frequency divider 50 or the variable frequency divider 50 or the variable frequency divider 40. The device 150 corresponds to the "variable frequency divider", and the harmonic mixer 54 and the low-pass filter 56 correspond to the "second frequency adjusting unit". Further, the fixed frequency divider 52 corresponds to the “fixed frequency divider”.

Regarding the correspondence between the main elements of the examples and the main elements of the invention described in the column of means for solving the problem, the invention described in the column of the means for solving the problem in the examples is carried out. Since it is an example for specifically explaining the form for solving the problem, the elements of the invention described in the column of means for solving the problem are not limited. That is, the interpretation of the invention described in the column of means for solving the problem should be performed based on the description in the column, and the examples are the inventions described in the column of means for solving the problem. It is just a concrete example.

Although the embodiments for carrying out the present invention have been described above with reference to examples, the present invention is not limited to these examples, and various embodiments are used without departing from the gist of the present invention. Of course, it can be done.

The present invention can be used in the manufacturing industry of fractional phase-locked loops and phase-locked loop devices.

Claims

A fractional phase-locked loop that multiplies the frequency of the reference signal by a non-integer and outputs it to the output section.
A first frequency adjusting unit that controls the frequency of the signal output to the output unit based on the phase difference between the two input signals.
A variable frequency divider that divides the frequency of the reference signal or the signal from the first frequency adjustment unit by a variable division ratio and outputs it to the first frequency adjustment unit.
A second that outputs a signal of the second related frequency of the difference between the frequency of the signal from the first frequency adjusting unit and the first related frequency based on the frequency of the reference signal or the multiplication of the difference to the first frequency adjusting unit. Frequency control unit and
Fractional phase-locked loop with.
The fractional phase-locked loop according to claim 1.
The second frequency adjusting unit is
A harmonic mixer that generates a signal including a frequency component of each difference between the frequency of the signal from the first frequency adjusting unit and the frequency of each multiplication of the frequency of the reference signal or the frequency of the related signal based on the reference signal.
It has a low-pass filter that extracts and outputs a frequency component of a predetermined frequency or less from each frequency component included in the signal from the harmonic mixer.
Fractional phase-locked loop.
The fractional phase-locked loop according to claim 2.
The low-pass filter extracts and outputs only the minimum frequency component from each of the frequency components.
Fractional phase-locked loop.
The fractional phase-locked loop according to claim 2 or 3.
The second frequency adjusting unit further includes an integer phase-locked loop that multiplies and outputs the frequency of the signal from the low-pass filter.
Fractional phase-locked loop.
The fractional phase-locked loop according to any one of claims 1 to 4.
A fixed frequency divider that divides the reference signal by a fixed frequency division ratio and outputs it to the second frequency adjustment unit.
Fractional phase-locked loop with.
The fractional phase-locked loop according to any one of claims 1 to 5.
The first frequency adjusting unit is
A phase detector that compares two input signals and outputs a signal according to the phase difference,
A charge pump that converts the signal from the phase detector into an electric current,
A loop filter that removes frequency components higher than the predetermined frequency of the current from the charge pump and converts it into a voltage.
It has a voltage controlled oscillator that controls the frequency of a signal output to the output unit based on the voltage from the loop filter.
Fractional phase-locked loop.
The fractional phase-locked loop according to any one of claims 1 to 6.
A second integer phase-locked loop that multiplies the frequency of the initial reference signal and outputs it as the reference signal to the fractional phase-locked loop.
A phase-locked loop device comprising.
The phase-locked loop device according to claim 7.
The variable frequency divider divides the frequency of the signal from the first frequency control unit by a variable frequency division ratio and outputs it to the first frequency control unit.
Phase-locked loop device.