WO2021077487A1 - 像素单元及显示面板 - Google Patents

像素单元及显示面板 Download PDF

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Publication number
WO2021077487A1
WO2021077487A1 PCT/CN2019/117882 CN2019117882W WO2021077487A1 WO 2021077487 A1 WO2021077487 A1 WO 2021077487A1 CN 2019117882 W CN2019117882 W CN 2019117882W WO 2021077487 A1 WO2021077487 A1 WO 2021077487A1
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WIPO (PCT)
Prior art keywords
light
emitting unit
thin film
film transistor
electrically connected
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2019/117882
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English (en)
French (fr)
Inventor
刘世奇
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
Original Assignee
Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Application filed by Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd filed Critical Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
Priority to US16/626,531 priority Critical patent/US20210358401A1/en
Publication of WO2021077487A1 publication Critical patent/WO2021077487A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2003—Display of colours
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0439—Pixel structures
    • G09G2300/0452—Details of colour pixel setup, e.g. pixel composed of a red, a blue and two green components
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0852—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor being a dynamic memory with more than one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0257—Reduction of after-image effects
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/043—Preventing or counteracting the effects of ageing
    • G09G2320/045—Compensation of drifts in the characteristics of light emitting or modulating elements

Definitions

  • This application relates to the field of display, and in particular to a pixel unit and a display panel.
  • OLED Organic Light-Emitting Diode
  • LCD liquid crystal display
  • the disadvantages of OLED display panels gradually appear.
  • the OLED devices will gradually attenuate or/and the threshold voltage of the TFT devices will drift, resulting in afterimages on the display panel and reducing the display.
  • the quality of the panel is improved.
  • the present application provides a pixel unit and a display panel to solve the technical problem of image sticking in the existing display panel.
  • the present application provides a pixel unit, wherein the pixel unit at least includes a first area and a second area;
  • At least one first light-emitting unit is provided in the first area
  • At least one second light-emitting unit is provided in the second area
  • one of the first light-emitting unit and the second light-emitting unit is in a light-emitting state.
  • the first area is further provided with a first driving circuit, and the first driving circuit is electrically connected to the first light-emitting unit;
  • the second area is further provided with a second driving circuit, and the second driving circuit is electrically connected to the second light-emitting unit;
  • the first drive circuit is used to drive the first light-emitting unit to emit light
  • the second drive circuit is used to drive the second light-emitting unit to emit light
  • the first driving circuit includes at least a first thin film transistor, a second thin film transistor, and a first storage capacitor;
  • the second driving circuit includes at least a third thin film transistor, a fourth thin film transistor, and a second storage capacitor;
  • the first thin film transistor, the second thin film transistor, the third thin film transistor, and the fourth thin film transistor are one of a P-type transistor or an N-type transistor;
  • the transistor type of the fourth thin film transistor is different from the first thin film transistor, the second thin film transistor, and the third thin film transistor.
  • the gate of the first thin film transistor is electrically connected to the scan signal line
  • the source/drain of the first thin film transistor is electrically connected to the data signal line
  • the The drain/source is electrically connected to the first electrode plate of the first storage capacitor and the gate of the second thin film transistor
  • the source/drain of the second thin film transistor is electrically connected to the input terminal of the pixel unit, and the drain/source of the second thin film transistor is connected to the second electrode plate of the first storage capacitor and the first The light-emitting unit is electrically connected;
  • the gate of the third thin film transistor is electrically connected to the scan signal line, the source/drain of the third thin film transistor is electrically connected to the data signal line, and the drain/source of the first thin film transistor is electrically connected to The first electrode plate of the second storage capacitor and the gate of the second thin film transistor are electrically connected;
  • the source/drain of the fourth thin film transistor is electrically connected to the input terminal of the pixel unit and the second electrode plate of the fourth storage capacitor is electrically connected, and the drain/source of the second thin film transistor is electrically connected to the The second light-emitting unit is electrically connected.
  • the colors of the first light-emitting unit and the second light-emitting unit are the same.
  • the pixel unit of the present application further includes a third area
  • the third area is provided with a third driving circuit and a third light-emitting unit, and the third driving circuit is electrically connected to the third light-emitting unit;
  • the structure of the third driving circuit is the same as the structure of the first driving circuit or the second driving circuit.
  • the colors of the first light-emitting unit, the second light-emitting unit, and the third light-emitting unit are the same.
  • the pixel unit further includes a fourth light-emitting unit
  • the fourth light emitting unit is located in the first area or the second area;
  • the color of the fourth light-emitting unit is the same as the color of the light-emitting unit in the corresponding area.
  • the fourth light emitting unit is located in the first area
  • the first driving circuit is electrically connected to the fourth light-emitting unit, and the first driving circuit is used to drive the first light-emitting unit and the fourth light-emitting unit to emit light;
  • the fourth light emitting unit is located in the second area
  • the second driving circuit is electrically connected to the fourth light-emitting unit, and the second driving circuit is used to drive the second light-emitting unit and the fourth light-emitting unit to emit light.
  • the application also proposes a display panel, including a pixel unit, wherein:
  • the pixel unit includes at least a first area and a second area
  • At least one first light-emitting unit is provided in the first area
  • At least one second light-emitting unit is provided in the second area
  • one of the first light-emitting unit and the second light-emitting unit is in a light-emitting state.
  • the first area is further provided with a first driving circuit, and the first driving circuit is electrically connected to the first light-emitting unit;
  • the second area is further provided with a second driving circuit, and the second driving circuit is electrically connected to the second light-emitting unit;
  • the first drive circuit is used to drive the first light-emitting unit to emit light
  • the second drive circuit is used to drive the second light-emitting unit to emit light
  • the first driving circuit includes at least a first thin film transistor, a second thin film transistor, and a first storage capacitor;
  • the second driving circuit includes at least a third thin film transistor, a fourth thin film transistor, and a second storage capacitor;
  • the first thin film transistor, the second thin film transistor, the third thin film transistor, and the fourth thin film transistor are one of a P-type transistor or an N-type transistor;
  • the transistor type of the fourth thin film transistor is different from the first thin film transistor, the second thin film transistor, and the third thin film transistor.
  • the gate of the first thin film transistor is electrically connected to the scan signal line
  • the source/drain of the first thin film transistor is electrically connected to the data signal line
  • the The drain/source is electrically connected to the first electrode plate of the first storage capacitor and the gate of the second thin film transistor
  • the source/drain of the second thin film transistor is electrically connected to the input terminal of the pixel unit, and the drain/source of the second thin film transistor is connected to the second electrode plate of the first storage capacitor and the first The light-emitting unit is electrically connected;
  • the gate of the third thin film transistor is electrically connected to the scan signal line, the source/drain of the third thin film transistor is electrically connected to the data signal line, and the drain/source of the first thin film transistor is electrically connected to The first electrode plate of the second storage capacitor and the gate of the second thin film transistor are electrically connected;
  • the source/drain of the fourth thin film transistor is electrically connected to the input end of the pixel unit and the second electrode plate of the second storage capacitor is electrically connected, and the drain/source of the fourth thin film transistor is electrically connected to the The second light-emitting unit is electrically connected.
  • the colors of the first light-emitting unit and the second light-emitting unit are the same.
  • the pixel unit further includes a third area
  • the third area is provided with a third driving circuit and a third light-emitting unit, and the third driving circuit is electrically connected to the third light-emitting unit;
  • the structure of the third driving circuit is the same as the structure of the first driving circuit or the second driving circuit.
  • the colors of the first light-emitting unit, the second light-emitting unit, and the third light-emitting unit are the same.
  • the pixel unit further includes a fourth light-emitting unit
  • the fourth light emitting unit is located in the first area or the second area;
  • the color of the fourth light-emitting unit is the same as the color of the light-emitting unit in the corresponding area.
  • the fourth light emitting unit is located in the first area
  • the first driving circuit is electrically connected to the fourth light-emitting unit, and the first driving circuit is used to drive the first light-emitting unit and the fourth light-emitting unit to emit light;
  • the fourth light emitting unit is located in the second area
  • the second driving circuit is electrically connected to the fourth light-emitting unit, and the second driving circuit is used to drive the second light-emitting unit and the fourth light-emitting unit to emit light.
  • At least two light-emitting units are provided in one pixel unit, one light-emitting unit corresponds to a drive circuit, and different driving signals are input to the pixel unit to enable the first light-emitting unit and the second light-emitting unit to interact Work, prolong the service life of organic light-emitting diodes and thin film transistors, and avoid technical problems such as image retention on the display panel.
  • FIG. 1 is a diagram of the first circuit structure of a pixel unit of this application.
  • FIG. 2 is a timing control diagram of the pixel unit driving circuit of this application.
  • FIG. 3 is a diagram of the second circuit structure of the pixel unit of this application.
  • FIG. 4 is a third circuit structure diagram of the pixel unit of this application.
  • the OLED device Due to the long-term lighting of the existing display panel, the OLED device will gradually attenuate or/and the threshold voltage of the TFT device will drift, resulting in technical problems such as image retention on the display panel.
  • the present application provides a pixel unit, which includes at least a first area and a second area.
  • the first area is provided with at least one first light-emitting unit
  • the second area is provided with at least one second light-emitting unit.
  • At least two light-emitting units are provided in one pixel unit.
  • the two light-emitting colors can be the same or different, and the specific setting of the color can be set according to the corresponding driving circuit.
  • the present application greatly extends the service life of the light-emitting unit by enabling the light-emitting units located in one pixel unit to work interactively, and avoids the occurrence of image retention of the display panel.
  • FIG. 1 is the first circuit structure diagram of the pixel unit of this application.
  • the display unit includes a first area 10 and a second area 20.
  • the first area 10 is provided with a first driving circuit 12 and a first light emitting unit 11 located on the first driving circuit 12, and the first driving circuit 12 is electrically connected to the first light emitting unit 11, so The first driving circuit 12 is used to drive the first light-emitting unit 11 to emit light.
  • a second driving circuit 22 and a second light emitting unit 21 located on the second driving circuit 22 are provided in the second area 20, and the second driving circuit 22 is electrically connected to the second light emitting unit 21, so The second driving circuit 22 is used to drive the second light-emitting unit 21 to emit light.
  • the first driving circuit 12 when the pixel unit is in the working state, the first driving circuit 12 is used to drive the first light-emitting unit 11 to emit light, or the second driving circuit 22 is used to drive the first light-emitting unit 11 to emit light.
  • the two light-emitting units 21 emit light.
  • the first light-emitting unit 11/the second light-emitting unit 21 performs interactive work in the pixel unit through the first driving circuit 12/the second driving circuit 22.
  • the service life of the first light-emitting unit 11, the second light-emitting unit 21, the first driving circuit 12, and the second driving circuit 22 is prolonged.
  • the first driving circuit 12 may include at least a first thin film transistor T1, a second thin film transistor T2, and a first storage capacitor C1.
  • the second driving circuit 22 includes at least a third thin film transistor T3, a fourth thin film transistor T4, and a second storage capacitor C2.
  • the driving circuit of the present application takes a simple 2T1C (2 thin film transistors and 1 storage capacitor) as an example for description.
  • the first thin film transistor T1, the second thin film transistor T2, the third thin film transistor T3, and the fourth thin film transistor T4 in this application are one of a P-type transistor or an N-type transistor.
  • the transistor type of the fourth thin film transistor T4 is different from the first thin film transistor T1, the second thin film transistor T2, and the third thin film transistor T3.
  • the first thin film transistor T1, the second thin film transistor T2, and the third thin film transistor T3 are N-type transistors
  • the fourth thin film transistor T4 is a P-type transistor as an example.
  • the gate of the first thin film transistor T1 is electrically connected to the scan signal line
  • the source/drain of the first thin film transistor T1 is electrically connected to the data signal line
  • the first thin film transistor T1 The drain/source is electrically connected to the first electrode plate of the first storage capacitor C1 and the gate of the second thin film transistor T2.
  • the source/drain of the second thin film transistor T2 is electrically connected to the input terminal of the pixel unit, and the drain/source of the second thin film transistor T2 is connected to the second electrode plate of the first storage capacitor C1 and all The first light-emitting unit 11 is electrically connected.
  • the gate of the third thin film transistor T3 is electrically connected to the scan signal line
  • the source/drain of the third thin film transistor T3 is electrically connected to the data signal line
  • the drain of the first thin film transistor T1 is electrically connected to the scan signal line.
  • the source is electrically connected to the first electrode plate of the second storage capacitor C2 and the gate of the second thin film transistor T2.
  • the source/drain of the fourth thin film transistor T4 is electrically connected to the input terminal of the pixel unit and the second electrode plate of the second storage capacitor C2 is electrically connected, and the drain/source of the fourth thin film transistor T4 It is electrically connected to the second light-emitting unit 21.
  • the first light emitting unit 11 and the second light emitting unit 21 are organic light emitting diodes.
  • the anode of the first light-emitting unit 11 is electrically connected to the source/drain of the second thin film transistor T2 and the second electrode plate of the first storage capacitor C1
  • the anode of the second light-emitting unit 21 is electrically connected to the second electrode plate of the first storage capacitor C1.
  • the source/drain of the fourth thin film transistor T4 are electrically connected
  • the cathodes of the first light-emitting unit 11 and the second light-emitting unit 21 are electrically connected to a constant voltage low-level source VSS.
  • the colors of the first light-emitting unit 11 and the second light-emitting unit 21 may be the same.
  • FIG. 2 is a timing control diagram of the pixel unit driving circuit of the present application.
  • One cycle in the above timing control diagram includes four periods of 0 ⁇ t1, t1 ⁇ t2, t2 ⁇ t3, and t3 ⁇ t4, and different voltage signals are input to the data signal lines and the scan signal lines in different time periods.
  • the scan signal line and the data signal line output high-level signals.
  • the gate of the first thin film transistor T1 is electrically connected to the scan signal line. Since the first thin film transistor T1 is an N-type transistor, the high level signal input to the scan signal line will The switch of the first thin film transistor T1 is turned on, and the high-level signal input from the data signal line is input from the source of the first thin film transistor T1 to the drain of the first thin film transistor T1, and is transmitted to all The gate of the second thin film transistor T2 and the first electrode plate of the first storage capacitor C1.
  • the second thin film transistor T2 is an N-type thin film transistor
  • the high-level signal transmitted from the first thin film transistor T1 makes the switch of the second thin film transistor T2 open, and the constant voltage and high voltage of the pixel unit
  • the flat source VDD is input to the drain of the second thin film transistor T2 through the source of the second thin film transistor T2, and is transmitted to the second electrode plate of the first storage capacitor C1 and the first light emitting unit 11 Of the anode.
  • the first storage capacitor C1 is in a charged state.
  • the cathode of the first light-emitting unit 11 is connected to a constant-voltage low-level source, so the first light-emitting unit 11 emits light during a period of 0 to t1.
  • the gate of the third thin film transistor T3 receives the high-level signal output by the scan signal line. Since the third thin film transistor T3 is an N-type transistor, the switch of the third thin film transistor T3 is turned on, and the data The high-level signal input from the signal line is input from the source of the third thin film transistor T3 to the drain of the third thin film transistor T3, and is transmitted to the gate of the fourth thin film transistor T4. Since the fourth thin film transistor T4 is a P-type transistor, a high-level signal cannot turn on the switch of the fourth thin film transistor T4, so the second light-emitting unit 21 does not emit light during the period of 0 to t1.
  • the scan signal line outputs a low-level signal
  • the data signal line outputs a high-level signal
  • the gate of the first thin film transistor T1 is electrically connected to the scan signal line. Since the first thin film transistor T1 is an N-type transistor, the scan signal line cannot input low-level signals. When the switch of the first thin film transistor T1 is turned on, the signal output by the data signal line cannot be transmitted to the second thin film transistor T2. At this time, the first storage capacitor C1 is in a discharged state, the high-level signal released by the first storage capacitor C1 turns on the second thin film transistor T2, and the constant voltage high-level source VDD of the pixel unit passes through The source of the second thin film transistor T2 is input to the drain of the second thin film transistor T2 and is transmitted to the anode of the first light-emitting unit 11. The cathode of the first light-emitting unit 11 is connected to a constant-voltage low-level source, so the first light-emitting unit 11 emits light during the period t1 to t2.
  • the switch of the third thin film transistor T3 cannot be turned on. In the time period from 0 to t1, the second storage capacitor C2 is not charged, so the second light emitting unit 21 does not emit light in the time period from t1 to t2.
  • the scan signal line In the time period t2 ⁇ t3, the scan signal line outputs a high-level signal, and the data signal line outputs a low-level signal.
  • the gate of the first thin film transistor T1 is electrically connected to the scan signal line. Since the first thin film transistor T1 is an N-type transistor, the scan signal line cannot input low-level signals. When the switch of the first thin film transistor T1 is turned on, the signal output by the data signal line cannot be transmitted to the second thin film transistor T2. However, the first storage capacitor C1 is released without capacitance, and the second thin film transistor T2 is turned off. Therefore, the constant voltage high-level source VDD of the pixel unit cannot be transmitted to the anode of the first light-emitting unit 11. Therefore, the first light-emitting unit 11 does not emit light during the period of t2 to t3.
  • the gate of the third thin film transistor T3 is electrically connected to the scan signal line. Since the third thin film transistor T3 is an N-type transistor, the scan signal line inputs a high-level signal to make the third thin film transistor The switch of T3 is turned on, and the low-level signal input from the data signal line is input from the source of the third thin film transistor T3 to the drain of the third thin film transistor T3, and is transmitted to the fourth thin film transistor T4 And the first electrode plate of the second storage capacitor C2.
  • the fourth thin film transistor T4 is a P-type thin film transistor
  • the low-level signal transmitted from the third thin film transistor T3 makes the switch of the fourth thin film transistor T4 open, and the constant voltage and high voltage of the pixel unit
  • the flat source VDD is input to the drain of the second thin film transistor T2 through the source of the second thin film transistor T2, and is transmitted to the second electrode plate of the second storage capacitor C2 and the second light emitting unit 21 Of the anode.
  • the second storage capacitor C2 is in a charged state.
  • the cathode of the second light-emitting unit 21 is connected to a constant-voltage low-level source, so the second light-emitting unit 21 emits light during the period t2 to t3.
  • the scan signal line and the data signal line output low-level signals.
  • the gate of the third thin film transistor T3 is electrically connected to the scan signal line. Since the third thin film transistor T3 is an N-type transistor, the scan signal line cannot input low-level signals.
  • the switch of the first thin film transistor T1 is turned on, the signal output by the data signal line cannot be transmitted to the second thin film transistor T2.
  • the second storage capacitor C2 is in a discharged state, the low-level signal released by the second storage capacitor C2 turns on the fourth thin film transistor T4, and the constant voltage high-level source VDD of the pixel unit passes through
  • the source of the fourth thin film transistor T4 is input to the drain of the fourth thin film transistor T4 and is transmitted to the anode of the second light-emitting unit 21.
  • the cathode of the second light-emitting unit 21 is connected to a constant-voltage low-level source, so the second light-emitting unit 21 emits light during the period t3 to t4.
  • the switch of the first thin film transistor T1 cannot be turned on. In the time period t2 to t3, the first storage capacitor C1 is not charged, so the first light-emitting unit 11 does not emit light in the time period t3 to t4.
  • the pixel unit may further include a third region 30.
  • the third area 30 is provided with a third driving circuit 32 and a third light emitting unit 31, the third driving circuit 32 is electrically connected to the third light emitting unit 31, and the third driving circuit 32 is used to drive the The third light emitting unit 31 emits light.
  • the structure of the third driving circuit 32 may be the same as the structure of the first driving circuit 12 or the second driving circuit 22.
  • FIG. 3 is a second circuit structure diagram of the pixel unit of this application.
  • the structure of the third driving circuit 32 is the same as the structure of the first driving circuit 12.
  • the scan signal line and the data signal line output high-level signals.
  • the first light-emitting unit 11 and the third light-emitting unit 31 emit light, and the second light-emitting unit 21 does not emit light.
  • the scan signal line outputs a low-level signal
  • the data signal line outputs a high-level signal.
  • the first light-emitting unit 11 and the third light-emitting unit 31 emit light
  • the second light-emitting unit 21 does not emit light.
  • the scan signal line outputs a high-level signal
  • the data signal line outputs a low-level signal.
  • the first light-emitting unit 11 and the third light-emitting unit 31 do not emit light
  • the second light-emitting unit 21 emits light.
  • the scan signal line and the data signal line output low-level signals.
  • the first light-emitting unit 11 and the third light-emitting unit 31 do not emit light, and the second light-emitting unit 21 emits light.
  • the colors of the first light-emitting unit 11, the second light-emitting unit 21, and the third light-emitting unit 31 may be the same.
  • the pixel unit may further include a fourth light-emitting unit 13.
  • the fourth light emitting unit 13 may be located in the first area 10 or the second area 20.
  • the fourth light emitting unit 13 is located in the first area 10, the first driving circuit 12 is electrically connected to the fourth light emitting unit 13, and the first driving circuit 12 is used to drive the first light emitting unit 11 and The fourth light emitting unit 13 emits light. or
  • the fourth light emitting unit 13 is located in the second area 20, the second driving circuit 22 is electrically connected to the fourth light emitting unit 13, and the second driving circuit 22 is used to drive the second light emitting unit 21 and The fourth light emitting unit 13 emits light.
  • FIG. 4 is a third circuit structure diagram of the pixel unit of this application.
  • the fourth light emitting unit 13 is located in the first area 10.
  • the first driving circuit 12 controls the first light-emitting unit 11 and the fourth light-emitting unit 13 at the same time.
  • the color of the fourth light-emitting unit 13 is the same as the color of the light-emitting unit in the corresponding area.
  • the second light-emitting unit 21 emits light in the time periods of t2 to t3 and t3 to t4. Therefore, in the time period from 0 to t2, the corresponding display device luminous brightness is greater than the time period from t2 to t4.
  • the pixel unit can be controlled to be in the t2 ⁇ t4 time period.
  • the pixel unit can be controlled to be in the 0 ⁇ t2 time period.
  • the application also proposes a display panel including the above-mentioned pixel unit.
  • the working principle of the display panel is the same or similar to that of the above-mentioned pixel unit, and will not be repeated in this application.
  • the present application proposes a pixel unit and a display panel.
  • the pixel unit includes at least a first area and a second area; the first area is provided with at least a first light-emitting unit, and the second area is provided with at least a second light-emitting unit .
  • the pixel unit is in a working state, one of the first light-emitting unit and the second light-emitting unit is in a light-emitting state.
  • At least two light-emitting units are provided in one pixel unit, one light-emitting unit corresponds to a drive circuit, and different driving signals are input to the pixel unit to enable the first light-emitting unit and the second light-emitting unit to interact Work, prolong the service life of organic light-emitting diodes and thin film transistors, and avoid technical problems such as image retention on the display panel.

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Abstract

本申请提出了一种像素单元及显示面板，该像素单元至少包括第一区和第二区；该第一区至少设置有一第一发光单元，该第二区至少设置有一第二发光单元。当该像素单元处于工作状态时，该第一发光单元、该第二发光单元中的一者处于发光状态。

Description

像素单元及显示面板 技术领域
本申请涉及显示领域，尤其涉及一种像素单元及显示面板。
 背景技术
在显示技术中，有机发光二极管（Organic Light-Emitting Diode，OLED）显示器具有轻薄、主动发光、响应速度快、可视角大、色域宽、亮度高和功耗低等众多优点，逐渐成为继液晶显示器（LCD）后的第三代显示技术。
随着屏幕点亮时间变长，OLED显示面板的弊病逐步展现，例如当显示面板长时间点亮时，OLED器件将逐渐衰减或/和TFT器件阈值电压漂移，导致显示面板出现残影，降低显示面板的品质。
因此，亟需一种显示面板以解决上述技术问题。
 技术问题
本申请提供一种像素单元及显示面板，以解决现有显示面板出现残影的技术问题。
 技术解决方案
本申请提供一种像素单元，其中，所述像素单元至少包括第一区和第二区；
所述第一区至少设置有一第一发光单元；
所述第二区至少设置有一第二发光单元；
当所述像素单元处于工作状态时，所述第一发光单元、所述第二发光单元中的一者处于发光状态。
在本申请的像素单元中，所述第一区还设置有第一驱动电路，所述第一驱动电路与所述第一发光单元电连接；
所述第二区还设置有第二驱动电路，所述第二驱动电路与所述第二发光单元电连接；
当所述像素单元处于工作状态时，所述第一驱动电路用于驱动所述第一发光单元发光、或者所述第二驱动电路用于驱动所述第二发光单元发光。
在本申请的像素单元中，所述第一驱动电路至少包括第一薄膜晶体管、第二薄膜晶体管及第一存储电容；
所述第二驱动电路至少包括第三薄膜晶体管、第四薄膜晶体管及第二存储电容；
其中，所述第一薄膜晶体管、所述第二薄膜晶体管、所述第三薄膜晶体管、及所述第四薄膜晶体管为P型晶体管或N型晶体管中的一种；
所述第四薄膜晶体管的晶体管类型与所述第一薄膜晶体管、所述第二薄膜晶体管、及所述第三薄膜晶体管相异。
在本申请的像素单元中，所述第一薄膜晶体管的栅极与扫描信号线电连接，所述第一薄膜晶体管的源极/漏极与数据信号线电连接，所述第一薄膜晶体管的漏极/源极与所述第一存储电容的第一电极板及所述第二薄膜晶体管的栅极电连接；
所述第二薄膜晶体管的源极/漏极与像素单元的输入端电连接，所述第二薄膜晶体管的漏极/源极与所述第一存储电容的第二电极板及所述第一发光单元电连接；
所述第三薄膜晶体管的栅极与所述扫描信号线电连接，所述第三薄膜晶体管的源极/漏极与数据信号线电连接，所述第一薄膜晶体管的漏极/源极与所述第二存储电容的第一电极板及所述第二薄膜晶体管的栅极电连接；
所述第四薄膜晶体管的源极/漏极与像素单元的输入端电连接及所述第四存储电容的第二电极板电连接，所述第二薄膜晶体管的漏极/源极与所述第二发光单元电连接。
在本申请的像素单元中，
所述第一发光单元和所述第二发光单元的颜色相同。
在本申请的像素单元中，所述像素单元还包括第三区；
所述第三区设置有第三驱动电路和第三发光单元，所述第三驱动电路与所述第三发光单元电连接；
所述第三驱动电路的结构与第一驱动电路或第二驱动电路的结构相同。
在本申请的像素单元中，所述第一发光单元、所述第二发光单元及所述第三发光单元的颜色相同。
在本申请的像素单元中，所述像素单元还包括第四发光单元；
所述第四发光单元位于所述第一区或者所述第二区内；
所述第四发光单元的颜色与对应区域内发光单元的颜色相同。
在本申请的像素单元中，
所述第四发光单元位于所述第一区内；
第一驱动电路与所述第四发光单元电连接，所述第一驱动电路用于驱动所述第一发光单元及所述第四发光单元发光；
或者
所述第四发光单元位于所述第二区内；
第二驱动电路与所述第四发光单元电连接，所述第二驱动电路用于驱动所述第二发光单元及所述第四发光单元发光。
本申请还提出了一种显示面板，包括像素单元，其中，
所述像素单元包括至少包括第一区和第二区；
所述第一区至少设置有一第一发光单元；
所述第二区至少设置有一第二发光单元；
当所述像素单元处于工作状态时，所述第一发光单元、所述第二发光单元中的一者处于发光状态。
在本申请的显示面板中，所述第一区还设置有第一驱动电路，所述第一驱动电路与所述第一发光单元电连接；
所述第二区还设置有第二驱动电路，所述第二驱动电路与所述第二发光单元电连接；
当所述像素单元处于工作状态时，所述第一驱动电路用于驱动所述第一发光单元发光、或者所述第二驱动电路用于驱动所述第二发光单元发光。
在本申请的显示面板中，所述第一驱动电路至少包括第一薄膜晶体管、第二薄膜晶体管及第一存储电容；
所述第二驱动电路至少包括第三薄膜晶体管、第四薄膜晶体管及第二存储电容；
其中，所述第一薄膜晶体管、所述第二薄膜晶体管、所述第三薄膜晶体管、及所述第四薄膜晶体管为P型晶体管或N型晶体管中的一种；
所述第四薄膜晶体管的晶体管类型与所述第一薄膜晶体管、所述第二薄膜晶体管、及所述第三薄膜晶体管相异。
在本申请的显示面板中，所述第一薄膜晶体管的栅极与扫描信号线电连接，所述第一薄膜晶体管的源极/漏极与数据信号线电连接，所述第一薄膜晶体管的漏极/源极与所述第一存储电容的第一电极板及所述第二薄膜晶体管的栅极电连接；
所述第二薄膜晶体管的源极/漏极与像素单元的输入端电连接，所述第二薄膜晶体管的漏极/源极与所述第一存储电容的第二电极板及所述第一发光单元电连接；
所述第三薄膜晶体管的栅极与所述扫描信号线电连接，所述第三薄膜晶体管的源极/漏极与数据信号线电连接，所述第一薄膜晶体管的漏极/源极与所述第二存储电容的第一电极板及所述第二薄膜晶体管的栅极电连接；
所述第四薄膜晶体管的源极/漏极与像素单元的输入端电连接及所述第二存储电容的第二电极板电连接，所述第四薄膜晶体管的漏极/源极与所述第二发光单元电连接。
在本申请的显示面板中，
所述第一发光单元和所述第二发光单元的颜色相同。
在本申请的显示面板中，
所述像素单元还包括第三区；
所述第三区设置有第三驱动电路和第三发光单元，所述第三驱动电路与所述第三发光单元电连接；
所述第三驱动电路的结构与第一驱动电路或第二驱动电路的结构相同。
在本申请的显示面板中，所述第一发光单元、所述第二发光单元及所述第三发光单元的颜色相同。
在本申请的显示面板中，
所述像素单元还包括第四发光单元；
所述第四发光单元位于所述第一区或者所述第二区内；
所述第四发光单元的颜色与对应区域内发光单元的颜色相同。
在本申请的显示面板中，
所述第四发光单元位于所述第一区内；
第一驱动电路与所述第四发光单元电连接，所述第一驱动电路用于驱动所述第一发光单元及所述第四发光单元发光；
或者
所述第四发光单元位于所述第二区内；
第二驱动电路与所述第四发光单元电连接，所述第二驱动电路用于驱动所述第二发光单元及所述第四发光单元发光。
 有益效果
本申请通过在一个像素单元内设置至少两个发光单元，一发光单元对应一驱动电路，通过对所述像素单元输入不同的驱动信号，使所述第一发光单元及所述第二发光单元交互工作，延长了有机发光二极管及薄膜晶体管的使用寿命，避免了显示面板出现残影等技术问题。
 附图说明
为了更清楚地说明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请像素单元的第一种电路结构图；
图2为本申请像素单元驱动电路的时序控制图；
图3为本申请像素单元的第二种电路结构图；
图4为本申请像素单元的第三种电路结构图。
 本发明的实施方式
以下各实施例的说明是参考附加的图示，用以例示本申请可用以实施的特定实施例。本申请所提到的方向用语，例如[上]、[下]、[前]、[后]、[左]、[右]、[内]、[外]、[侧面]等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本申请，而非用以限制本申请。在图中，结构相似的单元是用以相同标号表示。
现有显示面板由于长时间的点亮，使得OLED器件将逐渐衰减或/和TFT器件阈值电压漂移，导致显示面板出现残影等技术问题。
本申请提供一种像素单元，所述像素单元至少包括第一区和第二区。所述第一区至少设置有一第一发光单元，所述第二区至少设置有一第二发光单元。当所述像素单元处于工作状态时，所述第一发光单元、所述第二发光单元中的一者处于发光状态。
本申请通过在一个像素单元内设置至少两个发光单元。两个发光的颜色可以相同或不同，颜色的具体设置可以根据对应驱动电路设置。本申请通过使得位于一个像素单元内的发光单元交互工作，大大延长了发光单元的使用寿命，避免了显示面板残影的发生。
请参阅图1，图1为本申请像素单元的第一种电路结构图。
所述显示单元包括第一区10和第二区20。
所述第一区10内设置有第一驱动电路12及位于所述第一驱动电路12上的第一发光单元11，所述第一驱动电路12与所述第一发光单元11电连接，所述第一驱动电路12用于驱动所述第一发光单元11发光。
所述第二区20内设置有第二驱动电路22及位于所述第二驱动电路22上的第二发光单元21，所述第二驱动电路22与所述第二发光单元21电连接，所述第二驱动电路22用于驱动所述第二发光单元21发光。
在一种实施例中，当所述像素单元处于工作状态时，所述第一驱动电路12用于驱动所述第一发光单元11发光、或者所述第二驱动电路22用于驱动所述第二发光单元21发光。
所述第一发光单元11/所述第二发光单元21通过所述第一驱动电路12/所述第二驱动电路22在所述像素单元内进行交互性工作。延长了所述第一发光单元11、所述第二发光单元21、所述第一驱动电路12、以及所述第二驱动电路22的使用寿命。
在一种实施例中，所述第一驱动电路12可以至少包括第一薄膜晶体管T1、第二薄膜晶体管T2及第一存储电容C1。所述第二驱动电路22至少包括第三薄膜晶体管T3、第四薄膜晶体管T4及第二存储电容C2。
请参阅图1，本申请的驱动电路以简单的2T1C（2个薄膜晶体管以及1个存储电容）为例进行说明。
本申请中所述第一薄膜晶体管T1、所述第二薄膜晶体管T2、所述第三薄膜晶体管T3、及所述第四薄膜晶体管T4为P型晶体管或N型晶体管中的一种。
在一种实施例中，所述第四薄膜晶体管T4的晶体管类型与所述第一薄膜晶体管T1、所述第二薄膜晶体管T2、及所述第三薄膜晶体管T3相异。本申请实施例以所述第一薄膜晶体管T1、所述第二薄膜晶体管T2、所述第三薄膜晶体管T3为N型晶体管，所述第四薄膜晶体管T4为P型晶体管为例进行说明。
请参阅图1，所述第一薄膜晶体管T1的栅极与扫描信号线电连接，所述第一薄膜晶体管T1的源极/漏极与数据信号线电连接，所述第一薄膜晶体管T1的漏极/源极与所述第一存储电容C1的第一电极板及所述第二薄膜晶体管T2的栅极电连接。
所述第二薄膜晶体管T2的源极/漏极与像素单元的输入端电连接，所述第二薄膜晶体管T2的漏极/源极与所述第一存储电容C1的第二电极板及所述第一发光单元11电连接。
所述第三薄膜晶体管T3的栅极与所述扫描信号线电连接，所述第三薄膜晶体管T3的源极/漏极与数据信号线电连接，所述第一薄膜晶体管T1的漏极/源极与所述第二存储电容C2的第一电极板及所述第二薄膜晶体管T2的栅极电连接。
所述第四薄膜晶体管T4的源极/漏极与像素单元的输入端电连接及所述第二存储电容C2的第二电极板电连接，所述第四薄膜晶体管T4的漏极/源极与所述第二发光单元21电连接。
在一种实施例中，所述第一发光单元11及所述第二发光单元21为有机发光二极管。所述第一发光单元11的阳极与所述第二薄膜晶体管T2的源极/漏极及所述第一存储电容C1的第二电极板电连接，所述第二发光单元21的阳极与所述第四薄膜晶体管T4的源极/漏极电连接，所述第一发光单元11及所述第二发光单元21的阴极与恒压低电平源VSS电连接。
在一种实施例中，所述第一发光单元11和所述第二发光单元21的颜色可以相同。
请参阅图2，图2为本申请像素单元驱动电路的时序控制图。
上述时序控制图中的一个周期包括0~t1、t1~t2、t2~t3、t3~t4四个时段，不同时间段数据信号线及扫描信号线输入不同电压信号。
在0~t1时间段，所述扫描信号线及所述数据信号线输出高电平信号。
在本实施例中，所述第一薄膜晶体管T1的栅极与所述扫描信号线电连接，由于所述第一薄膜晶体管T1为N型晶体管，因此所述扫描信号线输入高电平信号将所述第一薄膜晶体管T1的开关打开，所述数据信号线输入的高电平信号从所述第一薄膜晶体管T1的源极输入至所述第一薄膜晶体管T1的漏极，并传输至所述第二薄膜晶体管T2的栅极以及所述第一存储电容C1的第一电极板。
由于所述第二薄膜晶体管T2为N型薄膜晶体管，因此所述第一薄膜晶体管T1传输过来的高电平信号使得所述第二薄膜晶体管T2的开关打开，所述像素单元的恒压高电平源VDD通过所述第二薄膜晶体管T2的源极输入至所述第二薄膜晶体管T2的漏极，并传输至所述第一存储电容C1的第二电极板及所述第一发光单元11的阳极。所述第一存储电容C1处于充电状态。所述第一发光单元11的阴极连接恒压低电平源，因此在0~t1时间段所述第一发光单元11发光。
所述第三薄膜晶体管T3的栅极接收所述扫描信号线输出的高电平信号，由于所述第三薄膜晶体管T3为N型晶体管，所述第三薄膜晶体管T3的开关打开，所述数据信号线输入的高电平信号从所述第三薄膜晶体管T3的源极输入至所述第三薄膜晶体管T3的漏极，并传输至所述第四薄膜晶体管T4的栅极。由于所述第四薄膜晶体管T4为P型晶体管，因此高电平信号无法将所述第四薄膜晶体管T4的开关打开，因此在0~t1时间段所述第二发光单元21不发光。
在t1~t2时间段，所述扫描信号线输出低电平信号，所述数据信号线输出高电平信号。
在本实施例中，所述第一薄膜晶体管T1的栅极与所述扫描信号线电连接，由于所述第一薄膜晶体管T1为N型晶体管，因此所述扫描信号线输入低电平信号无法将所述第一薄膜晶体管T1的开关打开，所述数据信号线输出的信号无法传输至所述第二薄膜晶体管T2。此时，所述第一存储电容C1处于放电状态，所述第一存储电容C1释放的高电平信号将所述第二薄膜晶体管T2打开，所述像素单元的恒压高电平源VDD通过所述第二薄膜晶体管T2的源极输入至所述第二薄膜晶体管T2的漏极，并传输至所述第一发光单元11的阳极。所述第一发光单元11的阴极连接恒压低电平源，因此在t1~t2时间段所述第一发光单元11发光。
由于所述扫描信号线输出低电平信号，因此所述第三薄膜晶体管T3的开关无法打开。而在0~t1时间段，所述第二存储电容C2没有进行充电，因此在t1~t2时间段所述第二发光单元21不发光。
在t2~t3时间段，所述扫描信号线输出高电平信号，所述数据信号线输出低电平信号。
在本实施例中，所述第一薄膜晶体管T1的栅极与所述扫描信号线电连接，由于所述第一薄膜晶体管T1为N型晶体管，因此所述扫描信号线输入低电平信号无法将所述第一薄膜晶体管T1的开关打开，所述数据信号线输出的信号无法传输至所述第二薄膜晶体管T2。而所述第一存储电容C1无电容释放，所述第二薄膜晶体管T2处于关闭状态，因此所述像素单元的恒压高电平源VDD无法传输至所述第一发光单元11的阳极。因此在t2~t3时间段所述第一发光单元11不发光。
所述第三薄膜晶体管T3的栅极与所述扫描信号线电连接，由于所述第三薄膜晶体管T3为N型晶体管，因此所述扫描信号线输入高电平信号将所述第三薄膜晶体管T3的开关打开，所述数据信号线输入的低电平信号从所述第三薄膜晶体管T3的源极输入至所述第三薄膜晶体管T3的漏极，并传输至所述第四薄膜晶体管T4的栅极以及所述第二存储电容C2的第一电极板。
由于所述第四薄膜晶体管T4为P型薄膜晶体管，因此所述第三薄膜晶体管T3传输过来的低电平信号使得所述第四薄膜晶体管T4的开关打开，所述像素单元的恒压高电平源VDD通过所述第二薄膜晶体管T2的源极输入至所述第二薄膜晶体管T2的漏极，并传输至所述第二存储电容C2的第二电极板及所述第二发光单元21的阳极。所述第二存储电容C2处于充电状态。所述第二发光单元21的阴极连接恒压低电平源，因此在t2~t3时间段所述第二发光单元21发光。
在t3~t4时间段，所述扫描信号线及所述数据信号线输出低电平信号。
在本实施例中，所述第三薄膜晶体管T3的栅极与所述扫描信号线电连接，由于所述第三薄膜晶体管T3为N型晶体管，因此所述扫描信号线输入低电平信号无法将所述第一薄膜晶体管T1的开关打开，所述数据信号线输出的信号无法传输至所述第二薄膜晶体管T2。此时，所述第二存储电容C2处于放电状态，所述第二存储电容C2释放的低电平信号将所述第四薄膜晶体管T4打开，所述像素单元的恒压高电平源VDD通过所述第四薄膜晶体管T4的源极输入至所述第四薄膜晶体管T4的漏极，并传输至所述第二发光单元21的阳极。所述第二发光单元21的阴极连接恒压低电平源，因此在t3~t4时间段所述第二发光单元21发光。
由于所述扫描信号线输出低电平信号，因此所述第一薄膜晶体管T1的开关无法打开。而在t2~t3时间段，所述第一存储电容C1没有进行充电，因此在t3~t4时间段所述第一发光单元11不发光。
在一种实施例中，所述像素单元还可以包括第三区30。
所述第三区30设置有第三驱动电路32和第三发光单元31，所述第三驱动电路32与所述第三发光单元31电连接，所述第三驱动电路32用于驱动所述第三发光单元31发光。
在一种实施例中，所述第三驱动电路32的结构可以与所述第一驱动电路12或所述第二驱动电路22的结构相同。
请参阅图3，图3为本申请像素单元的第二种电路结构图。
所述第三驱动电路32的结构与所述第一驱动电路12的结构相同。
在0~t1时间段，所述扫描信号线及所述数据信号线输出高电平信号。所述第一发光单元11及所述第三发光单元31发光，所述第二发光单元21不发光。
在t1~t2时间段，所述扫描信号线输出低电平信号，所述数据信号线输出高电平信号。所述第一发光单元11及所述第三发光单元31发光，所述第二发光单元21不发光。
在t2~t3时间段，所述扫描信号线输出高电平信号，所述数据信号线输出低电平信号。所述第一发光单元11及所述第三发光单元31不发光，所述第二发光单元21发光。
在t3~t4时间段，所述扫描信号线及所述数据信号线输出低电平信号。所述第一发光单元11及所述第三发光单元31不发光，所述第二发光单元21发光。
在一种实施例中，所述第一发光单元11、所述第二发光单元21及所述第三发光单元31的颜色可以相同。
在一种实施例中，所述像素单元还可以包括第四发光单元13。
所述第四发光单元13可以位于所述第一区10或者所述第二区20内。
所述第四发光单元13位于所述第一区10内，第一驱动电路12与所述第四发光单元13电连接，所述第一驱动电路12用于驱动所述第一发光单元11及所述第四发光单元13发光。或者
所述第四发光单元13位于所述第二区20内，第二驱动电路22与所述第四发光单元13电连接，所述第二驱动电路22用于驱动所述第二发光单元21及所述第四发光单元13发光。
请参阅图4，图4为本申请像素单元的第三种电路结构图。
所述第四发光单元13位于所述第一区10内。所述第一驱动电路12同时控制所述第一发光单元11及所述第四发光单元13。
在一种实施例中，所述第四发光单元13的颜色与对应区域内发光单元的颜色相同。
由于在0~t1、t1~t2时间段，所述第一发光单元11及所述第四发光单元13发光，t2~t3、t3~t4时间段，所述第二发光单元21发光。因此在0~t2时间段，对应的显示设备发光亮度大于t2~t4时间段。当显示设备在暗光环境下，可以控制使像素单元处于t2~t4时间段。当显示设备在强光环境下时，可以控制使像素单元处于0~t2时间段。
本申请还提出了一种显示面板，所述显示面板包括上述像素单元。所述显示面板的工作原理与上述像素单元的相同或相似，本申请不再赘述。
本申请提出了一种像素单元及显示面板，该像素单元至少包括第一区和第二区；所述第一区至少设置有一第一发光单元，所述第二区至少设置有一第二发光单元。当所述像素单元处于工作状态时，所述第一发光单元、所述第二发光单元中的一者处于发光状态。本申请通过在一个像素单元内设置至少两个发光单元，一发光单元对应一驱动电路，通过对所述像素单元输入不同的驱动信号，使所述第一发光单元及所述第二发光单元交互工作，延长了有机发光二极管及薄膜晶体管的使用寿命，避免了显示面板出现残影等技术问题。
综上所述，虽然本申请已以优选实施例揭露如上，但上述优选实施例并非用以限制本申请，本领域的普通技术人员，在不脱离本申请的精神和范围内，均可作各种更动与润饰，因此本申请的保护范围以权利要求界定的范围为准。

Claims (18)

  1. 一种像素单元，其中，至少包括第一区和第二区；
    所述第一区至少设置有一第一发光单元；
    所述第二区至少设置有一第二发光单元；
    当所述像素单元处于工作状态时，所述第一发光单元、所述第二发光单元中的一者处于发光状态。
  2. 根据权利要求1所述的像素单元，其中，
    所述第一区还设置有第一驱动电路，所述第一驱动电路与所述第一发光单元电连接；
    所述第二区还设置有第二驱动电路，所述第二驱动电路与所述第二发光单元电连接；
    当所述像素单元处于工作状态时，所述第一驱动电路用于驱动所述第一发光单元发光、或者所述第二驱动电路用于驱动所述第二发光单元发光。
  3. 根据权利要求2所述的像素单元，其中，
    所述第一驱动电路至少包括第一薄膜晶体管、第二薄膜晶体管及第一存储电容；
    所述第二驱动电路至少包括第三薄膜晶体管、第四薄膜晶体管及第二存储电容；
    其中，所述第一薄膜晶体管、所述第二薄膜晶体管、所述第三薄膜晶体管、及所述第四薄膜晶体管为P型晶体管或N型晶体管中的一种；
    所述第四薄膜晶体管的晶体管类型与所述第一薄膜晶体管、所述第二薄膜晶体管、及所述第三薄膜晶体管相异。
  4. 根据权利要求3所述的像素单元，其中，
    所述第一薄膜晶体管的栅极与扫描信号线电连接，所述第一薄膜晶体管的源极/漏极与数据信号线电连接，所述第一薄膜晶体管的漏极/源极与所述第一存储电容的第一电极板及所述第二薄膜晶体管的栅极电连接；
    所述第二薄膜晶体管的源极/漏极与像素单元的输入端电连接，所述第二薄膜晶体管的漏极/源极与所述第一存储电容的第二电极板及所述第一发光单元电连接；
    所述第三薄膜晶体管的栅极与所述扫描信号线电连接，所述第三薄膜晶体管的源极/漏极与数据信号线电连接，所述第一薄膜晶体管的漏极/源极与所述第二存储电容的第一电极板及所述第二薄膜晶体管的栅极电连接；
    所述第四薄膜晶体管的源极/漏极与像素单元的输入端电连接及所述第二存储电容的第二电极板电连接，所述第四薄膜晶体管的漏极/源极与所述第二发光单元电连接。
  5. 根据权利要求1所述的像素单元，其中，
    所述第一发光单元和所述第二发光单元的颜色相同。
  6. 根据权利要求1所述的像素单元，其中，
    所述像素单元还包括第三区；
    所述第三区设置有第三驱动电路和第三发光单元，所述第三驱动电路与所述第三发光单元电连接；
    所述第三驱动电路的结构与第一驱动电路或第二驱动电路的结构相同。
  7. 根据权利要求6所述的像素单元，其中，所述第一发光单元、所述第二发光单元及所述第三发光单元的颜色相同。
  8. 根据权利要求1所述的像素单元，其中，
    所述像素单元还包括第四发光单元；
    所述第四发光单元位于所述第一区或者所述第二区内；
    所述第四发光单元的颜色与对应区域内发光单元的颜色相同。
  9. 根据权利要求8所述的像素单元，其中，
    所述第四发光单元位于所述第一区内；
    第一驱动电路与所述第四发光单元电连接，所述第一驱动电路用于驱动所述第一发光单元及所述第四发光单元发光；
    或者
    所述第四发光单元位于所述第二区内；
    第二驱动电路与所述第四发光单元电连接，所述第二驱动电路用于驱动所述第二发光单元及所述第四发光单元发光。
  10. 一种显示面板，包括像素单元，其中，
    所述像素单元包括至少包括第一区和第二区；
    所述第一区至少设置有一第一发光单元；
    所述第二区至少设置有一第二发光单元；
    当所述像素单元处于工作状态时，所述第一发光单元、所述第二发光单元中的一者处于发光状态。
  11. 根据权利要求10所述的显示面板，其中，
    所述第一区还设置有第一驱动电路，所述第一驱动电路与所述第一发光单元电连接；
    所述第二区还设置有第二驱动电路，所述第二驱动电路与所述第二发光单元电连接；
    当所述像素单元处于工作状态时，所述第一驱动电路用于驱动所述第一发光单元发光、或者所述第二驱动电路用于驱动所述第二发光单元发光。
  12. 根据权利要求11所述的显示面板，其中，
    所述第一驱动电路至少包括第一薄膜晶体管、第二薄膜晶体管及第一存储电容；
    所述第二驱动电路至少包括第三薄膜晶体管、第四薄膜晶体管及第二存储电容；
    其中，所述第一薄膜晶体管、所述第二薄膜晶体管、所述第三薄膜晶体管、及所述第四薄膜晶体管为P型晶体管或N型晶体管中的一种；
    所述第四薄膜晶体管的晶体管类型与所述第一薄膜晶体管、所述第二薄膜晶体管、及所述第三薄膜晶体管相异。
  13. 根据权利要求12所述的显示面板，其中，
    所述第一薄膜晶体管的栅极与扫描信号线电连接，所述第一薄膜晶体管的源极/漏极与数据信号线电连接，所述第一薄膜晶体管的漏极/源极与所述第一存储电容的第一电极板及所述第二薄膜晶体管的栅极电连接；
    所述第二薄膜晶体管的源极/漏极与像素单元的输入端电连接，所述第二薄膜晶体管的漏极/源极与所述第一存储电容的第二电极板及所述第一发光单元电连接；
    所述第三薄膜晶体管的栅极与所述扫描信号线电连接，所述第三薄膜晶体管的源极/漏极与数据信号线电连接，所述第一薄膜晶体管的漏极/源极与所述第二存储电容的第一电极板及所述第二薄膜晶体管的栅极电连接；
    所述第四薄膜晶体管的源极/漏极与像素单元的输入端电连接及所述第二存储电容的第二电极板电连接，所述第四薄膜晶体管的漏极/源极与所述第二发光单元电连接。
  14. 根据权利要求10所述的显示面板，其中，
    所述第一发光单元和所述第二发光单元的颜色相同。
  15. 根据权利要求10所述的显示面板，其中，
    所述像素单元还包括第三区；
    所述第三区设置有第三驱动电路和第三发光单元，所述第三驱动电路与所述第三发光单元电连接；
    所述第三驱动电路的结构与第一驱动电路或第二驱动电路的结构相同。
  16. 根据权利要求15所述的显示面板，其中，所述第一发光单元、所述第二发光单元及所述第三发光单元的颜色相同。
  17. 根据权利要求10所述的显示面板，其中，
    所述像素单元还包括第四发光单元；
    所述第四发光单元位于所述第一区或者所述第二区内；
    所述第四发光单元的颜色与对应区域内发光单元的颜色相同。
  18. 根据权利要求17所述的显示面板，其中，
    所述第四发光单元位于所述第一区内；
    第一驱动电路与所述第四发光单元电连接，所述第一驱动电路用于驱动所述第一发光单元及所述第四发光单元发光；
    或者
    所述第四发光单元位于所述第二区内；
    第二驱动电路与所述第四发光单元电连接，所述第二驱动电路用于驱动所述第二发光单元及所述第四发光单元发光。
PCT/CN2019/117882 2019-10-25 2019-11-13 像素单元及显示面板 Ceased WO2021077487A1 (zh)

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