WO2021072731A1 - Structure d'emballage de puce à semi-conducteurs, procédé d'emballage et dispositif électronique - Google Patents

Structure d'emballage de puce à semi-conducteurs, procédé d'emballage et dispositif électronique Download PDF

Info

Publication number
WO2021072731A1
WO2021072731A1 PCT/CN2019/111874 CN2019111874W WO2021072731A1 WO 2021072731 A1 WO2021072731 A1 WO 2021072731A1 CN 2019111874 W CN2019111874 W CN 2019111874W WO 2021072731 A1 WO2021072731 A1 WO 2021072731A1
Authority
WO
WIPO (PCT)
Prior art keywords
end surface
edge
interval
semiconductor
emitting
Prior art date
Application number
PCT/CN2019/111874
Other languages
English (en)
Chinese (zh)
Inventor
罗飞宇
Original Assignee
深圳市大疆创新科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 深圳市大疆创新科技有限公司 filed Critical 深圳市大疆创新科技有限公司
Priority to CN201980034236.8A priority Critical patent/CN113016079B/zh
Priority to PCT/CN2019/111874 priority patent/WO2021072731A1/fr
Publication of WO2021072731A1 publication Critical patent/WO2021072731A1/fr

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages

Definitions

  • the semiconductor light-emitting chip has a light-emitting end surface and a second end surface opposite to the light-emitting end surface; when the semiconductor light-emitting chip is fixed to the first carrying surface through the first solder layer, the second edge extends beyond the The second end surface forms a second interval with the second end surface, and the light-emitting end surface extends beyond the first edge or is flush with the first edge;
  • a semiconductor packaging method includes:
  • Fig. 3 is a left side view of a conventional semiconductor packaging structure
  • the third interval and the fourth interval can also be used for accommodating a small portion of the solder diffusion part like the first interval.
  • the third interval and the fourth interval may be equal, and specifically, both the third interval and the fourth interval are equal to the first interval.
  • the first solder layer may be a prefabricated solder sheet, and the first solder layer may be disposed on the first bearing surface of the first carrier table in advance.
  • a thin film process may be used to prefabricate the first solder layer on the first bearing surface of the first stage.
  • the thin film process includes a coating process and a patterned etching process, and the specific implementation method can be referred to the prior art, which will not be described in detail here.
  • a plurality of semiconductor chips can be packaged on the substrate at one time, specifically: a plurality of first slide stages are arranged on the substrate; at the same time, the first substrates respectively arranged on the respective first bearing surfaces of the plurality of first slide stages
  • the solder layer is heated to obtain molten solder; a plurality of semiconductor chips are mounted on the molten solder on the respective first bearing surfaces of the plurality of first carrier tables in one-to-one correspondence;
  • the molten solder on the first carrying surface is cooled, so that the plurality of semiconductor chips are fixed on the first carrying surface of each of the plurality of first slide tables in one-to-one correspondence.
  • the material of the first solder layer 302 is specifically a metal material, including: a single metal material or an alloy material.
  • the material of the first solder layer 302 may be one of PbSn, SnAgCu, SnBi, AuSn, Sn, and InP.
  • the semiconductor light emitting chip 303 further has a fourth end surface 3034 opposite to the third end surface 3033; the first bearing surface also has a fourth edge that extends beyond the fourth end surface 3034 3014; A fourth gap is formed between the fourth end surface 3034 and the fourth edge 3014; the fourth gap is smaller than the second gap.
  • the fourth end surface 3034 is also connected to the light emitting end surface 3031 and the second end surface 3032.
  • each light emitting unit 30 there are multiple light emitting units 30 arranged on the substrate 300; multiple light emitting units 30 are arranged side by side and spaced apart on the substrate 300; the multiple light emitting units
  • the light-emitting end surfaces of the semiconductor light-emitting chips 303 in each light-emitting unit in 30 are located on the same side.
  • the light-emitting end surface of the semiconductor light-emitting chip 303 in each light-emitting unit of the plurality of light-emitting units 30 all faces the reflector 400.
  • Another embodiment of the present application further provides an electronic device, which includes the semiconductor light-emitting chip packaging structure in each of the foregoing embodiments.
  • the specific implementation of the semiconductor light-emitting chip packaging structure can refer to the relevant content in the above-mentioned embodiments, which will not be repeated here.
  • the material of the first solder layer 302 is specifically a metal material, including: a single metal material or an alloy material.
  • the material of the first solder layer 302 may be one of PbSn, SnAgCu, SnBi, AuSn, Sn, and InP.
  • the third interval and the fourth interval can also be used to accommodate a small portion of the solder diffusion portion.
  • the third interval and the fourth interval may be equal. It needs to be added that the third interval and the fourth interval are both smaller than the second interval.
  • the above-mentioned guiding area is provided on the second end face 3032 side of the semiconductor light-emitting chip 303, so that the excess molten solder can be directionally guided and accommodated, so that the distance between the semiconductor light-emitting chips in any adjacent two light-emitting units is It can be reduced to 10um ⁇ 70um, which can effectively improve the integration of semiconductor packaging structure, and can also effectively reduce the scanning blind area and improve the scanning resolution.
  • solder bridging short-circuit problem can also effectively improve the integration.

Abstract

La présente invention concerne une structure d'emballage de puce à semi-conducteurs, un procédé d'emballage et un dispositif électronique. La structure d'emballage comprend des unités électroluminescentes (30) et un réflecteur (400) qui sont disposés sur un substrat (300). Chacune des unités électroluminescentes (30) comprend : un premier étage de puce (301) disposé sur le substrat (300) ; une première couche de brasure (302) disposée sur une première surface d'appui du premier étage de puce (301) ; et une puce électroluminescente à semi-conducteurs (303) ayant une surface d'extrémité de sortie de lumière (3031) et une seconde surface d'extrémité (3032) opposée à la surface d'extrémité de sortie de lumière (3031). Lorsque la puce électroluminescente à semi-conducteurs (303) est fixée sur la première surface d'appui au moyen de la première couche de brasure (302), la première surface d'appui a un premier bord (3011) s'étendant au-delà de la surface d'extrémité de sortie de lumière (3031) et un second bord (3012) s'étendant au-delà de la seconde surface d'extrémité (3032), et un premier espacement formé entre la surface d'extrémité de sortie de lumière (3031) et le premier bord (3011) est inférieur à un second espacement formé entre la seconde surface d'extrémité (3032) et le second bord (3012). Le réflecteur (400) a au moins une surface réfléchissante, et la surface réfléchissante est proche de la surface d'extrémité de sortie de lumière (3031). La structure peut guider et recevoir l'excès de brasure en débordement et empêcher la brasure de déborder de l'étage de puce.
PCT/CN2019/111874 2019-10-18 2019-10-18 Structure d'emballage de puce à semi-conducteurs, procédé d'emballage et dispositif électronique WO2021072731A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN201980034236.8A CN113016079B (zh) 2019-10-18 2019-10-18 半导体芯片封装结构、封装方法及电子设备
PCT/CN2019/111874 WO2021072731A1 (fr) 2019-10-18 2019-10-18 Structure d'emballage de puce à semi-conducteurs, procédé d'emballage et dispositif électronique

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2019/111874 WO2021072731A1 (fr) 2019-10-18 2019-10-18 Structure d'emballage de puce à semi-conducteurs, procédé d'emballage et dispositif électronique

Publications (1)

Publication Number Publication Date
WO2021072731A1 true WO2021072731A1 (fr) 2021-04-22

Family

ID=75537658

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2019/111874 WO2021072731A1 (fr) 2019-10-18 2019-10-18 Structure d'emballage de puce à semi-conducteurs, procédé d'emballage et dispositif électronique

Country Status (2)

Country Link
CN (1) CN113016079B (fr)
WO (1) WO2021072731A1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115090491A (zh) * 2022-07-13 2022-09-23 北京无线电测量研究所 一种微小型高密度载片贴片工装和贴片方法

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101156236A (zh) * 2005-04-06 2008-04-02 松下电器产业株式会社 倒装片安装方法及凸块形成方法
US20120181678A1 (en) * 2010-07-29 2012-07-19 Nxp B.V. Leadless chip carrier having improved mountability
CN203910779U (zh) * 2014-06-26 2014-10-29 三垦电气株式会社 半导体装置
CN104201120A (zh) * 2014-08-28 2014-12-10 南通富士通微电子股份有限公司 半导体倒装封装方法
CN204732400U (zh) * 2015-06-11 2015-10-28 亚昕科技股份有限公司 引线框架结构
US20160003436A1 (en) * 2013-02-08 2016-01-07 Osram Opto Semiconductors Gmbh Optoelectronic Lighting Module, Optoelectronic Lighting Apparatus and Vehicle Headlamp
CN106856218A (zh) * 2016-12-20 2017-06-16 创维液晶器件(深圳)有限公司 一种免封装led结构及其制作方法

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008198841A (ja) * 2007-02-14 2008-08-28 Elpida Memory Inc 半導体装置
JP4966283B2 (ja) * 2008-10-14 2012-07-04 シャープ株式会社 半導体レーザ装置およびその製造方法
US8686461B2 (en) * 2011-01-03 2014-04-01 SemiLEDs Optoelectronics Co., Ltd. Light emitting diode (LED) die having stepped substrates and method of fabrication
TWI633686B (zh) * 2016-06-23 2018-08-21 億光電子工業股份有限公司 發光二極體及其製作方法

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101156236A (zh) * 2005-04-06 2008-04-02 松下电器产业株式会社 倒装片安装方法及凸块形成方法
US20120181678A1 (en) * 2010-07-29 2012-07-19 Nxp B.V. Leadless chip carrier having improved mountability
US20160003436A1 (en) * 2013-02-08 2016-01-07 Osram Opto Semiconductors Gmbh Optoelectronic Lighting Module, Optoelectronic Lighting Apparatus and Vehicle Headlamp
CN203910779U (zh) * 2014-06-26 2014-10-29 三垦电气株式会社 半导体装置
CN104201120A (zh) * 2014-08-28 2014-12-10 南通富士通微电子股份有限公司 半导体倒装封装方法
CN204732400U (zh) * 2015-06-11 2015-10-28 亚昕科技股份有限公司 引线框架结构
CN106856218A (zh) * 2016-12-20 2017-06-16 创维液晶器件(深圳)有限公司 一种免封装led结构及其制作方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115090491A (zh) * 2022-07-13 2022-09-23 北京无线电测量研究所 一种微小型高密度载片贴片工装和贴片方法
CN115090491B (zh) * 2022-07-13 2024-04-26 北京无线电测量研究所 一种微小型高密度载片贴片工装和贴片方法

Also Published As

Publication number Publication date
CN113016079A (zh) 2021-06-22
CN113016079B (zh) 2022-06-24

Similar Documents

Publication Publication Date Title
US6940704B2 (en) Semiconductor light emitting device
US9978915B2 (en) Manufacturing method of a flip-chip light emitting diode package module
US9058971B2 (en) Electro-optical module
EP0313174B1 (fr) Méthode de production de dispositifs optiques et de boîtiers
US8598602B2 (en) Light emitting device packages with improved heat transfer
US7462880B2 (en) Semiconductor light-emitting element assembly
US20080194054A1 (en) Led array package structure having silicon substrate and method of making the same
TW200915616A (en) Semiconductor light-emitting device
JP2013153136A (ja) 発光モジュール及び光トランシーバ
US11862929B2 (en) Laser diode packaging module, distance detection device, and electronic device
JP2018152465A (ja) 半導体モジュール
WO2021072731A1 (fr) Structure d'emballage de puce à semi-conducteurs, procédé d'emballage et dispositif électronique
KR20210119310A (ko) 반도체 패키지용 헤더, 및 반도체 패키지
WO2017163593A1 (fr) Module semi-conducteur et son procédé de fabrication
TW201511192A (zh) 有受控模造邊界的層壓無引線載體組件中的光半導體元件及形成該元件之方法
EP2820726B1 (fr) Boîtier de puce laser à semi-conducteurs, avec renfoncement encapsulé, moulé sur substrat, et procédé de formation de celui-ci
CN107749561B (zh) 一种半导体激光器封装结构及其制备方法
CN211320093U (zh) 半导体发光芯片封装结构及电子设备
US20150060894A1 (en) Light Emitting Device
WO2023089059A2 (fr) Boîtier laser et procédé de fabrication d'un boîtier laser
KR101433248B1 (ko) 발광장치 및 이를 포함하는 백라이트 유닛
JP5179106B2 (ja) 半導体発光装置
JP4166471B2 (ja) 光モジュール
KR20040020239A (ko) 고출력 ｌｅｄ를 위한 역피라미드형 플립 칩
JP2012222128A (ja) パワーモジュール

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 19949460

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 19949460

Country of ref document: EP

Kind code of ref document: A1