WO2021072731A1

WO2021072731A1 - Semiconductor chip packaging structure, packaging method, and electronic device

Info

Publication number: WO2021072731A1
Application number: PCT/CN2019/111874
Authority: WO
Inventors: 罗飞宇
Original assignee: 深圳市大疆创新科技有限公司
Priority date: 2019-10-18
Filing date: 2019-10-18
Publication date: 2021-04-22
Also published as: CN113016079B; CN113016079A

Abstract

A semiconductor chip packaging structure, a packaging method, and an electronic device. The packaging structure comprises light emitting units (30) and a reflector (400) which are provided on a substrate (300). Each of the light emitting units (30) comprises: a first chip stage (301) provided on the substrate (300); a first solder layer (302) provided on a first bearing surface of the first chip stage (301); and a semiconductor light emitting chip (303) having a light exiting end surface (3031) and a second end surface (3032) opposite to the light exiting end surface (3031). When the semiconductor light emitting chip (303) is fixed on the first bearing surface by means of the first solder layer (302), the first bearing surface has a first edge (3011) going beyond the light exiting end surface (3031) and a second edge (3012) going beyond the second end surface (3032), and a first spacing formed between the light exiting end surface (3031) and the first edge (3011) is smaller than a second spacing formed between the second end surface (3032) and the second edge (3012). The reflector (400) has at least one reflecting surface, and the reflecting surface is close to the light exiting end surface (3031). The structure can guide and accommodate overflowing excess solder and prevent the solder from overflowing the chip stage.

Description

Semiconductor chip packaging structure, packaging method and electronic equipment

Technical field

This application relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor chip packaging structure, packaging method, and electronic equipment.

Background technique

At present, the semiconductor production process consists of wafer manufacturing, wafer testing, chip packaging, and post-package testing.

In the chip packaging process, the required chips are soldered to the substrate to obtain the semiconductor packaging structure. Then, the semiconductor package structure that has passed the test is applied to various electronic devices.

Summary of the invention

The present application provides a semiconductor chip packaging structure, packaging method, and electronic equipment to guide and contain the excess part of the molten solder overflowing under the extrusion of the semiconductor light-emitting chip, so as to avoid the problem of the molten solder overflowing the stage.

Therefore, in an embodiment of the present application, a semiconductor light emitting chip packaging structure is provided. The semiconductor light emitting chip packaging structure includes:

Substrate

A light emitting unit and a reflecting mirror arranged on the substrate;

Wherein, the light-emitting unit includes:

The first slide table is set on the substrate;

The first solder layer is arranged on the first bearing surface of the first slide table;

The semiconductor light-emitting chip has a light-emitting end surface and a second end surface opposite to the light-emitting end surface; when the semiconductor light-emitting chip is fixed to the first bearing surface by the first solder layer, the first bearing surface has A first edge that extends beyond the light-emitting end surface and a second edge that extends beyond the second end surface. The first interval formed by the light-emitting end surface and the first edge is smaller than that formed by the second end surface and the second edge. Second interval

The reflecting mirror has at least one reflecting surface, and the reflecting surface is close to the light emitting end surface.

In yet another embodiment of the present application, an electronic device is provided. The device includes the semiconductor light-emitting chip packaging structure described above.

In yet another embodiment of the present application, a semiconductor packaging method is provided. The method includes: heating a first solder layer provided on a first bearing surface of a first slide table to obtain molten solder; the first slide table is provided on a substrate;

Mounting a semiconductor light-emitting chip on the molten solder;

Cooling the molten solder so that the semiconductor light-emitting chip is fixed on the first carrying surface;

Wherein, the semiconductor light-emitting chip has a light-emitting end surface and a second end surface opposite to the light-emitting end surface; when the semiconductor light-emitting chip is fixed to the first bearing surface through the first solder layer, the first A bearing surface has a first edge that extends beyond the light-emitting end surface and a second edge that extends beyond the second end surface. The first interval formed by the light-emitting end surface and the first edge is smaller than the second end surface and the first edge. The second interval formed by the two edges.

In an embodiment of the present application, a semiconductor light emitting chip packaging structure is provided. The semiconductor light emitting chip packaging structure includes:

Substrate

A light emitting unit and a reflecting mirror arranged on the substrate;

Wherein, the light-emitting unit includes:

The first slide table is set on the substrate;

The first solder layer is arranged on the first bearing surface of the first slide table; the first bearing surface has a first edge and a second edge opposite to each other;

The semiconductor light-emitting chip has a light-emitting end surface and a second end surface opposite to the light-emitting end surface; when the semiconductor light-emitting chip is fixed to the first carrying surface through the first solder layer, the second edge extends beyond the The second end surface forms a second interval with the second end surface, and the light-emitting end surface extends beyond the first edge or is flush with the first edge;

In yet another embodiment of the present application, a semiconductor packaging method is provided. The method includes:

The first solder layer arranged on the first bearing surface of the first stage is heated to obtain molten solder; the first stage is arranged on the substrate, and the first bearing surface has opposite first edges And the second edge;

Mounting a semiconductor light-emitting chip on the molten solder;

Wherein, the semiconductor light-emitting chip has a light-emitting end surface and a second end surface opposite to the light-emitting end surface; when the semiconductor light-emitting chip is fixed to the first bearing surface through the first solder layer, the first Two edges extend beyond the second end surface and form a second gap with the second end surface, and the light-emitting end surface extends beyond the first edge or is flush with the first edge.

In an embodiment of the present application, a semiconductor chip packaging structure is provided. The semiconductor chip packaging structure includes:

Substrate

A first unit arranged on the substrate;

Wherein, the first unit includes:

The first slide table is set on the substrate;

The semiconductor chip has a first end surface and a second end surface opposite to the first end surface; when the semiconductor chip is fixed to the first bearing surface through the first solder layer, the first bearing surface has an overhang The first edge of the first end surface and the second edge beyond the second end surface, the first interval formed by the first end surface and the first edge is smaller than that formed by the second end surface and the second edge The second interval.

In yet another embodiment of the present application, an electronic device is provided. The device includes the semiconductor chip packaging structure described above.

Heating the first solder layer provided on the first bearing surface of the first slide table to obtain molten solder; the first slide table is provided on the substrate;

Mounting a semiconductor chip on the molten solder;

Cooling the molten solder so that the semiconductor chip is fixed on the first carrying surface;

Wherein, the semiconductor chip has a first end surface and a second end surface opposite to the first end surface; when the semiconductor chip is fixed to the first bearing surface through the first solder layer, the first The bearing surface has a first edge that extends beyond the first end surface and a second edge that extends beyond the second end surface. The first interval formed by the first end surface and the first edge is smaller than that between the second end surface and the second edge. The second interval formed by the second edge.

Substrate

A first unit arranged on the substrate;

Wherein, the first unit includes:

The first slide table is set on the substrate;

A semiconductor chip has a first end surface and a second end surface opposite to the first end surface; when the semiconductor chip is fixed to the first carrying surface through the first solder layer, the second edge extends beyond the The second end surface forms a second interval with the second end surface, and the first end surface extends beyond the first edge or is flush with the first edge.

Mounting a semiconductor chip on the molten solder;

Wherein, the semiconductor chip has a first end surface and a second end surface opposite to the first end surface; when the semiconductor chip is fixed to the first carrying surface through the first solder layer, the second The edge extends beyond the second end surface and forms a second interval with the second end surface, and the first end surface extends beyond the first edge or is flush with the first edge.

In the technical solution provided by the embodiments of the present application, when the semiconductor light-emitting chip is fixed to the first bearing surface of the first stage by soldering, a gap is formed between the second edge of the first bearing surface and the second end surface of the semiconductor light-emitting chip. The second interval is greater than the first interval formed between the first edge of the first carrying surface and the light-emitting end surface of the semiconductor light-emitting chip. In this way, the area where the first bearing surface is located at the second interval can guide and contain the excess part of the molten solder overflowing under the extrusion of the semiconductor light-emitting chip when the semiconductor light-emitting chip is soldered, so as to prevent the molten solder from overflowing the stage. .

In the technical solution provided by the embodiments of the present application, when the semiconductor light-emitting chip is fixed to the first bearing surface of the first stage by soldering, there is no need to reserve a first gap on the first edge side of the first bearing surface, so that A larger second gap is reserved on the second edge side of the first bearing surface, so that the area where the first bearing surface is located at the second gap can guide and accommodate the molten solder on the semiconductor light-emitting chip when the semiconductor light-emitting chip is soldered. Squeeze the excess part that overflows underneath to prevent molten solder from overflowing the slide table.

Description of the drawings

The drawings described here are used to provide a further understanding of the application and constitute a part of the application. The exemplary embodiments and descriptions of the application are used to explain the application, and do not constitute an improper limitation of the application. In the attached picture:

Fig. 1 is a rear view of a conventional semiconductor packaging structure;

FIG. 2 is a top view of a conventional semiconductor packaging structure;

Fig. 3 is a left side view of a conventional semiconductor packaging structure;

4 is a top view of a conventional semiconductor package structure with solder overflow;

FIG. 5 is a top view of the first semiconductor package structure provided by an embodiment of the application;

6 is a left side view of the first semiconductor package structure provided by an embodiment of the application;

FIG. 7 is a diagram of the first structural state during welding provided by an embodiment of the application;

8 is a left side view of the first semiconductor package structure with solder accumulation provided by an embodiment of the application;

FIG. 9 is a top view of the first semiconductor package structure with solder accumulation provided by an embodiment of the application; FIG.

FIG. 10 is a top view of a second semiconductor package structure provided by an embodiment of the application;

FIG. 11 is a top view of a third semiconductor package structure provided by an embodiment of the application;

FIG. 12 is a rear view of the first semiconductor package structure provided by an embodiment of the application;

FIG. 13 is a left side view of a fourth semiconductor package structure provided by an embodiment of the application;

FIG. 14 is a left side view of a fifth semiconductor package structure provided by an embodiment of the application;

15 is a schematic flowchart of a semiconductor packaging method provided by an embodiment of the application;

FIG. 16 is a schematic flowchart of a semiconductor packaging method provided by another embodiment of this application.

Detailed ways

In order to make the purpose, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described clearly and completely in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments It is a part of the embodiments of the present application, but not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without creative work shall fall within the protection scope of this application.

Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the technical field of this application. The terminology used in the specification of the application herein is only for the purpose of describing specific embodiments, and is not intended to limit the application.

In order to facilitate the understanding of the technical solutions and technical effects of this application, a brief description will be given below in conjunction with the lidar in the prior art:

Lidar is a perception system of the outside world, which can learn the three-dimensional three-dimensional information of the outside world. Its principle is to actively transmit laser pulse signals to the outside, detect the reflected echo signal, and judge the distance of the measured object according to the time difference between transmission and reception. ; Combined with the emission direction information of the light pulse, the three-dimensional depth information of the object can be reconstructed.

How to measure as many azimuths as possible in the field of view within a specific time is a technical difficulty of lidar. One solution is to use a multi-line light source to detect multiple directions, which can effectively increase the orientation of the detection, thereby obtaining environmental data with higher spatial resolution.

In a multi-line laser sensor, it is expected that the emitting end chips of different channels can emit light in a time-sharing manner, which can reduce the total peak radiation power, meet laser safety regulations, and avoid harm to human eyes. In addition, time-sharing lighting also helps to reduce the mutual interference between different channels and improve the performance of the system. Semiconductor laser diodes have been widely used in laser radars due to their ease of mass production and low cost. Since the divergence angle of the light radiated by the laser diode is usually very large, it is usually necessary to use a lens for collimation, which requires fine adjustment of the relative position of the laser diode and the lens.

When packaging a multi-line laser sensor, it is expected that the spacing between the transmitter chips of different channels is as small as possible, so as to obtain a smaller sensor spacing, which can not only improve the integration level, but also reduce the detection blind area in a certain period of time. Higher resolution. However, the smaller the distance between the chip and the chip, the more likely it is that the solder bridging short-circuit problem occurs when the chip is soldered to the substrate. In order to avoid this problem, the prior art usually designs the gap between the chip and the chip to be greater than or equal to 150um, which will lead to a larger chip-to-chip distance, which not only leads to lower integration, but also leads to a relatively low detection blind area of the laser sensor. Big.

Figures 1 and 2 show a semiconductor light emitting chip packaging structure commonly used in the prior art. Among them, the semiconductor light emitting chip is usually a light emitting diode chip, the top surface (Top surface) of the light emitting diode chip is P pole, and the bottom surface (Bottom surface) of the light emitting diode chip is N pole. Since the external drive adopts N-pole driving, the N-poles of all light-emitting diode chips must be separated, and the short-circuit of the N-pole bridge of the light-emitting diode chip will cause the laser sources in the multi-line laser chip array to emit light at the same time. The laser source emits light at the same time, not only will there be interference between different lines, but at the same time, the output power is large, which is easy to cause damage to the human eyes.

As shown in Figure 1 (rear view), Figure 2 (top view) and Figure 3 (left view), the stage 101, the solder 102 and the chip 103 are designed to be centered up and down, and the chip 103 is thermally soldered to the substrate 100 during the process of melting The solder 102 is diffused and overflowed around the stage 101 under the squeeze force of the chip 103, and it is prone to disorder and uncontrollable random solder bridging short circuits (as shown in FIG. 4). In order to avoid the problem of solder bridging short circuit, the gap between the chip and the chip usually needs to be designed to be greater than or equal to 150um in the prior art. However, such a design will make the chip-to-chip spacing larger, which not only leads to a lower degree of integration of the package structure, but also leads to problems such as an increase in the detection blind area of the sensor and a reduction in resolution. It should be supplemented that a reflector 200 is usually provided on the substrate 100 to reflect the light emitted by the chip.

Hereinafter, some embodiments of the present application will be described in detail with reference to the accompanying drawings. As long as there is no conflict between the various embodiments, the following embodiments and the features in the embodiments can be combined with each other.

5 and 6 show schematic structural diagrams of a semiconductor chip packaging structure provided by an embodiment of the present application. As shown in FIGS. 5 and 6, the semiconductor chip packaging structure includes: a substrate 300; a first unit 30 disposed on the substrate 300; wherein, the first unit 30 includes: a first stage 301 , Disposed on the substrate 300; a first solder layer 302, disposed on the first bearing surface of the first stage 301; a semiconductor chip 303, having a first end surface 3031 and opposite to the first end surface 3031 When the semiconductor chip 303 is fixed to the first bearing surface by the first solder layer 302, the first bearing surface has a first edge 3011 that extends beyond the first end surface 3031 and Exceeding the second edge 3012 of the second end face 3032, the first interval formed by the first end face 3031 and the first edge 3011 is smaller than the second interval formed by the second end face 3032 and the second edge 3012 .

In the semiconductor package structure provided by the embodiment of the present application, the mounting positions of the mounting table 301, the first solder layer 302, and the semiconductor chip 303 are in a non-centered alignment structure, and the first solder layer 302 and the semiconductor chip 303 are close to the first The first edge 3011 side of the slide table 301 is arranged to leave a space on the second edge 3012 side of the first slide table 301.

Wherein, the second interval is greater than the first interval, so that the flow resistance of the molten solder at the second interval on the first bearing surface is smaller than the flowing resistance at the first interval on the first bearing surface, that is, the first bearing surface The upper area at the second interval (hereinafter referred to as the guiding area) plays a role of directional guiding and accommodating the molten solder.

During the high temperature soldering process of the chip, the solder provided on the first bearing surface of the first stage 301 may be heated first to melt the solder. Due to capillary action, the molten solder will spread around the first stage 301, and the area of the solder will increase compared to before it melted. At the same time, due to the effect of surface tension, the molten solder presents a drop-like shape with a height in the middle and a low periphery (as shown in Figure 7). Due to the guiding effect of the guiding area, the molten solder is shifted to one side of the guiding area, so that the center of the molten solder is shifted from the center of the semiconductor chip 303.

When the semiconductor chip is placed on the molten solder through the suction head for pressure welding, the molten solder spreads around the first stage 301 under the action of the squeezing force, because the insulating layer on the substrate located around the first stage will melt The solder has a certain blocking effect, and the resistance on the side of the guide area is the least. The molten solder accelerates to the side of the guide area under the extrusion of the semiconductor chip 303, and finally accumulates in the guide area (as shown in FIG. 8). The guiding area has a better guiding effect, thereby improving the problem that the molten solder overflows randomly under the squeezing force and causes a bridge short circuit.

As shown in FIG. 5, the first edge 3011 and the second edge 3012 of the first bearing surface are disposed opposite to each other.

Wherein, the first stage 301 may include a contact surface with the substrate. The contact surface and the bearing surface may be two opposite end surfaces of the first slide table 301.

In the technical solution provided by the embodiments of the present application, when the semiconductor chip is fixed to the first bearing surface of the first stage by soldering, the second edge formed between the second edge of the first bearing surface and the second end surface of the semiconductor chip The interval is greater than the first interval formed between the first edge of the first carrying surface and the light-emitting end surface of the semiconductor chip. In this way, the area where the first bearing surface is located at the second interval can guide and contain the excess part of the molten solder overflowing under the extrusion of the semiconductor chip when the semiconductor chip is soldered, so as to prevent the molten solder from overflowing the slide table. Avoiding the molten solder overflowing the stage, also avoids the molten solder flowing into the insulating grooves (gaps) between the stage and other chips on the substrate, causing solder bridging and short-circuit problems. Using the technical solution provided by the embodiments of the present application can effectively improve the packaging yield and reduce the packaging cost.

In addition, with the technical solution provided by the embodiments of the present application, it is only necessary to design such a solder guide area on one side of the semiconductor chip, and the distance between the other side of the semiconductor chip and other chips can be designed to be very small. The problem of solder bridging short circuit will occur, and the integration can be effectively improved. In order to play a better guiding role, the difference between the second interval and the first interval may be greater than 5 microns.

The inventor found through experiments that when the difference between the second interval and the first interval is greater than or equal to 10 microns, the flow resistance of the molten solder at the second interval on the first bearing surface can be made significantly smaller than that on the first bearing surface. The flow resistance at the first interval can improve the guiding effect.

In practical applications, the size of the semiconductor package structure is required, so the second interval will not be designed to be very large. In an example, the difference between the second interval and the first interval may be 10-100 microns.

In a specific example, the difference between the second interval and the first interval may be 15 microns.

In another specific example, the difference between the second interval and the first interval may be 20 microns.

In another specific example, the difference between the second interval and the first interval may be 25 microns.

In another specific example, the difference between the second interval and the first interval may be 30 microns.

The increment of the difference between the second interval and the first interval in multiples of 5 microns is just an exemplary illustration. The difference between the second interval and the first interval may vary in units of 1 micron or less, for example, 11 microns, 12 Micron, 13 microns, 14 microns, 15 microns and so on. The size difference can be different according to the size of the solder layer on the stage, the specific size of the first interval and the second interval, and the molten state.

In practical applications, the specific value of the difference between the second interval and the first interval needs to be determined in combination with the thickness of the solder, the composition of the solder, the area of the semiconductor chip, and the packaging process conditions, which are not specifically limited in the embodiment of the present application.

The material of the first solder layer 302 is specifically a metal material, including: a single metal material or an alloy material. For example, the material of the first solder layer 302 may be one of PbSn, SnAgCu, SnBi, AuSn, Sn, and InP.

Among them, the first stage 301 may specifically be a metal stage, and its material may be a single metal material or an alloy material, for example: the material of the first stage 301 may be W, Cu, WNiAu, NiAu, Ag, TiNiPtAu One of, Pd, TiPtAu, NiPdAu, WTiNiPtAu.

It needs to be supplemented that the diffusion method of the solder of different materials on the metal stage of different materials is different. In practical applications, the solder and metal carrier materials can be designed according to actual needs. For example, when the solder layer material uses PbSn, and the stage material uses W, Cu or other materials, due to the different microscopic forces between the materials, the molten solder spreads differently on the stage, and different settings are set. The first interval, the second interval, and the difference between the first interval and the second interval are adjusted. More specifically, it is also possible to adjust the third interval and the fourth interval on both sides of the chip and the stage according to different combinations of solder and stage material. As mentioned above, when the second interval is greater than the first interval, the molten solder will flow in the direction of the second interval due to the microscopic force. This phenomenon is more obvious when the spacing difference is greater than 10 microns. A reasonable placement of the chip during soldering can ensure that the molten solder flows in the second spacing direction and avoids flowing out of the slide table.

The first stage 301 can be obtained by coating and patterning the substrate 300.

It needs to be supplemented that, in actual applications, the first slide table may be a semiconductor slide table with metal wires arranged inside and on the surface in addition to a metal slide table.

The inventor’s further research found that after adopting the semiconductor package structure provided by the embodiments of the present application, the overflow part of the molten solder in the guide area is mainly concentrated in the middle part of the guide area (as shown in FIG. 9), that is, the first load The film stage 301 at the two ends of the second edge 3012 does not actually serve to contain the overflowing molten solder. Therefore, notches 3015 can be provided on the first stage 301 at the two ends of the second edge 3012. In this way, the area occupied by the first slide table on the substrate can be reduced, the integration degree of the semiconductor packaging can be improved, and the overall weight of the semiconductor packaging structure can be reduced at the same time. As shown in FIG. 5, the first slide table 301 is provided with notches 3015 at both ends of the second edge 3012, so as to form protrusions at the first slide table 301 at the second interval. .

It should be supplemented that by providing notches at both ends of the second edge 3012, the overflow solder guided to the guiding area can be further prevented from spreading to both ends of the second edge 3012, thereby avoiding the contact with the first bearing surface. The other chips on the third edge 3013 side and the fourth edge 3014 side adjacent to the second edge 3012 have the problem of solder bridging shorting.

In specific implementation, the shape of the above-mentioned notch 3015 can be designed according to actual needs, which is not specifically limited in the embodiment of the present application.

In an example, the first bearing surface includes a first area located on the protrusion; the first area is rectangular (as shown in FIG. 9), triangle (as shown in FIG. 10), or semi-ellipse Shape (as shown in Figure 11). That is, the above-mentioned protrusion is specifically a convex rectangular portion (as shown in FIG. 9), a triangular portion (as shown in FIG. 10), or a semi-elliptical portion (as shown in FIG. 11).

Due to the capillary action, the molten solder will spread around the first stage 301, and the area of the solder will increase compared to before melting. Therefore, the above-mentioned first space can be used to accommodate a small portion of the solder spreading part.

Further, as shown in FIG. 12, the semiconductor chip 303 further has a third end surface 3033 connecting the first end surface 3031 and the second end surface 3032; the first bearing surface also has a third end surface that extends beyond the third end surface. The third edge 3013 of 3033; a third interval is formed between the third end surface 3033 and the third edge 3013; the third interval is smaller than the second interval.

Further, as shown in FIG. 12, the semiconductor chip 303 further has a fourth end surface 3034 opposite to the third end surface 3033; the first bearing surface also has a fourth edge 3014 that extends beyond the fourth end surface 3034 A fourth interval is formed between the fourth end surface 3034 and the fourth edge 3014; the fourth interval is smaller than the second interval.

Wherein, the fourth end surface 3034 is also connected to the first end surface 3031 and the second end surface 3032.

Wherein, as shown in FIG. 5, the third edge 3013 and the fourth edge 3014 are two edges opposite to the first bearing surface.

Among them, the third interval and the fourth interval can also be used for accommodating a small portion of the solder diffusion part like the first interval. The third interval and the fourth interval may be equal, and specifically, both the third interval and the fourth interval are equal to the first interval.

When the semiconductor chip is placed on the molten solder for extrusion, the third interval and the fourth interval can provide more flow channels for the solder to move to the second interval on the first stage, which helps the excess solder to flow The flow of the first stage at the second interval improves the guiding effect.

It should be noted that when the above-mentioned first and second intervals are not provided, the molten solder can also move to the second interval on the first stage through the flow channel formed between the chip and the stage.

Further, as shown in FIG. 6, the semiconductor chip 303 has a first end surface 3031 and a second end surface 3032 along the first direction. As shown in FIG. 5, there are multiple first units 30 arranged on the substrate 300; multiple first units 30 are arranged side by side and spaced apart on the substrate 300; each of the multiple first units 30 The first end face of a unit is located on the same side. Specifically, the arrangement direction of the plurality of first units 30 is perpendicular to the first direction.

The area where the upper surface of the above-mentioned substrate is located between any two of the first units 30 is an insulating area. Specifically, the upper surface of the above-mentioned substrate is located between the two first slide stages in any two of the first units 30. The area is an insulating area.

It is precisely because the above-mentioned guide area is provided on the second end face 3032 side of the semiconductor chip 303 to guide and accommodate the excess molten solder, the distance between the semiconductor chips in any two adjacent first units can be reduced to 10um～70um, effectively improving the integration degree of semiconductor packaging structure.

In an example, the aforementioned semiconductor chip 303 may be a semiconductor light-emitting chip, specifically, a laser diode chip. Correspondingly, the above-mentioned first unit is a light-emitting unit. The above-mentioned first end surface 3031 is the light-emitting end surface. When the semiconductor chip 303 is a semiconductor light-emitting chip, the above-mentioned semiconductor chip packaging structure further includes a reflector 400 disposed on the substrate 300; the reflector 400 has at least one reflective surface, and the reflective surface is close to the light emitting end surface. Specifically, the light-emitting end surface is arranged toward the reflective surface, so that the light emitted by the light-emitting end surface is reflected by the reflective surface.

Since the light emitted from the light emitting end surface of the semiconductor light emitting chip 303 has a certain divergence angle, when the distance between the reflector 400 and the semiconductor light emitting chip 303 is large, part of the light emitted from the light emitting end surface will hit the substrate 300, causing light loss . Using the technical solution provided by the embodiments of the present application, a guide area is provided on the second end surface side of the semiconductor light-emitting chip 303, so that the distance between the reflector 400 and the semiconductor light-emitting chip 303 can be reduced, not only without solder Bridging short circuits can also reduce light loss. In addition, adopting the technical solutions in the above-mentioned embodiments can reduce the spacing between the multiple semiconductor light-emitting chips, which can effectively reduce the scanning blind area and improve the scanning resolution.

Another embodiment of the present application further provides an electronic device, which includes the semiconductor chip packaging structure in each of the foregoing embodiments. Among them, the specific implementation of the semiconductor chip packaging structure can refer to the relevant content in the above-mentioned embodiments, which will not be repeated here.

The electronic equipment can be unmanned aerial vehicles, robots, mobile phones, computers, smart watches, smart glasses, etc.

FIG. 15 shows a schematic flow chart of a semiconductor packaging method of the above-mentioned semiconductor packaging structure. As shown in Figure 15, the method includes:

1201. Heating the first solder layer provided on the first bearing surface of the first slide table to obtain molten solder.

Wherein, the first slide stage is arranged on the substrate.

1202. Mount a semiconductor chip on the molten solder.

1203. Perform a cooling process on the molten solder, so that the semiconductor chip is fixed on the first carrying surface.

As shown in FIGS. 5 and 6, the semiconductor chip 303 has a first end surface 3031 and a second end surface 3032 opposite to the first end surface 3031; when the semiconductor chip 303 is fixed by the first solder layer 302 In the case of the first bearing surface, the first bearing surface has a first edge 3011 extending beyond the first end surface 3031 and a second edge 3012 extending beyond the second end surface 3032. The first end surface 3031 is connected to the The first interval formed by the first edge 3011 is smaller than the second interval formed by the second end surface 3032 and the second edge 3012.

In the above 1201, in an example, the first solder layer may be a prefabricated solder sheet, and the first solder layer may be disposed on the first bearing surface of the first carrier table in advance. In another example, a thin film process may be used to prefabricate the first solder layer on the first bearing surface of the first stage. The thin film process includes a coating process and a patterned etching process, and the specific implementation method can be referred to the prior art, which will not be described in detail here.

Since the first solder layer has been disposed on the substrate, heating the first solder layer, that is, heating the substrate to melt it. The heating temperature is set according to the material of the first solder layer, which is not specifically limited in this application.

In the above-mentioned 1202, as shown in FIG. 7, the semiconductor chip is mounted on the molten solder so as to be close to the first edge 3011 side.

In one example, the semiconductor chip can be mounted on the molten solder by a placement device. Specifically, the placement device places the semiconductor chip on the molten solder through a suction head and presses and solders the semiconductor chip.

In the above 1203, the molten solder can be naturally cooled, so that the fusion solder is solidified, so that the semiconductor chip is fixed on the first carrying surface.

In the technical solution provided by the embodiments of the present application, when the semiconductor chip is fixed to the first bearing surface of the first stage by soldering, the second edge formed between the second edge of the first bearing surface and the second end surface of the semiconductor chip The interval is greater than the first interval formed between the first edge of the first carrying surface and the light-emitting end surface of the semiconductor chip. In this way, the area where the first bearing surface is located at the second interval can guide and contain the excess part of the molten solder overflowing under the extrusion of the semiconductor chip when the semiconductor chip is soldered, so as to prevent the molten solder from overflowing the slide table.

Avoiding the molten solder from overflowing the stage, it also prevents the molten solder from flowing into the insulating trenches (gaps) between the stage and other chips on the substrate, causing solder bridging and short-circuit problems. Using the technical solution provided by the embodiments of the present application can effectively improve the packaging yield and reduce the packaging cost.

In addition, with the technical solution provided by the embodiments of the present application, it is only necessary to design such a solder guide area on one side of the semiconductor chip, and the distance between the other side of the semiconductor chip and other chips can be designed to be very small. The problem of solder bridging short circuit will occur, and the integration can be effectively improved.

For the value range of the difference between the second interval and the first interval, refer to the corresponding content in the foregoing embodiments, and details are not described herein again. In practical applications, as shown in FIG. 6, before heating, the first solder layer 302 may be disposed close to the first edge 3011 side of the first bearing surface. Specifically, the first solder layer 302 has a fifth end surface 3021 and a sixth end surface 3022 opposite to each other. When the first solder layer 302 is disposed on the first bearing surface, the first edge 3011 extends beyond the fifth end surface 3021 and is in line with the fifth end surface. 3021 forms a fifth gap; the second edge 3012 extends beyond the sixth end surface 3022 and forms a sixth gap with the sixth end surface 3022, the sixth gap being greater than the fifth gap. In this way, after the first solder layer is heated and melted, the area where the first bearing surface is located at the sixth interval will guide the molten solder to deviate toward the second edge. After the first solder layer is melted, the contact area with the first bearing surface will increase, and the fifth gap can be used to accommodate the expanded molten solder.

Similarly, as shown in FIG. 12, before heating, the first solder layer 302 has a seventh end surface 3023 and an eighth end surface 3024 opposite to each other. When the first solder layer 302 is disposed on the first bearing surface, the The third edge 3013 extends beyond the seventh end surface 3023 and forms a seventh interval with the seventh end surface 3023; the fourth edge 3014 of the first bearing surface extends beyond the eighth end surface 3024 and forms an eighth interval with the eighth end surface 3024. After the first solder layer is melted, the contact area with the first bearing surface will increase, and the seventh interval and the eighth interval can be used to accommodate the expanded molten solder.

The seventh interval and the eighth interval may be opposite, and both are smaller than the sixth interval. In practical applications, the seventh interval and the eighth interval may be set at the same time, or only one of them may be set.

In practical applications, multiple semiconductor chips need to be packaged on a substrate. A plurality of semiconductor chips can be packaged on the substrate at one time, specifically: a plurality of first slide stages are arranged on the substrate; at the same time, the first substrates respectively arranged on the respective first bearing surfaces of the plurality of first slide stages The solder layer is heated to obtain molten solder; a plurality of semiconductor chips are mounted on the molten solder on the respective first bearing surfaces of the plurality of first carrier tables in one-to-one correspondence; The molten solder on the first carrying surface is cooled, so that the plurality of semiconductor chips are fixed on the first carrying surface of each of the plurality of first slide tables in one-to-one correspondence.

When the aforementioned semiconductor chip 303 is specifically a semiconductor light-emitting chip, it is usually necessary to provide a reflector 400 on the substrate 300. The reflector 400 and the semiconductor light emitting chip 303 can be packaged on the substrate 300 at one time. Specifically, as shown in FIG. 6, a first stage 301 and a second stage 401 are arranged on the substrate 300; at the same time, the first solder layer 302 and the second stage 401 arranged on the first bearing surface of the first stage 301 The second solder layer 402 provided on the second bearing surface of the second stage 401 is heated to obtain molten solder; the semiconductor chip 303 is mounted on the molten solder on the first bearing surface of the first stage 301, And mount the reflector 400 on the molten solder on the second bearing surface of the second stage 401; compare the molten solder on the first bearing surface of the first stage 301 and the second stage of the second stage 401 The molten solder on the carrying surface is cooled, so that the semiconductor chip 303 is fixed on the first carrying surface, and the reflector 400 is fixed on the second carrying surface.

In an example, the above-mentioned first stage 301 may also be prefabricated on the substrate 300 by the above-mentioned thin film process. Specifically, the first slide table 301 can be prefabricated on the substrate through a coating process and a patterned etching process, and the prefabricated first slide table 301 is located at both ends of the second edge 3012. Notches 3015 may be provided. .

It should be noted that the specific structure and beneficial effects of the semiconductor chip packaging structure obtained after cooling in this embodiment can be referred to the content in the corresponding embodiment above, and will not be repeated here.

13 and FIG. 14 show schematic structural diagrams of a semiconductor chip packaging structure provided by another embodiment of the present application. The semiconductor chip packaging structure includes: a substrate 300; a first unit 30 disposed on the substrate 300; wherein, the first unit 30 includes: a first stage 301 disposed on the substrate 300; The first solder layer 302 is disposed on the first bearing surface of the first stage 301; the first bearing surface has a first edge 3011 and a second edge 3012 opposite to each other; the semiconductor chip 303 has a first end surface 3031 and a second end surface 3032 opposite to the first end surface 3031; when the semiconductor chip 303 is fixed to the first carrying surface by the first solder layer 302, the second edge 3012 extends beyond the first bearing surface The two end surfaces 3032 and the second end surface 3032 form a second interval, and the first end surface 3031 extends beyond the first edge 3011 (as shown in FIG. 13) or is flush with the first edge 3011 ( As shown in Figure 14).

In the semiconductor package structure provided by the embodiment of the present application, the mounting positions of the mounting table 301, the first solder layer 302, and the semiconductor chip 303 are in a non-centered alignment structure, and the positions of the first solder layer 302 and the semiconductor chip 303 are biased toward the first A slide table 301 is provided on the first edge 3011 side. Since there is no need to leave the first gap on the side of the first edge 3011 of the first stage 301, a larger second gap can be left on the side of the second edge 3012 of the first stage 301, that is, to leave a longer interval. The large space for guiding and accommodating the solder minimizes the flow resistance of the molten solder on the first bearing surface at the second interval, that is, the area on the first bearing surface at the second interval (referred to as the guiding area for short) To the role of directional guiding of molten solder.

In the technical solution provided by the embodiments of the present application, when the semiconductor chip is fixed to the first carrying surface of the first stage by soldering, there is no need to reserve a first interval on the first edge side of the first carrying surface, so that the A larger second space is reserved on the second edge side of the first carrying surface, so that the area where the first carrying surface is located at the second space can guide and contain the molten solder under the extrusion of the semiconductor chip when the semiconductor chip is soldered. The excess part of the overflow, so as to prevent the molten solder from overflowing the stage.

Avoiding the molten solder from overflowing the stage, it also prevents the molten solder from flowing into the insulating trenches (gaps) between the stage and other chips on the substrate, causing solder bridging and short-circuit problems. The technical solution provided by the embodiment of the present application can effectively improve the packaging yield and reduce the packaging cost.

Using the technical solution provided by the embodiments of the present application, it is only necessary to design such a solder guide area on one side of the semiconductor chip, and the distance between the other side of the semiconductor chip and other chips can be designed to be small, not only does not appear The solder bridging short-circuit problem can also effectively improve the integration.

In order to play a better guiding role, the second interval may be greater than 5 microns.

The inventor’s experiment found that when the second interval is greater than or equal to 10 microns, the flow resistance of the molten solder at the second interval on the first bearing surface can be made to be significantly smaller than the flow resistance on the first edge side of the first bearing surface , Can improve the guiding effect.

In an example, the second interval may be 10-100 microns.

In a specific example, the second interval may be 15 microns.

In yet another specific example, the second interval may be 20 microns.

In yet another specific example, the second interval may be 25 microns.

In yet another specific example, the second interval may be 30 microns.

In practical applications, the specific value of the second interval needs to be determined in combination with the thickness of the solder, the composition of the solder, the area of the semiconductor chip, and the packaging process conditions, which are not specifically limited in the embodiment of the present application.

The diffusion method of solder of different materials on the metal stage of different materials is different. In practical applications, the solder and metal carrier materials can be designed according to actual needs. For example, when the solder layer material uses PbSn, and the stage material uses W, Cu or other materials, due to the different microscopic forces between the materials, the molten solder spreads differently on the stage, and different settings are set. The first interval, the second interval, and the difference between the first interval and the second interval are adjusted. More specifically, it is also possible to adjust the third interval and the fourth interval on both sides of the chip and the stage according to different combinations of solder and stage material. As mentioned above, when the second interval is greater than the first interval, the molten solder will flow in the direction of the second interval due to the microscopic force. This phenomenon is more obvious when the spacing difference is greater than 10 microns. A reasonable placement of the chip during soldering can ensure that the molten solder flows in the second spacing direction and avoids flowing out of the slide table.

In practical applications, when the semiconductor chip 303 is a semiconductor light-emitting chip, the first end surface 3031 is the light-emitting end surface, and the substrate 300 is further provided with a reflector 400 having at least one reflective surface. The surface is close to the light-emitting end surface. Specifically, the light-emitting end surface may be arranged toward the reflecting surface, so that the light emitted by the light-emitting end surface can be reflected out through the reflecting surface. At this time, if the light emitting end surface exceeds the first edge 3011 (as shown in FIG. 13), it can be closer to the reflector to reduce light loss. However, because the bottom surface of the semiconductor chip 303 is not completely in contact with the slide table, the result is Poor heat dissipation.

It should be noted that the structure and beneficial effects of the semiconductor chip packaging structure in this embodiment that are not described in detail can be referred to the corresponding content in the foregoing embodiments, and will not be repeated here.

1202. Mount a semiconductor chip on the molten solder.

Wherein, as shown in FIGS. 13 and 14, the first stage 301 is disposed on the substrate 300, and the first bearing surface has a first edge 3011 and a second edge 3012 opposite to each other; wherein, the semiconductor chip 303, having a first end surface 3031 and a second end surface 3032 opposite to the first end surface 3031; when the semiconductor chip 303 is fixed to the first carrying surface through the first solder layer 302, the second The edge 3012 extends beyond the second end surface 3032 and forms a second interval with the second end surface 3032. The first end surface 3031 extends beyond the first edge 3011 or is flush with the first edge 3011.

For the specific implementation of the foregoing

steps

1201, 1202, and 1203, refer to the corresponding content in the foregoing embodiments, and details are not described herein again.

For the value range of the foregoing second interval, reference may be made to the content in the foregoing corresponding embodiment, and details are not described herein again. It should be noted that the specific structure and beneficial effects of the semiconductor chip packaging structure obtained after cooling in this embodiment can be referred to the content in the corresponding embodiment above, and will not be repeated here.

What needs to be explained here is that the content of each step in the method provided in the embodiment of the present application that is not described in detail can be referred to the corresponding content in the foregoing embodiment, and will not be repeated here. In addition, in addition to the foregoing steps, the method provided in the embodiments of the present application may also include other parts or all of the steps in the foregoing embodiments. For details, please refer to the corresponding content of the foregoing embodiments, which will not be repeated here.

5 and 6 show schematic structural diagrams of a semiconductor light emitting chip packaging structure provided by an embodiment of the present application. As shown in FIGS. 5 and 6, the semiconductor light-emitting chip packaging structure includes: a substrate 300; a light-emitting unit 30 and a reflector 400 disposed on the substrate 300; wherein, the light-emitting unit 30 includes: a first carrier The stage 301 is arranged on the substrate 300; the first solder layer 302 is arranged on the first bearing surface of the first stage 301; the semiconductor light-emitting chip 303 has a light-emitting end surface 3031 and is connected to the light-emitting end surface 3031. The second end surface 3032 opposite to the end surface 3031; when the semiconductor light-emitting chip 303 is fixed to the first bearing surface through the first solder layer 302, the first bearing surface has a first end surface that extends beyond the light emitting end surface 3031. The edge 3011 and the second edge 3012 beyond the second end face 3032, the first interval formed by the light-emitting end face 3031 and the first edge 3011 is smaller than the first interval formed by the second end face 3032 and the second edge 3012 Two intervals; the reflecting mirror 400 has at least one reflecting surface, and the reflecting surface is close to the light emitting end surface 3031.

Wherein, the light emitting end surface 3031 may face the reflecting surface.

With the technical solution provided by the embodiments of the present application, it is only necessary to design such a solder guide area on one side of the semiconductor light-emitting chip, and the distance between the other side of the semiconductor light-emitting chip and other chips can be designed to be very small. The problem of solder bridging short circuit will occur, and the integration can be effectively improved.

In addition, adopting the technical solution provided by the embodiments of the present application can effectively improve the packaging yield and reduce the packaging cost.

For the value range of the difference between the second interval and the first interval, refer to the corresponding content in the foregoing embodiments, and details are not described herein again.

It needs to be supplemented that the diffusion method of the solder of different materials on the metal stage of different materials is different. In practical applications, the solder and metal carrier materials can be designed according to actual needs.

Further, as shown in FIG. 5, the first slide table 301 is located at the two ends of the second edge 3012 with notches 3015, so as to form a gap 3015 where the first slide table 301 is located at the second interval. Bulge. This can reduce the area occupied by the slide table on the substrate, which not only improves the integration of the semiconductor package and reduces the overall weight of the semiconductor package structure, but also further prevents the overflow solder guided to the guiding area from spreading to both ends of the second edge 3012 This avoids the problem of solder bridging shorting with other chips on the third edge 3013 side and the fourth edge 3014 side adjacent to the second edge 3012 on the first bearing surface of the first stage 301.

Further, as shown in FIG. 11, the semiconductor light-emitting chip 303 further has a third end surface 3033 connecting the light-emitting end surface 3031 and the second end surface 3032; the first bearing surface also has a third end surface that extends beyond the third end surface. The third edge 3013 of 3033; a third interval is formed between the third end surface 3033 and the third edge 3013; the third interval is smaller than the second interval.

Further, as shown in FIG. 12, the semiconductor light emitting chip 303 further has a fourth end surface 3034 opposite to the third end surface 3033; the first bearing surface also has a fourth edge that extends beyond the fourth end surface 3034 3014; A fourth gap is formed between the fourth end surface 3034 and the fourth edge 3014; the fourth gap is smaller than the second gap.

Wherein, the fourth end surface 3034 is also connected to the light emitting end surface 3031 and the second end surface 3032.

Further, as shown in FIG. 6, there are multiple light emitting units 30 arranged on the substrate 300; multiple light emitting units 30 are arranged side by side and spaced apart on the substrate 300; the multiple light emitting units The light-emitting end surfaces of the semiconductor light-emitting chips 303 in each light-emitting unit in 30 are located on the same side. In an example, the light-emitting end surface of the semiconductor light-emitting chip 303 in each light-emitting unit of the plurality of light-emitting units 30 all faces the reflector 400.

It is precisely because the above-mentioned guiding area is provided on the second end face 3032 side of the semiconductor light-emitting chip 303, so that the excess molten solder can be directionally guided and accommodated, so that the distance between the semiconductor light-emitting chips in any adjacent two light-emitting units is It can be reduced to 10um～70um, which can effectively improve the integration of semiconductor packaging structure, and can also effectively reduce the scanning blind area and improve the scanning resolution.

It should be noted that the structure and beneficial effects of the semiconductor light emitting chip package structure in this embodiment that are not described in detail can be referred to the corresponding content in the foregoing embodiments, and will not be repeated here.

In addition, in multi-line sensors, often when the chip size is determined, in order to reduce the distance between the chip and the chip and reduce the scanning blind area, the gap between the chip and the chip can only be reduced from greater than or equal to 150um to 70um or even smaller by reducing the gap between the chip and the chip. With the integration of more and more lines of the emitter chip (ie, the aforementioned semiconductor light-emitting chip) array, there are considerable gains in reducing the package size; at the same time, the docked receiver chip, in order to obtain higher receiving efficiency, the spacing Keep the chip pitch consistent with that of the transmitter. The chip pitch of the transmitter is reduced, and the pitch of the receiver chip can also be reduced. More chips can be obtained on the same size wafer, and the cost of the receiver chip can be reduced.

Another embodiment of the present application further provides an electronic device, which includes the semiconductor light-emitting chip packaging structure in each of the foregoing embodiments. Among them, the specific implementation of the semiconductor light-emitting chip packaging structure can refer to the relevant content in the above-mentioned embodiments, which will not be repeated here.

FIG. 16 shows a schematic flow diagram of a semiconductor packaging method of the above-mentioned semiconductor packaging structure. As shown in Figure 16, the method includes:

1601. Heating the first solder layer provided on the first bearing surface of the first stage to obtain molten solder.

Wherein, the first slide stage is arranged on the substrate.

1602. Mount the semiconductor light-emitting chip on the molten solder.

1603. Perform a cooling process on the molten solder, so that the semiconductor light-emitting chip is fixed on the first carrying surface.

As shown in FIGS. 5 and 6, the semiconductor light emitting chip 303 has a light emitting end surface 3031 and a second end surface 3032 opposite to the light emitting end surface 3031; when the semiconductor light emitting chip 303 passes through the first solder layer 302 When fixed to the first bearing surface, the first bearing surface has a first edge 3011 that extends beyond the light-emitting end surface 3031 and a second edge 3012 that extends beyond the second end surface 3032. The light-emitting end surface 3031 and the The first interval formed by the first edge 3011 is smaller than the second interval formed by the second end surface 3032 and the second edge 3012.

For the specific implementation of the foregoing

steps

1601, 1602, and 1603, refer to the corresponding content in the foregoing embodiments, and details are not described herein again.

What needs to be explained here is that the content of the steps in the method provided in the embodiments of the present application that are not described in detail can be referred to the corresponding content in the foregoing embodiments, and will not be repeated here. In addition, in addition to the foregoing steps, the method provided in the embodiments of the present application may also include other parts or all of the steps in the foregoing embodiments. For details, refer to the corresponding content of the foregoing embodiments, and details are not described herein again.

13 and FIG. 14 show schematic structural diagrams of a semiconductor chip packaging structure provided by another embodiment of the present application. The semiconductor chip packaging structure includes: a substrate 300; a light emitting unit 30 and a reflector 400 arranged on the substrate 300; wherein, the light emitting unit 30 includes: a first stage 301 arranged on the substrate 300 On; the first solder layer 302 is provided on the first bearing surface of the first stage 301; the first bearing surface has a first edge 3011 and a second edge 3012 opposite to each other; the semiconductor light-emitting chip 303 has The light-emitting end surface 3031 and the second end surface 3032 opposite to the light-emitting end surface 3031; when the semiconductor light-emitting chip 303 is fixed to the first carrying surface through the first solder layer 302, the second edge 3012 extends beyond the The second end surface 3032 and the second end surface 3032 form a second interval, and the light-emitting end surface 3031 extends beyond the first edge 3011 (as shown in FIG. 13) or is flush with the first edge 3011 (As shown in FIG. 14); the reflecting mirror 400 has at least one reflecting surface, and the reflecting surface is close to the light emitting end surface 3031.

In the technical solution provided by the embodiments of the present application, when the semiconductor light-emitting chip is fixed to the first bearing surface of the first stage by soldering, there is no need to reserve a first gap on the first edge side of the first bearing surface, so that A larger second gap is reserved on the second edge side of the first bearing surface, so that the area where the first bearing surface is located at the second gap can guide and accommodate the molten solder on the semiconductor light-emitting chip when the semiconductor light-emitting chip is soldered. Squeeze the excess part that overflows underneath to prevent molten solder from overflowing the slide table. Avoiding the molten solder from overflowing the stage, it also prevents the molten solder from flowing into the insulating trenches (gaps) between the stage and other chips on the substrate, causing solder bridging and short-circuit problems. Using the technical solution provided by the embodiments of the present application can effectively improve the packaging yield and reduce the packaging cost.

Using the technical solution provided by the embodiments of the present application, it is only necessary to design such a solder guide area on one side of the semiconductor chip, and the distance between the other side of the semiconductor light-emitting chip and other chips can be designed to be very small. The solder bridging short-circuit problem can also effectively improve the integration.

For the value range of the foregoing second interval, refer to the corresponding content in the foregoing embodiments, and details are not described herein again. In practical applications, the specific value of the second interval needs to be determined in combination with the thickness of the solder, the composition of the solder, the area of the semiconductor chip, and the packaging process conditions, which are not specifically limited in the embodiment of the present application.

The diffusion method of solder of different materials on the metal stage of different materials is different. In practical applications, the solder and metal carrier materials can be designed according to actual needs.

Further, as shown in FIG. 5, the first slide table 301 is located at the two ends of the second edge 3012 with notches 3015, so as to form a gap 3015 where the first slide table 301 is located at the second interval. Bulge. In this way, the area occupied by the slide table on the substrate can be reduced, the integration degree of the semiconductor package can be improved, and the overall weight of the semiconductor package structure can be reduced.

It should be supplemented that by providing notches at both ends of the second edge 3012, the overflow solder guided to the guide area can be further prevented from spreading to both ends of the second edge 3012, thereby avoiding being set on the first stage 301 The problem of solder bridging and shorting occurs in other chips on the third edge 3013 side and the fourth edge 3014 side adjacent to the second edge 3012 of the first bearing surface.

Among them, the third interval and the fourth interval can also be used to accommodate a small portion of the solder diffusion portion. The third interval and the fourth interval may be equal. It needs to be added that the third interval and the fourth interval are both smaller than the second interval.

Further, as shown in FIG. 6, there are multiple light emitting units 30 arranged on the substrate 300; multiple light emitting units 30 are arranged side by side and spaced apart on the substrate 300; the multiple light emitting units The light-emitting end surfaces of the semiconductor light-emitting chips 303 in each light-emitting unit in 30 are located on the same side. In an example, the light-emitting end surface of the semiconductor light-emitting chip 303 in each light-emitting unit of the plurality of light-emitting units 30 is set toward the reflector 400.

Another embodiment of the present application also provides an electronic device, which includes the semiconductor light-emitting chip packaging structure in each of the foregoing embodiments. Among them, the specific implementation of the semiconductor light-emitting chip packaging structure can refer to the relevant content in the above-mentioned embodiments, which will not be repeated here.

FIG. 16 shows a schematic flow chart of a semiconductor packaging method of the above-mentioned semiconductor packaging structure. As shown in Figure 16, the method includes:

1602. Mount the semiconductor light-emitting chip on the molten solder.

Wherein, as shown in FIG. 13 and FIG. 14, the first slide table is arranged on the substrate, and the first bearing surface has a first edge and a second edge opposite to each other.

The semiconductor light emitting chip 303 has a first end surface 3031 and a second end surface 3032 opposite to the light emitting end surface 3031; when the semiconductor light emitting chip 303 is fixed to the first carrying surface through the first solder layer 302 , The second edge 3012 extends beyond the second end surface 3032 and forms a second interval with the second end surface 3032, and the light-emitting end surface 3031 extends beyond the first edge 3011 or is connected to the first edge 3011. Flush.

For the specific implementation of the foregoing

steps

For the value range of the foregoing second interval, refer to the corresponding content in the foregoing embodiments, and details are not described herein again.

The technical solutions and technical features in each of the above embodiments can be singly or combined in case of conflict with the present invention, as long as they do not exceed the cognitive scope of those skilled in the art, they all belong to the equivalent embodiments within the protection scope of this application. .

The above are only examples of this application, and do not limit the scope of this application. Any equivalent structure or equivalent process transformation made using the content of the description and drawings of this application, or directly or indirectly applied to other related technologies In the same way, all fields are included in the scope of patent protection of this application.

Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the application, not to limit them; although the application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: It is still possible to modify the technical solutions described in the foregoing embodiments, or equivalently replace some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the technical solutions of the embodiments of the present application. range.

Claims

A semiconductor light emitting chip packaging structure, which is characterized in that it comprises:

Substrate

A light emitting unit and a reflecting mirror arranged on the substrate;

Wherein, the light-emitting unit includes:

The first slide table is set on the substrate;

The first solder layer is arranged on the first bearing surface of the first slide table;

The semiconductor light-emitting chip has a light-emitting end surface and a second end surface opposite to the light-emitting end surface; when the semiconductor light-emitting chip is fixed to the first bearing surface by the first solder layer, the first bearing surface has A first edge that extends beyond the light-emitting end surface and a second edge that extends beyond the second end surface. The first interval formed by the light-emitting end surface and the first edge is smaller than that formed by the second end surface and the second edge. Second interval

The reflecting mirror has at least one reflecting surface, and the reflecting surface is close to the light emitting end surface.
The semiconductor light emitting chip packaging structure of claim 1, wherein the difference between the second interval and the first interval is greater than 10 micrometers.
The semiconductor light emitting chip packaging structure of claim 1, wherein:

The first slide table is provided with notches at both ends of the second edge, so as to form protrusions where the first slide table is located at the second interval.
The semiconductor light emitting chip packaging structure of claim 3, wherein:

The first bearing surface includes a first area located on the protrusion;

The first area is rectangular, triangular or semi-elliptical.
The semiconductor light emitting chip packaging structure according to any one of claims 1 to 4, wherein the semiconductor light emitting chip further has a third end surface connecting the light emitting end surface and the second end surface;

The first bearing surface also has a third edge that extends beyond the third end surface;

A third gap is formed between the third end surface and the third edge;

The third interval is smaller than the second interval.
5. The semiconductor light emitting chip packaging structure of claim 5, wherein the semiconductor light emitting chip further has a fourth end surface opposite to the third end surface;

The first bearing surface also has a fourth edge that extends beyond the fourth end surface;

A fourth gap is formed between the fourth end surface and the fourth edge;

The fourth interval is smaller than the second interval.
The semiconductor light emitting chip packaging structure according to any one of claims 1 to 4, wherein there are multiple light emitting units provided on the substrate;

A plurality of the light-emitting units are arranged side by side and spaced apart on the substrate;

The light-emitting end faces of the semiconductor light-emitting chips in each light-emitting unit of the plurality of light-emitting units are located on the same side.
The semiconductor light emitting chip packaging structure according to any one of claims 1 to 4, wherein the material of the first solder layer is PbSn, SnAgCu, SnBi, AuSn, Sn or InP.
The semiconductor light emitting chip packaging structure according to any one of claims 1 to 4, wherein the material of the first stage is W, Cu, WNiAu, NiAu, Ag, TiNiPtAu, Pd, TiPtAu, NiPdAu Or WTiNiPtAu.
An electronic device, characterized by comprising the semiconductor light emitting chip packaging structure according to any one of claims 1 to 9.
A semiconductor packaging method, characterized in that it comprises:

Heating the first solder layer provided on the first bearing surface of the first slide table to obtain molten solder; the first slide table is provided on the substrate;

Mounting a semiconductor light-emitting chip on the molten solder;

Cooling the molten solder so that the semiconductor light-emitting chip is fixed on the first carrying surface;

Wherein, the semiconductor light-emitting chip has a light-emitting end surface and a second end surface opposite to the light-emitting end surface; when the semiconductor light-emitting chip is fixed to the first bearing surface through the first solder layer, the first A bearing surface has a first edge that extends beyond the light-emitting end surface and a second edge that extends beyond the second end surface. The first interval formed by the light-emitting end surface and the first edge is smaller than the second end surface and the first edge. The second interval formed by the two edges.
The method according to claim 11, wherein the difference between the second interval and the first interval is greater than 10 microns.
A semiconductor light emitting chip packaging structure, which is characterized in that it comprises:

Substrate

A light emitting unit and a reflecting mirror arranged on the substrate;

Wherein, the light-emitting unit includes:

The first slide table is set on the substrate;

The first solder layer is arranged on the first bearing surface of the first slide table; the first bearing surface has a first edge and a second edge opposite to each other;

The semiconductor light-emitting chip has a light-emitting end surface and a second end surface opposite to the light-emitting end surface; when the semiconductor light-emitting chip is fixed to the first carrying surface through the first solder layer, the second edge extends beyond the The second end surface forms a second interval with the second end surface, and the light-emitting end surface extends beyond the first edge or is flush with the first edge;

The reflecting mirror has at least one reflecting surface, and the reflecting surface is close to the light emitting end surface.
The semiconductor light emitting chip packaging structure of claim 13, wherein the second interval is greater than 10 microns.
The semiconductor light emitting chip packaging structure of claim 13, wherein:

The first slide table is provided with notches at both ends of the second edge, so as to form protrusions where the first slide table is located at the second interval.
The semiconductor light emitting chip packaging structure of claim 15, wherein:

The first bearing surface includes a first area located on the protrusion;

The first area is rectangular, triangular or semi-elliptical.
The semiconductor light emitting chip packaging structure according to any one of claims 13 to 16, wherein the semiconductor light emitting chip further has a third end surface connecting the light emitting end surface and the second end surface;

The first bearing surface also has a third edge that extends beyond the third end surface;

A third gap is formed between the third end surface and the third edge;

The third interval is smaller than the second interval.
18. The semiconductor light emitting chip packaging structure of claim 17, wherein the semiconductor light emitting chip further has a fourth end surface opposite to the third end surface;

The first bearing surface also has a fourth edge that extends beyond the fourth end surface;

A fourth gap is formed between the fourth end surface and the fourth edge;

The fourth interval is smaller than the second interval.
The semiconductor light emitting chip packaging structure according to any one of claims 13 to 16, wherein there are multiple light emitting units provided on the substrate;

A plurality of the light-emitting units are arranged side by side and spaced apart on the substrate;

The light-emitting end faces of the semiconductor light-emitting chips in each light-emitting unit of the plurality of light-emitting units are located on the same side.
The semiconductor light emitting chip packaging structure according to any one of claims 13 to 16, wherein the material of the first solder layer is PbSn, SnAgCu, SnBi, AuSn, Sn or InP.
The semiconductor light emitting chip packaging structure according to any one of claims 13 to 16, wherein the material of the first stage is W, Cu, WNiAu, NiAu, Ag, TiNiPtAu, Pd, TiPtAu, NiPdAu Or WTiNiPtAu.
An electronic device, characterized by comprising the semiconductor light emitting chip packaging structure according to any one of claims 13 to 21.
A semiconductor packaging method, characterized in that it comprises:

The first solder layer arranged on the first bearing surface of the first stage is heated to obtain molten solder; the first stage is arranged on the substrate, and the first bearing surface has opposite first edges And the second edge;

Mounting a semiconductor light-emitting chip on the molten solder;

Cooling the molten solder so that the semiconductor light-emitting chip is fixed on the first carrying surface;

Wherein, the semiconductor light-emitting chip has a light-emitting end surface and a second end surface opposite to the light-emitting end surface; when the semiconductor light-emitting chip is fixed to the first bearing surface through the first solder layer, the first Two edges extend beyond the second end surface and form a second gap with the second end surface, and the light-emitting end surface extends beyond the first edge or is flush with the first edge.
The method of claim 23, wherein the second interval is greater than 10 microns.
A semiconductor chip packaging structure, characterized in that it comprises:

Substrate

A first unit arranged on the substrate;

Wherein, the first unit includes:

The first slide table is set on the substrate;

The first solder layer is arranged on the first bearing surface of the first slide table;

The semiconductor chip has a first end surface and a second end surface opposite to the first end surface; when the semiconductor chip is fixed to the first bearing surface through the first solder layer, the first bearing surface has an overhang The first edge of the first end surface and the second edge beyond the second end surface, the first interval formed by the first end surface and the first edge is smaller than that formed by the second end surface and the second edge The second interval.
The semiconductor chip packaging structure of claim 25, wherein the difference between the second interval and the first interval is greater than 10 micrometers.
An electronic device, characterized by comprising the semiconductor chip packaging structure of claim 25 or 26.
A semiconductor packaging method, characterized in that it comprises:

Heating the first solder layer provided on the first bearing surface of the first slide table to obtain molten solder; the first slide table is provided on the substrate;

Mounting a semiconductor chip on the molten solder;

Cooling the molten solder so that the semiconductor chip is fixed on the first carrying surface;

Wherein, the semiconductor chip has a first end surface and a second end surface opposite to the first end surface; when the semiconductor chip is fixed to the first bearing surface through the first solder layer, the first The bearing surface has a first edge that extends beyond the first end surface and a second edge that extends beyond the second end surface. The first interval formed by the first end surface and the first edge is smaller than that between the second end surface and the second edge. The second interval formed by the second edge.
The method of claim 28, wherein the difference between the second interval and the first interval is greater than 10 microns.
A semiconductor chip packaging structure, characterized in that it comprises:

Substrate

A first unit arranged on the substrate;

Wherein, the first unit includes:

The first slide table is set on the substrate;

The first solder layer is arranged on the first bearing surface of the first slide table; the first bearing surface has a first edge and a second edge opposite to each other;

A semiconductor chip has a first end surface and a second end surface opposite to the first end surface; when the semiconductor chip is fixed to the first carrying surface through the first solder layer, the second edge extends beyond the The second end surface forms a second interval with the second end surface, and the first end surface extends beyond the first edge or is flush with the first edge.
The semiconductor chip packaging structure of claim 30, wherein the second interval is greater than 10 microns.
An electronic device, characterized by comprising the semiconductor chip packaging structure of claim 30 or 31.
A semiconductor packaging method, characterized in that it comprises:

The first solder layer arranged on the first bearing surface of the first stage is heated to obtain molten solder; the first stage is arranged on the substrate, and the first bearing surface has opposite first edges And the second edge;

Mounting a semiconductor chip on the molten solder;

Cooling the molten solder so that the semiconductor chip is fixed on the first carrying surface;

Wherein, the semiconductor chip has a first end surface and a second end surface opposite to the first end surface; when the semiconductor chip is fixed to the first carrying surface through the first solder layer, the second The edge extends beyond the second end surface and forms a second interval with the second end surface, and the first end surface extends beyond the first edge or is flush with the first edge.
The method of claim 33, wherein the second interval is greater than 10 microns.