CN203910779U - Semiconductor device - Google Patents
Semiconductor device Download PDFInfo
- Publication number
- CN203910779U CN203910779U CN201420348295.7U CN201420348295U CN203910779U CN 203910779 U CN203910779 U CN 203910779U CN 201420348295 U CN201420348295 U CN 201420348295U CN 203910779 U CN203910779 U CN 203910779U
- Authority
- CN
- China
- Prior art keywords
- chip bearing
- resin
- chip
- scolding tin
- encapsulated body
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 75
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims abstract description 62
- 238000005476 soldering Methods 0.000 abstract description 7
- 229920005989 resin Polymers 0.000 abstract description 5
- 239000011347 resin Substances 0.000 abstract description 5
- 238000004806 packaging method and process Methods 0.000 abstract description 4
- 239000000463 material Substances 0.000 description 8
- 239000000758 substrate Substances 0.000 description 7
- 230000000694 effects Effects 0.000 description 5
- 229910010271 silicon carbide Inorganic materials 0.000 description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 4
- 229910052802 copper Inorganic materials 0.000 description 4
- 239000010949 copper Substances 0.000 description 4
- 229910000881 Cu alloy Inorganic materials 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000002844 melting Methods 0.000 description 3
- 230000008018 melting Effects 0.000 description 3
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 238000009434 installation Methods 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 238000010992 reflux Methods 0.000 description 2
- 229910000838 Al alloy Inorganic materials 0.000 description 1
- WKBOTKDWSSQWDR-UHFFFAOYSA-N Bromine atom Chemical compound [Br] WKBOTKDWSSQWDR-UHFFFAOYSA-N 0.000 description 1
- 229910002601 GaN Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- GDTBXPJZTBHREO-UHFFFAOYSA-N bromine Substances BrBr GDTBXPJZTBHREO-UHFFFAOYSA-N 0.000 description 1
- 229910052794 bromium Inorganic materials 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 238000005755 formation reaction Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000001721 transfer moulding Methods 0.000 description 1
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
The utility model provides a semiconductor device. When soldering tin is fused, a danger, that the residual soldering tin and soldering tin born by adjacent chip or a chip bearing contact to cause an electric short circuit, is present. The semiconductor device provided by the utility model is characterized by comprising a lead frame, provided with the chip bearing and a terminal; a semiconductor chip, carried on an upper surface of the chip bearing; and a resin packaging body, used for covering the upper surfaces of the semiconductor chip, the chip bearing and the terminal. The semiconductor device is provided with the chip bearing for carrying multiple rows and multiple columns (at least two rows and two columns) of the chips, and at least more than one back side of the chip bearing is exposed with HOSN packaging from a packaging back side. The semiconductor device is provided with a soldering tin guiding circuit, to enable the residual soldering tin to move in a way that the soldering tin born by the chip bearing cannot flow to the adjacent chip bearing.
Description
Technical field
The utility model relates to semiconductor device, and particularly face is installed on the semiconductor device of circuit substrate etc.
Background technology
Semiconductor device possesses: lead frame, and it possesses chip bearing (die pad); Semiconductor chip, it carries on chip bearing; And resin-encapsulated body, it gets up semiconductor die package, and in this semiconductor device, resin-encapsulated body covers upper surface and the semiconductor chip of chip bearing, and makes the lower surface of chip bearing be exposed to the lower surface of packaging body.Thus, can improve thermal diffusivity.And when semiconductor device face is installed on to circuit substrate, the electrical connection region that the lower surface of chip bearing is used as between semiconductor device and circuit substrate is used.
In addition, as prior art, known have possess a plurality of weld pads (chip bearing) and make the back side be exposed to the outside semiconductor device (for example, with reference to patent documentation 1, Fig. 1, Fig. 2) of resin molded portion (resin-encapsulated body).Thus, can become the surface installation type semiconductor device that is equipped with a plurality of semiconductor chips that guarantee that temperature differs from one another.
Prior art document
Patent documentation 1: TOHKEMY 2008-187101 communique
Conventionally, in the situation that the back side face of semiconductor device is installed to circuit substrate etc., use the grafting materials such as scolding tin, while utilize hot reflux device etc. to heat, make scolding tin melting.According to prior art, can utilize a plurality of chip bearings to carry a plurality of semiconductor chips.
Yet, there is following problem: when scolding tin melting, worry that remaining scolding tin contacts and electrical short occurs with scolding tin or the chip bearing of adjacent chip bearing.
Utility model content
Therefore, the utility model completes in order to solve above-mentioned problem just, and its object is to provide a kind of surface installation type semiconductor device, has prevented that remaining scolding tin from contacting and electrical short occurs with the scolding tin of adjacent chip bearing or adjacent chip bearing.
In order to solve above-mentioned problem, the utility model is the following structure of recording.
Semiconductor device of the present utility model possesses: chip bearing; Semiconductor chip, it is equipped on an interarea of described chip bearing; Terminal, it is electrically connected to described semiconductor chip; And resin-encapsulated body, it covers described semiconductor chip, described chip bearing and described terminal, another interarea of described chip bearing exposes from the interarea of described resin-encapsulated body, described semiconductor device is characterised in that, described chip bearing possesses scolding tin guiding road, described scolding tin guiding road and described chip bearing link and extend towards the side of described resin-encapsulated body, and end and the interarea on described scolding tin guiding road expose from the side of described resin-encapsulated body and the interarea of described resin-encapsulated body respectively.
Semiconductor device of the present utility model is characterised in that, described terminal exposes at the first side of described resin-encapsulated body, and expose from second side of intersecting with the first side of described resin-encapsulated body on described scolding tin guiding road.
Semiconductor device of the present utility model possesses: the first chip bearing and the second chip bearing, their spaced compartment of terrain configurations, terminal, itself and described the first chip bearing and described the second chip bearing are adjacent to configuration, and resin-encapsulated body, it covers described the first chip bearing, the second chip bearing and described terminal, the interarea of described the first chip bearing and described the second chip bearing exposes from the interarea of described resin-encapsulated body, described semiconductor device is characterised in that, described terminal exposes at the first side of described resin-encapsulated body, described the first chip bearing possesses the first scolding tin guiding road, the interarea on described the first scolding tin guiding road and the link of this first chip bearing and this first scolding tin guiding road exposes from the described interarea of described resin-encapsulated body, described the second chip bearing possesses the second scolding tin guiding road, the interarea on described the second scolding tin guiding road and the link of this second chip bearing and this second scolding tin guiding road exposes from the described interarea of described resin-encapsulated body, described the first scolding tin guiding road direction is extended away from the direction of described the second chip bearing, and expose from second side of intersecting with described the first side of described resin-encapsulated body, described the second scolding tin guiding road direction is extended away from the direction of described the first chip bearing, and exposing with opposed the 3rd side, described the second side from described resin-encapsulated body.
Utility model effect
The utility model forms as described above, therefore plays following effect: can provide a kind of semiconductor device that has reduced the electrical short being caused by scolding tin.
Accompanying drawing explanation
Fig. 1 is the birds-eye perspective of the semiconductor device of embodiment 1 of the present utility model.
Fig. 2 is the sectional side view of the semiconductor device of embodiment 1 of the present utility model.
Fig. 3 is the key diagram of face installment state that the semiconductor device of embodiment 1 of the present utility model is shown.
Fig. 4 is the upward view of the semiconductor device of variation 1 of the present utility model.
Fig. 5 is the state diagram of chip bearing of the semiconductor device of variation 2 of the present utility model.
Fig. 6 is the state diagram of terminal of the semiconductor device of variation 3 of the present utility model.
Label declaration
1: semiconductor device; 2: lead frame; 3: chip bearing; 4: terminal; 5: semiconductor chip; 6: wire; 7: resin-encapsulated body; 8: chamfered section; 9: scolding tin guiding road; 10: stage portion; 11: terminal ends portion; 12: circuit substrate; 13: grafting material.
Embodiment
Below, with reference to accompanying drawing to describing for implementing mode of the present utility model.In addition, in the record of following accompanying drawing, for same or similar part, with same or similar label, represent.Wherein, accompanying drawing is that schematically the ratio of size relationship etc. are different from real situation.Therefore, the reply such as concrete size judges according to the following description.And certainly, accompanying drawing also comprises relation and the different part of ratio of size each other each other.
And execution mode shown below is for by the specific example of the technological thought of this utility model, the material of the structure member in the execution mode of this utility model, shape, structure, configuration etc. are not limited to following record.The execution mode of this utility model can carry out various changes enforcement in the scope that does not depart from purport.
Embodiment 1
Below, with reference to accompanying drawing, the semiconductor device of embodiment 1 of the present utility model is described.Fig. 1 is the birds-eye perspective of the semiconductor device 1 of embodiment 1 of the present utility model.Fig. 2 is its sectional side view.
As shown in Figure 1, semiconductor device 1 consists of lead frame 2 (chip bearing 3, terminal 4), semiconductor chip 5, wire 6 and resin-encapsulated body 7.
Lead frame 2 has chip bearing 3 and terminal 4.Upper surface at an interarea as chip bearing 3, is equipped with semiconductor chip 5 by grafting material.Terminal 4 is electrically connected to semiconductor chip 5, and this terminal 4 is the internal terminals that are connected with one end of the wire 6 connecting up from semiconductor chip 5 specifically, and terminal 4 exports to the outside of resin-encapsulated body, becomes the outside terminal of semiconductor device 1.In addition, resin-encapsulated body 7 covers described semiconductor chip 5, described chip bearing 2 and described terminal 3, as the lower surface of another interarea of chip bearing 3, be configured in the plane identical with the lower surface as interarea of resin-encapsulated body 7 and from the lower surface of resin-encapsulated body 7 and expose, when semiconductor device 1 face is arranged on circuit substrate, the lower surface of chip bearing 3 is connected with heat radiation for the electrical connection between semiconductor device 1 and circuit substrate.
And lead frame 2 consists of the high copper of pyroconductivity or copper alloy, for example its thickness is about 0.2mm.Described chip bearing 3 possesses scolding tin guiding road 9, described scolding tin guiding road 9 links with described chip bearing 3 and towards the side of described resin-encapsulated body (for example, upper side in Fig. 1 and downside) extend, end and the interarea (lower surface) on described scolding tin guiding road 9 for example, expose from the side (, the upper side in Fig. 1 and downside) of described resin-encapsulated body 7 and the interarea (lower surface) of described resin-encapsulated body 7 respectively.
Described terminal 4 at the first side of described resin-encapsulated body 7 (for example, left surface side in Fig. 1) expose, expose with the first side (left surface) crossing second side (upper side) from described resin-encapsulated body 7 on described scolding tin guiding road 9.
Semiconductor chip 5 has electrode (not shown) at upper surface.Semiconductor chip 5 is transistor, for example, be as the carborundum (SiC) that can carry out the compound semiconductor element of hot operation.
Wire 6 is fine rules of being made by copper or copper alloy, is connected in the upper surface (faying face) of the electrode of semiconductor chip 5 and the terminal 4 of lead frame 2.The diameter that is for example fine rule is the copper cash of 28 microns.Material can be also gold or billon.
And the faying face of terminal 4 bends and lifts upward than the lower surface of resin-encapsulated body (back side).Thus, in conjunction with the back side, from the back side of resin-encapsulated body, do not expose, therefore, can realize fixing in resin-encapsulated body of terminal 4, suppress the intrusion of moisture, and can guarantee the insulation distance of chip bearing 3 on the back side of resin-encapsulated body and terminal 4.
Resin-encapsulated body 7 covers the upper surface of chip bearing 3 of lead frames 2, the upper surface of terminal 4, semiconductor chip 5 and wire 6, thereby forms the outer shape of semiconductor device 1.For example, the epoxy resin as resin material that use has sufficient thermal endurance and insulating properties to the working temperature of semiconductor chip 5 utilizes transfer molding mould to carry out moulding.
And at the lower surface of resin-encapsulated body 7, the lower surface of chip bearing 3 exposes, the lower surface of the lower surface of chip bearing and resin-encapsulated body be take the central point of resin-encapsulated body, and as summit, towards the upper surface of resin-encapsulated body, to form integral body gently crooked.(with reference to Fig. 3)
Thus, semiconductor device 1 completes.
Next, the effect of the semiconductor device 1 of the above embodiments 1 is described.
In the semiconductor device 1 of embodiment 1 of the present utility model, the lower surface of chip bearing is configured in the plane identical with the lower surface of resin-encapsulated body, and expose at the lower surface of resin-encapsulated body, using the grafting materials such as scolding tin, in installing while the face that utilizes hot reflux device etc. to heat to make scolding tin melting, from a chip bearing, towards the edge of resin-encapsulated body, form to a plurality of scolding tin guiding road that at least both direction is given prominence to, thus, can prevent that remaining scolding tin from contacting and electrical short occurs with the scolding tin of adjacent chip bearing or adjacent chip bearing.
In the semiconductor device of this structure, at first side that disposes terminal of resin-encapsulated body, there is no scolding tin guiding road.So, can avoid terminal and scolding tin guiding road to approach and equally with chip bearing cause soldering to contact and cause short circuit.
Recorded as described above for implementing mode of the present utility model, but obviously those skilled in the art can realize various alternate embodiments, embodiment according to the disclosure.
Above-mentioned semiconductor device can also be implemented in the following manner.
A kind of semiconductor device is provided, and it possesses: the first chip bearing 2 and the second chip bearing 2, their spaced compartment of terrain configurations, terminal 4, itself and described the first chip bearing 2 and described the second chip bearing 2 are adjacent to configuration, and resin-encapsulated body 7, it covers described the first chip bearing 2, the second chip bearing 2 and described terminal 4, the interarea of described the first chip bearing 2 and described the second chip bearing 2 is that lower surface is that lower surface exposes from the interarea of described resin-encapsulated body 7, described terminal 4 at the first side of described resin-encapsulated body 7 (for example, left surface side) expose, described the first chip bearing 2 possesses the first scolding tin guiding road 9, expose from the described interarea (lower surface) of described resin-encapsulated body 7 with the interarea (lower surface) on this first chip bearing link 2 and this first scolding tin guiding road 9 on described the first scolding tin guiding road 9, described the second chip bearing 2 possesses the second scolding tin guiding road 9, described the second scolding tin guiding road 9 links with this second chip bearing 2 and the interarea (lower surface) on this second scolding tin guiding road 9 exposes from the described interarea (lower surface) of described resin-encapsulated body 7, extend to the direction away from described the second chip bearing on described the first scolding tin guiding road 9, and expose from second side (upper side) of intersecting with described the first side of described resin-encapsulated body, extend to the direction away from described the first chip bearing on described the second scolding tin guiding road 9, and exposing with opposed the 3rd side (downside), described the second side from described resin-encapsulated body.
In this embodiment, be separated with possibility more than needed, scolding tin contact between between terminal and scolding tin guiding road when few, can form scolding tin at the first side that disposes terminal and guide road.
In the example of above-mentioned Fig. 1, chip bearing 3 is for everywhere, but in this case, can possess chamfered section 8 in the part of joining each other separately.Thus, can prevent that electric field is concentrated.(variation 1, with reference to Fig. 4)
In addition, can be in the surrounding of chip bearing with end difference.(approximately 0.1mm) below half of the thickness of slab that the end difference of take is terminal is advisable.Thus, the erection space on chip bearing surface can be guaranteed, the distance between the chip bearing back side can also be guaranteed.And, there is such effect: prevent scolding tin bridging when face is installed, prevent that chip bearing from departing from from chip bearing and resin-encapsulated body, suppresses moisture and invade.
In addition, the shape that terminal 4 lifts for bending, but the end side of terminal 4 can be with a small amount of inclination.To tilt to be of a size of half following (approximately 0.1mm) of the thickness of slab of terminal, be advisable.Can improve wire in conjunction with time terminal pressing property.(variation 3, with reference to Fig. 6)
In addition, moulded resin is epoxy resin, but can be also the halogen-free resin that does not contain bromine (Br).Thus, can improve environmental performance.
In addition, lead frame is copper or copper alloy, but can be also aluminum or aluminum alloy.Thus, can reduce Master Cost.But, preferably process having implemented various platings with the mode that grafting material and wire engage on its surface.
In addition, semiconductor chip consists of carborundum (SiC), but such as also can be by formations such as gallium nitride (GaN), silicon (Si).Thus, above-mentioned structure and effect can not change.
In addition, in above-mentioned example, be single semiconductor chip, but be equipped with a plurality of semiconductor chip on lead frame in the situation that, can be also the combination of carborundum and gallium nitride etc.
Claims (3)
1. a semiconductor device, it possesses: chip bearing; Semiconductor chip, it is equipped on an interarea of described chip bearing; Terminal, it is electrically connected to described semiconductor chip; And resin-encapsulated body, it covers described semiconductor chip, described chip bearing and described terminal, and another interarea of described chip bearing exposes from the interarea of described resin-encapsulated body, and described semiconductor device is characterised in that,
Described chip bearing possesses scolding tin guiding road, and described scolding tin guiding road and described chip bearing link and extend towards the side of described resin-encapsulated body,
End and the interarea on described scolding tin guiding road expose from the side of described resin-encapsulated body and the interarea of described resin-encapsulated body respectively.
2. semiconductor device according to claim 1, is characterized in that,
Described terminal exposes at the first side of described resin-encapsulated body,
Expose from second side of intersecting with the first side of described resin-encapsulated body on described scolding tin guiding road.
3. a semiconductor device, it possesses: the first chip bearing and the second chip bearing, their spaced compartment of terrain configurations; Terminal, itself and described the first chip bearing and described the second chip bearing are adjacent to configuration; And resin-encapsulated body, it covers described the first chip bearing, the second chip bearing and described terminal, and the interarea of described the first chip bearing and described the second chip bearing exposes from the interarea of described resin-encapsulated body, and described semiconductor device is characterised in that,
Described terminal exposes at the first side of described resin-encapsulated body,
Described the first chip bearing possesses the first scolding tin guiding road, and the interarea on described the first scolding tin guiding road and the link of this first chip bearing and this first scolding tin guiding road exposes from the described interarea of described resin-encapsulated body,
Described the second chip bearing possesses the second scolding tin guiding road, and the interarea on described the second scolding tin guiding road and the link of this second chip bearing and this second scolding tin guiding road exposes from the described interarea of described resin-encapsulated body,
Described the first scolding tin guiding road direction is extended away from the direction of described the second chip bearing, and exposes from second side of intersecting with described the first side of described resin-encapsulated body,
Described the second scolding tin guiding road direction is extended away from the direction of described the first chip bearing, and exposing with opposed the 3rd side, described the second side from described resin-encapsulated body.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420348295.7U CN203910779U (en) | 2014-06-26 | 2014-06-26 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420348295.7U CN203910779U (en) | 2014-06-26 | 2014-06-26 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN203910779U true CN203910779U (en) | 2014-10-29 |
Family
ID=51785033
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201420348295.7U Expired - Lifetime CN203910779U (en) | 2014-06-26 | 2014-06-26 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN203910779U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105304600A (en) * | 2014-06-30 | 2016-02-03 | 瑞萨电子株式会社 | Semiconductor device and manufacturing method of semiconductor device |
| WO2021072731A1 (en) * | 2019-10-18 | 2021-04-22 | 深圳市大疆创新科技有限公司 | Semiconductor chip packaging structure, packaging method, and electronic device |
-
2014
- 2014-06-26 CN CN201420348295.7U patent/CN203910779U/en not_active Expired - Lifetime
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105304600A (en) * | 2014-06-30 | 2016-02-03 | 瑞萨电子株式会社 | Semiconductor device and manufacturing method of semiconductor device |
| CN105304600B (en) * | 2014-06-30 | 2020-06-26 | 瑞萨电子株式会社 | Semiconductor device and method for manufacturing semiconductor device |
| WO2021072731A1 (en) * | 2019-10-18 | 2021-04-22 | 深圳市大疆创新科技有限公司 | Semiconductor chip packaging structure, packaging method, and electronic device |
| CN113016079A (en) * | 2019-10-18 | 2021-06-22 | 深圳市大疆创新科技有限公司 | Semiconductor chip packaging structure, packaging method and electronic equipment |
| CN113016079B (en) * | 2019-10-18 | 2022-06-24 | 深圳市大疆创新科技有限公司 | Semiconductor chip packaging structure, packaging method and electronic equipment |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CX01 | Expiry of patent term |
Granted publication date: 20141029 |
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| CX01 | Expiry of patent term |