WO2021068805A1 - 显示面板及其制造方法、显示装置 - Google Patents

显示面板及其制造方法、显示装置 Download PDF

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Publication number
WO2021068805A1
WO2021068805A1 PCT/CN2020/118821 CN2020118821W WO2021068805A1 WO 2021068805 A1 WO2021068805 A1 WO 2021068805A1 CN 2020118821 W CN2020118821 W CN 2020118821W WO 2021068805 A1 WO2021068805 A1 WO 2021068805A1
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Prior art keywords
pattern
base substrate
sub
binding pattern
binding
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PCT/CN2020/118821
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English (en)
French (fr)
Inventor
杨中流
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京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Priority to US17/419,812 priority Critical patent/US12034014B2/en
Publication of WO2021068805A1 publication Critical patent/WO2021068805A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/022—Protective coating, i.e. protective bond-through coating
    • H01L2224/0221—Shape of the protective coating
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05073—Single internal layer
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05553—Shape in top view being rectangular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05556—Shape in side view
    • H01L2224/05559—Shape in side view non conformal layer on a patterned surface
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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    • H01L2224/05573—Single external layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits

Definitions

  • This application relates to the field of display technology, and in particular to a display panel, a manufacturing method thereof, and a display device.
  • the binding structure is a structure for connecting the circuit board and the display panel.
  • the binding structure can transmit the data signal received from the circuit board to the display panel to drive the display panel for display.
  • the binding structure connects the circuit board and the display panel through the binding pattern set thereon.
  • the bonding pattern on the bonding structure and the source and drain metal patterns are arranged in the same layer.
  • a flat layer is first covered on the display panel where the source and drain metal patterns and the binding pattern are formed, and then the flat layer covered on the binding pattern is removed to retain the display A flat layer on the source and drain metal patterns in the display area of the panel, and then an anode is formed on the source and drain metal patterns in the display area through a patterning process.
  • the embodiments of the present application provide a display panel, a manufacturing method thereof, and a display device.
  • the technical solution is as follows:
  • a display panel including a base substrate, a bonding pattern, and a flat layer pattern
  • the binding pattern is located on the base substrate, the binding pattern includes at least one conductive block, the conductive block has a binding area on a side away from the base substrate, and the flat layer pattern is parallel to the base substrate.
  • the base substrate has an opening area and a shielding area on the plane, the orthographic projection of the binding area on the base substrate is located in the orthographic projection of the opening area on the base substrate, and the flat layer
  • the pattern covers at least a part of the side surface of the conductive block, and the side surface is the surface of the conductive block except the surface close to the base substrate and the surface away from the base substrate.
  • the binding pattern includes a first sub-binding pattern and a second sub-binding pattern, and the first sub-binding pattern includes at least one of the conductive blocks;
  • the display panel includes a first insulating layer, a second insulating layer, and an interlayer dielectric layer, the first insulating layer, the second sub-binding pattern, the second insulating layer, the interlayer dielectric layer, and The first sub-binding patterns are sequentially arranged on the base substrate.
  • the conductive block includes source and drain lines.
  • the second sub-binding pattern includes a gate pattern.
  • the interlayer dielectric layer and the second insulating layer have via holes, and the first sub-binding pattern passes through the via hole and the second sub-binding pattern.
  • the The shielding area of the flat layer pattern is flush with the side of the binding pattern away from the base substrate.
  • the thickness of the shielding area of the flat layer pattern ranges from 6500 angstroms to 8800 angstroms.
  • the shielding area of the flat layer pattern includes at least one groove.
  • the side of the shielding area of the flat layer pattern away from the base substrate is flush with the side of the binding pattern away from the base substrate;
  • the binding pattern includes a first sub-binding pattern and a second sub-binding pattern, and the first sub-binding pattern includes at least one of the conductive blocks;
  • the display panel includes a first insulating layer, a second insulating layer, and an interlayer dielectric layer, the first insulating layer, the second sub-binding pattern, the interlayer dielectric layer, and the first sub-binding The patterns are sequentially arranged on the base substrate;
  • the conductive block includes source and drain lines
  • the second sub-binding pattern includes a gate pattern
  • the interlayer dielectric layer and the second insulating layer have via holes, and the first sub-binding pattern is electrically connected to the second sub-binding pattern through the via hole.
  • a method of manufacturing a display panel including:
  • the binding pattern includes at least one conductive block, and each conductive block has a binding area on a side away from the base substrate;
  • the flat layer is processed into a flat layer pattern, the flat layer pattern has an opening area and a shielding area on a plane parallel to the base substrate, and the orthographic projection of the binding area on the base substrate is located In the orthographic projection of the opening area on the base substrate, the flat layer pattern covers at least a part of the side surface of the conductive block, and the side surface is the surface of the conductive block except the surface close to the base substrate And the surface away from the surface of the base substrate.
  • the material of the flat layer includes a photoresist material
  • the processing the flat layer into a flat layer pattern includes:
  • the flat layer is processed into a flat layer pattern including at least one groove, and the at least one groove is located in a shielding area of the flat layer pattern.
  • the processing the flat layer into a flat layer pattern including at least one groove includes:
  • a flat layer pattern including the at least one groove is formed;
  • the designated mask includes a gray-scale mask area, and the gray-scale mask area corresponds to the groove.
  • the designated mask includes a first area and a second area, the first area corresponds to the shielding area, and the second area corresponds to the opening area.
  • the processing the flat layer into a flat layer pattern includes:
  • the flat layer is processed into a flat layer pattern through a gray-scale mask process, and the side of the flat layer pattern that is away from the base substrate is flush with the side of the binding pattern away from the base substrate.
  • the binding pattern includes a first sub-binding pattern and a second sub-binding pattern
  • forming the binding pattern on the base substrate includes:
  • the first sub-binding pattern is formed on the base substrate on which the interlayer dielectric layer is formed, and the first sub-binding pattern includes at least one of the conductive blocks.
  • the method before the forming the first sub-binding pattern on the base substrate on which the interlayer dielectric layer is formed, the method includes:
  • the forming the first sub-binding pattern on the base substrate on which the interlayer dielectric layer is formed includes:
  • a first sub-binding pattern is formed on the base substrate of the interlayer dielectric layer with via holes, and the first sub-binding pattern passes through the interlayer dielectric layer and the second insulating layer.
  • the hole is connected with the second sub-binding pattern.
  • the conductive block includes source and drain lines, and the second sub-binding pattern includes a gate pattern.
  • the thickness of the shielding area of the flat layer pattern ranges from 6500 angstroms to 8800 angstroms.
  • the material of the flat layer includes a photoresist material
  • the processing the flat layer into a flat layer pattern includes:
  • a flat layer pattern including the at least one groove is formed;
  • the designated mask includes a gray-scale mask area, a first area, and a second area
  • the gray-scale mask area corresponds to the groove
  • the first area corresponds to the shielding area
  • the second area corresponds to the opening area
  • the binding pattern includes a first sub-binding pattern and a second sub-binding pattern, and forming the binding pattern on a base substrate includes:
  • the first sub-binding pattern is formed on the base substrate on which the interlayer dielectric layer is formed, and the first sub-binding pattern includes at least one of the conductive blocks.
  • a display device is provided, and the display device includes any of the above-mentioned display panels.
  • Figure 1 is a partial structure diagram of a display panel
  • Figure 2 is a partial structure diagram of another display panel
  • FIG. 3 is a partial structural diagram of a display panel provided by an embodiment of the present application.
  • FIG. 4 is a top view of a display panel provided by an embodiment of the present application.
  • FIG. 5 is a top view of another display panel provided by an embodiment of the present application.
  • FIG. 6 is a partial structural diagram of another display panel provided by an embodiment of the present application.
  • FIG. 7 is a schematic structural diagram of another display panel provided by an embodiment of the present application.
  • FIG. 8 is a schematic structural diagram of another display panel provided by an embodiment of the present application.
  • FIG. 9 is a flowchart of a method for manufacturing a display panel provided by an embodiment of the present application.
  • FIG. 10 is a flowchart of another method for manufacturing a display panel provided by an embodiment of the present application.
  • the multi-layer metal material is a titanium/aluminum/titanium (ie Ti/Al/Ti) material, that is, the multi-layer metal material is a three-layer metal material, the metal material of the middle interlayer is aluminum, and the upper and lower sides of the middle interlayer
  • the two layers of metal materials are both titanium;
  • the anode to be etched can also be made of multilayer materials, for example, the multilayer material is indium tin oxide/silver/indium tin oxide (ie ITO/Ag/ITO) material, that is, ,
  • the multilayer material is a three-layer material, the material of the middle interlayer is silver, and the upper and lower layers of the middle interlayer are both indium tin oxide; the anode is etched with a silver (Ag) etchant (Etchant), and the silver is etched
  • the agent has silver ions.
  • the silver etchant has a corrosive effect on the aluminum in the binding pattern.
  • the aluminum atoms and the silver ions in the etchant undergo a substitution reaction, and the resulting silver is easily adsorbed on the uneven surface of the binding pattern, resulting in binding There is a risk of short-circuiting in certain patterns.
  • FIG. 1 shows a partial structure diagram of a display panel.
  • the display panel 00 includes a base substrate 01, a gate pattern 02 formed on the base substrate 01, an interlayer dielectric (ILD) layer 03 formed on the gate pattern 02, and an interlayer dielectric layer 03 formed on the interlayer dielectric layer.
  • the dashed circle in FIG. 1 also schematically shows the side surface of the binding pattern formed by three layers of metal materials, and the exposed metal interlayer on the side surface is likely to undergo substitution reaction with the etchant.
  • the binding pattern 04 is usually a plurality of raised areas on the base substrate 01.
  • the reason for the formation of the multiple raised areas can be as follows: Since the thickness of the interlayer dielectric layer 03 is generally thin, after the interlayer dielectric layer 03 is covered on the gate layer 02, the interlayer dielectric layer 03 will be The outline of the gate pattern 02 is convex, so that the surface of the interlayer dielectric layer 03 has a plurality of convex areas; similarly, since the thickness of the binding pattern 04 is usually thin, it should be covered in the interlayer After the dielectric layer 03, the binding pattern 04 will be raised along the outline of the interlayer dielectric layer 03, so that the finally formed binding pattern 04 is a plurality of raised areas on the base substrate 01, and the plurality of raised areas The area is an uneven area, and the uneven area is easy to be attached to the replaced metal.
  • Fig. 1 schematically shows the uneven area A.
  • FIG. 2 shows a partial structure diagram of another display panel provided in the related art.
  • the display panel 00 shown in FIG. 2 is provided with via holes on the interlayer dielectric layer 03.
  • the via allows the bonding pattern 04 and the gate layer 02 to be electrically connected. Since the interlayer dielectric layer 03 is provided with a via hole, when the binding pattern 04 is formed, a recessed area is formed on the binding pattern 04 corresponding to the via hole, and the recessed area further causes the surface of the binding pattern 04 to be uneven , The area of the uneven area on the surface of the binding pattern 04 is increased. Since the recessed area is also easy to be attached to the replaced metal, the uneven area on the surface of the binding pattern 04 is easier to attach more metal.
  • metal not only easily adheres to uneven areas, but also easily suspends in the air, causing it to be oxidized to produce metal oxides. If the metal oxide falls on the bonding pattern, the conductivity of the bonding pattern is easily affected. For example, the replaced silver is oxidized to silver oxide (AgO) in the air. If the silver oxide falls on the bonding pattern, the conductivity of the bonding pattern is easily affected.
  • AgO silver oxide
  • FIG. 3 shows a partial structure diagram of a display panel 30 provided by an embodiment of the present application.
  • the display panel 30 includes: a base substrate 31, a bonding pattern 32, and a planarization layer (PLN) pattern 33.
  • PPN planarization layer
  • the bonding pattern 32 is formed on the base substrate 31, and the bonding pattern 32 includes at least one conductive block 321, and the conductive block 321 has a bonding area 3211 on a side away from the base substrate 31.
  • the binding area 3211 is used to connect a display panel or a circuit board.
  • FIG. 3 shows a case where the binding pattern 23 includes two conductive blocks 321, but the number of conductive blocks can also be more, which is not limited in the embodiment of the present application.
  • the flat layer pattern 33 is formed by processing the flat layer after forming a flat layer on the base substrate 31 on which the binding pattern 32 is formed.
  • the flat layer pattern 33 has an opening area 331 and a shielding area 332 on a plane parallel to the base substrate 31, and the orthographic projection of the binding area 3211 on the base substrate 31 is located in the orthographic projection of the opening area 331 on the base substrate 31 ,
  • the side surface of the conductive block 321 (the conductive block can be surrounded by two opposite surfaces in the direction perpendicular to the base substrate and a surface connecting the two surfaces, and the surface connecting the two opposite surfaces is the conductive block
  • the orthographic projection on the base substrate 31 is located in the orthographic projection of the shielding area 332 on the base substrate 31, that is, the flat layer pattern 33 covers at least a part of the side surface of the conductive block 321, which is the conductive block 321 Except for the surface close to the base substrate 31 and the surface away from the base substrate 31.
  • the flat layer covers part of the side surface of the conductive block in the binding pattern, the area of the side surface of the conductive block exposed to the interlayer is reduced, and the occurrence of the anodic etching solution and the interlayer is reduced.
  • the displacement reaction also reduces the risk of short-circuiting the bonding pattern due to the replaced metal being attached to the bonding pattern, thereby reducing the phenomenon of abnormal display of the display panel.
  • FIG. 4 shows a top view of the display panel shown in FIG. 3, and the display panel shown in FIG. 3 is a cross-sectional view of the display panel shown in FIG. 4 at DD'.
  • the bonding pattern 32 can also be called a chip on film (COF) unit (COF is a package that fixes the driver integrated circuit on a flexible circuit board). Structure), multiple COF units can form a binding area, and multiple COF units can be set on the display panel.
  • the binding pattern 32 may include the first sub-binding pattern, and FIG. 3 shows the case where the binding pattern 32 includes the first sub-binding pattern.
  • the first sub-binding pattern includes at least one conductive block 321, and the conductive block 321 may also be referred to as a source-drain line (the source-drain line may include a source line, a drain line, or both a source line and a drain line).
  • the source-drain line may be a source-drain metal line), that is, each COF unit may include a first sub-binding pattern, and the first sub-binding pattern includes at least one source-drain metal line.
  • the flat layer includes an organic flat layer, and the material that forms the flat layer includes a photoresist material (ie, photoresist), and the flat layer pattern 33 may be after the flat layer is exposed and developed through a gray-scale mask process. Forming.
  • the gray-scale mask process can also be called a half-exposure process, and the gray-scale mask process can provide different amounts of light at different positions of the mask (also called a gray-scale mask).
  • the gray-scale mask process can provide different amounts of light at different positions of the mask (also called a gray-scale mask).
  • the gray-scale mask may include a first area and a second area.
  • the properties (such as thickness) of the photoresist the light transmittance of the first region and the second region can be different.
  • the photoresist as a positive photoresist as an example, it is used for exposing the positive photoresist.
  • the light transmittance of the first area of the gray-scale mask is smaller than the light transmittance of the second area (for example, it can be realized that the thickness of the first area is greater than the thickness of the second area).
  • the first area corresponds to the shielding area 332 of the flat layer pattern 33
  • the second area corresponds to the area on the display panel excluding the shielding area 332.
  • the area on the display panel excluding the shielding area 332 includes the opening area 331 of the flat layer pattern 33.
  • the flat layer pattern 33 can be formed.
  • a common mask may also be used to form the flat layer pattern 33, which is not limited in the embodiment of the present application.
  • the shielding area 332 of the flat layer pattern (the reference number is not shown in FIG. 4) may have at least one Groove 3321.
  • the shielding area 332 formed with the grooves 3321 has a height difference at each groove 3321. Based on the fluidity of the photoresist material, the photoresist material at a high place will spontaneously flow to a low place to fill up each groove 3321.
  • the size of the opening area of the flat layer is usually larger (the size of the opening area is usually much larger than the size of the groove), so the fluidity of the photoresist material will not affect the opening area), so speed up
  • the surface of the shielding area 332 tends to be flat at a speed, which effectively saves the time of the display panel manufacturing process.
  • the number of grooves 3321 on the shielding area 332 is proportional to the flatness of the surface of the shielding area 332 formed and the speed at which the surface becomes flat, that is, the more the number of grooves 3321 on the shielding area 332 is , The flatter the surface of the shielding region 332 is, and the faster the surface of the flat layer pattern 332 tends to be flat.
  • the groove may also be a through groove, which is not limited in the embodiment of the present application.
  • the thickness of the shielding area is not less than the thickness of the binding pattern, so that the shielding area can cover the area where the side surface of the conductive block may expose the interlayer.
  • the binding pattern 32 is used to connect the circuit board and the display panel, the circuit board and the display panel are connected to the binding pattern 32 through pins (Pin feet) to achieve electrical connection, in order to avoid the pin and the binding pattern 32 It can be stably overlapped, and the shielding area 332 of the flat layer pattern 33 can be set to be flush with the binding pattern 32 (the flush may mean that the shielding area of the flat layer pattern is away from the substrate and the binding pattern is away from the substrate.
  • the shielding area 332 of the flat layer pattern 33 can also be set higher than the binding pattern 32, so that the shielding area 332 can effectively wrap the side surface of the conductive block included in the binding pattern 32 , To avoid being corroded by anode etching solution.
  • the shielding area 332 of the flat layer pattern 33 is flush with the binding pattern 32, which refers to the surface of the shielding area 332 that is far away from the base substrate and the binding pattern 32 is far away from the base substrate after the horizontal plane is allowed to stand for a period of time. The surface is flush. In this way, it is avoided that the thickness of the shielding area 332 of the flat layer pattern 33 is inconsistent before and after the stationary layer due to the fluidity of the forming material of the flat layer, and the shielding area 332 is not finally flush with the binding pattern 32.
  • the binding pattern may further include a second sub-binding pattern, that is, the binding pattern includes a first sub-binding pattern and a second sub-binding pattern.
  • the second sub-binding pattern includes at least one gate pattern
  • the first sub-binding pattern includes at least one conductive block as an example for description.
  • FIG. 6 shows a partial structure diagram of another display panel provided by an embodiment of the present application.
  • FIG. 6 may be a cross-sectional view of the display panel shown in FIG. 5 at EE'.
  • the display panel 30 includes a substrate formed on a base substrate.
  • At least one gate pattern 35 is formed on the base substrate 31 on which the first gate insulating layer 34 is formed (two gate patterns 35 are taken as an example for illustration in FIG. 6),
  • At least one conductive block 321 is formed on the base substrate of the layer 37 (two conductive blocks 321 are taken as an example for illustration in FIG. 6).
  • FIG. 6 shows a case where via holes are provided on the interlayer dielectric layer 37 and the second gate insulating layer 36.
  • the at least one gate pattern 35 corresponds to the at least one conductive block 321 in a one-to-one manner and is electrically connected through the interlayer dielectric layer 37 and the via holes provided on the second gate insulating layer 36.
  • the binding pattern 32 in addition to at least one conductive block 321, also includes at least one gate pattern 35 connected to the conductive block in a one-to-one correspondence, one conductive block 321 and a corresponding one.
  • the gate pattern 35 may be used to form a COF pad, and a COF pad may be referred to as a bonding pattern 32.
  • FIG. 7 shows a top cross-sectional view of the display panel shown in FIG. 6 (the cross-section may be a surface parallel to the base substrate and intersecting the via hole), and in the shielding area 332 of the display panel shown in FIG. 6
  • FIG. 8 schematically shows a structural diagram of a display panel.
  • the display panel includes an operational area (Active Area, AA) and three COF units (that is, three binding patterns 32), wherein each COF unit is It includes at least one COF Pad (that is, includes at least one conductive block 321 and at least one corresponding gate pattern).
  • the AA and the three COF units (ie, binding patterns) are all disposed on a base substrate 31, and the base substrate 31 may be thin film transistor (TFT) glass, and the TFT glass may also be called liquid crystal glass or Electronically controlled liquid crystal glass, etc.
  • TFT thin film transistor
  • the thickness of the shielding area of the flat layer pattern 33 may range from 6500 angstroms to 8800 angstroms.
  • the thickness of the shielding area of the flat layer pattern 33 is 8800 angstroms. Please continue to refer to FIG.
  • the thickness of the second gate insulating layer 36 in the figure is 1300 angstroms
  • the thickness of the interlayer dielectric layer 37 is 5000 angstroms
  • the thickness of each gate pattern 35 is 2500 angstroms
  • each conductive block 321 When the thickness of the shielding area of the flat layer pattern 33 is 8800 angstroms, the shielding area of the flat layer pattern 33 can fill the gap between the conductive block 321 and the interlayer dielectric layer 37, so that the conductive block 321 It can be flat with the conductive block 321, which not only avoids the interlayer exposed on the side of the conductive block, but also enables the circuit board and the display panel to be stably overlapped with the binding pattern 32 through the pin, ensuring the normal display of the display panel display effect.
  • the flat layer covers the side surface of the conductive block in the binding pattern, the area where the side surface of the conductive block is exposed to the interlayer will not contact the outside, and avoid the anodic etching solution and the conductive block.
  • the replacement reaction of the interlayer also avoids the risk of short circuiting of the binding pattern due to the replacement of the metal attached to the binding pattern, and also avoids the phenomenon of abnormal display of the display panel.
  • the shielding area of the flat layer pattern is set to be flush with the binding pattern, the circuit board and the display panel can be stably overlapped with the binding pattern, avoiding pin breakage, and also avoiding the display to a certain extent. An abnormal display appears on the panel.
  • FIG. 9 shows a flowchart of a method for manufacturing a display panel provided by an embodiment of the present application.
  • the method may be used to manufacture the display panel shown in FIG. 3, and the method includes:
  • Step 901 A binding pattern is formed on a base substrate, the binding pattern includes at least one conductive block, and each conductive block has a binding area on a side away from the base substrate.
  • Step 902 forming a flat layer on the base substrate on which the binding pattern is formed.
  • Step 903 Process the flat layer into a flat layer pattern.
  • the flat layer pattern has an opening area and a shielding area on a plane parallel to the base substrate, the orthographic projection of the binding area on the base substrate is located in the orthographic projection of the opening area on the base substrate, and the flat layer pattern is at least At least a part of the side surface of the conductive block is covered, and the side surface is the surface of the conductive block except the surface close to the base substrate and the surface away from the base substrate.
  • the flat layer pattern covers the entire side surface of the conductive block.
  • the flat layer covers part of the side surface of the conductive block in the binding pattern
  • the area where the side surface of the conductive block exposes the interlayer is reduced, and the anodic etching solution and the interlayer are reduced.
  • the replacement reaction of the interlayer also reduces the risk of short-circuiting of the binding pattern due to the attachment of the replaced metal to the binding pattern, which in turn reduces the phenomenon of abnormal display of the display panel.
  • the binding pattern may include a first sub-binding pattern, and the first sub-binding pattern includes at least one conductive block.
  • the manufacturing method of the display panel can refer to the embodiment shown in FIG. 9.
  • the binding pattern may further include a second sub-binding pattern, that is, the binding pattern includes a first sub-binding pattern and a second sub-binding pattern.
  • the second sub-binding pattern includes at least one gate pattern
  • the first sub-binding pattern includes at least one conductive block
  • the first insulating layer includes the first gate insulating layer
  • the second insulating layer includes the second The gate insulating layer will be described as an example.
  • Fig. 10 shows a flowchart of another method for manufacturing a display panel provided by an embodiment of the present application. The method may be used to form the display panel shown in Fig. 7, and the method includes:
  • Step 1001 forming a first gate insulating layer on a base substrate.
  • the first gate insulating layer is formed on the base substrate by coating or the like.
  • the first gate insulating layer may be provided in the same layer as the first gate insulating layer formed in AA.
  • Step 1002 forming a gate pattern on the base substrate on which the first gate insulating layer is formed.
  • the first gate insulating layer formed on the base substrate is processed by a patterning process to form at least one gate pattern.
  • the at least one gate pattern may be arranged in the same layer as the gate pattern of each pixel in AA, and be formed by a patterning process.
  • the patterning process may include the steps of coating photoresist, exposing, developing, etching, and stripping the photoresist.
  • Step 1003 forming a second gate insulating layer on the base substrate on which the gate pattern is formed.
  • the second gate insulating layer is formed on the base substrate by coating or the like.
  • the second gate insulating layer can be provided in the same layer as the second gate insulating layer formed in AA, that is, the second gate insulating layer and the second gate insulating layer formed in AA can be formed in the same layer structure at the same time.
  • Step 1004 forming an interlayer dielectric layer on the base substrate on which the second gate insulating layer is formed.
  • an interlayer dielectric layer is formed on the base substrate on which the second gate insulating layer is formed by coating or the like.
  • the interlayer dielectric layer may be arranged in the same layer as the interlayer dielectric layer formed in AA, and the interlayer dielectric layer may be the same layer structure formed at the same time as the interlayer dielectric layer formed in AA.
  • Step 1005 forming via holes on the interlayer dielectric layer and the second insulating layer.
  • the number of the vias can be multiple.
  • Step 1006 forming at least one conductive block on the base substrate of the interlayer dielectric layer formed with the via hole.
  • Each conductive block of the at least one conductive block may be connected to the corresponding gate pattern through a via hole.
  • at least one conductive block is formed on the base substrate on which the interlayer dielectric layer is formed by a patterning process.
  • the at least one conductive block may be arranged in the same layer as the source and drain metal patterns of each pixel in AA, and formed by a patterning process.
  • the binding pattern includes at least one conductive block, and each conductive block has a binding area on a side away from the base substrate.
  • Step 1007 forming a flat layer on the base substrate on which at least one conductive block is formed.
  • a flat layer is formed on the base substrate by coating or the like.
  • the flat layer can be provided in the same layer as the flat layer formed in AA.
  • Step 1008 processing the flat layer into a flat layer pattern.
  • the flat layer pattern has an opening area and a shielding area on a plane parallel to the base substrate, the orthographic projection of the binding area on the base substrate is located in the orthographic projection of the opening area on the base substrate, and the flat layer pattern is at least At least a part of the side surface of the conductive block is covered, and the side surface is the surface of the conductive block except the surface close to the base substrate and the surface away from the base substrate.
  • the flat layer pattern covers the entire side surface of the conductive block.
  • step 1008 may include: processing the flat layer into a flat layer pattern through a gray-scale mask process, and the shielding area of the flat layer pattern is flush with the binding pattern.
  • the binding pattern includes the first sub-binding pattern and the second sub-binding pattern
  • the shielding area is flush with the outer surface of a layer of the sub-binding pattern that is far from the base substrate in the binding pattern.
  • step 1008 may include: after exposing and developing the flat layer with a designated mask as a mask, forming a flat layer pattern including at least one groove.
  • the designated mask may be the gray-scale mask described above, or other masks, which are not limited in the embodiment of the present application.
  • the designated mask may include a first area, a second area, and a gray-scale mask area.
  • the first area surrounds the gray-scale mask area, the first area may correspond to the shielding area, and the second area may correspond to The opening area corresponds, and the gray-scale mask area may correspond to the at least one groove.
  • a flat layer pattern can be formed.
  • the flat layer pattern includes an opening area and a shielding area, and at least one groove is also formed in the shielding area.
  • the groove please refer to the aforementioned device-side embodiment, which will not be repeated here.
  • the designated mask can also be a common mask (ie, a binary mask), and the flat layer is processed into a flat layer pattern by a common mask process, and the common mask can have at least one concave pattern.
  • the area corresponding to the groove may form at least one groove in the shielding area, which is not limited in the embodiment of the present application.
  • the thickness of the shielding area of the flat layer pattern is 8800 angstroms.
  • the flat layer covers the side surface of the conductive block in the binding pattern, the area where the side surface of the conductive block is exposed to the interlayer will not contact the outside, avoiding the anodic etching solution.
  • the substitution reaction with the interlayer also avoids the risk of short-circuiting the binding pattern due to the substituted metal being attached to the binding pattern, and further avoids the phenomenon of abnormal display of the display panel.
  • the shielding area of the flat layer pattern is set to be flush with the binding pattern, the circuit board and the display panel can be stably overlapped with the binding pattern, avoiding pin breakage, and also avoiding the display to a certain extent. An abnormal display appears on the panel.
  • An embodiment of the present application also provides a display device, which includes the display panel provided in the foregoing embodiment.
  • the display device can be any product or component with display function such as electronic paper, mobile phone, tablet computer, television, monitor, notebook computer, digital photo frame, navigator, etc.

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Abstract

公开了一种显示面板及其制造方法、显示装置，属于显示技术领域。该显示面板包括：衬底基板(31)、绑定图案(32)以及平坦层图案(33)；绑定图案(32)包括至少一个导电块(321)，导电块(321)远离衬底基板的一面具有绑定区域，平坦层图案(33)具有开口区域(331)和遮挡区域(332)，绑定区域(3211)在衬底基板(31)上的正投影位于开口区域(331)在衬底基板(31)上的正投影中，平坦层图案(33)至少覆盖导电块(321)的侧面的至少一部分。如此降低了绑定图案(32)的侧面遭到损坏的可能性，进而减少了显示面板出现异常显示的现象。

Description

显示面板及其制造方法、显示装置
本申请要求于2019年10月9日提交的申请号为201910955832.1、发明名称为“显示面板及其制造方法、显示装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及显示技术领域，特别涉及一种显示面板及其制造方法、显示装置。
背景技术
绑定结构是一种用于连接电路板以及显示面板的结构，绑定结构可以将从电路板接收到的数据信号传输至显示面板，以驱动显示面板进行显示。
其中，绑定结构通过其上设置的绑定图案来连接电路板以及显示面板。相关技术中，为了简化显示面板的制作工艺，绑定结构上的绑定图案与源漏极金属图案同层设置。在源漏极金属图案上通过构图工艺形成阳极时，会先在形成源漏极金属图案以及绑定图案的显示面板上覆盖一层平坦层，再去除绑定图案上覆盖的平坦层而保留显示面板的显示区域中源漏极金属图案上的平坦层，然后在显示区域中的源漏极金属图案上通过构图工艺形成阳极。
发明内容
本申请实施例提供了一种显示面板及其制造方法、显示装置。所述技术方案如下：
根据本申请的一方面，提供了一种显示面板，所述显示面板包括衬底基板、绑定图案以及平坦层图案；
所述绑定图案位于所述衬底基板上，所述绑定图案包括至少一个导电块，所述导电块远离所述衬底基板的一面具有绑定区域，所述平坦层图案在平行于所述衬底基板的平面上具有开口区域和遮挡区域，所述绑定区域在所述衬底基板上的正投影位于所述开口区域在所述衬底基板上的正投影中，所述平坦层图案至少覆盖所述导电块的侧面的至少一部分，所述侧面为所述导电块除靠近所 述衬底基板的表面和远离所述衬底基板的表面外的表面。
可选地，所述绑定图案包括第一子绑定图案和第二子绑定图案，所述第一子绑定图案包括至少一个所述导电块；
所述显示面板包括第一绝缘层、第二绝缘层和层间介质层，所述第一绝缘层、所述第二子绑定图案、所述第二绝缘层、所述层间介质层以及所述第一子绑定图案依次设置于所述衬底基板上。
可选地，所述导电块包括源漏极线。
可选地，所述第二子绑定图案包括栅极图案。
可选地，所述层间介质层和所述第二绝缘层上具有过孔，所述第一子绑定图案通过所述过孔与所述第二子绑定图案可选地，所述平坦层图案的遮挡区域远离所述衬底基板的一面与所述绑定图案远离所述衬底基板的一面平齐。
可选地，所述平坦层图案的遮挡区域的厚度范围为6500埃至8800埃。
可选地，所述平坦层图案的遮挡区域中包括至少一个凹槽。
可选地，所述平坦层图案的遮挡区域远离所述衬底基板的一面与所述绑定图案远离所述衬底基板的一面平齐；
所述绑定图案包括第一子绑定图案和第二子绑定图案，所述第一子绑定图案包括至少一个所述导电块；
所述显示面板包括第一绝缘层、第二绝缘层和层间介质层，所述第一绝缘层、所述第二子绑定图案、所述层间介质层以及所述第一子绑定图案依次设置于所述衬底基板上；
所述导电块包括源漏极线；
所述第二子绑定图案包括栅极图案；
所述层间介质层和所述第二绝缘层上具有过孔，所述第一子绑定图案通过所述过孔与所述第二子绑定图案电连接。
根据本申请的另一方面，提供一种显示面板的制造方法，所述方法包括：
在衬底基板上形成绑定图案，所述绑定图案包括至少一个导电块，每个所述导电块远离所述衬底基板的一面具有绑定区域；
在形成有所述绑定图案的衬底基板上形成平坦层；
将所述平坦层处理为平坦层图案，所述平坦层图案在平行于所述衬底基板的平面上具有开口区域和遮挡区域，所述绑定区域在所述衬底基板上的正投影位于所述开口区域在所述衬底基板上的正投影中，所述平坦层图案至少覆盖所 述导电块的侧面的至少一部分，所述侧面为所述导电块除靠近所述衬底基板的表面和远离所述衬底基板的表面外的表面。
可选地，所述平坦层的材料包括光阻材料，所述将所述平坦层处理为平坦层图案，包括：
将所述平坦层处理为包括至少一个凹槽的平坦层图案，所述至少一个凹槽位于所述平坦层图案的遮挡区域中。
可选地，所述将所述平坦层处理为包括至少一个凹槽的平坦层图案，包括：
以指定掩膜板作为掩膜对所述平坦层进行曝光、显影后，形成包括所述至少一个凹槽的平坦层图案；
其中，所述指定掩膜板包括灰度掩膜区域，所述灰度掩模区域与所述凹槽对应。
可选地，所述指定掩膜板包括第一区域和第二区域，所述第一区域与所述遮挡区域对应，所述第二区域与所述开口区域对应。
可选地，所述将所述平坦层处理为平坦层图案，包括：
通过灰度掩膜工艺将所述平坦层处理为平坦层图案，所述平坦层图案的遮挡区域远离所述衬底基板的一面与所述绑定图案远离所述衬底基板的一面平齐。
可选地，所述绑定图案包括第一子绑定图案和第二子绑定图案，所述在衬底基板上形成绑定图案，包括:
在衬底基板上形成第一绝缘层；
在形成有所述第一绝缘层的衬底基板上形成所述第二子绑定图案；
在形成有所述第二子绑定图案的衬底基板上形成第二绝缘层；
在形成有所述第二绝缘层的衬底基板上形成层间介质层；
在形成有所述层间介质层的衬底基板上所述第一子绑定图案，所述第一子绑定图案包括至少一个所述导电块。
可选地，所述在形成有所述层间介质层的衬底基板上形成所述第一子绑定图案之前，所述方法包括：
在所述层间介质层和所述第二绝缘层上形成过孔；
所述在形成有所述层间介质层的衬底基板上形成所述第一子绑定图案，包括：
在形成有过孔的所述层间介质层的衬底基板上形成第一子绑定图案，所述 第一子绑定图案通过所述层间介质层和所述第二绝缘层上的过孔与所述第二子绑定图案连接。
可选地，所述导电块包括源漏极线，所述第二子绑定图案包括栅极图案。
可选地，所述平坦层图案的遮挡区域的厚度范围为6500埃至8800埃。
可选地，所述平坦层的材料包括光阻材料，所述将所述平坦层处理为平坦层图案，包括：
以指定掩膜板作为掩膜对所述平坦层进行曝光、显影后，形成包括所述至少一个凹槽的平坦层图案；
其中，所述指定掩膜板包括灰度掩膜区域、第一区域和第二区域，所述灰度掩模区域与所述凹槽对应，所述第一区域与所述遮挡区域对应，所述第二区域与所述开口区域对应；
所述绑定图案包括第一子绑定图案和第二子绑定图案，所述在衬底基板上形成绑定图案，包括:
在衬底基板上形成第一绝缘层；
在形成有所述第一绝缘层的衬底基板上形成所述第二子绑定图案；
在形成有所述第二子绑定图案的衬底基板上形成第二绝缘层；
在形成有所述第二绝缘层的衬底基板上形成层间介质层；
在形成有所述层间介质层的衬底基板上所述第一子绑定图案，所述第一子绑定图案包括至少一个所述导电块。
根据本申请的另一方面，提供一种显示装置，所述显示装置包括上述任一所述的显示面板。
附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是一种显示面板的部分结构图；
图2是另一种显示面板的部分结构图；
图3是本申请实施例提供的一种显示面板的部分结构图；
图4是本申请实施例提供的一种显示面板的俯视图；
图5是本申请实施例提供的另一种显示面板的俯视图；
图6是本申请实施例提供的另一种显示面板的部分结构图；
图7是本申请实施例提供的另一种显示面板的结构示意图；
图8是本申请实施例提供的另一种显示面板的结构示意图；
图9是本申请实施例提供的一种显示面板制造方法的流程图；
图10是本申请实施例提供的另一种显示面板制造方法的流程图。
具体实施方式
下面将结合附图对本申请实施方式进行描述。
目前，常采用多层金属材料来形成绑定图案，在采用刻蚀液对阳极层进行刻蚀时，绑定图案侧面露出的多层金属材料的夹层会与刻蚀液发生置换反应。
例如，该多层金属材料为钛/铝/钛(即Ti/Al/Ti)材料，也即是，该多层金属材料为三层金属材料，中间夹层的金属材料为铝，中间夹层的上下两层金属材料均为钛；待刻蚀的阳极也可以由多层材料制成，例如该多层材料为氧化铟锡/银/氧化铟锡(即ITO/Ag/ITO)材料，也即是，该多层材料为三层材料，中间夹层的材料为银，中间夹层的上下两层材料均为氧化铟锡；刻蚀该阳极采用银(Ag)刻蚀剂(Etchant)，该银刻蚀剂中具有银离子。银蚀刻剂对绑定图案中的铝有腐蚀作用，在腐蚀的过程中，铝原子和蚀刻剂中的银离子发生置换反应，生成物银易吸附在绑定图案表面的不平整区域，导致绑定图案有短路的风险。
图1示出的是一种显示面板的部分结构图。该显示面板00包括衬底基板01、形成于衬底基板01上的栅极图案02、形成于栅极图案02上的层间介质(Inter Layer Dielectric，ILD)层03以及形成于层间介质层03上的绑定图案04。图1中的虚线圈内还示意性地示出了由三层金属材料形成的绑定图案的侧面，该侧面露出的金属夹层易与刻蚀剂发生置换反应。
为了便于搭接显示面板以及电路板(如印刷电路板)，绑定图案04通常为衬底基板01上的多个凸起区域。该多个凸起区域的形成原因可以如下：由于层间介质层03的厚度通常较薄，因此，在将层间介质层03覆盖在栅极层02上之后，该层间介质层03会沿着栅极图案02的轮廓凸起，使得该层间介质层03的表面具有多个凸起区域；类似的，由于绑定图案04的厚度通常也较薄，因此，在将其覆盖在层间介质层03上之后，该绑定图案04会沿着层间介质层03的轮廓凸起，使得最终形成的绑定图案04为衬底基板01上的多个凸起区域，该多个凸起区域为不平整区域，该不平整区域易被置换出的金属附着。图1示意性 地示出了该不平整区域A。
图2示出的是相关技术中提供的另一种显示面板的部分结构图。图2示出的显示面板00在图1所示的显示面板00的基础上，在层间介质层03上设置了过孔。该过孔使得绑定图案04与栅极层02能够电连接。由于层间介质层03上设置了过孔，使得在形成绑定图案04时，绑定图案04上与该过孔对应的地方会形成凹陷区域，该凹陷区域进一步导致绑定图案04表面不平整，增大了绑定图案04表面的不平整区域的面积。由于该凹陷区域也易被置换出的金属附着，导致绑定图案04表面的不平整区域较易附着更多的金属。
另外，金属不但易附着在不平整区域上，也易悬浮在空气中导致被氧化生成金属氧化物。该金属氧化物若掉落在绑定图案上易影响绑定图案的导电性。例如，置换出的银在空气中氧化成氧化银(AgO)，氧化银若掉落在绑定图案上易影响该绑定图案的导电性。
图3示出了本申请实施例提供的一种显示面板30的部分结构图，显示面板30包括：衬底基板31、绑定图案32以及平坦层(Planarization Layer，PLN)图案33。
其中，绑定图案32形成于衬底基板31上，绑定图案32包括至少一个导电块321，导电块321远离衬底基板31的一面具有绑定区域3211。绑定区域3211用于连接显示面板或者电路板。其中，图3示出的是绑定图案23包括两个导电块321的情况，但导电块的数量还可以更多，本申请实施例对此不进行限制。
平坦层图案33为在形成有绑定图案32的衬底基板31上形成平坦层后，将平坦层处理形成的。平坦层图案33在平行于衬底基板31的平面上具有开口区域331和遮挡区域332，绑定区域3211在衬底基板31上的正投影位于开口区域331在衬底基板31上的正投影中，导电块321的侧面(导电块可以由垂直于衬底基板的方向上相对的两个面以及将这两个面连接的一个面围成，连接该相对的两个面的面即为导电块的侧面)在衬底基板31上的正投影位于遮挡区域332在衬底基板31上的正投影中，也即是平坦层图案33至少覆盖导电块321的侧面的至少一部分，该侧面为导电块321除靠近衬底基板31的表面和远离衬底基板31的表面外的表面。
综上所述，本申请实施例提供的显示面板，由于平坦层覆盖了绑定图案中导电块的部分侧面，减小了导电块侧面露出夹层的区域，减少了阳极刻蚀液与 该夹层发生置换反应，也降低了由于置换出的金属附着在绑定图案而导致绑定图案短路的风险，进而也降低了显示面板出现异常显示的现象。
图4示出的是图3所示的显示面板的俯视图，图3所示的显示面板为图4所示的显示面板在DD’处的剖面图。
需要说明的是，在其他可选的实现方式中，绑定图案32也可以称为覆晶薄膜(Chip on film，COF)单元(COF是一种将驱动集成电路固定于柔性线路板上的封装结构)，多个COF单元可以组成绑定区域，显示面板上可以设置有多个COF单元。绑定图案32可以包括第一子绑定图案，图3示出的即是该绑定图案32包括第一子绑定图案的情况。该第一子绑定图案包括至少一个导电块321，该导电块321也可以称为源漏极线(该源漏极线可以包括源极线、漏极线或者既包括源极线也包括漏极线，该源漏极线可以为源漏极金属线)，也即是，每个COF单元可以包括第一子绑定图案，该第一子绑定图案包括至少一个源漏极金属线。可选的，平坦层包括有机平坦层，形成该平坦层的材料包括光阻材料(即光刻胶)，则平坦层图案33可以为通过灰度掩膜工艺对平坦层进行曝光、显影处理后形成的。
其中，灰度掩膜板工艺也可以称为半曝光工艺，灰度掩膜板工艺可以在掩膜板(也称为灰度掩膜板)的不同位置提供不同的透光量，在经过一次显影之后，便可以形成厚度不同的多个光刻胶区域，进而可以光刻出厚度不同的多个图案。
在本申请实施例中，该灰度掩膜板可以包括第一区域和第二区域。根据光刻胶的性质(如厚度)不同，第一区域和第二区域的透光量可以不同，以光刻胶为正性光刻胶为例，用于对正性光刻胶进行曝光的灰度掩膜板的第一区域的透光量小于第二区域的透光量(例如第一区域的厚度大于第二区域的厚度即可以实现)。该第一区域对应平坦层图案33的遮挡区域332，第二区域对应显示面板上除遮挡区域332之外的区域，显示面板上除遮挡区域332之外的区域包括平坦层图案33的开口区域331。在经过一次显影之后，便可以形成平坦层图案33。当然，在其他可选的实现方式中也可以采用普通掩膜板形成平坦层图案33，本申请实施例对此不进行限制。
可选的，由于光阻材料具有流动性，将显示面板在水平面上静置一段时间之后，遮挡区域332的表面可以趋于平坦。为了保证遮挡区域332的表面可以 较快速地趋于平坦，如图5所示，在显示面板的制造过程中，平坦层图案(该标号图4中未示出)的遮挡区域332可以具有至少一个凹槽3321。形成有凹槽3321的遮挡区域332在每个凹槽3321处均具有高低落差，基于光阻材料的流动性，处于高处的光阻材料会自发地流向低处以将每个凹槽3321填平(需要说明的是，平坦层的开口区域的尺寸通常较大(开口区域的尺寸通常远大于凹槽的尺寸)，因而光阻材料的流动性不会对该开口区域造成影响)，如此加快了遮挡区域332的表面趋于平坦的速度，有效节约了显示面板制造工艺的时间。需要说明的是，遮挡区域332上凹槽3321的数量与形成的遮挡区域332表面的平坦程度以及该表面趋于平坦的速度成正比，也即是，遮挡区域332上凹槽3321的数量越多，遮挡区域332的表面越平坦，且平坦层图案332的表面趋于平坦的速度越快。当然，该凹槽也可以为通槽，本申请实施例对此不进行限制。
可选的，在本申请实施例中，遮挡区域的厚度不小于绑定图案的厚度，如此可以使遮挡区域能够覆盖导电块侧面可能会露出夹层的区域。考虑到绑定图案32用于连接电路板以及显示面板，该电路板以及显示面板均通过引脚(Pin脚)与绑定图案32搭接以实现电连接，为了避免引脚与绑定图案32可以稳定搭接，可以将平坦层图案33的遮挡区域332设置为与绑定图案32平齐(该平齐可以是指平坦层图案的遮挡区域远离衬底基板的一面与绑定图案远离衬底基板的一面平齐，该平齐可以是指共面)，参考图3所示的显示面板。当然，在其他可选的实现方式中，平坦层图案33的遮挡区域332也可以设置为高于绑定图案32，使得该遮挡区域332可以有效将绑定图案32包括的导电块的侧面包裹住，避免被阳极刻蚀液腐蚀。
需要说明的是，平坦层图案33的遮挡区域332与绑定图案32平齐，指的是在水平面静置一段时间之后的遮挡区域332远离衬底基板的表面与绑定图案32远离衬底基板的表面平齐。如此避免了由于平坦层的形成材料具有流动性而导致静置前和静置后平坦层图案33的遮挡区域332厚度不一致，而导致遮挡区域332最终并非与绑定图案32平齐的情况。
在其他可选的实现方式中，绑定图案还可以包括第二子绑定图案，即该绑定图案包括第一子绑定图案和第二子绑定图案，在本申请实施例中，以第二子绑定图案包括至少一个栅极图案，第一子绑定图案包括至少一个导电块为例进行说明。图6示出了本申请实施例提供的另一种显示面板的部分结构图，图6可以是图5所示的显示面板在EE’处的剖面图，该显示面板30包括形成于衬 底基板上的第一栅绝缘层34，在形成有第一栅绝缘层34的衬底基板31上形成的至少一个栅极图案35(图6中以两个栅极图案35为例进行说明)、在形成有栅极图案35的衬底基板31上形成的第二栅绝缘层36、在形成有第二栅绝缘层36的衬底基板31上形成的层间介质层37以及在形成有层间介质层37的衬底基板上形成的至少一个导电块321(图6中以两个导电块321为例进行说明)。另外，该显示面板30的平坦层图案33的遮挡区域332中，设置有多个凹槽3321。需要说明的是，图6示出的是在层间介质层37以及第二栅绝缘层36上设置了过孔的情况。至少一个栅极图案35与至少一个导电块321一一对应并通过层间介质层37以及第二栅绝缘层36上设置的过孔电连接。
在图6所示的实现方式中，绑定图案32除了包括至少一个导电块321之外，还包括与该导电块一一对应连接的至少一个栅极图案35，一个导电块321和一个对应的栅极图案35可以用于组成一个COF焊盘(pad)，一个COF pad可以称为一个绑定图案32。
图7示出的是图6所示的显示面板的俯视剖面图(剖面可以为平行于衬底基板，且与过孔相交的面)，并且，在图6所示的显示面板的遮挡区域332中形成有至少一个凹槽3321的示意图。从图7中可以看出，至少一个导电块321上具有用于连接第一子图案和第二子绑定图案的多个过孔D。
图8示意性地示出了一种显示面板的结构示意图，该显示面板包括可操作区域(Active Area，AA)以及3个COF单元(即3个绑定图案32)，其中每个COF单元均包括至少一个COF Pad(即包括至少一个导电块321以及对应的至少一个栅极图案)。AA和该3个COF单元(即绑定图案)均设置于衬底基板31上，该衬底基板31可以为薄膜晶体管(Thin Film Transistor，TFT)玻璃，该TFT玻璃也可以称为液晶玻璃或者电控液晶玻璃等。
可选的，平坦层图案33的遮挡区域的厚度范围可以为6500埃至8800埃，示例的，平坦层图案33的遮挡区域的厚度为8800埃。请继续参考图6，假设该图中第二栅绝缘层36的厚度为1300埃、层间介质层37的厚度为5000埃、每个栅极图案35的厚度为2500埃以及每个导电块321的厚度为6300埃，当平坦层图案33的遮挡区域的厚度为8800埃时，该平坦层图案33的遮挡区域可以填充导电块321与层间介质层37之间的断差，使得导电块321与导电块321之间可以趋于平坦，既避免了导电块的侧面会露出夹层的情况，又使得电路板以及显示面板可以通过Pin脚与绑定图案32稳定搭接，保证了显示面板的正常显示 效果。
综上所述，本申请实施例提供的显示面板，由于平坦层覆盖了绑定图案中导电块的侧面，使得导电块侧面露出夹层的区域不会与外界接触，避免了阳极刻蚀液与该夹层发生置换反应，也避免了由于置换出的金属附着在绑定图案而导致绑定图案短路的风险，进而也避免了显示面板出现异常显示的现象。另外，由于将平坦层图案的遮挡区域设置为与绑定图案平齐，使得电路板以及显示面板可以与绑定图案进行稳定搭接，避免引脚断裂的情况，也在一定程度上避免了显示面板出现异常显示的现象。
图9示出的是本申请实施例提供的一种显示面板制造方法的流程图，该方法可以用于制造图3所示的显示面板，该方法包括：
步骤901、在衬底基板上形成绑定图案，绑定图案包括至少一个导电块，每个导电块远离衬底基板的一面具有绑定区域。
步骤902、在形成有绑定图案的衬底基板上形成平坦层。
步骤903、将平坦层处理为平坦层图案。
该平坦层图案在平行于衬底基板的平面上具有开口区域和遮挡区域，绑定区域在衬底基板上的正投影位于开口区域在所述衬底基板上的正投影中，平坦层图案至少覆盖导电块的侧面的至少一部分，该侧面为导电块除靠近衬底基板的表面和远离衬底基板的表面外的表面。可选地，平坦层图案覆盖导电块的整个侧面。
综上所述，本申请实施例提供的显示面板制造方法，由于平坦层覆盖了绑定图案中导电块的部分侧面，减小了导电块侧面露出夹层的区域，减少了阳极刻蚀液与该夹层发生置换反应，也降低了由于置换出的金属附着在绑定图案而导致绑定图案短路的风险，进而也降低了显示面板出现异常显示的现象。
可选的，绑定图案可以包括第一子绑定图案，该第一子绑定图案包括至少一个导电块。则该显示面板的制造方法可以参考图9所示的实施例。
可选的，绑定图案还可以包括第二子绑定图案，即该绑定图案包括第一子绑定图案和第二子绑定图案。本申请实施例中，以第二子绑定图案包括至少一个栅极图案，第一子绑定图案包括至少一个导电块，第一绝缘层包括第一栅绝缘层以及第二绝缘层包括第二栅绝缘层为例进行说明。图10示出了本申请实施 例提供的另一种显示面板的制造方法的流程图，该方法可以用于形成图7所示的显示面板，该方法包括：
步骤1001、在衬底基板上形成第一栅绝缘层。
可选的，通过涂覆等方式在衬底基板上形成第一栅绝缘层。该第一栅绝缘层可以与AA中形成的第一栅绝缘层同层设置。
步骤1002、在形成有第一栅绝缘层的衬底基板上形成栅极图案。
可选的，通过构图工艺将衬底基板上形成的第一栅绝缘层处理形成至少一个栅极图案。该至少一个栅极图案可以与AA中每个像素的栅极图案同层设置，且通过一次构图工艺形成。本申请实施例中，构图工艺可以包括涂覆光刻胶、曝光、显影、刻蚀和剥离光刻胶等步骤。
步骤1003、在形成有栅极图案的衬底基板上形成第二栅绝缘层。
可选的，通过涂覆等方式在衬底基板上形成第二栅绝缘层。该第二栅绝缘层可以与AA中形成的第二栅绝缘层同层设置，也即是该第二栅绝缘层可以与AA中形成的第二栅绝缘层为同时形成的同层结构。
步骤1004、在形成有第二栅绝缘层的衬底基板上形成层间介质层。
可选的，通过涂覆等方式在形成有第二栅绝缘层的衬底基板上形成层间介质层。该层间介质层可以与AA中形成的层间介质层同层设置，该层间介质层可以与AA中形成的层间介质层为同时形成的同层结构。
步骤1005、在层间介质层和第二绝缘层上形成过孔。
该过孔的数量可以为多个。
步骤1006、在形成有过孔的层间介质层的衬底基板上形成至少一个导电块。
该至少一个导电块中的每个导电块可以通过一个过孔与对应的栅极图案连接。可选的，通过构图工艺在形成有层间介质层的衬底基板上形成至少一个导电块。该至少一个导电块可以与AA中每个像素的源漏极金属图案同层设置，且通过一次构图工艺形成。该绑定图案包括至少一个导电块，每个导电块远离衬底基板的一面具有绑定区域。
步骤1007、在形成有至少一个导电块的衬底基板上形成平坦层。
可选的，通过涂覆等方式在衬底基板上形成平坦层。该平坦层可以与AA中形成的平坦层同层设置。
步骤1008、将平坦层处理为平坦层图案。
该平坦层图案在平行于衬底基板的平面上具有开口区域和遮挡区域，绑定 区域在衬底基板上的正投影位于开口区域在所述衬底基板上的正投影中，平坦层图案至少覆盖导电块的侧面的至少一部分，该侧面为导电块除靠近衬底基板的表面和远离衬底基板的表面外的表面。可选地，平坦层图案覆盖导电块的整个侧面。
可选的，步骤1008可以包括：通过灰度掩膜板工艺将平坦层处理为平坦层图案，平坦层图案的遮挡区域与绑定图案平齐。当绑定图案包括第一子绑定图案和第二子绑定图案时，该遮挡区域与绑定图案中远离衬底基板的一层子绑定图案的外表面平齐。平坦层图案的遮挡区域与绑定图案平齐的相关描述可以参考前述装置侧实施例，在此不再赘述。
可选的，步骤1008可以包括：以指定掩膜板作为掩膜对平坦层进行曝光、显影后，形成包括至少一个凹槽的平坦层图案。可选的，该指定掩膜板可以为前述描述的灰度掩膜板，或者其他掩膜板，本申请实施例对此不进行限制。该指定掩膜板可以包括第一区域、第二区域以及灰度掩模区域，该第一区域围绕在灰度掩模区域四周，该第一区域可以与遮挡区域对应，该第二区域可以与开口区域对应，该灰度掩模区域可以与该至少一个凹槽对应。在采用该指定掩膜板对平坦层进行曝光显影之后，可以形成平坦层图案，该平坦层图案包括开口区域和遮挡区域，该遮挡区域中还形成有至少一个凹槽。与凹槽有关的描述可以参考前述装置侧实施例，在此不再赘述。
当然，该指定掩膜板也可以为普通掩膜板(即二元掩膜板)，采用普通的掩膜工艺将平坦层处理为平坦层图案，该普通掩膜板中可以具有与至少一个凹槽对应的区域，以在遮挡区域中形成至少一个凹槽，本申请实施例对此不进行限制。
可选的，平坦层图案的遮挡区域的厚度为8800埃。
综上所述，本申请实施例提供的显示面板制造方法，由于平坦层覆盖了绑定图案中导电块的侧面，使得导电块侧面露出夹层的区域不会与外界接触，避免了阳极刻蚀液与该夹层发生置换反应，也避免了由于置换出的金属附着在绑定图案而导致绑定图案短路的风险，进而也避免了显示面板出现异常显示的现象。另外，由于将平坦层图案的遮挡区域设置为与绑定图案平齐，使得电路板以及显示面板可以与绑定图案进行稳定搭接，避免引脚断裂的情况，也在一定程度上避免了显示面板出现异常显示的现象。
本申请实施例还提供一种显示装置，该显示装置包括上述实施例提供的显示面板。显示装置可以为电子纸、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
上述可选技术方案，可以采用任意结合形成本申请的可选实施例，在此不再一一赘述。
以上所述仅为本申请的可选实施例，并不用以限制本申请，凡在本申请的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本申请的保护范围之内。

Claims (20)

  1. 一种显示面板，所述显示面板(30)包括衬底基板(31)、绑定图案(32)以及平坦层图案(33)；
    所述绑定图案(32)位于所述衬底基板(31)上，所述绑定图案(32)包括至少一个导电块(321)，所述导电块(321)远离所述衬底基板的一面具有绑定区域，所述平坦层图案(33)在平行于所述衬底基板(31)的平面上具有开口区域(331)和遮挡区域(332)，所述绑定区域(3211)在所述衬底基板(31)上的正投影位于所述开口区域(331)在所述衬底基板(31)上的正投影中，所述平坦层图案(33)至少覆盖所述导电块(321)的侧面的至少一部分，所述侧面为所述导电块(321)除靠近所述衬底基板(31)的表面和远离所述衬底基板(31)的表面外的表面。
  2. 根据权利要求1所述的显示面板，所述绑定图案(32)包括第一子绑定图案和第二子绑定图案，所述第一子绑定图案包括至少一个所述导电块(321)；
    所述显示面板(30)包括第一绝缘层(34)、第二绝缘层(36)和层间介质层(37)，所述第一绝缘层(34)、所述第二子绑定图案、所述第二绝缘层(36)、所述层间介质层(37)以及所述第一子绑定图案依次设置于所述衬底基板(31)上。
  3. 根据权利要求2所述的显示面板，所述导电块(321)包括源漏极线。
  4. 根据权利要求2所述的显示面板，所述第二子绑定图案包括栅极图案(35)。
  5. 根据权利要求2-4任一所述的显示面板，所述层间介质层(37)和所述第二绝缘层(36)上具有过孔，所述第一子绑定图案通过所述过孔与所述第二子绑定图案电连接。
  6. 根据权利要求1所述的显示面板，所述平坦层图案(33)的遮挡区域(332)远离所述衬底基板的一面与所述绑定图案(32)远离所述衬底基板的一面平齐。
  7. 根据权利要求1-6任一所述的显示面板，所述平坦层图案(33)的遮挡区域(332)的厚度范围为6500埃至8800埃。
  8. 根据权利要求1-6任一所述的显示面板，所述平坦层图案(33)的遮挡区域中包括至少一个凹槽。
  9. 根据权利要求1所述的显示面板，所述平坦层图案(33)的遮挡区域(332)远离所述衬底基板(31)的一面与所述绑定图案(32)远离所述衬底基板(31)的一面平齐；
    所述绑定图案包括第一子绑定图案和第二子绑定图案，所述第一子绑定图案包括至少一个所述导电块(321)；
    所述显示面板包括第一绝缘层(34)、第二绝缘层(36)和层间介质层(37)，所述第一绝缘层(34)、所述第二子绑定图案、所述层间介质层(37)以及所述第一子绑定图案依次设置于所述衬底基板(31)上；
    所述导电块(321)包括源漏极线；
    所述第二子绑定图案包括栅极图案(35)；
    所述层间介质层(37)和所述第二绝缘层(36)上具有过孔，所述第一子绑定图案通过所述过孔与所述第二子绑定图案电连接。
  10. 一种显示面板的制造方法，所述方法包括：
    在衬底基板上形成绑定图案，所述绑定图案包括至少一个导电块，每个所述导电块远离所述衬底基板的一面具有绑定区域；
    在形成有所述绑定图案的衬底基板上形成平坦层；
    将所述平坦层处理为平坦层图案，所述平坦层图案在平行于所述衬底基板的平面上具有开口区域和遮挡区域，所述绑定区域在所述衬底基板上的正投影位于所述开口区域在所述衬底基板上的正投影中，所述平坦层图案至少覆盖所述导电块的侧面的至少一部分，所述侧面为所述导电块除靠近所述衬底基板的表面和远离所述衬底基板的表面外的表面。
  11. 根据权利要求10所述的显示面板的制造方法，所述平坦层的材料包括光阻材料，所述将所述平坦层处理为平坦层图案，包括：
    将所述平坦层处理为包括至少一个凹槽的平坦层图案，所述至少一个凹槽位于所述平坦层图案的遮挡区域中。
  12. 根据权利要求11所述的显示面板的制造方法，所述将所述平坦层处理为包括至少一个凹槽的平坦层图案，包括：
    以指定掩膜板作为掩膜对所述平坦层进行曝光、显影后，形成包括所述至少一个凹槽的平坦层图案；
    其中，所述指定掩膜板包括灰度掩膜区域，所述灰度掩模区域与所述凹槽对应。
  13. 根据权利要求12所述的显示面板的制造方法，所述指定掩膜板包括第一区域和第二区域，所述第一区域与所述遮挡区域对应，所述第二区域与所述开口区域对应。
  14. 根据权利要求10所述的显示面板的制造方法，所述将所述平坦层处理为平坦层图案，包括：
    通过灰度掩膜工艺将所述平坦层处理为平坦层图案，所述平坦层图案的遮挡区域远离所述衬底基板的一面与所述绑定图案远离所述衬底基板的一面平齐。
  15. 根据权利要求10至14任一所述的显示面板的制造方法，所述绑定图案包括第一子绑定图案和第二子绑定图案，所述在衬底基板上形成绑定图案，包括:
    在衬底基板上形成第一绝缘层；
    在形成有所述第一绝缘层的衬底基板上形成所述第二子绑定图案；
    在形成有所述第二子绑定图案的衬底基板上形成第二绝缘层；
    在形成有所述第二绝缘层的衬底基板上形成层间介质层；
    在形成有所述层间介质层的衬底基板上所述第一子绑定图案，所述第一子 绑定图案包括至少一个所述导电块。
  16. 根据权利要求15所述的显示面板的制造方法，所述在形成有所述层间介质层的衬底基板上形成所述第一子绑定图案之前，所述方法包括：
    在所述层间介质层和所述第二绝缘层上形成过孔；
    所述在形成有所述层间介质层的衬底基板上形成所述第一子绑定图案，包括：
    在形成有过孔的所述层间介质层的衬底基板上形成第一子绑定图案，所述第一子绑定图案通过所述层间介质层和所述第二绝缘层上的过孔与所述第二子绑定图案连接。
  17. 根据权利要求15或16所述的显示面板的制造方法，所述导电块包括源漏极线，所述第二子绑定图案包括栅极图案。
  18. 根据权利要求10至14任一所述的显示面板的制造方法，所述平坦层图案的遮挡区域的厚度范围为6500埃至8800埃。
  19. 根据权利要求10所述的显示面板的制造方法，所述平坦层的材料包括光阻材料，所述将所述平坦层处理为平坦层图案，包括：
    以指定掩膜板作为掩膜对所述平坦层进行曝光、显影后，形成包括所述至少一个凹槽的平坦层图案；
    其中，所述指定掩膜板包括灰度掩膜区域、第一区域和第二区域，所述灰度掩模区域与所述凹槽对应，所述第一区域与所述遮挡区域对应，所述第二区域与所述开口区域对应；
    所述绑定图案包括第一子绑定图案和第二子绑定图案，所述在衬底基板上形成绑定图案，包括:
    在衬底基板上形成第一绝缘层；
    在形成有所述第一绝缘层的衬底基板上形成所述第二子绑定图案；
    在形成有所述第二子绑定图案的衬底基板上形成第二绝缘层；
    在形成有所述第二绝缘层的衬底基板上形成层间介质层；
    在形成有所述层间介质层的衬底基板上所述第一子绑定图案，所述第一子绑定图案包括至少一个所述导电块。
  20. 一种显示装置，所述显示装置包括权利要求1至8任一所述的显示面板。
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104536207A (zh) * 2014-12-31 2015-04-22 京东方科技集团股份有限公司 一种显示基板及显示装置
CN107272244A (zh) * 2017-08-15 2017-10-20 京东方科技集团股份有限公司 一种阵列基板及其制作方法、显示面板、显示装置
CN107579040A (zh) * 2017-09-07 2018-01-12 京东方科技集团股份有限公司 一种掩膜版、阵列基板及其制作方法
CN108550588A (zh) * 2018-06-08 2018-09-18 京东方科技集团股份有限公司 显示面板、显示面板的制造方法和显示装置
CN110676217A (zh) * 2019-10-09 2020-01-10 京东方科技集团股份有限公司 显示面板及其制造方法、显示装置

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9324449B2 (en) * 2012-03-28 2016-04-26 Semiconductor Energy Laboratory Co., Ltd. Driver circuit, signal processing unit having the driver circuit, method for manufacturing the signal processing unit, and display device

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104536207A (zh) * 2014-12-31 2015-04-22 京东方科技集团股份有限公司 一种显示基板及显示装置
CN107272244A (zh) * 2017-08-15 2017-10-20 京东方科技集团股份有限公司 一种阵列基板及其制作方法、显示面板、显示装置
CN107579040A (zh) * 2017-09-07 2018-01-12 京东方科技集团股份有限公司 一种掩膜版、阵列基板及其制作方法
CN108550588A (zh) * 2018-06-08 2018-09-18 京东方科技集团股份有限公司 显示面板、显示面板的制造方法和显示装置
CN110676217A (zh) * 2019-10-09 2020-01-10 京东方科技集团股份有限公司 显示面板及其制造方法、显示装置

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