WO2021068456A1 - 半导体器件及其制作方法 - Google Patents

半导体器件及其制作方法 Download PDF

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WO2021068456A1
WO2021068456A1 PCT/CN2020/079512 CN2020079512W WO2021068456A1 WO 2021068456 A1 WO2021068456 A1 WO 2021068456A1 CN 2020079512 W CN2020079512 W CN 2020079512W WO 2021068456 A1 WO2021068456 A1 WO 2021068456A1
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dielectric layer
insulating dielectric
manufacturing
blind hole
patterned
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PCT/CN2020/079512
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English (en)
French (fr)
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曹立强
张春艳
孙鹏
李恒甫
包焓
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上海先方半导体有限公司
华进半导体封装先导技术研发中心有限公司
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Publication of WO2021068456A1 publication Critical patent/WO2021068456A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/7684—Smoothing; Planarisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
    • H01L2221/1068—Formation and after-treatment of conductors

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  • the present invention relates to the technical field of semiconductor device manufacturing technology, and more specifically, to a semiconductor device and a manufacturing method thereof.
  • TSV through silicon vias
  • the TSV technology is a technology in which vertical through holes are made by etching or laser drilling between different device structures, and then conductive materials are deposited in the vertical through holes by electroplating to form conductive pillars to achieve electrical interconnection. If the Via-First method is adopted, since the depth of the through hole is smaller than the thickness of the substrate, the prior art generally thins the back of the device, and then exposes the inside of the through hole on the back of the device through an etching process. This method will lead to the problem of inconsistent exposure height of the conductive pillars exposed on the back of the device.
  • the present application provides a semiconductor device and a manufacturing method thereof, which solves the problem of inconsistent exposure heights of conductive pillars in the TSV structure.
  • the technical solution of the present invention is as follows:
  • a method for manufacturing a semiconductor device includes:
  • a semiconductor substrate with a TSV structure is provided.
  • the semiconductor substrate has a first surface and a second surface opposite to each other.
  • the TSV structure includes a blind hole on the first surface, a sidewall of the blind hole, and
  • the bottom surface has a first insulating dielectric layer; a conductive post filling the blind hole;
  • a patterned second insulating dielectric layer is formed on the second surface, and the second insulating dielectric layer exposes the conductive pillars.
  • the second surface is thinned.
  • the method further includes:
  • the semiconductor substrate and the bonding carrier are separated.
  • the method of forming the patterned second insulating dielectric layer includes:
  • the second insulating dielectric layer covering the second surface and the conductive pillar is formed;
  • the second insulating medium layer is a photosensitive organic insulating layer formed on the second surface by a coating method
  • the second insulating dielectric layer is patterned through an exposure process to remove the part of the second insulating dielectric layer covering the conductive pillars.
  • the second insulating dielectric layer is an inorganic dielectric layer formed on the second surface by a deposition method
  • the second insulating dielectric layer is patterned through an etching process to remove the portion of the second insulating dielectric layer covering the conductive pillars.
  • a layer of the inorganic medium layer or a plurality of stacked inorganic medium layers is formed on the second surface by a deposition method.
  • the manufacturing method of the semiconductor substrate includes:
  • the conductive pillar is formed in the blind hole whose surface is covered with the first insulating dielectric layer.
  • the hole diameter of the blind hole is not less than 10 ⁇ m.
  • the present invention also provides a semiconductor device, which is prepared by using any of the above-mentioned manufacturing methods.
  • the second surface of the semiconductor substrate is thinned, the second surface is subjected to chemical mechanical polishing, so that the mechanical polishing is performed Combined with the chemical polishing method, the semiconductor substrate, the first insulating dielectric layer of the TSV structure and the conductive pillars can be polished and removed at the same time, so that the exposed conductive pillars are flush with the polished second surface, and the height of each conductive pillar is flush.
  • a patterned second insulating dielectric layer is formed on the second surface after the chemical mechanical polishing treatment. Since the heights of the conductive pillars relative to the second insulating dielectric layer are also the same, the exposed height of the conductive pillars in the prior art is avoided. The problem of inconsistency.
  • Figures 1 to 5 are a process flow chart for exposing conductive pillars in TSV based on a wet etching process
  • 6 to 13 are process flow diagrams of a method for manufacturing a semiconductor device according to an embodiment of the present invention.
  • Fig. 1 to Fig. 5 is a process flow diagram of exposing conductive pillars in TSV based on a wet etching process, and the process includes:
  • Step S11 As shown in FIG. 1, a silicon substrate 11 with a TSV structure is provided.
  • the silicon substrate 11 has a first surface and a second surface opposite to each other.
  • the TSV structure includes a blind hole located on the first surface, a first insulating dielectric layer 12 is provided on the sidewall and bottom surface of the blind hole, and a conductive pillar 13 filling the blind hole. After the second surface is thinned, it is bonded and fixed to the bonding carrier 14 through the adhesive layer 15.
  • Step S12 As shown in FIG. 2, the second surface is wet-etched with a chemical reagent to expose the TSV structure.
  • Step S13 As shown in FIGS. 3 and 4, firstly, an insulating photoresist layer is coated, and the photoresist layer covers the TSV structure. Then, the photoresist layer is under-exposed to remove part of the photoresist layer. The thickness of the photoresist layer exposes the TSV structure.
  • Step S14 As shown in FIG. 5, the first insulating dielectric layer 12 on the surface of the TSV structure is removed by a dry etching process, and the conductive pillars 13 are exposed. Finally, the bonding carrier 14 is separated from the silicon substrate 11.
  • the problem of the inconsistency in the exposed height of the conductive pillars 13 in the TSV structure is the uniformity of the etching depth of the through holes during the formation of the TSV structure, and the uniformity of the bonding of the adhesive layer 15 between the silicon substrate 11 and the bonding carrier 14
  • the uniformity of the thinning of the second surface of the silicon substrate 11 and the uniformity of the TSV structure wet etching outcrop are the result of the accumulation of tolerances of multiple processes, which are problems that cannot be avoided and solved by the traditional process.
  • the second surface Carry out chemical mechanical polishing treatment in this way, through the method of mechanical polishing combined with chemical polishing, the semiconductor substrate, the first insulating dielectric layer of the TSV structure and the conductive pillars can be polished and removed at the same time, so that the exposed conductive pillars are aligned with the polished second surface.
  • the height of each conductive pillar is even.
  • each conductive pillar relative to the second insulating dielectric layer is also the same This avoids the problem of inconsistent exposed heights of conductive pillars in the prior art.
  • FIGS. 6-13 are process flow diagrams of a manufacturing method of a semiconductor device according to an embodiment of the present invention, and the manufacturing method includes:
  • Step S21 As shown in FIG. 6, a semiconductor substrate 21 having a TSV structure is provided.
  • the semiconductor substrate 21 has a first surface and a second surface opposite to each other.
  • the TSV structure includes a blind hole located on the first surface, and the sidewall and bottom surface of the blind hole have a first insulating dielectric layer 22; The conductive pillar 23 of the blind hole 22 is filled.
  • the manufacturing method of the semiconductor substrate 21 includes: first, forming a blind hole on the first surface; then, depositing the first insulating dielectric layer 22 on the sidewall and bottom of the blind hole; finally, The conductive pillar 23 is formed in the blind hole whose surface is covered with the first insulating dielectric layer 22.
  • the conductive pillar 23 may be a metal pillar, such as a copper pillar, an aluminum pillar, or a silver pillar.
  • the conductive pillar may be formed by an electroplating process.
  • the semiconductor substrate 21 may be a silicon substrate.
  • the first insulating dielectric layer 22 may be a silicon dioxide layer.
  • the semiconductor substrate 21 is not limited to a silicon substrate, and may also be a semiconductor substrate 21 such as germanium, gallium nitride, or gallium arsenide.
  • Step S22 As shown in FIGS. 7-9, after the second surface is thinned, chemical mechanical polishing (CMP) is performed on the second surface to expose the conductive pillars 23, due to the TSV The conductive pillar 23 and the first insulating dielectric layer 22 of the structure are chemically mechanically polished simultaneously with the semiconductor substrate 21, so the conductive pillar 23 is flush with the polished second surface.
  • CMP chemical mechanical polishing
  • the second surface is thinned to reduce The thickness of the semiconductor substrate 21 is reduced, and the distance between the TSV structure and the second surface is reduced.
  • the second surface is subjected to a chemical mechanical polishing process to expose the conductive pillar 23 .
  • the method of bonding and fixing the first surface and the bonding carrier sheet 24 can be as shown in FIG. 7, using an adhesive layer 25 for bonding and fixing, or other bonding and fixing methods, which are in this embodiment of the present invention. There is no specific limitation.
  • Step S23 As shown in FIGS. 10 and 11, after the thinning treatment, a patterned second insulating dielectric layer 26 is formed on the second surface, and the second insulating dielectric layer 26 exposes the conductive pillars twenty three.
  • the method of forming the patterned second insulating dielectric layer 26 includes: first, as shown in FIG. 10, after the thinning treatment, a layer covering the second surface and the conductive pillar 23 is formed The second insulating dielectric layer 26; then, as shown in FIG. 11, the portion of the second insulating dielectric layer 26 covering the conductive pillar 23 is removed to form the patterned second insulating dielectric layer 26.
  • the patterned second insulating dielectric layer 26 has openings 27 corresponding to the TSV structure one-to-one to expose the corresponding conductive pillars 23 of the TSV structure.
  • the opening 27 is arranged directly opposite to the conductive pillar 23 of the corresponding TSV structure, and the aperture of the opening 27 can be set not less than the width of the conductive pillar 23 and not greater than the aperture of the blind hole.
  • the second insulating medium layer 26 is a photosensitive organic insulating layer formed on the second surface by a coating method; the second insulating medium layer 26 is patterned through an exposure process to remove The second insulating dielectric layer 26 covers a portion of the conductive pillar 23.
  • the second insulating dielectric layer 26 is an inorganic dielectric layer formed on the second surface by a deposition method; the second insulating dielectric layer 26 is patterned through an etching process to remove The second insulating dielectric layer 26 covers a portion of the conductive pillar 23. At this time, wet etching or dry etching may be used to remove the patterned second insulating dielectric layer 26. In this manner, one layer of the inorganic dielectric layer or a multilayer laminated inorganic dielectric layer is formed on the second surface. Since the inorganic dielectric layer has higher temperature resistance and insulation properties, this method is suitable for preparing semiconductor devices with higher requirements for temperature and insulation properties.
  • the method further includes:
  • Step S23 As shown in FIG. 12 and FIG. 13, the semiconductor substrate 21 is separated from the bonding carrier sheet 24, and the final product structure is as shown in FIG.
  • the method of mechanical polishing combined with chemical polishing can simultaneously remove the semiconductor substrate 21 and TSV.
  • the structure of the first insulating dielectric layer 22 and the conductive pillars 23 makes the exposed conductive pillars 23 flush with the polished second surface.
  • the height of each conductive pillar 23 is flush.
  • the patterned second insulating dielectric layer 26 is formed. Since the heights of the conductive pillars 23 relative to the second insulating dielectric layer 26 are also the same, the problem of inconsistent exposed heights of the conductive pillars 23 in the prior art is avoided.
  • the manufacturing method described in the embodiment of the present invention does not need to use wet etching to expose the TSV structure, and because the semiconductor substrate 21, the first insulating dielectric layer 22 of the TSV structure, and the first insulating dielectric layer 22 of the TSV structure are simultaneously polished and removed by the method of mechanical polishing combined with chemical polishing
  • the conductive pillar 23 can completely eliminate the cumulative tolerance of the etching depth uniformity of the blind hole, the bonding uniformity, the thinning uniformity of the second surface, and the cumulative tolerance of the TSV structure wet etching outcrop, so that each conductive pillar 23 flush with the same exposed height.
  • the conductive pillar can be made by one-time chemical mechanical polishing.
  • One end of 23 on the second surface is flush, so that all conductive pillars 23 have the same exposed height on the second surface.
  • the hole diameter of the blind hole is not less than 10 ⁇ m.
  • the blind hole has a larger hole diameter, no high-precision patterning process is required. That is, an opening 27 can be formed on the surface of the second insulating layer 26 to expose the corresponding conductive material. ⁇ 23 ⁇ Post 23.
  • the conductive pillar 23 located at the bottom of the opening 27 has a sufficient area for electrically connecting the redistribution layer (RDL), bumps or solder balls.
  • RDL redistribution layer
  • the present invention preferably provides that the aperture of the blind hole is not less than 10 ⁇ m.
  • the polishing force of the CMP process can be controlled to make the process have a greater polishing and removal effect, so as to remove part of the semiconductor substrate 21 and the conductive pillars 23 at the same time, so that the polished conductive pillars 23 are flush, and at the same time, the first polished
  • the two surfaces have greater smoothness relative to the surface of the second insulating dielectric layer 26.
  • the polished second surface and the second insulating dielectric layer 26 are the contact between the semiconductor substrate 21 and the insulating material.
  • the greater smoothness is beneficial to
  • the second insulating dielectric layer 26 has an adhesion effect, and when the subsequent process forms an interconnection circuit electrically connected to the conductive pillar 23 on the surface of the second insulating dielectric layer 26, it is the contact between the insulating material and the conductive material, and the smaller smoothness is beneficial to the interconnection circuit.
  • the adhesion effect is beneficial to
  • the manufacturing method according to the embodiment of the present invention can make the end faces of the conductive pillars 23 exposing the semiconductor substrate 21 lie on the same plane, which facilitates the electrical conduction of the subsequent process.
  • the subsequent process is performed in the second
  • an interconnection circuit is formed on the surface of the insulating dielectric layer 26, whether a rewiring layer (RDL), bumps or solder balls are used, good coplanarity can be achieved.
  • the circuit insulation layer of the subsequent interconnection circuit can be an inorganic dielectric layer with good temperature resistance and insulation, which can meet the special requirements of the prepared semiconductor device for temperature and insulation.
  • another embodiment of the present invention also provides a semiconductor device, which is manufactured using the manufacturing method described in the foregoing embodiment.
  • the structure of the semiconductor device may be as shown in FIG. 13, having a semiconductor substrate 21, the semiconductor substrate 21 has a first surface and a second surface, the first surface is formed by TSV process TSV structure, and then located on the first surface The area outside the TSV structure forms the functional structure of the semiconductor device. Then, based on the solution described in the above embodiment, the second surface is thinned, and then the second surface is chemically mechanically polished to expose the conductive pillar 23 On the second surface, the conductive pillars 23 are flush with the polished second surface, and the conductive pillars 23 are flush, so that the conductive pillars 23 are at the same distance from the surface of the patterned second insulating dielectric layer 26 formed on the second surface. This solves the problem of inconsistent exposure heights of the conductive pillars 23 in the prior art.
  • the functional structure of the semiconductor device is not shown in the drawings of the embodiment of the present invention.
  • the functional structure can be set to be a photosensitive pixel, a microelectromechanical structure, or a piezoelectric structure based on the type of semiconductor.
  • the embodiment of the present invention The functional structure is not specifically limited.

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Abstract

一种半导体器件及其制作方法，对半导体衬底（21）的第二表面进行减薄处理后，对所述第二表面进行化学机械研磨处理，通过机械研磨结合化学研磨的方法，可以同时研磨去除半导体衬底（21）、TSV结构的第一绝缘介质层（22）以及导电柱（23），使得露出的导电柱（23）和研磨后的第二表面齐平，各个导电柱（23）的高度齐平，当在经过化学机械研磨处理后的第二表面形成图形化的第二绝缘介质层（26），由于各个导电柱（23）相对于所述第二绝缘介质层（26）的高度也是一致的，避免了现有技术中导电柱露出高度不一致的问题。

Description

半导体器件及其制作方法
本申请要求于2019年10月12日提交中国专利局、申请号为201910967723.1、发明名称为“半导体器件及其制作方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明涉及半导体器件制作工艺技术领域，更具体的说，涉及一种半导体器件及其制作方法。
背景技术
随着半导体技术的发展，集成电路的特征尺寸不断缩小，器件互连密度不断提高，传统的二维封装已经不能满足业界的需求，因此基于硅通孔(Through，Silicon Via，简称TSV)垂直互连的层叠封装方式以其短距离互连和高密度集成的关键技术优势，成为封装技术发展的主流方向。
TSV技术是通过在不同器件结构之间通过刻蚀或是激光钻孔等方式制作垂直通孔，然后在垂直通孔内通过电镀等方式沉积导电物质形成导电柱，实现电互连的技术。如果采用先通孔(Via-First)方法，由于通孔的深度要小于所在衬底的厚度，现有技术一般是对器件背面进行减薄处理后，通过刻蚀工艺在器件背面露出通孔内的导电柱，该方式会导致器件背面露出导电柱存在露出高度不一致的问题。
发明内容
有鉴于此，本申请提供了一种半导体器件及其制作方法，解决了TSV结构中导电柱露出高度不一致的问题，本发明技术方案如下：
一种半导体器件的制作方法，包括：
提供一具有TSV结构的半导体衬底，所述半导体衬底具有相对的第一表面和第二表面，所述TSV结构包括：位于所述第一表面的盲孔，所述盲孔的侧壁以及底面具有第一绝缘介质层；填充所述盲孔的导电柱；
对所述第二表面进行减薄处理后，对所述第二表面进行化学机械研磨处理，露出所述导电柱；
经过所述化学机械研磨处理后，在所述第二表面形成图形化的第二绝缘介质层，所述第二绝缘介质层露出所述导电柱。
优选的，在上述制作方法中，将所述第一表面与键合载片键合固定后，对所述第二表面进行减薄处理。
优选的，在上述制作方法中，形成图形化的所述第二绝缘介质层后，还包括：
将所述半导体衬底与所述键合载片进行分离。
优选的，在上述制作方法中，形成图形化的所述第二绝缘介质层的方法包括：
经过所述减薄处理后，形成覆盖所述第二表面以及所述导电柱的所述第二绝缘介质层；
去除所述第二绝缘介质层覆盖所述导电柱的部分，形成图形化的所述第二绝缘介质层。
优选的，在上述制作方法中，所述第二绝缘介质层的为采用涂布方法形成在所述第二表面的感光有机绝缘层；
通过曝光工艺对所述第二绝缘介质层进行图形化处理，以去除所述第二绝 缘介质层覆盖所述导电柱的部分。
优选的，在上述制作方法中，所述第二绝缘介质层为采用沉积方法形成在所述第二表面的无机介质层；
通过刻蚀工艺对所述第二绝缘介质层进行图形化处理，以去除所述第二绝缘介质层覆盖所述导电柱的部分。
优选的，在上述制作方法中，通过沉积方法，在所述第二表面形成一层所述无机介质层或多层层叠的所述无机介质层。
优选的，在上述制作方法中，所述半导体衬底的制作方法包括：
在所述第一表面形成盲孔；
在所述盲孔的侧壁以及底部沉积所述第一绝缘介质层；
在表面覆盖有所述第一绝缘介质层的所述盲孔内形成所述导电柱。
优选的，在上述制作方法中，所述盲孔的孔径不小于10μm。
本发明还提供了一种半导体器件，所述半导体器件采用上述任一项所述的制作方法制备。
通过上述描述可知，本发明技术方案提供的半导体器件及其制作方法中，对半导体衬底的第二表面进行减薄处理后，对所述第二表面进行化学机械研磨处理，这样，通过机械研磨结合化学研磨的方法，可以同时研磨去除半导体衬底、TSV结构的第一绝缘介质层以及导电柱，使得露出的导电柱和研磨后的第二表面齐平，各个导电柱的高度齐平，当在经过化学机械研磨处理后的第二表面形成图形化的第二绝缘介质层，由于各个导电柱相对于所述第二绝缘介质层的高度也是一致的，避免了现有技术中导电柱露出高度不一致的问题。
附图说明
为了更清楚地说明本申请实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据提供的附图获得其他的附图。
图1-图5为一种基于湿法刻蚀工艺露出TSV中导电柱的工艺流程图；
图6-图13为本发明实施例提供的一种半导体器件制作方法的工艺流程图。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
参考图1-图5，图1-图5为一种基于湿法刻蚀工艺露出TSV中导电柱的工艺流程图，该工艺包括：
步骤S11：如图1所示，提供一具有TSV结构的硅衬底11。所述硅衬底11具有相对的第一表面和第二表面。所述TSV结构包括：位于所述第一表面的盲孔，所述盲孔的侧壁以及底面具有第一绝缘介质层12；填充所述盲孔的导电柱13。将所述第二表面进行减薄后，将其通过胶层15与键合载片14键合固定。
步骤S12：如图2所示，采用化学试剂对所述第二表面进行湿法刻蚀，露出所述TSV结构。
步骤S13：如图3和图4所示，首先，涂布绝缘的光刻胶层，所述光刻胶层覆盖所述TSV结构，然后，对所述光刻胶层进行欠曝光，去除部分厚度所述光 刻胶层，露出所述TSV结构。
步骤S14：如图5所示，通过干法刻蚀工艺去除所述TSV结构表面的第一绝缘介质层12，露出导电柱13。最后，将所述键合载片14与所述硅衬底11分离。
基于图1-图5所述工艺流程可知，其需要通过湿法刻蚀工艺，利用化学试剂对硅和氧化硅的不同选择比来使得所述TSV结构露出第二表面，并通过后续的光刻胶层欠曝光以及干法刻蚀工艺去除所述TSV结构表面的第一绝缘介质层12，以便于所述硅衬底11可以在其第二表面与其他器件电连接。该工艺流程会导致所述硅衬底11的第二表面露出的导电柱13存在露出高度不一致问题，使得采用硅衬底11制备的半导体器件与其他器件电连接时，容易出现电性开路或短路等异常。如果后续进行凸点(Bump)，受导电柱13露出高度不一致影响，凸点的共面性较差。
发明人研究发现，TSV结构中导电柱13露出高度不一致问题是TSV结构形成过程中通孔的刻蚀深度均匀性、硅衬底11和键合载片14之间胶层15的键合均匀性、硅衬底11第二表面的减薄均匀性以及TSV结构湿法刻蚀露头均匀性这多道工艺的公差共同累积形成的结果，是传统工艺无法避免和解决的问题。
为解决上述多道工艺公差形成的累积误差导致的导电柱露出高度不一致问题，本发明实施例所述技术方案中，对半导体衬底的第二表面进行减薄处理后，对所述第二表面进行化学机械研磨处理，这样，通过机械研磨结合化学研磨的方法，可以同时研磨去除半导体衬底、TSV结构的第一绝缘介质层以及导电柱，使得露出的导电柱和研磨后的第二表面齐平，各个导电柱的高度齐平，当在经过化学机械研磨处理后的第二表面形成图形化的第二绝缘介质层，由于各个导电柱相对于所述第二绝缘介质层的高度也是一致的，避免了现有技术中 导电柱露出高度不一致的问题。
为使本申请的上述目的、特征和优点能够更加明显易懂，下面结合附图和具体实施方式对本申请作进一步详细的说明。
参考图6-图13，图6-图13为本发明实施例提供的一种半导体器件制作方法的工艺流程图，所述制作方法包括：
步骤S21：如图6所示，提供一具有TSV结构的半导体衬底21。
所述半导体衬底21具有相对的第一表面和第二表面，所述TSV结构包括：位于所述第一表面的盲孔，所述盲孔的侧壁以及底面具有第一绝缘介质层22；填充所述盲孔22的导电柱23。
其中，所述半导体衬底21的制作方法包括：首先，在所述第一表面形成盲孔；然后，在所述盲孔的侧壁以及底部沉积所述第一绝缘介质层22；最后，在表面覆盖有所述第一绝缘介质层22的所述盲孔内形成所述导电柱23。
所述导电柱23可以为金属柱，如铜柱、铝柱或是银柱等。可以采用电镀工艺形成所述导电柱。所述半导体衬底21可以为硅衬底。所述第一绝缘介质层22可以为二氧化硅层。所述半导体衬底21不局限于为硅衬底，如还可以为锗、氮化镓、或砷化镓等半导体衬底21。
步骤S22：如图7-图9所示，对所述第二表面进行减薄处理后，对所述第二表面进行化学机械研磨(CMP)处理，露出所述导电柱23，由于所述TSV结构的导电柱23和第一绝缘介质层22是与所述半导体衬底21同时进行化学机械研磨，故所述导电柱23与研磨后的所述第二表面齐平。
该步骤中，首先，如图7所示，将所述第一表面与键合载片24键合固定 后，然后，如图8所示，对所述第二表面进行减薄处理，以减小所述半导体衬底21的厚度，缩小所述TSV结构与所述第二表面的间距，最后，如图9所示，对所述第二表面进行化学机械研磨处理，露出所述导电柱23。所述第一表面与所述键合载片24键合固定的方式可以如图7所示，采用胶层25进行键合固定，也可以采用其他键合固定的方式，本发明实施例对此不做具体限定。
步骤S23：如图10和图11所示，经过所述减薄处理后，在所述第二表面形成图形化的第二绝缘介质层26，所述第二绝缘介质层26露出所述导电柱23。
该步骤中，形成图形化的所述第二绝缘介质层26的方法包括：首先，如图10所示，经过所述减薄处理后，形成覆盖所述第二表面以及所述导电柱23的所述第二绝缘介质层26；然后，如图11所示，去除所述第二绝缘介质层26覆盖所述导电柱23的部分，形成图形化的所述第二绝缘介质层26。图形化的所述第二绝缘介质层26具有与所述TSV结构一一对应的开口27，以露出所对应的TSV结构的导电柱23。所述开口27与所述对应的TSV结构的导电柱23正对设置，可以设置所述开口27的孔径不小于导电柱23的宽度，且不大于所述盲孔的孔径。
一种方式中，所述第二绝缘介质层26为采用涂布方法形成在所述第二表面的感光有机绝缘层；通过曝光工艺对所述第二绝缘介质层26进行图形化处理，以去除所述第二绝缘介质层26覆盖所述导电柱23的部分。
另一种方式中，所述第二绝缘介质层26为采用沉积方法形成在所述第二表面的无机介质层；通过刻蚀工艺对所述第二绝缘介质层26进行图形化处理，以去除所述第二绝缘介质层26覆盖所述导电柱23的部分。此时，可以采用湿法刻蚀或是干法刻蚀去除图形化所述第二绝缘介质层26。该方式中，在所述 第二表面形成一层所述无机介质层或多层层叠的所述无机介质层。由于无机介质层具有较高的耐温以及绝缘性能，故该方式适用于制备温度和绝缘性能具有较高要求的半导体器件。
本发明实施例所述制作方法中，形成图形化的所述第二绝缘介质层26后，还包括：
步骤S23：如图12和图13所示，将所述半导体衬底21与所述键合载片24进行分离，最终形成的产品结构如图13所示。
本发明对半导体衬底21的第二表面进行减薄处理后，对所述第二表面进行化学机械研磨处理，这样，通过机械研磨结合化学研磨的方法，可以同时研磨去除半导体衬底21、TSV结构的第一绝缘介质层22以及导电柱23，使得露出的导电柱23和研磨后的第二表面齐平，各个导电柱23的高度齐平，当在经过化学机械研磨处理后的第二表面形成图形化的第二绝缘介质层26，由于各个导电柱23相对于所述第二绝缘介质层26的高度也是一致的，避免了现有技术中导电柱23露出高度不一致的问题。
这是由于本发明实施例所述制作方法，无需采用湿法刻蚀露出TSV结构，且由于通过机械研磨结合化学研磨的方法同时研磨去除半导体衬底21、TSV结构的第一绝缘介质层22以及导电柱23，可以彻底消除盲孔的刻蚀深度均匀性、键合均匀性、第二表面的减薄均匀性的累积公差以及TSV结构湿法刻蚀露头这些工艺的累积公差，使得各个导电柱23齐平，具有相同的露出高度。也就是说，无论盲孔的刻蚀深度是否一致，无论用于键合固定的胶层25厚度是否一致，第二表面较薄的厚度是否一致，均可以通过一次性的化学机械研磨使得导电柱23位于第二表面的一端齐平，使得所有导电柱23在第二表面具有 相同的露出高度。
本发明实施例所述制作方法中，所述盲孔的孔径不小于10μm。相对于所述盲孔的孔径小于10μm的TSV结构，由于所述盲孔的孔径较大，无需高精度的图形化处理工艺，即可以在第二绝缘层26表面形成开口27，露出对应的导电柱23。而且由于所述盲孔的孔径较大，位于开口27底部的导电柱23具有足够的面积用于电连接重布线层(RDL)、凸点(Bump)或是锡球。如果孔径10μm的TSV结构，需要较高精度的图形处理工艺对第二绝缘层26图形化，而且会导致第二绝缘层26表面开口27露出的导电柱23的面积较小，不便于后续互连电路与导电柱23的电连接，故本发明优选设置所述盲孔的孔径不小于10μm。
可以通过控制CMP处理的研磨力度，使得该处理过程具有较大的研磨去除效果，以同时去除部分半导体衬底21以及导电柱23，使得研磨后的导电柱23齐平，同时使得研磨后的第二表面相对于第二绝缘介质层26的表面具有较大的光滑度，研磨后的第二表面与第二绝缘介质层26是半导体衬底21与绝缘材料的接触，较大的光滑度有利于第二绝缘介质层26附着效果，而后续工艺在第二绝缘介质层26表面形成与导电柱23电连接的互联电路时，是绝缘材料与导电材料的接触，较小的光滑度有利于互联电路的附着效果。
通过上述描述可知，本发明实施例所述制作方法可以使得露出所述半导体衬底21的各个导电柱23的端面均位于同一平面，方便后续工艺的电性导通，后续工艺在所述第二绝缘介质层26表面形成互连电路时，无论是采用重布线层(RDL)、凸点(Bump)或是锡球，都可以实现良好的共面性。后续互连电路的线路绝缘层可以采用耐温和绝缘性较好的无机介质层，能够满足所制备的 半导体器件对温度和绝缘性的特殊要求。
基于上述实施例所述制作方法，本发明另一实施例还提供了一种半导体器件，所述半导体器件采用上述实施例所述制作方法制备。
所述半导体器件的结构可以如图13所示，具有半导体衬底21，半导体衬底21具有第一表面和第二表面，第一表面通过TSV工艺形成TSV结构，再在所述第一表面位于所述TSV结构之外的区域形成半导体器件的功能结构，然后基于上述实施例所述方案，对第二表面进行减薄处理后，再通过对第二表面进行化学机械研磨，使得导电柱23露出第二表面，导电柱23和研磨后的第二表面齐平，各个导电柱23齐平，这样，使得各个导电柱23与形成在第二表面的图形化的第二绝缘介质层26表面距离相同，解决了现有技术中导电柱23露出高度不一致的问题。
需要说明的是，本发明实施例附图中并未示出半导体器件的功能结构，可以基于半导体的类型设置所述功能结构为感光像素、微机电结构或是压电结构等，本发明实施例对所述功能结构不作具体限定。
本说明书中各个实施例采用递进、或并列、或递进和并列结合的方式描述，每个实施例重点说明的都是与其他实施例的不同之处，各个实施例之间相同相似部分互相参见即可。对于实施例公开的半导体器件而言，由于其与实施例公开的制作方法相对应，所以描述的比较简单，相关之处参见制作方法对应部分说明即可。
还需要说明的是，在本文中，诸如第一和第二等之类的关系术语仅仅用来 将一个实体或者操作与另一个实体或操作区分开来，而不一定要求或者暗示这些实体或操作之间存在任何这种实际的关系或者顺序。而且，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的物品或者设备不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种物品或者设备所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括上述要素的物品或者设备中还存在另外的相同要素。
对所公开的实施例的上述说明，使本领域专业技术人员能够实现或使用本申请。对这些实施例的多种修改对本领域的专业技术人员来说将是显而易见的，本文中所定义的一般原理可以在不脱离本申请的精神或范围的情况下，在其它实施例中实现。因此，本申请将不会被限制于本文所示的这些实施例，而是要符合与本文所公开的原理和新颖特点相一致的最宽的范围。

Claims (10)

  1. 一种半导体器件的制作方法，其特征在于，包括：
    提供一具有TSV结构的半导体衬底，所述半导体衬底具有相对的第一表面和第二表面，所述TSV结构包括：位于所述第一表面的盲孔，所述盲孔的侧壁以及底面具有第一绝缘介质层；填充所述盲孔的导电柱；
    对所述第二表面进行减薄处理后，对所述第二表面进行化学机械研磨处理，露出所述导电柱；
    经过所述化学机械研磨处理后，在所述第二表面形成图形化的第二绝缘介质层，所述第二绝缘介质层露出所述导电柱。
  2. 根据权利要求1所述的制作方法，其特征在于，将所述第一表面与键合载片键合固定后，对所述第二表面进行减薄处理。
  3. 根据权利要求2所述的制作方法，其特征在于，形成图形化的所述第二绝缘介质层后，还包括：
    将所述半导体衬底与所述键合载片进行分离。
  4. 根据权利要求1所述的制作方法，其特征在于，形成图形化的所述第二绝缘介质层的方法包括：
    经过所述减薄处理后，形成覆盖所述第二表面以及所述导电柱的所述第二绝缘介质层；
    去除所述第二绝缘介质层覆盖所述导电柱的部分，形成图形化的所述第二绝缘介质层。
  5. 根据权利要求4所述的制作方法，其特征在于，所述第二绝缘介质层 的为采用涂布方法形成在所述第二表面的感光有机绝缘层；
    通过曝光工艺对所述第二绝缘介质层进行图形化处理，以去除所述第二绝缘介质层覆盖所述导电柱的部分。
  6. 根据权利要求4所述的制作方法，其特征在于，所述第二绝缘介质层为采用沉积方法形成在所述第二表面的无机介质层；
    通过刻蚀工艺对所述第二绝缘介质层进行图形化处理，以去除所述第二绝缘介质层覆盖所述导电柱的部分。
  7. 根据权利要求6所述的制作方法，其特征在于，通过沉积方法，在所述第二表面形成一层所述无机介质层或多层层叠的所述无机介质层。
  8. 根据权利要求1所述的制作方法，其特征在于，所述半导体衬底的制作方法包括：
    在所述第一表面形成盲孔；
    在所述盲孔的侧壁以及底部沉积所述第一绝缘介质层；
    在表面覆盖有所述第一绝缘介质层的所述盲孔内形成所述导电柱。
  9. 根据权利要求1-8任一项所述的制作方法，其特征在于，所述盲孔的孔径不小于10μm。
  10. 一种半导体器件，其特征在于，所述半导体器件采用如权利要求1-9任一项所述的制作方法制备。
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CN110690164A (zh) * 2019-10-12 2020-01-14 上海先方半导体有限公司 半导体器件及其制作方法

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