WO2021063314A1 - 显示装置、栅极驱动电路、移位寄存电路及其驱动方法 - Google Patents

显示装置、栅极驱动电路、移位寄存电路及其驱动方法 Download PDF

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Publication number
WO2021063314A1
WO2021063314A1 PCT/CN2020/118411 CN2020118411W WO2021063314A1 WO 2021063314 A1 WO2021063314 A1 WO 2021063314A1 CN 2020118411 W CN2020118411 W CN 2020118411W WO 2021063314 A1 WO2021063314 A1 WO 2021063314A1
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Prior art keywords
potential
transistor
node
circuit
shift register
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PCT/CN2020/118411
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English (en)
French (fr)
Inventor
冯雪欢
李永谦
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京东方科技集团股份有限公司
合肥京东方卓印科技有限公司
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Priority to US17/424,482 priority Critical patent/US11763726B2/en
Publication of WO2021063314A1 publication Critical patent/WO2021063314A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/061—Details of flat display driving waveforms for resetting or blanking

Definitions

  • the present disclosure relates to the field of display technology, in particular to a display device, a gate driving circuit, a shift register circuit, and a driving method of the shift register circuit.
  • the present disclosure provides a shift register circuit, including: an input sub-circuit, connected to a first node of the shift register circuit, configured to receive a first control signal, and make the first control signal according to the first control signal The potential of a node jumps from an initial potential to a first potential, the first potential being greater than the initial potential; an output sub-circuit, connected to the first node of the shift register circuit, and configured to receive a first clock signal , And generate an output signal according to the first clock signal and the potential of the first node and make the potential of the first node jump from the first potential to a third potential, wherein the third potential is greater than The first potential; a corner-cutting sub-circuit, connected to the first node of the shift register circuit, is configured to receive a second control signal, according to the second control signal to make the potential of the first node from the The third potential is gradually reduced to the fourth potential, so that the potential of the output signal is gradually reduced, and the potential of the first node is jumped from the fourth potential to the initial
  • the input sub-circuit includes: a first transistor, a gate of the first transistor is connected to receive the first control signal, and a first electrode of the first transistor is connected to the first transistor.
  • the gate of the first transistor is connected, and the second electrode of the first transistor is connected to the first node.
  • the output sub-circuit includes: a second transistor, the gate of the second transistor is connected to the first node, and the first electrode of the second transistor is connected to receive the first clock Signal, the second pole of the second transistor is used as the output terminal of the shift register circuit to output the output signal; a first capacitor, one end of the first capacitor and the gate of the second transistor Connected, the other end of the first capacitor is connected to the second electrode of the second transistor.
  • the corner-cutting sub-circuit includes: a third transistor, a gate of the third transistor is connected to receive the second control signal, and a first electrode of the third transistor is connected to receive a first reference. Voltage, the second electrode of the third transistor is connected to the first node; a fourth transistor, the gate of the fourth transistor is connected to receive the third control signal, and the first electrode of the fourth transistor Is connected to the first node, the second electrode of the fourth transistor is connected to receive a second reference voltage; the fifth transistor, the first electrode and the gate of the fifth transistor are both connected to the first electrode of the third transistor One pole is connected; a sixth transistor, the gate of the sixth transistor is connected to the first node, and the first pole of the sixth transistor is connected to the second pole of the fifth transistor to form a second node , The second electrode of the sixth transistor is connected to receive the second reference voltage; the seventh transistor, the gate of the seventh transistor is connected to the second node, and the first electrode of the seventh transistor serves as The output terminal of the shift register circuit
  • the corner-cutting sub-circuit further includes: an eighth transistor, the gate of the eighth transistor is connected to the second node, and the first electrode of the eighth transistor is connected to the first node , The second electrode of the eighth transistor is connected to receive the second reference voltage.
  • the output sub-circuit further includes a ninth transistor, the gate of the ninth transistor is connected to the first node, and the first pole of the ninth transistor is connected to receive a second clock signal, The second pole of the ninth transistor serves as the control output terminal of the shift register circuit for outputting the control output signal of the shift register circuit;
  • the angle-cutting sub-circuit also includes a tenth transistor, the tenth The gate of the transistor is connected to the second node, the first electrode of the tenth transistor is connected to the second electrode of the ninth transistor, and the second electrode of the tenth transistor is connected to receive the second reference Voltage.
  • the reset sub-circuit includes: an eleventh transistor, the gate of the eleventh transistor is connected to receive a reset signal, and the first electrode of the eleventh transistor is connected to The first node is connected, and the second electrode of the eleventh transistor is connected to receive a second reference voltage.
  • the angle-cutting sub-circuit is configured to gradually reduce the potential of the output signal during a period when the first clock signal and the second control signal are both at a high potential.
  • the present disclosure also provides a method for driving a shift register circuit, wherein, for driving the shift register circuit as described above, the method includes: in a first time period, the input sub-circuit receives a first control signal , And make the potential of the first node jump from the initial potential to the first potential according to the first control signal, wherein the first potential is greater than the initial potential; in the second time period, the The output sub-circuit receives the first clock signal, generates an output signal according to the first clock signal and the potential of the first node, and causes the potential of the first node to jump from the first potential to the third Electric potential, wherein the third electric potential is greater than the first electric potential; in the third time period, the angle-cutting sub-circuit receives a second control signal, and according to the second control signal, causes the electric potential of the first node to change from The third potential is gradually reduced to the fourth potential, so that the potential of the output signal generated by the output sub-circuit according to the first clock signal and the potential of the first node is gradually reduced
  • the present disclosure also provides a gate driving circuit, which includes a multi-stage shift register circuit, and each stage of the shift register circuit adopts the above-mentioned shift register circuit.
  • the first control signal, the second control signal and the third control signal of the Nth stage shift register circuit are respectively the N-4th stage, the N+3 stage and the N+8th stage shift register.
  • the present disclosure also provides a display device, which includes the gate driving circuit as described above.
  • Fig. 1 is a structural block diagram of a shift register circuit of an embodiment of the present disclosure
  • Figure 2 is a schematic diagram of the structure of a commonly used 3T1C pixel circuit
  • 3 is a timing diagram of the working process of the shift register circuit of an embodiment of the present disclosure.
  • FIG. 4 is a simulation result diagram of part of the signal timing diagram of FIG. 3;
  • FIG. 5 is a schematic structural diagram of a shift register circuit of an example of the present disclosure.
  • Fig. 6 is a schematic structural diagram of a shift register circuit of another example of the present disclosure.
  • FIG. 7 is a flowchart of a driving method of a shift register circuit according to an embodiment of the present disclosure.
  • FIG. 8 is a structural block diagram of a gate driving circuit of an embodiment of the present disclosure.
  • Fig. 9 is a structural block diagram of a display device according to an embodiment of the present disclosure.
  • Fig. 1 is a structural block diagram of a shift register circuit of an embodiment of the present disclosure.
  • the shift register circuit 100 includes an input sub-circuit 10, an output sub-circuit 20, and a corner-cutting sub-circuit 30 all connected to the first node d1, wherein the input sub-circuit 10 is used to receive the first control signal CR1 , And according to the first control signal CR1 to make the potential of the first node d1 jump from the initial potential V0 to the first potential V1, the first potential V1 is greater than the initial potential V0; the angle-cutting sub-circuit 30 is used to receive the second control signal CR2, and The potential of the first node d1 is gradually reduced to the second potential V2 according to the second control signal CR2, and is used to receive the third control signal CR3, and according to the third control signal CR3, the potential of the first node d1 is changed from the second potential V2 to the second potential V2.
  • the output sub-circuit 20 is used to receive the first clock signal CLKE, and according to the first clock signal CLKE and the first node d1 The potential output of the output signal OUT with chamfered angle.
  • the potential of the output signal OUT gradually decreases. That is, when the second control signal CR2 is at a high potential, the angle-cutter sub-circuit 30 gradually reduces the potential of the first node d1 to the second potential V2 according to the second control signal CR2, and when the first clock signal CLKE is at a high potential
  • the output sub-circuit 20 outputs the chamfered output signal OUT according to the first clock signal CLKE and the potential of the first node d1
  • the width of the overlapping portion of the high potential of the first clock signal CLKE and the high potential of the second control signal CR2 Larger, the greater the width of the chamfer.
  • the first control signal CR1 can be received through the input sub-circuit 10, and the potential of the first node d1 can be jumped from the initial potential V0 to the first according to the first control signal CR1.
  • the potential V1; then the second control signal CR2 and the third control signal CR3 are received through the angle-cutter sub-circuit 30, and the potential of the first node d1 is gradually reduced from the first potential V1 to the second potential V2 according to the second control signal CR2, according to
  • the third control signal CR3 causes the potential of the first node d1 to jump from the second potential V2 to the initial potential V0.
  • the output sub-circuit 20 receives the first clock signal CLKE, and outputs a chamfered output signal OUT according to the first clock signal CLKE and the potential of the first node d1.
  • the output sub-circuit 20 outputs a chamfered signal according to the first clock signal CLKE and the potential of the first node d1 The output signal OUT, avoid the output signal OUT from directly jumping from high level to low level.
  • a commonly used pixel circuit includes three TFTs and a storage capacitor Cst.
  • the output signal OUT of the shift register circuit 100 With chamfering, it can prevent the output of the gate potential G1 of the driving thin film transistor T1 from directly jumping from a high level to a low level.
  • the potential of the first node first jumps from the initial potential to the first potential, and then gradually decreases from the first potential to the second potential, which can avoid
  • the phenomenon of the output signal jump caused by the excessive change of the potential of the first node causes the output sub-circuit to output a chamfered output signal to prevent the gate potential signal of the pixel circuit from directly jumping from a high level to a low level.
  • the output sub-circuit 20 is further used to generate the output signal OUT according to the first clock signal CLKE and the potential of the first node d1, and to make the potential of the first node d1 jump from the first potential V1 to the first potential V1.
  • the angle-cutter sub-circuit 30 is used to gradually reduce the third potential of the first node d1 to the fourth potential V4 according to the second control signal CR2, so that the output signal OUT is The potential gradually decreases, and the potential of the first node d1 jumps from the fourth potential V4 to the initial potential V0 according to the third control signal CR3, wherein the fourth potential is greater than the initial potential and smaller than the third potential.
  • the output sub-circuit 20 can also be used according to the first clock signal CLKE and the first The potential of the node d1 makes the potential of the first node d1 jump from the first potential V1 to the third potential V3, and then the angle-cutting sub-circuit 30 gradually reduces the potential of the first node d1 from the third potential V3 according to the second control signal CR2 To the fourth potential V4, and according to the third control signal CR3, the potential of the first node d1 is jumped from the fourth potential V4 to the initial potential V0.
  • the fourth potential V4 and the first potential V1 may be equal or not equal.
  • the potential of the output signal OUT gradually decreases. That is to say, during the period when the second control signal CR2 is at a high potential, the angle-cutting sub-circuit 30 gradually reduces the potential of the first node d1 from the third potential V3 to the fourth potential V4 according to the second control signal CR2, and the output The potential of the signal OUT also gradually decreases, that is, the waveform of the output signal OUT is chamfered, and the width of the overlapping portion of the high potential of the first clock signal CLKE and the high potential of the second control signal CR2 is greater, the output signal OUT is The time for the potential to gradually decrease is also longer.
  • the first control signal CR1, the second control signal CR2, the third control signal CR3, and the first clock signal CLKE in this embodiment all correspond to a high-level signal (high potential) and a low-level signal ( Low potential), the high-level signal and the low-level signal are relative terms, the high-level signal has a higher potential, such as 10V, 15V, and multiple high-level signals may be the same or different. Similarly, the low-level signal has a relatively low potential, such as -5V, -10V, and multiple low-level signals may be the same or different.
  • the working process of the shift register circuit 100 in one cycle can be divided into four time periods.
  • the four time periods are described below with reference to FIG. 3.
  • the input sub-circuit 10 receives the first control signal CR1, and the first control signal CR1 is a high-level signal, and changes the potential of the first node d1 from the initial potential V0 according to the first control signal CR1. Jump to the first potential V1.
  • the output sub-circuit 20 In the second time period t2, the output sub-circuit 20 generates an output signal OUT according to the first clock signal CLKE and the potential of the first node d1 and makes the potential of the first node d1 jump from the first potential V1 to the third potential V3.
  • the first clock signal CLKE is a high-level signal.
  • the angle-cutting sub-circuit 30 gradually reduces the potential of the first node d1 from the third potential V3 to the fourth potential V4 according to the second control signal CR2, and the potential of the first node d1 changes from the third potential V3 to the third potential V3.
  • the potential of the output signal OUT generated by the output sub-circuit 20 according to the first clock signal CLKE and the potential of the first node d1 gradually decreases, so that the signal waveform of the output signal OUT is chamfered.
  • the second control signal CR2 is a high-level signal
  • the first clock signal CLKE is a high-level signal.
  • the corner-cutting sub-circuit 30 jumps the potential of the first node d1 from the fourth potential V4 to the initial potential V0 according to the third control signal CR3.
  • the third control signal CR3 is a high-level signal.
  • the output sub-circuit 20 responds to the first clock signal CLKE and the first The potential of the node d1 outputs the output signal OUT with a chamfered angle, so as to avoid the phenomenon of the output signal OUT jumping caused by the excessive change of the potential of the first node.
  • the input sub-circuit 10 may include a first transistor M1, the gate of the first transistor M1 is connected to receive the first control signal CR1, and the first electrode of the first transistor M1 It is connected to the gate of the first transistor M1, and the second electrode of the first transistor M1 is connected to the first node d1.
  • the output sub-circuit 20 may include: a second transistor M2 and a first capacitor C1.
  • the gate of the second transistor M2 is connected to the first node d1
  • the first electrode of the second transistor M2 is connected to receive the first clock signal CLKE
  • the second electrode of the second transistor M2 is used as the output terminal of the shift register circuit 100 ,
  • one end of the first capacitor C1 is connected to the gate of the second transistor M2, and the other end of the first capacitor C1 is connected to the second electrode of the second transistor M2.
  • the corner-cutting sub-circuit 30 may include: a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, and a seventh transistor M7.
  • the gate of the third transistor M3 is connected to receive the second control signal CR2, the first electrode of the third transistor M3 is connected to receive the first reference voltage VDD, and the second electrode of the third transistor M3 is connected to the first node d1;
  • the gate of the fourth transistor M4 is used to receive the third control signal CR3, the first pole of the fourth transistor M4 is connected to the first node d1, and the second pole of the fourth transistor M4 is connected to receive the second reference voltage VGL;
  • the first electrode and the gate of the transistor are both connected to the first electrode of the third transistor M3; the gate of the sixth transistor M6 is connected to the first node d1, and the first electrode of the sixth transistor M6 is connected to the second electrode of the fifth transistor M5.
  • the second electrode of the sixth transistor M6 is connected to receive the second reference voltage VGL; the gate of the seventh transistor M7 is connected to the second node d2, and the first electrode of the seventh transistor M7 is connected to the second node d2.
  • the second pole of the second transistor M2 is connected, and the second pole of the seventh transistor M7 is connected to receive the second reference voltage VGL.
  • the corner-cutting sub-circuit 30 may further include an eighth transistor M8.
  • the gate of the eighth transistor M8 is connected to the second node d2, and the first electrode of the eighth transistor M8 is connected to the first node d1.
  • the second pole of the eight transistor M8 is connected to receive the second reference voltage VGL.
  • the first reference voltage VDD signal in this example is a DC high-level signal
  • the second reference voltage VGL signal is a DC low-level signal.
  • the first transistor M1 to the eighth transistor M8 may all be thin film transistors, and the first electrode may be a source or a drain, and the second electrode may be a drain or a gate.
  • the first control signal CR1 is a high-level signal
  • the first transistor M1 receives the first control signal CR1 to make the potential of the first node d1 jump from the initial potential V0 according to the first control signal CR1 Change to the first potential V1.
  • the first clock signal CLKE is a high level signal
  • the second transistor M2 receives the first clock signal CLKE to generate a high level according to the first clock signal CLKE and the potential of the first node d1 And make the potential of the first node d1 jump from the first potential V1 to the third potential V3.
  • the second control signal CR2 is a high-level signal
  • the first clock signal CLKE is a high-level signal
  • the third transistor M3 changes the potential of the first node d1 from the first node d1 according to the second control signal CR2.
  • the three potential V3 is gradually reduced to the fourth potential V4.
  • the second transistor M2 is based on the first clock signal CLKE and the first node d1.
  • the potential of the output signal OUT of the potential output gradually decreases.
  • the third control signal CR3 is a high-level signal
  • the fourth transistor M4 jumps the potential of the first node d1 from the fourth potential V4 to the initial potential V0 according to the third control signal CR3.
  • the output sub-circuit 20 may further include a ninth transistor M9, the gate of the ninth transistor M9 is connected to the first node d1, and the first pole of the ninth transistor M9 is connected as Receiving the second clock signal CLKD, the second pole of the ninth transistor M9 serves as the control output terminal of the shift register circuit 100 for outputting the control output signal CR of the shift register circuit 100;
  • the angle-cutting sub-circuit 30 may also include a tenth transistor M10, the gate of the tenth transistor M10 is connected to the second node d2, the first electrode of the tenth transistor M10 is connected to the second electrode of the ninth transistor M9, and the second electrode of the tenth transistor M10 is connected to receive the second reference voltage VGL.
  • the ninth transistor M9 and the tenth transistor M10 in this example may be thin film transistors, and the first electrode may be a source or a drain, and the second electrode may be a drain or a gate.
  • the first control signal CR1 is a high-level signal
  • the first transistor M1 receives the first control signal CR1 to make the potential of the first node d1 jump from the initial potential V0 according to the first control signal CR1 Change to the first potential V1.
  • the first clock signal CLKE and the second clock signal CLKD are both high-level signals
  • the second transistor M2 receives the first clock signal CLKE to respond according to the first clock signal CLKE and the first node
  • the potential of d1 generates an output signal and makes the potential of the first node d1 jump from the first potential V1 to the third potential V3
  • the ninth transistor receives the second clock signal CLKD to respond to the second clock signal CLKD and the first node
  • the potential of d1 generates a control output signal CR, and the control output signal CR is a high-level signal.
  • the second control signal CR2 is a high-level signal
  • the first clock signal CLKE and the second clock signal CLKD are both high-level signals
  • the third transistor M3 makes the second control signal CR2 a high-level signal.
  • the potential of a node d1 is gradually reduced from the third potential V3 to the fourth potential V4.
  • the second transistor M2 responds to the first clock signal
  • the potential of the output signal OUT output by CLKE and the potential of the first node d1 gradually decreases; the potential of the control output signal CR output by the ninth transistor M9 according to the second clock signal CLKD and the potential of the first node d1 also gradually decreases, so that The waveform of the control output signal CR is chamfered.
  • the third control signal CR3 is a high-level signal
  • the fourth transistor M4 jumps the potential of the first node d1 from the fourth potential V4 to the initial potential V0 according to the third control signal CR3;
  • the nine transistor M9 outputs the control output signal CR according to the second clock signal CLKD (low level) and the fourth potential V4 of the first node d1, and the control output signal CR is a low level signal.
  • first clock signal CLKE, the second clock signal CLKD, the first reference voltage VDD, and the second reference voltage VGL in the examples of the present disclosure may all be external control signals, and the first control signal CR1, the second control signal The signal CR2 and the third control signal CR3 can be determined according to the control output signal CR.
  • the shift register circuit 100 in this example can be connected in multiple cascades to obtain a gate driving circuit, that is, the gate driving circuit includes multiple stages of the shift register circuit 100 in this example, where the Nth
  • the first control signal CR1, the second control signal CR2, and the third control signal CR3 of the stage shift register circuit are the control output signals of the N-4th stage, the N+3 stage and the N+8th stage shift register circuit, respectively CR, where N is an integer greater than 4.
  • the first control signal CR1 may be the control output signal CR ⁇ N-4>
  • the second control signal CR2 may be the control output signal CR ⁇ N+3>
  • the third control signal CR3 may be the control output signal CR ⁇ N+8>
  • the control output signal CR of the shift register circuit 100 is CR ⁇ N>.
  • the first control signal, the second control signal, the third control signal and the first clock signal make the output signal waveform of the shift register circuit have obvious corners, so as to avoid the defects caused by the direct jump of the output signal. influences.
  • the shift register circuit 100 may further include a reset sub-circuit 40.
  • the reset sub-circuit 40 includes an eleventh transistor M11. The gate of the eleventh transistor M11 is connected as Receiving the reset signal TRST, the first pole of the eleventh transistor M11 is connected to the first node d1, and the second pole of the eleventh transistor M11 is connected to receive the second reference voltage VGL.
  • the eleventh transistor M11 in this embodiment may be a thin film transistor, the first electrode of which may be a source or a drain, and the second electrode may be a drain or a gate.
  • the first node d1 can be reset according to the reset signal TRST through the eleventh transistor M11.
  • the reset signal TRST may be an external control signal.
  • the angle-cutting sub-circuit controls the potential of the first node d1 according to the second control signal, so that the output sub-circuit outputs the signal according to the first clock signal and the potential of the first node.
  • the output signal has a chamfered angle, thereby avoiding the phenomenon of the output signal jumping caused by the excessive change of the potential of the first node, and preventing the gate potential signal of the pixel circuit from directly jumping from a high level to a low level.
  • FIG. 7 is a flowchart of the method for driving a shift register circuit in an embodiment of the present disclosure.
  • the driving method of the shift register circuit is used to drive the shift register circuit 100 of the above-mentioned embodiment of the present disclosure. As shown in FIG. 7, the driving method of the shift register circuit includes the following steps:
  • the input sub-circuit receives a first control signal, and according to the first control signal, causes the potential of the first node to jump from an initial potential to the first potential, wherein the first potential is greater than the first potential.
  • the initial potential The initial potential.
  • the output sub-circuit receives the first clock signal, generates an output signal according to the first clock signal and the potential of the first node, and causes the potential of the first node to jump from the first potential to The third potential, wherein the third potential is greater than the first potential.
  • the angle-cutting sub-circuit receives a second control signal, and according to the second control signal, causes the potential of the first node to gradually decrease from the third potential to a fourth potential, so that the output sub-circuit is The potential of the output signal generated by the first clock signal and the potential of the first node gradually decreases.
  • the angle-cutter sub-circuit receives a third control signal, and according to the third control signal, causes the potential of the first node to jump from a fourth potential to an initial potential, where the fourth potential is less than the third potential and greater than the initial potential. Potential.
  • the input sub-circuit receives the first control signal, and according to the first control signal, the potential of the first node is jumped from the initial potential to the first potential, and then the output sub-circuit receives the first control signal.
  • Clock signal and according to the first clock signal, the potential of the first node is jumped from the first potential to the third potential, the second control signal is received through the angle-cutting sub-circuit, and the potential of the first node is changed from the first potential according to the second control signal
  • the three potentials are gradually reduced to the fourth potential.
  • the output sub-circuit outputs a chamfered output signal according to the first clock signal and the potential of the first node, and finally passes through the cut
  • the slot circuit receives the third control signal, and according to the third control signal, makes the potential of the first node jump from the fourth potential to the initial potential.
  • the angle-cutting sub-circuit controls the potential of the first node according to the second control signal, so that the output sub-circuit outputs a chamfered output according to the first clock signal and the potential of the first node Signal, thereby avoiding the phenomenon of the output signal jumping caused by the excessive change of the potential of the first node, and preventing the gate potential signal of the pixel circuit from directly jumping from the high level to the low level.
  • FIG. 8 is a structural block diagram of the gate drive circuit of the embodiment of the present disclosure.
  • the gate driving circuit 1000 includes multiple stages of shift register circuits, and each stage of shift register circuit adopts the shift register circuit 100 of the above-mentioned embodiment of the present disclosure.
  • the first control signal CR1, the second control signal CR2, and the third control signal CR3 of the Nth stage shift register circuit 100 are the N-4th stage, the N+3 stage, and the N+8th stage shift register respectively.
  • the first control signal CR1 may be the control output signal CR ⁇ N-4>
  • the second control signal CR2 may be the control output signal CR ⁇ N+3>
  • the third control signal CR3 may be the control output signal CR ⁇ N+8>
  • the control output signal CR of the shift register circuit 100 is CR ⁇ N>.
  • the gate driving circuit 1000 when the gate driving circuit 1000 is applied to the field of display technology, the gate driving circuit 1000 may be used to provide a gate driving signal to the pixel circuit shown in FIG. 2.
  • the gate drive circuit of the embodiment of the present disclosure through the shift register circuit of the embodiment of the present disclosure, enables the output sub-circuit to output a chamfered output signal according to the first clock signal and the potential of the first node, which can avoid the problem of the first node.
  • the phenomenon that the output signal jumps caused by the excessive change of the electric potential prevents the gate electric potential signal of the pixel circuit from directly jumping from the high level to the low level.
  • FIG. 9 is a structural block diagram of the display device of the embodiment of the present disclosure.
  • the display device 10000 includes the gate driving circuit 1000 of the above-mentioned embodiment of the present disclosure.
  • the display device 10000 may be any product or component with a display function, such as a mobile phone, a tablet computer, a notebook computer, and a liquid crystal screen.
  • the output sub-circuit can output a chamfered output signal according to the first clock signal and the potential of the first node, which can avoid the potential change of the first node
  • first and second are used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Therefore, the features defined with “first” and “second” may explicitly or implicitly include at least one of the features. In the description of the present disclosure, “plurality” means at least two, such as two, three, etc., unless specifically defined otherwise.
  • the terms “installed”, “connected”, “connected”, “fixed” and other terms should be understood in a broad sense, for example, it may be a fixed connection or a detachable connection. , Or integrated; it can be mechanically connected or electrically connected; it can be directly connected or indirectly connected through an intermediary, it can be the internal connection of two components or the interaction relationship between two components, unless otherwise specified The limit.
  • the meaning of the above-mentioned terms in the present disclosure can be understood according to the situation.

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Abstract

一种显示装置、栅极驱动电路、移位寄存电路及其驱动方法，其中，移位寄存电路包括输入子电路，连接至所述移位寄存电路的第一节点，被配置为接收第一控制信号，并根据所述第一控制信号使所述第一节点的电位由初始电位跳变至第一电位，所述第一电位大于所述初始电位；输出子电路，连接至所述移位寄存电路的第一节点，被配置为接收第一时钟信号，并根据所述第一时钟信号和所述第一节点的电位产生输出信号并使所述第一节点的电位由所述第一电位跳变至第三电位，其中，所述第三电位大于所述第一电位；削角子电路，连接至所述移位寄存电路的第一节点，被配置为接收第二控制信号，根据第二控制信号使所述第一节点的电位从所述第三电位逐渐降低至第四电位，使得所述输出信号的电位逐渐降低，以及根据第三控制信号使所述第一节点的电位由所述第四电位跳变至所述初始电位，其中，所述第四电位大于所述初始电位，且小于所述第三电位。

Description

显示装置、栅极驱动电路、移位寄存电路及其驱动方法
相关申请交叉引用
本申请要求于2019年9月30日提交的、申请号为201910940614.0的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本公开涉及显示技术领域，特别涉及一种显示装置、一种栅极驱动电路、一种移位寄存电路、一种移位寄存电路的驱动方法。
背景技术
在显示技术领域，特别是在LCD(Liquid Crystal Display，液晶显示器)和OLED(Organic Light Emitting Diode，有机发光二极管)的显示中，GOA(Gate Driver On Array，阵列基板行驱动)电路是减少panel(显示面板)显示不良和降低成本的有效手段。
发明内容
本公开提供一种移位寄存电路，包括：输入子电路，连接至所述移位寄存电路的第一节点，被配置为接收第一控制信号，并根据所述第一控制信号使所述第一节点的电位由初始电位跳变至第一电位，所述第一电位大于所述初始电位；输出子电路，连接至所述移位寄存电路的第一节点，被配置为接收第一时钟信号，并根据所述第一时钟信号和所述第一节点的电位产生输出信号并使所述第一节点的电位由所述第一电位跳变至第三电位，其中，所述第三电位大于所述第一电位；削角子电路，连接至所述移位寄存电路的第一节点，被配置为接收第二控制信号，根据所述第二控制信号使所述第一节点的电位从所述第三电位逐渐降低至第四电位，使得所述输出信号的电位逐渐降低，以及根据第三控制信号使所述第一节点的电位由所述第四电位跳变至所述初始电位，其中，所述第四电位大于所述初始电位，且小于所述第三电位。
在一些实施例中，所述输入子电路包括：第一晶体管，所述第一晶体管的栅极连接为接收所述第一控制信号，所述第一晶体管的第一极与所述第一晶体管的栅极连接，所述第一晶体管的第二极与所述第一节点连接。
在一些实施例中，所述输出子电路包括：第二晶体管，所述第二晶体管的栅极与所述第一节点连接，所述第二晶体管的第一极连接为接收所述第一时钟信号，所述第二晶体管的第二极作为所述移位寄存电路的输出端，用以输出所述输出信号；第一电容，所述第一电容的一端与所述第二晶体管的栅极连接，所述第一电容的另一端与所述第二晶体管的第二极连接。
在一些实施例中，所述削角子电路包括：第三晶体管，所述第三晶体管的栅极连接为接收所述第二控制信号，所述第三晶体管的第一极连接为接收第一参考电压，所述第三晶体管的第二极与所述第一节点连接；第四晶体管，所述第四晶体管的栅极连接为接收所述第三控制信号，所述第四晶体管的第一极与所述第一节点连接，所述第四晶体管的第二极连接为接收第二参考电压；第五晶体管，所述第五晶体管的第一极和栅极均与所述第三晶体管的第一极连接；第六晶体管，所述第六晶体管的栅极与所述第一节点连接，所述第六晶体管的第一极与所述第五晶体管的第二极连接，并形成第二节点，所述第六晶体管的第二极连接为接收所述第二参考电压；第七晶体管，所述第七晶体管的栅极与所述第二节点连接，所述第七晶体管的第一极作为所述移位寄存电路的输出端，所述第七晶体管的第二极连接为接收所述第二参考电压。
在一些实施例中，所述削角子电路还包括：第八晶体管，所述第八晶体管的栅极与所述第二节点连接，所述第八晶体管的第一极与所述第一节点连接，所述第八晶体管的第二极连接为接收所述第二参考电压。
在一些实施例中，所述输出子电路还包括第九晶体管，所述第九晶体管的栅极与所述第一节点连接，所述第九晶体管的第一极连接为接收第二时钟信号，所述第九晶体管的第二极作为所述移位寄存电路的控制输出端，用以输出所述移位寄存电路的控制输出信号；所述削角子电路还包括第十晶体管，所述第十晶体管的栅极与所述第二节点连接，所述第十晶体管的第一极与所述第九晶体管的第二极连接，所述第十晶体管的第二极连接为接收所述第二参考电压。
在一些实施例中，还包括复位子电路，所述复位子电路包括：第十一晶体管，所述第十一晶体管的栅极连接为接收复位信号，所述第十一晶体管的第一极与所述第一节点连接，所述第十一晶体管的第二极连接为接收第二参考电压。
在一些实施例中，所述削角子电路被配置为在所述第一时钟信号与所述第二控制信号均为高电位期间，使得所述输出信号的电位逐渐降低。
本公开还提供了一种移位寄存电路的驱动方法，其中，用于驱动如上所述的移位寄存电路，所述方法包括：在第一时间段，所述输入子电路接收第一控制信号，并根据所述第一控制信号使所述第一节点的电位由初始电位跳变至所述第一电位，其中，所述第一电位大于所述初始电位；在第二时间段，所述输出子电路接收第一时钟信号，并根据所述第一时钟信号和所述第一节点的电位产生输出信号并使所述第一节点的电位由所述第一电位跳变至所述第三电位，其中，所述第三电位大于所述第一电位；在第三时间段，所述削角子电路接收第二控制信号，并根据所述第二控制信号使得所述第一节点的电位从所述第三电位逐渐降低至第四电位，使得所述输出子电路根据所述第一时钟信号和所述第一节点的电位产生的输出信号的电位逐渐降低；以及在第四时间段，所述削角子电路接收第三控制信号，并根据所述第三控制信号使得所述第一节点的电位由所述第四电位跳变至所述初始电位，其中，所述第四电位小于所述第三电位，且大于所述初始电位。
本公开还提供了一种栅极驱动电路，其中，包括多级移位寄存电路，每一级移位寄存电路均采用如上所述的移位寄存电路。
在一些实施例中，第N级移位寄存电路的第一控制信号、第二控制信号和第三控制信号分别为第N-4级、第N+3级和第N+8级移位寄存电路的控制输出信号，其中，N为大于4的整数。
本公开还提供了一种显示装置，其中，包括如上所述的栅极驱动电路。
附图说明
图1是本公开实施例的移位寄存电路的结构框图；
图2是常用的3T1C像素电路的结构示意图；
图3是本公开一个实施例的移位寄存电路的工作过程的时序图；
图4是图3的部分信号时序图的仿真结果图；
图5是本公开一个示例的移位寄存电路的结构示意图；
图6是本公开另一个示例的移位寄存电路的结构示意图；
图7是本公开实施例的移位寄存电路的驱动方法的流程图；
图8是本公开实施例的栅极驱动电路的结构框图；
图9是本公开实施例的显示装置的结构框图。
具体实施方式
下面详细描述本公开的实施例，所述实施例的示例在附图中示出，其中自始至终相同或类似的附图标记表示相同或类似的元件或具有相同或类似功能的元件。下面通过参考附图描述的实施例是示例性的，旨在用于解释本公开，而不能理解为对本公开的限制。
图1是本公开实施例的移位寄存电路的结构框图。
如图1所示，该移位寄存电路100包括均与第一节点d1连接的输入子电路10、输出子电路20和削角子电路30，其中，输入子电路10用以接收第一控制信号CR1，并根据第一控制信号CR1使第一节点d1的电位由初始电位V0跳变至第一电位V1，第一电位V1大于初始电位V0；削角子电路30用以接收第二控制信号CR2，并根据第二控制信号CR2使第一节点d1的电位逐渐降低至第二电位V2，以及用以接收第三控制信号CR3，并根据第三控制信号CR3使第一节点d1的电位由第二电位V2跳变至初始电位V0，其中，第二电位V2小于第一电位V1，且大于初始电位V0；输出子电路20用以接收第一时钟信号CLKE，并根据第一时钟信号CLKE和第一节点d1的电位输出带削角的输出信号OUT。
该实施例中，在第一时钟信号CLKE的高电位与第二控制信号CR2的高电位重叠期间，输出信号OUT的电位逐渐降低。也就是说，在第二控制信号CR2为高电位，削角子电路30根据第二控制信号CR2使第一节点d1的电位逐渐降低至第二电位V2时，且在第一时钟信号CLKE为高电位，输出子电路20根据第一时钟信号CLKE和第一节点d1的电位输出带削角的输出信号OUT时，第一时钟信号CLKE的高电位与第二控制信号CR2的高电位重叠部分的宽度越大，该削角宽度越大。
例如，在移位寄存电路100的实际应用中，首先可通过输入子电路10接收第一控制信号CR1，并根据第一控制信号CR1使第一节点d1的电位由初始电位V0跳变至第一电位V1；然后通过削角子电路30接收第二控制信号CR2和第三控制信号CR3，并根据第二控制信号CR2使第一节点d1的电位由第一电位V1逐渐降低至第二电位V2，根据第三控制信号CR3使第一节点d1的电位由第二电位V2跳变至初始电位V0，在第一节点d1的电位由第一电位V1逐渐降低至第二电位V2的过程中，输出子电路20接收第一时钟信号CLKE，并根据第一时钟信号CLKE和第一节点d1的电位输出带削角的输出信号OUT。
也就是说，在该实施例中，第一节点d1的电位并不是直接由高压跳变至低压，而是首先由初始电位V0跳变至第一电位V1，然后由第一电位V1逐渐降低至第二电位V2，并在第一节点d1的电位由第一电位V1逐渐降低至第二电位V2的过程中，输出子电路20根据第一时钟信号CLKE和第一节点d1的电位输出带削角的输出信号OUT，避免输出信号OUT直接从高电平跳变至低电平。
如图2所示，常用的像素电路包括三个TFT和存储电容Cst，在该移位寄存电路100运用于如图2所示的像素电路中时，因该移位寄存电路100的输出信号OUT带有削角，能够避免驱动薄膜晶体管T1的栅极电位G1的输出从高电平直接跳变至低电平。
该实施例的移位寄存电路，根据第一控制信号和第二控制信号使第一节点的电位首先由初始电位跳变至第一电位，然后由第一电位逐渐降低至第二电位，能够避免第一节点的电位变化过大引起的输出信号跳变的现象，使输出子电路输出带削角的输出信号，避免像素电路的栅极电位信号从高电平直接跳变至低电平。
在本公开的一个实施例中，输出子电路20还用以根据第一时钟信号CLKE和第一节点d1的电位产生输出信号OUT并使第一节点d1的电位由第一电位V1跳变至第三电位V3，第三电位V3大于第一电位V1；其中，削角子电路30用以根据第二控制信号CR2使第一节点d1的第三电位逐渐降低至第四电位V4，使得输出信号OUT的电位逐渐降低，以及根据第三控制信号CR3使第一节点d1的电位由第四电位V4跳变至初始电位V0，其中，第四电位大于初始电位，且小于第三电位。
例如，可在输入子电路10根据第一控制信号CR1使第一节点d1的电位由初始电位V0跳变至第一电位V1之后，还可通过输出子电路20根据第一时钟信号CLKE和第一节点d1的电位使第一节点d1的电位由第一电位V1跳变至第三电位V3，再通过削角子电路30根据第二控制信号CR2使第一节点d1的电位由第三电位V3逐渐降低至第四电位V4，以及根据第三控制信号CR3使第一节点d1的电位由第四电位V4跳变至初始电位V0。其中，第四电位V4与第一电位V1可以相等，也可以不相等。
在该实施例中，在第一时钟信号CLKE的高电位与第二控制信号CR2的高电位重叠期间，输出信号OUT的电位逐渐降低。也就是说，在第二控制信号CR2为高电位，削角子电路30根据第二控制信号CR2使所述第一节点d1的电位从第三电位V3逐渐降低至第四电位V4期间，所述输出信号OUT的电位也逐渐降低，即所述输出信号OUT的波形带有削角，并且第一时钟信号CLKE的高电位与第二控制信号CR2的高电位重 叠部分的宽度越大，输出信号OUT的电位逐渐降低的时间也越长。
需要说明的是，该实施例中的第一控制信号CR1、第二控制信号CR2、第三控制信号CR3和第一时钟信号CLKE均对应有高电平信号(高电位)和低电平信号(低电位)，高电平信号和低电平信号是相对而言的，高电平信号具有较高的电位，例如10V、15V，且多个高电平信号可以相同也可以不同。类似地，低电平信号具有较低的电位，例如-5V、-10V，且多个低电平信号可以相同也可以不同。
例如，可将移位寄存电路100在一个周期内的工作过程分为四个时间段，下面参照图3描述该四个时间段：
在第一时间段t1内，输入子电路10接收第一控制信号CR1，且该第一控制信号CR1为高电平信号，并根据第一控制信号CR1使第一节点d1的电位由初始电位V0跳变至第一电位V1。
在第二时间段t2内，输出子电路20根据第一时钟信号CLKE和第一节点d1的电位产生输出信号OUT并使第一节点d1的电位由第一电位V1跳变至第三电位V3。其中，第一时钟信号CLKE为高电平信号。
在第三时间段t3内，削角子电路30根据第二控制信号CR2使第一节点d1的电位由第三电位V3逐渐降低至第四电位V4，在第一节点d1的电位由第三电位V3逐渐降低至第四电位V4的过程中，输出子电路20根据第一时钟信号CLKE和第一节点d1的电位产生的输出信号OUT的电位逐渐降低，使得输出信号OUT的信号波形带有削角。其中，第二控制信号CR2为高电平信号，第一时钟信号CLKE为高电平信号。
在第四时间段t4内，削角子电路30根据第三控制信号CR3使第一节点d1的电位由第四电位V4跳变至初始电位V0。其中，第三控制信号CR3为高电平信号。
该实施例的移位寄存电路，在削角子电路30使第一节点d1的电位由第三电位V3逐渐降低至第四电位V4的过程中，输出子电路20根据第一时钟信号CLKE和第一节点d1的电位输出带削角的输出信号OUT，以避免第一节点的电位变化过大引起的输出信号OUT跳变的现象。
在本公开的一个实施例中，如图5所示，输入子电路10可包括第一晶体管M1，第一晶体管M1的栅极连接为接收第一控制信号CR1，第一晶体管M1的第一极与第一晶体管M1的栅极连接，第一晶体管M1的第二极与第一节点d1连接。
在一个示例中，参照图5，输出子电路20可包括：第二晶体管M2和第一电容C1。 其中，第二晶体管M2的栅极与第一节点d1连接，第二晶体管M2的第一极连接为接收第一时钟信号CLKE，第二晶体管M2的第二极作为移位寄存电路100的输出端，用以输出带削角的输出信号OUT；第一电容C1的一端与第二晶体管M2的栅极连接，第一电容C1的另一端与第二晶体管M2的第二极连接。
进一步地，参照图5，削角子电路30可包括：第三晶体管M3、第四晶体管M4、第五晶体管M5、第六晶体管M6和第七晶体管M7。
其中，第三晶体管M3的栅极连接为接收第二控制信号CR2，第三晶体管M3的第一极连接为接收第一参考电压VDD，第三晶体管M3的第二极与第一节点d1连接；第四晶体管M4的栅极用以接收第三控制信号CR3，第四晶体管M4的第一极与第一节点d1连接，第四晶体管M4的第二极连接为接收第二参考电压VGL；第五晶体管的第一极和栅极均与第三晶体管M3的第一极连接；第六晶体管M6的栅极与第一节点d1连接，第六晶体管M6的第一极与第五晶体管M5的第二极连接，并形成第二节点d2，第六晶体管M6的第二极连接为接收第二参考电压VGL；第七晶体管M7的栅极与第二节点d2连接，第七晶体管M7的第一极与第二晶体管M2的第二极连接，第七晶体管M7的第二极连接为接收第二参考电压VGL。
又进一步地，参照图5，削角子电路30还可包括第八晶体管M8，第八晶体管M8的栅极与第二节点d2连接，第八晶体管M8的第一极与第一节点d1连接，第八晶体管M8的第二极连接为接收第二参考电压VGL。
需要说明的是，该示例中的第一参考电压VDD信号为直流高电平信号，第二参考电压VGL信号为直流低电平信号。第一晶体管M1至第八晶体管M8均可以是薄膜晶体管，其第一极均可以为源极或者漏极，第二极均可以为漏极或者栅极。
例如，下面参照图3-图5描述该示例中的移位寄存电路100的工作过程。
在第一时间段t1内，第一控制信号CR1为高电平信号，第一晶体管M1接收第一控制信号CR1，以根据该第一控制信号CR1使第一节点d1的电位由初始电位V0跳变至第一电位V1。
在第二时间段t2内，第一时钟信号CLKE为高电平信号，第二晶体管M2接收该第一时钟信号CLKE，以根据该第一时钟信号CLKE和第一节点d1的电位产生高电平的输出信号OUT并使第一节点d1的电位由第一电位V1跳变至第三电位V3。
在第三时间段t3内，第二控制信号CR2为高电平信号，第一时钟信号CLKE为高 电平信号，进而第三晶体管M3根据第二控制信号CR2使第一节点d1的电位由第三电位V3逐渐降低至第四电位V4，在第一节点d1的电位由第三电位V3逐渐降低至第四电位V4的过程中，第二晶体管M2根据第一时钟信号CLKE和第一节点d1的电位输出的输出信号OUT的电位逐渐降低。
在第四时间段t4内，第三控制信号CR3为高电平信号，进而第四晶体管M4根据第三控制信号CR3使第一节点d1的电位由第四电位V4跳变至初始电位V0。
参照图3和图4可知，输出信号OUT由高电平降低至低电平时，带有一个明显的削角，而不是直接从高电平跳变至低电平。由此，能够避免输出信号的直接跳变带来的不良影响。
在本公开的一个示例中，如图6所示，输出子电路20还可包括第九晶体管M9，第九晶体管M9的栅极与第一节点d1连接，第九晶体管M9的第一极连接为接收第二时钟信号CLKD，第九晶体管M9的第二极作为移位寄存电路100的控制输出端，用以输出移位寄存电路100的控制输出信号CR；削角子电路30还可包括第十晶体管M10，第十晶体管M10的栅极与第二节点d2连接，第十晶体管M10的第一极与第九晶体管M9的第二极连接，第十晶体管M10的第二极连接为接收第二参考电压VGL。
需要说明的是，该示例中的第九晶体管M9和第十晶体管M10可以是薄膜晶体管，其第一极均可以为源极或者漏极，第二极均可以为漏极或者栅极。
例如，下面参照图3、图4和图6描述该示例中的移位寄存电路100的工作过程：
在第一时间段t1内，第一控制信号CR1为高电平信号，第一晶体管M1接收第一控制信号CR1，以根据该第一控制信号CR1使第一节点d1的电位由初始电位V0跳变至第一电位V1。
在第二时间段t2内，第一时钟信号CLKE和第二时钟信号CLKD均为高电平信号，第二晶体管M2接收该第一时钟信号CLKE，以根据该第一时钟信号CLKE和第一节点d1的电位产生输出信号并使第一节点d1的电位由第一电位V1跳变至第三电位V3；第九晶体管接收该第二时钟信号CLKD，以根据该第二时钟信号CLKD和第一节点d1的电位产生控制输出信号CR，且该控制输出信号CR为高电平信号。
在第三时间段t3内，第二控制信号CR2为高电平信号，第一时钟信号CLKE和第二时钟信号CLKD均为高电平信号，进而第三晶体管M3根据第二控制信号CR2使第一节点d1的电位由第三电位V3逐渐降低至第四电位V4，在第一节点d1的电位由第三电 位V3逐渐降低至第四电位V4的过程中，第二晶体管M2根据第一时钟信号CLKE和第一节点d1的电位输出的输出信号OUT的电位逐渐降低；第九晶体管M9根据第二时钟信号CLKD和第一节点d1的电位输出的控制输出信号CR的电位也同样逐渐降低，从而使得所述控制输出信号CR的波形带有削角。
在第四时间段t4内，第三控制信号CR3为高电平信号，进而第四晶体管M4根据第三控制信号CR3使第一节点d1的电位由第四电位V4跳变至初始电位V0；第九晶体管M9根据第二时钟信号CLKD(低电平)和第一节点d1的第四电位V4输出所述控制输出信号CR，且该控制输出信号CR为低电平信号。
需要说明的是，本公开示例中的第一时钟信号CLKE、第二时钟信号CLKD、第一参考电压VDD和第二参考电压VGL均可以是外部控制信号，而第一控制信号CR1、第二控制信号CR2和第三控制信号CR3可以根据控制输出信号CR确定。
例如，可通过将该示例中的移位寄存电路100进行多个级联，以得到栅极驱动电路，即该栅极驱动电路包括多级该示例中的移位寄存电路100，其中，第N级移位寄存电路的第一控制信号CR1、第二控制信号CR2和第三控制信号CR3分别为第N-4级、第N+3级和第N+8级移位寄存电路的控制输出信号CR，其中，N为大于4的整数。
也可以说，第一控制信号CR1可以为控制输出信号CR<N-4>，第二控制信号CR2可以为控制输出信号CR<N+3>，第三控制信号CR3可以为控制输出信号CR<N+8>，移位寄存电路100的控制输出信号CR即为CR<N>。
由此，第一控制信号、第二控制信号、第三控制信号和第一时钟信号使移位寄存电路的输出信号波形带有明显的削角，以避免输出信号的直接跳变带来的不良影响。
在本公开的一个实施例中，参照图5、图6，移位寄存电路100还可包括复位子电路40，复位子电路40包括第十一晶体管M11，第十一晶体管M11的栅极连接为接收复位信号TRST，第十一晶体管M11的第一极与第一节点d1连接，第十一晶体管M11的第二极连接为接收第二参考电压VGL。
该实施例中的第十一晶体管M11可以是薄膜晶体管，其第一极可以为源极或者漏极，第二极可以为漏极或者栅极。
例如，可通过第十一晶体管M11根据复位信号TRST对第一节点d1进行复位。其中，复位信号TRST可以为外部控制信号。
综上所述，本公开实施例的移位寄存电路，其削角子电路根据第二控制信号控制第 一节点d1的电位，以使输出子电路根据第一时钟信号和第一节点的电位输出的输出信号带有削角，从而避免第一节点的电位变化过大引起的输出信号跳变的现象，避免像素电路的栅极电位信号从高电平直接跳变至低电平。
基于同样的思路，本公开实施例提出了一种移位寄存电路的驱动方法，图7是本公开实施例的移位寄存电路的驱动方法的流程图。
该移位寄存电路的驱动方法用于驱动本公开上述实施例的移位寄存电路100，如图7所示，该移位寄存电路的驱动方法包括以下步骤：
S1，所述输入子电路接收第一控制信号，并根据所述第一控制信号使所述第一节点的电位由初始电位跳变至所述第一电位，其中，所述第一电位大于所述初始电位。
S2，所述输出子电路接收第一时钟信号，并根据所述第一时钟信号和所述第一节点的电位产生输出信号并使所述第一节点的电位由所述第一电位跳变至所述第三电位，其中，所述第三电位大于所述第一电位。
S3，所述削角子电路接收第二控制信号，并根据所述第二控制信号使得所述第一节点的电位从所述第三电位逐渐降低至第四电位，使得所述输出子电路根据所述第一时钟信号和所述第一节点的电位产生的输出信号的电位逐渐降低。
S4，所述削角子电路接收第三控制信号，并根据第三控制信号使得所述第一节点的电位由第四电位跳变至初始电位，其中，第四电位小于第三电位，且大于初始电位。
例如，在驱动移位寄存电路时，首先输入子电路接收第一控制信号，并根据第一控制信号使第一节点的电位由初始电位跳变至第一电位，然后通过输出子电路接收第一时钟信号，并根据第一时钟信号使第一节点的电位由第一电位跳变至第三电位，通过削角子电路接收第二控制信号，并根据第二控制信号使第一节点的电位从第三电位逐渐降低至第四电位，在第一节点的电位逐渐降低至第四电位的过程中，输出子电路根据第一时钟信号和第一节点的电位输出带削角的输出信号，最后通过削角子电路接收第三控制信号，并根据第三控制信号使第一节点的电位由第四电位跳变至初始电位。
需要说明的是，本公开实施例的移位寄存电路的驱动方法的其他实施方式可参见本公开上述移位寄存电路的实施方式，此处不再赘述。
本公开实施例的移位寄存电路的驱动方法，通过削角子电路根据第二控制信号控制第一节点的电位，使输出子电路根据第一时钟信号和第一节点的电位输出带削角的输出 信号，从而避免第一节点的电位变化过大引起的输出信号跳变的现象，避免像素电路的栅极电位信号从高电平直接跳变至低电平。
基于同样的思路，本公开实施例提出了一种栅极驱动电路，图8是本公开实施例的栅极驱动电路的结构框图。
如图8所示，该栅极驱动电路1000包括多级移位寄存电路，每一级移位寄存电路均采用本公开上述实施例的移位寄存电路100。
其中，第N级移位寄存电路100的第一控制信号CR1、第二控制信号CR2和第三控制信号CR3分别为第N-4级、第N+3级和第N+8级移位寄存电路的控制输出信号CR，其中，N为大于4的整数。
也就是说，第一控制信号CR1可以为控制输出信号CR<N-4>，第二控制信号CR2可以为控制输出信号CR<N+3>，第三控制信号CR3可以为控制输出信号CR<N+8>，移位寄存电路100的控制输出信号CR即为CR<N>。
例如，在将该栅极驱动电路1000运用于显示技术领域时，可通过栅极驱动电路1000向图2所示的像素电路提供栅极驱动信号。
本公开实施例的栅极驱动电路，通过本公开实施例的移位寄存电路，使输出子电路根据第一时钟信号和第一节点的电位输出带削角的输出信号，能够避免第一节点的电位变化过大引起的输出信号跳变的现象，避免像素电路的栅极电位信号从高电平直接跳变至低电平。
基于同样的思路，本公开实施例提出了一种显示装置，图9是本公开实施例的显示装置的结构框图。
如图9所示，该显示装置10000包括本公开上述实施例的栅极驱动电路1000。该显示装置10000可以为：手机、平板电脑、笔记本电脑、液晶屏等任何具有显示功能的产品或部件。
本公开实施例的显示装置，通过本公开实施例的栅极驱动电路，使输出子电路根据第一时钟信号和第一节点的电位输出带削角的输出信号，能够避免第一节点的电位变化过大引起的输出信号跳变的现象，避免像素电路的栅极电位信号从高电平直接跳变至低电平。
此外，术语“第一”、“第二”用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明 示或者隐含地包括至少一个该特征。在本公开的描述中，“多个”的含义是至少两个，例如两个，三个等，除非另有明确的限定。
在本公开中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”、“固定”等术语应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或成一体；可以是机械连接，也可以是电连接；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通或两个元件的相互作用关系，除非另有明确的限定。对于本领域的普通技术人员而言，可以根据情况理解上述术语在本公开中的含义。
在本说明书的描述中，参考术语“一个实施例”、“一些实施例”、“示例”、“具体示例”、或“一些示例”等的描述意指结合该实施例或示例描述的特征、结构、材料或者特点包含于本公开的至少一个实施例或示例中。在本说明书中，对上述术语的示意性表述不必须针对的是相同的实施例或示例。而且，描述的特征、结构、材料或者特点可以在任一个或多个实施例或示例中以合适的方式结合。此外，在不相互矛盾的情况下，本领域的技术人员可以将本说明书中描述的不同实施例或示例以及不同实施例或示例的特征进行结合和组合。
尽管上面已经示出和描述了本公开的实施例，可以理解的是，上述实施例是示例性的，不能理解为对本公开的限制，本领域的普通技术人员在本公开的范围内可以对上述实施例进行变化、修改、替换和变型。

Claims (12)

  1. 一种移位寄存电路，包括：
    输入子电路，连接至所述移位寄存电路的第一节点，被配置为接收第一控制信号，并根据所述第一控制信号使所述第一节点的电位由初始电位跳变至第一电位，所述第一电位大于所述初始电位；
    输出子电路，连接至所述移位寄存电路的第一节点，被配置为接收第一时钟信号，并根据所述第一时钟信号和所述第一节点的电位产生输出信号并使所述第一节点的电位由所述第一电位跳变至第三电位，其中，所述第三电位大于所述第一电位；
    削角子电路，连接至所述移位寄存电路的第一节点，被配置为接收第二控制信号，根据所述第二控制信号使所述第一节点的电位从所述第三电位逐渐降低至第四电位，使得所述输出信号的电位逐渐降低，以及根据第三控制信号使所述第一节点的电位由所述第四电位跳变至所述初始电位，其中，所述第四电位大于所述初始电位，且小于所述第三电位。
  2. 如权利要求1所述的移位寄存电路，其中，所述输入子电路包括：
    第一晶体管，所述第一晶体管的栅极连接为接收所述第一控制信号，所述第一晶体管的第一极与所述第一晶体管的栅极连接，所述第一晶体管的第二极与所述第一节点连接。
  3. 如权利要求1或2所述的移位寄存电路，其中，所述输出子电路包括：
    第二晶体管，所述第二晶体管的栅极与所述第一节点连接，所述第二晶体管的第一极连接为接收所述第一时钟信号，所述第二晶体管的第二极作为所述移位寄存电路的输出端，用以输出所述输出信号；
    第一电容，所述第一电容的一端与所述第二晶体管的栅极连接，所述第一电容的另一端与所述第二晶体管的第二极连接。
  4. 如权利要求1至3中任一项所述的移位寄存电路，其中，所述削角子电路包括：
    第三晶体管，所述第三晶体管的栅极连接为接收所述第二控制信号，所述第三晶体管的第一极连接为接收第一参考电压，所述第三晶体管的第二极与所述第 一节点连接；
    第四晶体管，所述第四晶体管的栅极连接为接收所述第三控制信号，所述第四晶体管的第一极与所述第一节点连接，所述第四晶体管的第二极连接为接收第二参考电压；
    第五晶体管，所述第五晶体管的第一极和栅极均与所述第三晶体管的第一极连接；
    第六晶体管，所述第六晶体管的栅极与所述第一节点连接，所述第六晶体管的第一极与所述第五晶体管的第二极连接，并形成第二节点，所述第六晶体管的第二极连接为接收所述第二参考电压；
    第七晶体管，所述第七晶体管的栅极与所述第二节点连接，所述第七晶体管的第一极作为所述移位寄存电路的输出端，所述第七晶体管的第二极连接为接收所述第二参考电压。
  5. 如权利要求4所述的移位寄存电路，其中，所述削角子电路还包括：
    第八晶体管，所述第八晶体管的栅极与所述第二节点连接，所述第八晶体管的第一极与所述第一节点连接，所述第八晶体管的第二极连接为接收所述第二参考电压。
  6. 如权利要求4或5所述的移位寄存电路，其中，
    所述输出子电路还包括第九晶体管，所述第九晶体管的栅极与所述第一节点连接，所述第九晶体管的第一极连接为接收第二时钟信号，所述第九晶体管的第二极作为所述移位寄存电路的控制输出端，用以输出所述移位寄存电路的控制输出信号；
    所述削角子电路还包括第十晶体管，所述第十晶体管的栅极与所述第二节点连接，所述第十晶体管的第一极与所述第九晶体管的第二极连接，所述第十晶体管的第二极连接为接收所述第二参考电压。
  7. 如权利要求1至6中任一项所述的移位寄存电路，其中，还包括复位子电路，所述复位子电路包括：
    第十一晶体管，所述第十一晶体管的栅极连接为接收复位信号，所述第十一晶体管的第一极与所述第一节点连接，所述第十一晶体管的第二极连接为接收第二参考电压。
  8. 如权利要求1至7中任一项所述的移位寄存电路，其中，所述削角子电路被配置为在所述第一时钟信号与所述第二控制信号均为高电位期间，使得所述输出信号的电位逐渐降低。
  9. 一种移位寄存电路的驱动方法，其中，用于驱动如权利要求1-8中任一项所述的移位寄存电路，所述方法包括：
    在第一时间段，所述输入子电路接收第一控制信号，并根据所述第一控制信号使所述第一节点的电位由初始电位跳变至所述第一电位，其中，所述第一电位大于所述初始电位；
    在第二时间段，所述输出子电路接收第一时钟信号，并根据所述第一时钟信号和所述第一节点的电位产生输出信号并使所述第一节点的电位由所述第一电位跳变至所述第三电位，其中，所述第三电位大于所述第一电位；
    在第三时间段，所述削角子电路接收第二控制信号，并根据所述第二控制信号使得所述第一节点的电位从所述第三电位逐渐降低至第四电位，使得所述输出子电路根据所述第一时钟信号和所述第一节点的电位产生的输出信号的电位逐渐降低；以及
    在第四时间段，所述削角子电路接收第三控制信号，并根据所述第三控制信号使得所述第一节点的电位由所述第四电位跳变至所述初始电位，其中，所述第四电位小于所述第三电位，且大于所述初始电位。
  10. 一种栅极驱动电路，其中，包括多级移位寄存电路，每一级移位寄存电路均采用如权利要求1-8中任一项所述的移位寄存电路。
  11. 如权利要求10所述的栅极驱动电路，其中，第N级移位寄存电路的第一控制信号、第二控制信号和第三控制信号分别为第N-4级、第N+3级和第N+8级移位寄存电路的控制输出信号，其中，N为大于4的整数。
  12. 一种显示装置，其中，包括如权利要求10或11所述的栅极驱动电路。
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