WO2021056603A1 - 功率型半导体器件封装结构 - Google Patents

功率型半导体器件封装结构 Download PDF

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WO2021056603A1
WO2021056603A1 PCT/CN2019/109576 CN2019109576W WO2021056603A1 WO 2021056603 A1 WO2021056603 A1 WO 2021056603A1 CN 2019109576 W CN2019109576 W CN 2019109576W WO 2021056603 A1 WO2021056603 A1 WO 2021056603A1
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electrode
conductive layer
semiconductor device
flexible conductive
power semiconductor
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PCT/CN2019/109576
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English (en)
French (fr)
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邱宇峰
李现兵
赵志斌
吴军民
张朋
张雷
唐新灵
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全球能源互联网研究院有限公司
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Publication of WO2021056603A1 publication Critical patent/WO2021056603A1/zh

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/34Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367Cooling facilitated by shape of device
    • H01L23/3677Wire-like or pin-like cooling fins or heat sinks
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481Internal lead connections, e.g. via connections, feedthrough structures
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/49Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions wire-like arrangements or pins or rods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838Geometry or layout
    • H01L23/49844Geometry or layout for devices being provided for in H01L29/00
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/562Protection against mechanical damage
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N

Definitions

  • This article belongs to the field of semiconductor device manufacturing, for example, it relates to a power semiconductor device packaging structure.
  • thyristors insulated gate bipolar transistors
  • IGBTs are widely used in new energy, power transmission and transformation, rail transit, metallurgy, and chemical industries.
  • Chinese patent document CN105957888A discloses a power semiconductor device packaging structure.
  • the packaging structure restricts the horizontal movement of the power semiconductor device, emitter electrode, and collector electrode through a positioning member, and the gate electrode passes through a through hole on the positioning member. Connect with PCB board.
  • the power semiconductor device emitter electrode and collector electrode are directly connected to the device packaging electrode by pressure, and the power semiconductor device bears all the mounting pressure, whether it is a rigid electrode or an elastic electrode.
  • the device package electrode In the case of multi-power semiconductor devices in parallel, there is a problem of uneven pressure distribution; the device package electrode also assumes the role of electrical conductivity, heat conduction, and pressure support at the same time, and the multi-physical fields are tightly coupled with each other.
  • This article can solve the defects that the reliability of the related technology power semiconductor device packaging structure needs to be improved.
  • This article provides a power semiconductor device packaging structure.
  • the power semiconductor device package structure provided herein includes several chip components.
  • the chip component includes a first terminal and a second terminal.
  • the C electrode of the semiconductor device is connected to the first terminal, and the E electrode of the semiconductor device is connected to the second terminal.
  • the terminal connection also includes,
  • a flexible conductive layer and an insulating board covered with a conductive layer on both sides One side of the insulating board is connected to the first terminal, and the other side of the insulating board is provided with a plurality of first conductive protrusions for receiving the flexible conductive layer.
  • a conductive bump is connected to the other side of the insulating board and the flexible conductive layer, the flexible conductive layer is connected to the E electrode, and the flexible conductive layer is used to disperse the compressive stress acting on the chip assembly.
  • Figure 1 is an exploded view of the power semiconductor device packaging structure in this article
  • Figure 2 is a cross-sectional view of the power semiconductor device packaging structure in this article
  • FIG. 3 is another cross-sectional view of the power semiconductor device packaging structure in this article.
  • Figure 4 is the current, heat dissipation and driving path diagram of the power semiconductor device in this article
  • FIG. 5 is another cross-sectional view of the power semiconductor device packaging structure in this article.
  • Figure 6 is a schematic diagram of the structure of the E electrode in this article.
  • Figure 7 is a schematic diagram of the structure of the insulator in this article.
  • FIG. 8 is a schematic diagram of the structure of the C electrode, the flexible conductive layer and the driving electrode in this text;
  • Figure 9 is a top view of the structure in Figure 8.
  • FIG. 10 is a schematic diagram of the structure of the flexible conductive layer in this article.
  • FIG. 11 is a schematic diagram of the structure of the driving electrode in this article.
  • FIG. 12 is another cross-sectional view of the power semiconductor device packaging structure herein;
  • FIG. 13 is a cross-sectional view of the structure in FIG. 12 along AA.
  • this article provides a power semiconductor device packaging structure.
  • the power semiconductor device packaging structure has a circular pie shape with a small thickness, which is convenient for device pressing and series applications.
  • the chip assembly 4 includes a first terminal and a second terminal, the C electrode 1 of the semiconductor device is connected to the first terminal, in some embodiments, the connection between the two can be through direct crimping, The E electrode 3 of the semiconductor device is connected to the second terminal. In some embodiments, the connection between the two can be achieved by direct crimping, sintering, welding or conductive adhesive bonding. It is realized in the form of a transition metal layer connected to the expansion rate, and also includes,
  • the connection between the two can be through direct crimping, sintering, welding or conducting Glue bonding expansion ratio transition metal layer is realized.
  • the other side of the insulating board 10 is provided with a number of first conductive bumps 10a for receiving the flexible conductive layer 5, and the first conductive bumps 10a are connected to the insulating board.
  • connection between the two can be achieved by direct crimping, sintering, welding or conductive adhesive bonding the expansion rate transition metal layer, the flexible conductive
  • the layer 5 is connected to the E electrode 3.
  • the connection between the two can be achieved by direct crimping, sintering, welding or conductive adhesive bonding the expansion rate transition metal layer.
  • the flexible conductive layer 5 is used for The compressive stress acting on the chip assembly 4 is dispersed.
  • the E electrode 3 does not directly act on the chip component 4, and the current of the chip component 4 passes
  • the flexible conductive layer 5 reaches the E electrode 3, the heat of the chip assembly 4 is conducted to the heat dissipation working medium through the flexible conductive layer 5 in a vertical manner (for example, heat is transferred to the surrounding electrodes), and the first conductive protrusion 10a receives the flexible conductive layer 5 , Disperse the compressive stress acting on the chip component 4, the flexible conductive layer 5 realizes a smaller compressive stress on the welding surface of the chip component 4, avoiding greater pressure directly acting on the surface of the chip component 4, and reducing the temperature of the chip component 4
  • Three-way stress damage under high-pressure stress conditions during cycling improves connection reliability, realizes the decoupling of pressure and electrical and thermal conductivity, and ultimately improves the reliability of the power semiconductor device packaging structure.
  • the contact thermal resistance and the contact resistance are independent of each other, which realizes the decoupling of electrical and thermal conductivity, reduces the height of the device and reduces the stray inductance.
  • the flexible conductive layer 5 includes at least a flexible bonding wire, a bonding tape, a highly conductive metal or non-metallic material; the structure type includes an overall structure consistent with the shape of the electrode structure and various special-shaped structures.
  • the materials used for the flexible conductive layer 5 are metal conductive materials, non-metal conductive materials, graphene, non-metal composite materials with metal coatings, and the structure type is single layer, multi-layer, flat plate or wave shape and others. Structure type used to meet mechanical conditions and electrical design.
  • the insulating board 10 covered with a conductive layer on both sides is a variety of non-metallic boards and has various structural shapes for insulation and electrical connection.
  • a second conductive protrusion 3a is provided on the side of the E electrode 3 close to the flexible conductive layer 5, and the second conductive protrusion 3a corresponds to the first conductive protrusion 10a .
  • the chip assembly 4 further includes a third terminal connected to the G electrode 7 of the semiconductor device through the G electrode lead 11; and further includes a driving electrode 6, so The driving electrode 6 is connected to the G electrode 7 through the G electrode external wire 12.
  • the third terminal is connected to the G electrode 7 (for example, the G electrode DBC) of the semiconductor device through the G electrode lead 11; the G electrode 7 is arranged on the insulating board (for example, it can be a double-sided copper-clad insulation board).
  • the G electrode lead 11 is collected at the edge of the power semiconductor device at an equal distance, so that the G electrode lead 11 is drawn perpendicular to the direction of the power current, avoiding mutual interaction between the two. Interference realizes the decoupling of the control signal and the power current. Therefore, the multi-physics decoupling package design of power semiconductor devices is the key to solving the reliability of the package structure.
  • the insulating board 10 covered with a conductive layer on both sides is composed of several insulating blocks.
  • the several insulating blocks are arranged symmetrically.
  • the insulating blocks are provided with first conductive protrusions 10a.
  • the material of the insulating blocks is The thickness of the AlN material is determined according to the insulation voltage design, and the surface is coated with copper to facilitate double-sided welding; the first conductive bump 10a is made of red copper material (99.9% Cu), and its height can be adjusted according to structural requirements.
  • the C electrode 1 is a C electrode plate
  • the E electrode 3 is an E electrode plate
  • the driving electrode 6 is a PCB board
  • the materials of the C electrode plate, the E electrode plate and the E electrode flange 2b All are made of red copper (99.9% Cu), nickel-plated on the surface;
  • an insulator 2 having a first open end and a second open end oppositely arranged. In the direction of the first open end and the second open end, the insulator 2 is sequentially provided with the double-sided conductive layer-covered insulating board 10.
  • Chip assembly 4 flexible conductive layer 5, PCB board, said C electrode plate is suitable for covering said first open end, said E electrode plate is suitable for covering said second open end; said insulator 2
  • the material is ceramic, and the surface is covered with glaze.
  • the surface of the flexible conductive layer 5 and the insulating board 10 covered with a conductive layer on both sides is plated with a highly conductive anti-oxidation coating, such as a nickel layer;
  • the C electrode plate, the insulator 2 and the E electrode flange 2b can be sintered into one body at a high temperature (for example, 1000° C.).
  • a number of outer sheds 2a are provided at intervals on the outer surface of the insulator 2, and the outer sheds 2a are provided to meet different voltage levels and pollution. Creepage requirements under the level;
  • An insulating layer 8 is provided inside the insulator 2 to fill the remaining space inside the insulator 2 between the flexible conductive layer 5 and the C electrode plate.
  • the insulating layer 8 serves as the main internal insulating medium, and its material is generally epoxy resin. Or silicone gel, the insulation strength is required to be no less than 20kV/mm, and the insulating layer 8 will not generate air inside the insulator 2 during the temperature rise and fall process to damage the insulation.
  • the thermally conductive layer 9 is disposed inside the insulator 2 and located between the flexible conductive layer 5 and the E electrode plate to fill the flexible conductive layer 5.
  • the material of the thermal conductive layer 9 is an insulating, semi-insulating, and metallic material with elastic solid, fluid, powder, etc. that can be used for heat conduction; in some embodiments, the heat conduction Layer 9 is a homogeneous mixture of thermally conductive silicone grease and metal powder, which has high thermal conductivity.
  • the heat of the power semiconductor device vertically passes through the flexible conductive layer 5, and conducts the heat to the thermal conductive layer 9 (that is, the injected high thermal conductivity material).
  • the high thermal conductivity material increases the instantaneous thermal melting of the device package on the one hand, and on the other On the one hand, the heat is directed to the side electrodes and adjacent electrodes.
  • a pouring hole 3b is provided on the E electrode for pouring a high thermal conductivity material to form the thermal conductive layer 9.
  • positioning holes for device mounting are provided outside the C electrode and the E electrode.
  • the design of flexible conductive layer 5 and heat conductive layer 9 solves the problem of contact thermal resistance due to electrode pressure.
  • the coexistence area avoids the mutual interference between the two and realizes the decoupling of the control signal and the power current.
  • the chip assembly 4 includes a first transition layer, a chip 4b, and a second transition layer stacked in sequence, and the C electrode 1 is provided for placing
  • the positioning groove 1a of the chip assembly 4 the first transition layer is arranged in the positioning groove 1a, the second transition layer is provided with a third conductive protrusion 4d, and the third conductive protrusion 4d is connected to the flexible conductive Layer 5 is in contact;
  • the first transition layer is C gasket 4a, and the second transition layer is E gasket;
  • the material of C gasket 4a and E gasket can use the thermal characteristics of chip 4b, such as the material matching the expansion rate, in some
  • the material of the C gasket 4a and the E gasket can be made of pure molybdenum (99.93% Mo), and the surface is plated with nickel and then silver;
  • the material of the third conductive bump 4d is made of red copper, and its height can be adjusted according to The structure needs to be adjusted; as shown in Figures
  • the chip assembly 4 is fixed by a frame, the edge of the frame is injected with insulating material and fixed on the surface of the C electrode to compensate for the difference in expansion rate between the power semiconductor device and the electrode material, and the power semiconductor device is welded or sintered on the surface of the C electrode or to compensate for the expansion of the power semiconductor device and the electrode material Matching materials with different rates; single-sided or double-sided sintering of power semiconductor devices is conducive to making up for the difference in expansion rates between electrode materials and power semiconductor devices.
  • a mounting hole 5a is provided on the flexible conductive layer 5 for mounting the flexible conductive layer 5 on the third conductive protrusion 4d; in some embodiments Wherein, the flexible conductive layer 5 can be fixed on the third conductive protrusion 4d by screws;
  • the flexible conductive layer 5 is provided with a connection hole 5b for the G electrode external wire 12 to pass through the flexible conductive layer 5 through the connection hole 5b and connect to the driving electrode 6, so as to avoid contact with the flexible conductive layer 5 Contact and short-circuit;
  • the shape of the connecting hole 5b can be a square hole.
  • the flexible conductive layer 5 is made of red copper material (99.9% Cu), and the surface is plated with silver.
  • the flexible conductive layer 5 is not only a power current carrier, but also is arranged on the first conductive bump 10a and Between the second conductive bumps 3a, they are used to withstand the pressure during installation. In order to meet the design requirements of power current and the chip not bearing pressure, the thickness is generally less than 1 mm.
  • the driving electrode 6 is provided with a through hole 6a for the second conductive protrusion 3a to penetrate the driving electrode 6 through the through hole 6a; the driving electrode 6 is provided with a threading hole 6c , Used for the lead-out and welding of the G electrode external connection 12; in some embodiments, the G electrode lead 11 and the G electrode external connection 12 are made of soft copper foil material with a certain width and thickness, which effectively reduces parasitic inductance.
  • the G electrode 7 is made of AlN material with a certain thickness, and the surface is coated with copper.
  • the G electrode lead 11 and the G electrode external connection 12 can use various metal leads such as aluminum, gold, silver, or a spring probe with a length of less than 8 mm;
  • the driving electrode 6 is a PCB board with several copper layers; the insulating material of the PCB board is high temperature resistant polyether ether ketone (PEEK); the G electrode 7 is led out as a multilayer copper layer , Effectively reducing the parasitic inductance of the drive loop;
  • PEEK polyether ether ketone
  • An equipotential hole 6b is provided on the driving electrode, and the equipotential hole 6b is used for potential connection between copper layers.
  • various elastomer elements, high thermal conductivity elastomer materials, compressed gas, etc. are added to the interior of the insulator 2 between the flexible conductive layer 5 and the C electrode plate to relieve stress.
  • the above-mentioned power semiconductor device packaging structure uses the flexible conductive layer 5 as the connection medium (Bus) for chip paralleling and current collection, and divides the device into two upper and lower regions.
  • the lower half of the device is made of AlN insulating sheet and insulating potting material The coordination of the field strength solves the concentration of field strength and realizes the withstand voltage requirements.
  • the upper half of the device is filled with thermal grease and auxiliary heat dissipation.
  • the laminated copper foil is used to connect the driving PCB and the gate copper pillar by welding. Pressure is applied to the gate copper pillar and the double-sided copper-clad insulating board. The chip does not bear pressure.
  • the electrical connection can be directly connected without any spring.
  • the size of the power semiconductor device package structure It is ⁇ 82 ⁇ 27mm 3 , a total of 10 IGBT chips and 10 PiN chips are packaged, and the power density is 7.57W/mm 3 .
  • the E electrode does not directly act on the chip component by setting a flexible conductive layer and an insulating board covered with a conductive layer on both sides.
  • the current of the chip component reaches the E electrode through the flexible conductive layer.
  • the heat of the chip component is conducted to the heat dissipation medium through the flexible conductive layer in a vertical manner (for example, heat is transferred to the surrounding electrodes), and the first conductive bumps receive the flexible conductive layer, which disperses the compressive stress acting on the chip component, and is flexible
  • the conductive layer achieves a small compressive stress on the welding surface of the chip component, avoids greater pressure directly acting on the surface of the chip component, reduces the three-way stress damage under high-pressure stress conditions during the temperature cycle of the chip component, and improves the connection reliability. Realize the decoupling of pressure and electrical and thermal conductivity, and ultimately improve the reliability of the power semiconductor device packaging structure.
  • a flexible conductive layer is provided to make the current flow from the C electrode to the E electrode laterally along the flexible conductive layer, and the heat enters the heat dissipation working medium in the direction perpendicular to the flexible conductive layer.
  • the flow direction is vertical, and the contact thermal resistance and the contact resistance are independent of each other, which realizes the decoupling of electrical and thermal conductivity, reduces the height of the device, and reduces the stray inductance.
  • the chip assembly when the chip assembly further includes a third terminal, the third terminal is connected to the G electrode of the semiconductor device through the G electrode lead; the G electrode is arranged on the insulation of the double-sided conductive layer
  • the G electrode leads are collected at the edge of the power semiconductor device at an equal distance, so that the G electrode leads are drawn perpendicular to the direction of the power current, avoiding mutual interaction between the two Interference realizes the decoupling of the control signal and the power current. Therefore, the multi-physics decoupling package design of the power semiconductor device is the key to solving the reliability of the package structure.

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Abstract

一种功率型半导体器件封装结构,包括若干芯片组件(4),所述芯片组件(4)包括第一端子和第二端子,半导体器件的C电极(1)与第一端子连接,所述半导体器件的E电极(3)与第二端子连接,还包括,柔性导电层(5)及双面覆导电层的绝缘板(10),所述绝缘板(10)的一面与第一端子连接,所述绝缘板(10)的另一面设置若干用于承接柔性导电层(5)的第一导电凸起(10a),所述第一导电凸起(10a)连接所述绝缘板(10)的另一面与所述柔性导电层(5),所述柔性导电层(5)与E电极(3)连接。

Description

功率型半导体器件封装结构
本公开要求在2019年09月29日提交中国专利局、申请号为201910931350.2的中国专利申请的优先权,以上申请的全部内容通过引用结合在本公开中。
技术领域
本文属于半导体器件制备领域,例如涉及一种功率型半导体器件封装结构。
背景技术
目前,功率型半导体器件发展迅猛,例如,晶闸管、绝缘栅双极晶体管IGBT广泛应用于新能源、输变电、轨道交通、冶金以及化工等领域。例如中国专利文献CN105957888A中公开了一种功率型半导体器件封装结构,该封装结构通过定位件限制功率型半导体器件、发射极电极、集电极电极的水平移动,栅极电极通过定位件上的通孔与PCB板连接。
然而,在上述功率型半导体器件封装结构中,功率半导体器件发射极电极与集电极电极直接通过压力的形式与器件封装电极进行连接,功率半导体器件承受全部安装压力,无论是刚性电极还是弹性电极,多功率半导体器件并联情况下,均存在压力分布不均匀问题;器件封装电极同时还承担导电、导热、压力支撑作用,相互之间多物理场紧密耦合,由于压力不均匀性的绝对性存在,从而导致接触电阻和接触热阻的不均匀性趋势增加,对多功率半导体器件并联均流、散热以及应力分布集中程度产生了较大的影响,进而严重影响器件封装的可靠性;栅极引线平行与发射极电极,二者存在信号耦合,容易引起栅极的高频振荡。
发明内容
本文可以解决相关技术功率型半导体器件封装结构可靠性有待改善的缺陷,本文提供一种功率型半导体器件封装结构。
本文采用的技术方案如下:
本文所提供的功率型半导体器件封装结构,包括若干芯片组件,所述芯片组件包括第一端子和第二端子,半导体器件的C电极与第一端子连接,所述半导体器件的E电极与第二端子连接,还包括,
柔性导电层及双面覆导电层的绝缘板,所述绝缘板的一面与第一端子连接, 所述绝缘板的另一面设置若干用于承接柔性导电层的第一导电凸起,所述第一导电凸起连接所述绝缘板的另一面与所述柔性导电层,所述柔性导电层与E电极连接,所述柔性导电层用于分散作用于所述芯片组件上的压应力。
附图说明
下面将对具体实施方式或相关技术描述中所需要使用的附图作简单地介绍,显而易见地,下面描述中的附图是本文的一些实施方式,对于本领域普通技术人员来讲,在不付出创造性劳动的前提下,还可以根据这些附图获得其他的附图。
图1为本文中功率型半导体器件封装结构的爆炸图;
图2为本文中功率型半导体器件封装结构的一种剖视图;
图3为本文中功率型半导体器件封装结构的另一种剖视图;
图4为本文中功率型半导体器件工作时的电流、散热及驱动路径图;
图5为本文中功率型半导体器件封装结构的另一种剖视图;
图6为本文中E电极的结构示意图;
图7为本文中绝缘体的结构示意图;
图8为本文中C电极、柔性导电层及驱动电极的结构示意图;
图9为图8中结构的俯视图;
图10为本文中柔性导电层的结构示意图;
图11为本文中驱动电极的结构示意图;
图12为本文中功率型半导体器件封装结构的另一种剖视图;
图13为图12中结构沿AA的剖视图。
附图标记如下:
1-C电极;1a-定位凹槽;2-绝缘体;2a-外延伞裙;2b-E电极法兰;3-E电极;3a-第二导电凸起;3b-灌注孔;4-芯片组件;4a-C垫片;4b-芯片;4c-E垫片;4d-第三导电凸起;5-柔性导电层;5a-安装孔;5b-连接孔;6-驱动电极;6a-穿通孔;6b-等电位孔;6c-穿线孔;7-G电极;8-绝缘层;9-导热层;10-双面覆导电层的绝缘板;10a-第一导电凸起;11-G电极引线;12-G电极外连线;
具体实施方式
下面将结合附图对本文的技术方案进行清楚、完整地描述,显然,所描述 的实施例是本文一部分实施例,而不是全部的实施例。基于本文中的实施例,本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例,都属于本文保护的范围。
此外,下面所描述的本文不同实施方式中所涉及的技术特征只要彼此之间未构成冲突就可以相互结合。
如图1-13所示,本文提供了一种功率型半导体器件封装结构,如图3所示,功率型半导体器件封装结构的外形为圆形饼状,厚度小,便于器件压装和串联应用,包括若干芯片组件4,所述芯片组件4包括第一端子和第二端子,半导体器件的C电极1与第一端子连接,在一些实施例中,两者之间连接可通过直接压接、烧结、焊接或导电胶粘接的形式实现,所述半导体器件的E电极3与第二端子连接,在一些实施例中,两者之间连接可通过直接压接、烧结、焊接或导电胶粘接膨胀率过渡金属层的形式实现,还包括,
柔性导电层5及双面覆导电层的绝缘板10,所述绝缘板10的一面与第一端子连接,在一些实施例中,两者之间连接可通过直接压接、烧结、焊接或导电胶粘接膨胀率过渡金属层的形式实现,所述绝缘板10的另一面设置若干用于承接柔性导电层5的第一导电凸起10a,所述第一导电凸起10a连接所述绝缘板10的另一面与所述柔性导电层5,在一些实施例中,两者之间连接可通过直接压接、烧结、焊接或导电胶粘接膨胀率过渡金属层的形式实现,所述柔性导电层5与E电极3连接,在一些实施例中,两者之间连接可通过直接压接、烧结、焊接或导电胶粘接膨胀率过渡金属层的形式实现,所述柔性导电层5用于分散作用于所述芯片组件4上的压应力。
上述功率型半导体器件封装结构中,如图4所示,通过设置柔性导电层5及双面覆导电层的绝缘板10,E电极3不直接作用于芯片组件4上,芯片组件4的电流通过柔性导电层5到达E电极3,芯片组件4的热量以垂直方式通过柔性导电层5向散热工质传导(例如向四周的电极传热),且第一导电凸起10a来承接柔性导电层5,分散了作用于芯片组件4上的压应力,柔性导电层5对芯片组件4焊接面实现较小的压应力,避免了较大的压力直接作用在芯片组件4表面,减少了芯片组件4温度循环时高压应力条件下的三向应力损伤,提高了连接可靠性,实现压力与导电和导热的解耦,最终提高了功率型半导体器件封装结构可靠性。
此外,如图4所示,通过设置柔性导电层5,使电流沿着柔性导电层5横向 从C电极1到E电极3,热量沿垂直于柔性导电层5的方向进入散热工质,两者为垂直流向,接触热阻与接触电阻相互独立,实现了导电与导热的解耦,同时降低了器件高度,减少了杂散电感。
在一些实施例中,柔性导电层5至少包括柔性键合线、键合带、高导电性金属或者非金属材料;结构型式包括与电极结构形状一致的整体结构和各种异型结构。在一些实施例中,柔性导电层5所用材料为金属导电材料、非金属导电材料以及石墨烯、带金属覆层的非金属复合材料,结构型式为单层、多层、平板或者波浪形及其他用于满足力学条件和电气设计的结构型式。双面覆导电层的绝缘板10为各种非金属板以及具有用于绝缘和电气连接的各种结构形状。
如图3、6及12所示,所述E电极3靠近所述柔性导电层5的侧面上设置第二导电凸起3a,所述第二导电凸起3a与第一导电凸起10a相对应。
作为可选的实施方式,如图8所示,所述芯片组件4还包括第三端子,所述第三端子通过G电极引线11与半导体器件的G电极7连接;还包括驱动电极6,所述驱动电极6通过G电极外连线12与G电极7连接。当芯片组件4还包括第三端子,第三端子通过G电极引线11与半导体器件的G电极7(例如可为G电极DBC)连接;G电极7则设置于双面覆导电层的绝缘板(例如可为双面覆铜的绝缘板)上,通过G电极引线11在功率型半导体器件的边缘进行等距离汇集,使得G电极引线11垂直于功率电流方向引出,避免了两者之间的相互干扰,实现了控制信号与功率电流的解耦,因此,功率型半导体器件多物理场解耦封装设计是解决封装结构可靠性关键所在。
在一些实施例中,如图8所示,双面覆导电层的绝缘板10有若干绝缘块组成,若干绝缘块按对称布局,绝缘块上设置第一导电凸起10a,绝缘块的材质采用AlN材质,厚度根据绝缘电压设计确定,表面覆铜以便于双面焊接;第一导电凸起10a为紫铜材质(99.9%Cu),其高度可根据结构需要进行调整。
在一些实施例中,所述C电极1为C电极板,所述E电极3为E电极板,所述驱动电极6为PCB板;C电极板、E电极板及E电极法兰2b的材质均为紫铜材质(99.9%Cu),表面镀镍处理;
还包括具有相对设置的第一开口端和第二开口端的绝缘体2,沿所述第一开口端和第二开口端的方向上,所述绝缘体2内部依次设置所述双面覆导电层的绝缘板10、芯片组件4、柔性导电层5、PCB板,所述C电极板适于封盖所述第一开口端,所述E电极板适于封盖所述第二开口端;所述绝缘体2的材质为 陶瓷材质,表面覆釉。柔性导电层5和双面覆导电层的绝缘板10的表面镀高导电抗氧化镀层,例如镍层;
在实际制备过程中,C电极板、绝缘体2及E电极法兰2b可通过高温(例如1000℃)烧结为一体。
在一些实施例中,沿所述第一开口端和第二开口端的方向上,所述绝缘体2的外侧面上间隔设置若干外延伞裙2a,通过设置外延伞裙2a来满足不同电压等级和污秽等级下的爬电要求;
所述绝缘体2内部设置绝缘层8,以填充位于所述柔性导电层5与C电极板之间的所述绝缘体2内部剩余空间,绝缘层8作为内部主绝缘介质,其材质一般采用环氧树脂或者硅凝胶,要求绝缘强度不低于20kV/mm,绝缘层8在升降温过程中不会与绝缘体2内部产生气息而破坏绝缘。
如图2所示,作为可选的实施方式,还包括导热层9,设置于所述绝缘体2内部且位于所述柔性导电层5与E电极板之间,以填充位于所述柔性导电层5与E电极板之间的所述绝缘体2内部剩余空间;导热层9的材质为可用于导热的具有弹性的固体、流体、粉体等绝缘、半绝缘以及金属材料;在一些实施例中,导热层9为导热硅脂和金属粉末均匀混合物,具备高导热率。通过上述设置,功率型半导体器件的热量垂直通过柔性导电层5,将热量传导给导热层9(也即所灌注的高导热材料),高导热材料一方面增加器件封装的瞬时热熔,另一方面实现将热量导向侧边的电极和邻近电极。
在一些实施例中,E电极上设置灌注孔3b,用于灌注高导热材料以形成导热层9。
在一些实施例中,所述C电极与E电极外侧设置用于器件安装的定位孔。
此外,实现了将电极压力与接触电阻的解耦,避免了器件压力不均匀造成的多芯片并联不均流问题;柔性导电层5以及导热层9的设计,解决了接触热阻因为电极压力不均匀导致的散热均匀性差的问题,从而实现了压力与接触热阻的解耦设计;同时较薄的器件封装形式降低了器件封装内部的寄生参数,实现了较短的栅极信号与功率电流的共存区域,避免了二者的相互干扰,实现了控制信号与功率电流的解耦。
一种具体的实施方式,如图8、5和13所示,所述芯片组件4包括依次层叠设置的第一过渡层、芯片4b和第二过渡层,所述C电极1上设置用于放置芯片组件4的定位凹槽1a,所述第一过渡层设置于所述定位凹1a内,所述第二过 渡层上设置第三导电凸起4d,所述第三导电凸起4d与柔性导电层5接触;第一过渡层为C垫片4a,第二过渡层为E垫片;C垫片4a和E垫片的材质可采用与芯片4b热特性,例如膨胀率匹配的材质,在一些实施例中,C垫片4a和E垫片的材质可采用纯钼(99.93%Mo)材质,表面先镀镍再镀银处理;第三导电凸起4d的材质采用紫铜材质,其高度可根据结构需要进行调整;如图9和13所示,芯片组件4的布局为对称设计;
芯片组件4采用框架固定,框架边缘注入绝缘材料固定于C电极表面,弥补功率半导体器件与电极材料膨胀率的差异,将功率半导体器件焊接或者烧结于C电极表面或者弥补功率半导体器件与电极材料膨胀率差异的匹配材料;功率半导体器件的单面或者双面烧结有利于弥补电极材料与功率半导体器件膨胀率差异的金属或者合金材料。
作为可选的实施方式,如图10所示,所述柔性导电层5上设置安装孔5a,用于将所述柔性导电层5安装于所述第三导电凸起4d上;在一些实施例中,可通过螺钉将柔性导电层5固定于第三导电凸起4d上;
所述柔性导电层5上设置连接孔5b,用于所述G电极外连线12通过连接孔5b贯穿所述柔性导电层5并连接至所述驱动电极6上,避免与柔性导电层5发生接触而短路;连接孔5b形状可为方孔。
所述柔性导电层5采用紫铜材质(99.9%Cu),表面镀银处理,在功率型半导体器件封装结构中,柔性导电层5既为功率电流载体,又被设置于第一导电凸起10a与第二导电凸起3a之间,用于承受安装时的压力,为满足功率电流和芯片不承压的设计要求,厚度一般低于1mm。
如图11所示,所述驱动电极6上设置穿通孔6a,用于所述第二导电凸起3a通过所述穿通孔6a贯穿所述驱动电极6;所述驱动电极6上设置穿线孔6c,用于G电极外连线12引出和焊接;在一些实施例中,G电极引线11和G电极外连线12采用一定宽度和厚度的软铜箔材料,有效降低寄生电感。G电极7采用一定厚度的AlN材质,表面覆铜。当然,作为可变型的实施方式,G电极引线11和G电极外连线12可采用铝、金、银等各种金属引线或者长度在8mm以内的弹簧探针;
可选地,如图11所示,所述驱动电极6为具有若干铜层的PCB板;PCB板的绝缘材质为耐高温的聚醚醚酮(PEEK);G电极7引出为多层铜层,有效降低了驱动回路的寄生电感;
所述驱动电极上设置等电位孔6b,所述等电位孔6b用于铜层间的电位连接。
在一些实施例中,在所述柔性导电层5与C电极板之间的所述绝缘体2内部加入各种弹性体元件、高导热弹性体材料、压缩气体等,来减缓应力。
此外,上述功率型半导体器件封装结构采用柔性导电层5作为芯片并联及电流汇集的连接介质(Bus),并将器件分割为上下两个区域,器件下半区通过AlN绝缘片和绝缘灌封材料的配合,解决场强集中,实现耐压要求,器件上半区填充导热硅脂,并实现辅助散热,采用层叠铜箔以焊接方式连接驱动PCB与栅极铜柱。压力施加于栅极铜柱和双面覆铜的绝缘板上,芯片不承受压力,电气连接可全部采用直接连接方式,没有使用任何弹簧,在一个实施例中,功率型半导体器件封装结构的尺寸为φ82×27mm 3,共封装10枚IGBT芯片和10枚PiN芯片,功率密度为7.57W/mm 3
与相关技术相比,本文具有如下有益效果:
(1)本文所提供的功率型半导体器件封装结构,通过设置柔性导电层及双面覆导电层的绝缘板,E电极不直接作用于芯片组件上,芯片组件的电流通过柔性导电层到达E电极,芯片组件的热量以垂直方式通过柔性导电层向散热工质传导(例如向四周的电极传热),且第一导电凸起来承接柔性导电层,分散了作用于芯片组件上的压应力,柔性导电层对芯片组件焊接面实现较小的压应力,避免了较大的压力直接作用在芯片组件表面,减少了芯片组件温度循环时高压应力条件下的三向应力损伤,提高了连接可靠性,实现压力与导电和导热的解耦,最终提高了功率型半导体器件封装结构可靠性。
(2)本文所提供的功率型半导体器件封装结构,通过设置柔性导电层,使电流沿着柔性导电层横向从C电极到E电极,热量沿垂直于柔性导电层的方向进入散热工质,两者为垂直流向,接触热阻与接触电阻相互独立,实现了导电与导热的解耦,同时降低了器件高度,减少了杂散电感。
(3)本文所提供的功率型半导体器件封装结构,当芯片组件还包括第三端子,第三端子通过G电极引线与半导体器件的G电极连接;G电极则设置于双面覆导电层的绝缘板(例如可为双面覆铜的绝缘板)上,通过G电极引线在功率型半导体器件的边缘进行等距离汇集,使得G电极引线垂直于功率电流方向引出,避免了两者之间的相互干扰,实现了控制信号与功率电流的解耦,因此, 功率型半导体器件多物理场解耦封装设计是解决封装结构可靠性关键所在。

Claims (11)

  1. 一种功率型半导体器件封装结构,包括若干芯片组件,所述芯片组件包括第一端子和第二端子,半导体器件的C电极与第一端子连接,所述半导体器件的E电极与第二端子连接,所述功率型半导体器件封装结构还包括,
    柔性导电层及双面覆导电层的绝缘板,所述绝缘板的一面与第一端子连接,所述绝缘板的另一面设置若干用于承接柔性导电层的第一导电凸起,所述第一导电凸起连接所述绝缘板的另一面与所述柔性导电层,所述柔性导电层与E电极连接,所述柔性导电层用于分散作用于所述芯片组件上的压应力。
  2. 根据权利要求1所述的功率型半导体器件封装结构,其中,所述E电极靠近所述柔性导电层的侧面上设置第二导电凸起,所述第二导电凸起与第一导电凸起相对应。
  3. 根据权利要求2所述的功率型半导体器件封装结构,其中,所述芯片组件还包括第三端子,所述第三端子通过G电极引线与半导体器件的G电极连接;
    还包括驱动电极,所述驱动电极通过G电极外连线与G电极连接。
  4. 根据权利要求3所述的功率型半导体器件封装结构,其中,所述C电极为C电极板,所述E电极为E电极板,所述驱动电极为PCB板;
    还包括具有相对设置的第一开口端和第二开口端的绝缘体,沿所述第一开口端和第二开口端的方向上,所述绝缘体内部依次设置所述双面覆导电层的绝缘板、芯片组件、柔性导电层、PCB板,所述C电极板适于封盖所述第一开口端,所述E电极板适于封盖所述第二开口端。
  5. 根据权利要求4所述的功率型半导体器件封装结构,其中,沿所述第一开口端和第二开口端的方向上,所述绝缘体的外侧面上间隔设置若干外延伞裙;
    所述绝缘体内部设置绝缘层,以填充位于所述柔性导电层与C电极板之间的所述绝缘体内部剩余空间。
  6. 根据权利要求4或5所述的功率型半导体器件封装结构,还包括导热层,设置于所述绝缘体内部且位于所述柔性导电层与E电极板之间,以填充位于所述柔性导电层与E电极板之间的所述绝缘体内部剩余空间。
  7. 根据权利要求4-6中任一项所述的功率型半导体器件封装结构,其中,所述芯片组件包括依次层叠设置的第一过渡层、芯片和第二过渡层,所述C电极上设置用于放置芯片组件的定位凹槽,所述第一过渡层设置于所述定位凹槽内,所述第二过渡层上设置第三导电凸起,所述第三导电凸起与柔性导电层接触。
  8. 根据权利要求7所述的功率型半导体器件封装结构,其中,所述柔性导电层上设置安装孔,用于将所述柔性导电层安装于所述第三导电凸起上;
    所述柔性导电层上设置连接孔,用于所述G电极外连线通过连接孔贯穿所述柔性导电层并连接至所述驱动电极上。
  9. 根据权利要求4-6中任一项所述的功率型半导体器件封装结构,其中,所述驱动电极上设置穿通孔,用于所述第二导电凸起通过所述穿通孔贯穿所述驱动电极;所述驱动电极上设置穿线孔,用于G电极外连线引出和焊接。
  10. 根据权利要求4或5所述的功率型半导体器件封装结构,其中,所述驱动电极为具有若干铜层的PCB板;
    所述驱动电极上设置等电位孔,所述等电位孔用于铜层间的电位连接。
  11. 根据权利要求7所述的功率型半导体器件封装结构,其中,所述第一过渡层和第二过渡层均为钼层。
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Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110676176B (zh) * 2019-09-29 2021-04-13 全球能源互联网研究院有限公司 功率型半导体器件封装结构的制备工艺

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6281569B1 (en) * 1997-09-17 2001-08-28 Kabushiki Kaisha Toshiba Pressure-contact semiconductor device
CN105789157A (zh) * 2015-01-08 2016-07-20 英飞凌科技股份有限公司 具有低栅极驱动电感柔性板连接的功率半导体模块
CN107768328A (zh) * 2017-10-31 2018-03-06 华北电力大学 一种实现双面散热和压力均衡的功率器件
CN108122897A (zh) * 2016-11-30 2018-06-05 株洲中车时代电气股份有限公司 一种igbt模块
CN108172617A (zh) * 2017-12-23 2018-06-15 湖南大学 一种圆形大尺寸igbt芯片压接封装结构及制造方法
CN110676176A (zh) * 2019-09-29 2020-01-10 全球能源互联网研究院有限公司 功率型半导体器件封装结构的制备工艺

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1930545A1 (de) * 1968-06-25 1970-01-02 Texas Instruments Inc Halbleitervorrichtung,insbesondere Packungsaufbau fuer eine Halbleitervorrichtung
US5904499A (en) * 1994-12-22 1999-05-18 Pace; Benedict G Package for power semiconductor chips
US6670216B2 (en) * 2001-10-31 2003-12-30 Ixys Corporation Method for manufacturing a power semiconductor device and direct bonded substrate thereof
CN103515365B (zh) * 2013-10-14 2016-04-20 国家电网公司 一种大功率压接式igbt器件
CN105957888B (zh) * 2016-06-27 2023-09-08 南方电网科学研究院有限责任公司 一种压接式igbt子模组和igbt模块封装结构
CN107622954B (zh) * 2017-08-08 2020-02-07 全球能源互联网研究院有限公司 功率型半导体器件封装方法及封装结构
CN107731696B (zh) * 2017-09-13 2020-08-25 全球能源互联网研究院有限公司 一种功率芯片封装方法和结构
CN108520870B (zh) * 2018-04-16 2020-05-15 全球能源互联网研究院有限公司 一种功率器件封装结构
JP6898203B2 (ja) * 2017-10-27 2021-07-07 株式会社 日立パワーデバイス パワー半導体モジュール
CN109273371A (zh) * 2018-09-28 2019-01-25 全球能源互联网研究院有限公司 一种功率半导体器件封装结构及封装方法
CN210467812U (zh) * 2019-09-29 2020-05-05 全球能源互联网研究院有限公司 功率型半导体器件封装结构

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6281569B1 (en) * 1997-09-17 2001-08-28 Kabushiki Kaisha Toshiba Pressure-contact semiconductor device
CN105789157A (zh) * 2015-01-08 2016-07-20 英飞凌科技股份有限公司 具有低栅极驱动电感柔性板连接的功率半导体模块
CN108122897A (zh) * 2016-11-30 2018-06-05 株洲中车时代电气股份有限公司 一种igbt模块
CN107768328A (zh) * 2017-10-31 2018-03-06 华北电力大学 一种实现双面散热和压力均衡的功率器件
CN108172617A (zh) * 2017-12-23 2018-06-15 湖南大学 一种圆形大尺寸igbt芯片压接封装结构及制造方法
CN110676176A (zh) * 2019-09-29 2020-01-10 全球能源互联网研究院有限公司 功率型半导体器件封装结构的制备工艺

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