WO2021052138A1 - Circuit de qualité d'image, appareil de traitement d'image et procédé de détection de caractéristique de signal - Google Patents

Circuit de qualité d'image, appareil de traitement d'image et procédé de détection de caractéristique de signal Download PDF

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Publication number
WO2021052138A1
WO2021052138A1 PCT/CN2020/111831 CN2020111831W WO2021052138A1 WO 2021052138 A1 WO2021052138 A1 WO 2021052138A1 CN 2020111831 W CN2020111831 W CN 2020111831W WO 2021052138 A1 WO2021052138 A1 WO 2021052138A1
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Prior art keywords
signal
feature detection
image quality
image
quality circuit
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PCT/CN2020/111831
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English (en)
Chinese (zh)
Inventor
阿部裕俊
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海信视像科技股份有限公司
东芝视频解决方案株式会社
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Priority to CN202080004669.1A priority Critical patent/CN112673643B/zh
Publication of WO2021052138A1 publication Critical patent/WO2021052138A1/fr

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • G09G5/391—Resolution modifying circuits, e.g. variable screen formats
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
    • H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
    • H04N21/41—Structure of client; Structure of client peripherals
    • H04N21/426—Internal components of the client ; Characteristics thereof
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
    • H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
    • H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
    • H04N21/431—Generation of visual interfaces for content selection or interaction; Content or additional data rendering
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
    • H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
    • H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
    • H04N21/44—Processing of video elementary streams, e.g. splicing a video clip retrieved from local storage with an incoming video stream, rendering scenes according to MPEG-4 scene graphs
    • H04N21/4402—Processing of video elementary streams, e.g. splicing a video clip retrieved from local storage with an incoming video stream, rendering scenes according to MPEG-4 scene graphs involving reformatting operations of video signals for household redistribution, storage or real-time display
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/14—Picture signal circuitry for video frequency region
    • H04N5/20—Circuitry for controlling amplitude response
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/66—Transforming electric information into light information
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N7/00—Television systems
    • H04N7/01—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N7/00—Television systems
    • H04N7/20—Adaptations for transmission via a GHz frequency band, e.g. via satellite

Definitions

  • the embodiments of the present application relate to an image quality circuit, an image processing device, and a signal feature detection method.
  • a technique of performing feature detection of an image signal and using the feature detection result to perform various processing For example, a technique is known that detects a histogram obtained based on the brightness level of pixels of an image signal and displays the histogram, thereby confirming the actual dynamic range of the content (Dynamic range).
  • Patent Document 1 Japanese Patent Application Laid-Open No. 8-23460
  • the present invention was made in view of the above circumstances, and its object is to provide an image quality circuit, an image processing device, and a signal feature detection method that can realize higher-definition feature detection of a signal with a large number of pixels while maintaining the circuit scale.
  • the image quality circuit of the embodiment of the present application includes: a down-conversion unit that down-converts the input first signal into a second signal with a lower resolution than the first signal; Feature detection, wherein the third signal is a signal with a lower resolution than the first signal input from a system different from the system in which the first signal is input, and the feature detection unit performs the The down-conversion unit performs feature detection of the second signal that has been down-converted.
  • FIG. 1 is a block diagram showing the structure of an image processing apparatus according to a first embodiment
  • Fig. 2 is a diagram showing a configuration example of an image decoder and a signal processing unit
  • FIG. 3 is a diagram showing a configuration example of an image decoder and a signal processing unit in the second embodiment.
  • FIG. 1 is a block diagram showing the structure of the image processing apparatus according to the first embodiment.
  • description will be made by applying a digital television receiver 11 as an example of an image processing device.
  • the digital television receiver 11 is applied as an example of the image processing device, it is not limited to this, and may be a set-top box, an HDD video recorder, or the like.
  • the digital television receiver 11 includes an image display unit 14, a speaker 15, an operation unit 16, a light receiving unit 18, a broadcast signal input terminal 48, a broadcast signal input terminal 53, an output terminal 63, an output terminal 64, and a tuner. 49.
  • the BS/CS digital broadcast receiving antenna 47 and the terrestrial broadcast receiving antenna 52 are connected to the broadcast signal input terminal 48 and the broadcast signal input terminal 53, respectively.
  • the light receiving unit 18 receives the signal output from the remote controller 17.
  • the control unit 65 controls the operation of each unit in the digital television receiver 11.
  • the control unit 65 includes a CPU (Central Processing Unit) 69, a ROM (Read Only Memory) 66, a RAM (Random Access Memory) 67, and a non-volatile memory 68.
  • the ROM 66 stores control programs for the CPU 69 to execute.
  • the nonvolatile memory 68 stores various setting information and control information.
  • the CPU 69 loads the command group and data necessary for processing into the RAM 67 to execute the processing.
  • the operation information performed by the operation unit 16 or the operation information received by the light receiving unit 18 by the remote control 17 is input to the control unit 65.
  • the control unit 65 controls each unit reflecting the content of the operation.
  • the BS/CS digital broadcast receiving antenna 47 receives digital satellite television broadcast signals (including 4K/8K satellite broadcasts).
  • the BS/CS digital broadcast receiving antenna 47 outputs the received digital satellite television broadcast signal (including 4K/8K satellite broadcast) to the tuner 49 for digital satellite broadcast via the input terminal 48.
  • the tuner 49 selects the broadcast signal of the channel selected by the user from the broadcast signal.
  • the tuner 49 outputs the broadcast signal after the channel is selected to the PSK demodulator 50.
  • the PSK (Phase Shift Keying) demodulator 50 demodulates the broadcast signal after the channel is selected by the tuner 49 into digital image signals and audio signals.
  • the PSK demodulator 50 outputs the demodulated digital video signal and audio signal to the video decoder 70.
  • the terrestrial broadcast receiving antenna 52 receives terrestrial digital television broadcast signals.
  • the terrestrial broadcast receiving antenna 52 outputs a terrestrial digital television broadcast signal to the tuner 54 via the input terminal 53.
  • the tuner 54 selects the broadcast signal of the channel selected by the user from the broadcast signal.
  • the tuner 54 outputs the broadcast signal after the channel selection to the OFDM demodulator 55.
  • the OFDM (Orthogonal Frequency Division Multiplexing) demodulator 55 demodulates the broadcast signal after the channel selected by the tuner 54 into a digital image signal and a sound signal.
  • the OFDM demodulator 55 outputs the demodulated digital image signal and audio signal to the image decoder 70.
  • the image decoder 70 decodes the image signal that has been image-encoded using the moving image compression standards such as MPEG2, H.264/MPEG-4 AVC, H.265 (ISO/IEC 23008-2 HEVC), and sends it to signal processing Section 51 outputs.
  • the moving image compression standards such as MPEG2, H.264/MPEG-4 AVC, H.265 (ISO/IEC 23008-2 HEVC)
  • the signal processing unit 51 performs predetermined digital signal processing on the digital image signal and audio signal decoded by the image decoder 70.
  • the signal processing unit 51 outputs the image signal and audio signal subjected to predetermined digital signal processing to the graphic processing unit 58 and the audio processing unit 59.
  • the graphics processing unit 58 superimposes an OSD signal such as a menu generated by an OSD (On Screen Display) signal generating unit 61 on the digital image signal output from the signal processing unit 51.
  • the graphics processing unit 58 outputs the image signal on which the OSD signal is superimposed to the image processing unit 62.
  • the graphics processing unit 58 may selectively output the image signal as the output of the signal processing unit 51 and the OSD signal as the output of the OSD signal generating unit 61.
  • the image processing unit 62 converts the input digital image signal into an analog image signal that can be displayed by the image display unit 14.
  • the image processing unit 62 outputs the analog image signal to the image display unit 14.
  • the image display unit 14 displays an image based on the input analog image signal.
  • the image processing unit 62 may also export the analog image signal to the outside via the output terminal 63.
  • the sound processing unit 59 converts the input digital sound signal into an analog sound signal that can be played by the speaker 15.
  • the sound processing unit 59 outputs the analog sound signal to the speaker 15.
  • the speaker 15 plays a sound based on the input analog sound signal.
  • the sound processing unit 59 may also export the analog sound signal to the outside via the output terminal 64.
  • the signal processing unit 51 includes a histogram detection unit 60 as a feature detection unit that performs feature detection of a signal.
  • a luminance signal (Y) based on the luminance level of the pixel, for example, is input to the histogram detection unit 60.
  • the histogram detection unit 60 generates a histogram based on the luminance signal (Y).
  • an image signal is displayed based on the histogram generated by the histogram detection section 60.
  • FIG. 2 is a diagram showing a configuration example of the image decoder 70 and the signal processing unit 51.
  • the image decoder 70 includes an 8K decoder 56 and a 4K decoder 57.
  • the signal processing unit 51 includes an 8K image quality circuit 71, a 4K image quality circuit 72, an 8K ⁇ 4K down converter 73, a 4K ⁇ 8K up converter (UP converter) 74, a switch SW75, and a switch SW76. , Switch SW77.
  • the 8K image quality circuit 71 includes a first image quality circuit 711, an image quality control circuit 712, and a second image quality circuit 713, and executes various image quality processing for 8K signals.
  • the 4K image quality circuit 72 includes a first image quality circuit 721, an image quality control circuit 722, a second image quality circuit 723, and a histogram detection unit 60, and executes various image quality processing for 4K signals.
  • the first image quality circuit 721 performs an operation that does not affect the characteristic detection of the signal.
  • As one of the characteristic detection of the signal there is a histogram detection in the histogram detection unit 60 that indicates the brightness distribution of the brightness level of the pixel based on the signal.
  • the feature detection of the signal is not limited to the histogram detection indicating the brightness distribution, and may also be the histogram detection indicating the color distribution or the like.
  • the 8K broadcast signal (7680 ⁇ 4320) as the first signal is converted into a component signal (8K signal) by the 8K decoder 56.
  • This component signal and the 8K signal from an external input terminal (not shown) are switched by the switch SW75, and are input to the 8K image quality circuit 71 via the switch SW77.
  • the 8K broadcast signal and the 8K signal from the external input terminal are switched by the switch SW75 and input to the 8K ⁇ 4K down converter 73.
  • the 8K ⁇ 4K down converter 73 down-converts the 8K broadcast signal and the 8K signal from the external input terminal into a 4K signal (second signal), and outputs the signal obtained by the down conversion to the switch SW76.
  • the down-converted signal means a signal obtained by converting a signal with a large number of pixels of the original signal into a signal with a small number of pixels.
  • the 4K broadcast signal (3840 ⁇ 2160) as the third signal is converted into a component signal (4K signal) by the 4K decoder 57.
  • This component signal, the 4K signal from an external input terminal (not shown) and the 4K signal from the 8K ⁇ 4K down converter 73 are switched by the switch SW76 and input to the 4K image quality circuit 72.
  • the 4K broadcast signal input to the 4K image quality circuit 72 is converted into an 8K signal by the 4K ⁇ 8K up-converter 74 after various image quality processing is performed by the 4K image quality circuit 72.
  • the 8K signal obtained by the up-conversion is displayed on the image display unit 14 after performing various image quality processing by the 8K image quality circuit 71 via the switch SW77.
  • the 4K signal obtained by down-conversion by the 8K ⁇ 4K down converter 73 is switched by the switch SW76 and input to the 4K image quality circuit 72.
  • the down-converted 4K signal input to the 4K image quality circuit 72 is subjected to histogram detection by the histogram detection unit 60 after passing through the first image quality circuit 721 of the 4K image quality circuit 72.
  • the characteristics of the histogram of the 8K signal and the characteristics of the histogram of the 4K signal obtained by down-conversion are designed as the characteristics of the 8K signal.
  • the feature of the histogram is used instead.
  • the histogram detection unit 60 inputs the histogram detection result to the control unit 65.
  • the control unit 65 controls the OSD signal generation unit 61 to generate data based on the result of the histogram detection, and inputs the generated data to the graphics processing unit 58.
  • the graphics processing unit 58 outputs the image signal obtained by superimposing the OSD signal on the digital image signal output from the signal processing unit 51 to the image processing unit 62, wherein the OSD signal is generated by the OSD signal generating unit 61 based on histogram detection The resulting data.
  • the image processing unit 62 outputs the image signal to the image display unit 14.
  • the image display unit 14 displays an image based on the input image signal. The user can confirm the actual dynamic range of the content by viewing the histogram display of the content displayed on the image display section 14 in the form of a graph.
  • control unit 65 outputs a feedback signal for the image quality control of the 8K signal of the 8K image quality circuit 71 corresponding to the histogram detection result to the image quality control circuit of the 8K image quality circuit 71.
  • This feedback signal is the same as the feedback signal for the image quality control of the 4K signal of the 4K image quality circuit 72 corresponding to the histogram detection result.
  • the 8K signal is down-converted from 8K to 4K, and the signal is input to the 4K image quality circuit 72 as a 4K signal. Therefore, it is not necessary to perform feature detection (such as histogram detection) for 8K signals, and it is possible to achieve feature detection (such as histogram detection) for 8K signals while maintaining the circuit scale of feature detection (such as histogram detection) in 4K signals. Detection).
  • feature detection such as histogram detection
  • feature detection such as histogram detection
  • the result of feature detection for example, histogram detection
  • the result of feature detection for example, histogram detection
  • the result of feature detection for example, histogram detection
  • the feedback signal of the image quality control of the signal is the same.
  • the 4K signal obtained by down-conversion by the 8K ⁇ 4K down converter 73 is also included in the format used by the interface of a normal TV after the conversion, and becomes a signal in a format that can be output to the outside.
  • the 4K signal obtained by down-conversion by the 8K ⁇ 4K down-converter 73 also includes a signal converted into a format that is also used for HDD (Hard Disk Drive) recording and other purposes.
  • the positions of the 8K image quality circuit 71 and the 4K image quality circuit 72 and the position of the 4K ⁇ 8K upconverter 74 are not limited to the positions shown in FIG. 2.
  • the second embodiment is different from the first embodiment in that when the content does not correspond to the Dynamic HDR in which the meta information (Meta information) is recorded, the 8K signal is down-converted from 8K to 4K, and it is regarded as 4K.
  • the signal is input to the 4K image quality circuit 72.
  • the description of the same parts as the first embodiment will be omitted, and the parts different from the first embodiment will be described.
  • FIG. 3 is a diagram showing a configuration example of the image decoder 70 and the signal processing unit 51 according to the second embodiment.
  • the signal processing unit 51 of the digital television receiver 11 includes a meta-information extraction unit 80.
  • the meta-information extraction unit 80 extracts meta-information (brightness range per scene or per frame, etc.) from the component signal obtained by converting the received content (4K broadcast signal) by the 4K decoder 57.
  • the meta-information extraction unit 80 extracts meta-information (brightness range per scene or per frame, etc.) from the 4K signal from an external input terminal (not shown) and the 4K signal from the 8K ⁇ 4K down converter 73.
  • the control unit 65 of the digital television receiver 11 feeds back data based on the meta information extracted by the meta information extraction unit 80 to the image quality control circuit 712 of the 8K image quality circuit 71 and the image quality control circuit 722 of the 4K image quality circuit 72, To implement image quality control.
  • the histogram detection unit 60 of the 4K image quality circuit 72 performs the conversion from the 8K ⁇ 4K down converter 73 to the The 4K signal obtained by down-conversion performs histogram detection.
  • the histogram detection unit 60 inputs the histogram detection result to the control unit 65.
  • the control unit 65 converts the histogram detection result into the form of meta-information corresponding to Dynamic HDR, and feeds back the data based on the meta-information to the image quality control circuit 712 of the 8K image quality circuit 71 and the image quality of the 4K image quality circuit 72.
  • the quality control circuit 722 performs image quality control.
  • the 8K signal is down-converted from 8K to 4K and converted into a 4K signal. Input to 4K image quality circuit 72.
  • feature detection such as histogram detection
  • feature detection such as histogram detection
  • control unit 65 converts the result of feature detection (for example, histogram detection) into the form of meta-information for use with Dynamic HDR, thereby making it possible to achieve high image quality more easily.
  • feature detection for example, histogram detection

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  • Physics & Mathematics (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Nonlinear Science (AREA)
  • Astronomy & Astrophysics (AREA)
  • Mathematical Physics (AREA)
  • Optics & Photonics (AREA)
  • Picture Signal Circuits (AREA)
  • Controls And Circuits For Display Device (AREA)
  • Transforming Electric Information Into Light Information (AREA)
  • Television Systems (AREA)
  • Image Processing (AREA)
  • Facsimile Image Signal Circuits (AREA)

Abstract

L'invention concerne un circuit de qualité d'image capable de maintenir une échelle de circuit tout en réalisant une détection de haute précision de caractéristiques de signaux ayant un grand nombre de pixels, un appareil de traitement d'image et un procédé de détection de caractéristique de signal. Le circuit de qualité d'image comporte : une partie de conversion à la baisse, qui convertit à la baisse un premier signal d'entrée en un second signal ayant une résolution inférieure à celle du premier signal ; et une partie de détection de caractéristique, qui effectue une détection de caractéristique sur un troisième signal, le troisième signal étant un signal qui est entré par un système différent d'un système entrant le premier signal et qui possède une résolution inférieure à celle du premier signal ; et la partie de détection de caractéristique effectue une détection de caractéristique sur le second signal sur lequel la conversion à la baisse est effectuée par la partie de conversion à la baisse.
PCT/CN2020/111831 2019-09-19 2020-08-27 Circuit de qualité d'image, appareil de traitement d'image et procédé de détection de caractéristique de signal WO2021052138A1 (fr)

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JP2019170854A JP7232160B2 (ja) 2019-09-19 2019-09-19 画質回路、映像処理装置および信号特徴検出方法

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