WO2021051551A1 - Puce de mémoire à memristance et son procédé de fonctionnement - Google Patents

Puce de mémoire à memristance et son procédé de fonctionnement Download PDF

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Publication number
WO2021051551A1
WO2021051551A1 PCT/CN2019/117436 CN2019117436W WO2021051551A1 WO 2021051551 A1 WO2021051551 A1 WO 2021051551A1 CN 2019117436 W CN2019117436 W CN 2019117436W WO 2021051551 A1 WO2021051551 A1 WO 2021051551A1
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Prior art keywords
module
voltage
word line
mos tube
memristor
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PCT/CN2019/117436
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English (en)
Chinese (zh)
Inventor
王兴晟
黄恩铭
缪向水
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华中科技大学
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Publication of WO2021051551A1 publication Critical patent/WO2021051551A1/fr

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0004—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising amorphous/crystalline phase transition cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0038—Power supply circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/004—Reading or sensing circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0069—Writing or programming circuits or methods

Definitions

  • the present invention belongs to the field of memory, and more specifically, relates to a memristor chip and an operation method thereof.
  • the memristive material can switch between high resistance and low resistance.
  • the low resistance state is the state formed by the conductive path, which has a low resistance value, and the opposite is high.
  • the resistance state is a state in which the conductive path is disconnected and has a high resistance value, so data can be stored through high and low resistance.
  • the storage and read operations of the memristor include a variety of voltages with different amplitudes.
  • the most basic operations in the read and write operations of the memristor are set (write 1) and reset (write 0) operations.
  • Various operations need to quickly and accurately apply a voltage to the electrode terminal of the memristor, and the operation of the multi-resistance memristor is to add multiple corresponding set or reset pulse widths to achieve the corresponding resistance state.
  • the adjustment of this voltage requires the close cooperation of the control logic, and the appropriate operating voltage needs to be applied to the selected memory cell of the memristor to realize the storage function. If there is a misalignment in the operating voltage, it will cause the memristor The storage life becomes shorter and the probability of failure becomes higher, making the read data inaccurate.
  • the present invention provides a memristor chip, which can realize stable reading and writing operations.
  • a memristor chip which is characterized in that the chip includes a power management module, a decoding module, a storage module including a plurality of storage arrays, a logic control module, a read-write module, and /O module;
  • the logic control module provides control signals for the chip
  • the decoder module receives the control of the logic control module to perform address selection of the storage array to be operated
  • the read-write module performs address selection according to the logic control after the address selection.
  • the control signal provided by the module performs corresponding operations on the storage array
  • the interface module is used to output the data read by the read-write module
  • the word line decoder of the decoding module is arranged between the storage module There is a word line voltage conversion module. In this way, the voltage input to the gate of the word line transistor in the memory array is the adjusted voltage.
  • the word line voltage conversion circuit sets the gate voltage input to the word line transistor according to the current limit, including the following parameters: memristor memory cell high and low resistance, and the word line transistor parameters include width and length Ratio, process turn-on voltage Vth.
  • the word line voltage conversion circuit is composed of a first MOS tube and a second MOS tube, wherein the input signal to be converted is input to the gates of the first MOS tube and the second MOS tube at the same time, and the drain of the first MOS tube The pole is connected to the source of the second MOS tube, wherein the drain of the second MOS tube is grounded, and the source of the first MOS tube outputs the converted voltage.
  • the word line voltage conversion circuit has a third MOS tube, a fourth MOS tube, a fifth MOS tube, a sixth MOS tube, and an inverter.
  • the voltage before conversion is simultaneously input to the fifth MOS tube and passes through all
  • the drains of the fifth and sixth MOS transistors are connected to ground at the same time, and the source of the fifth MOS transistor is connected to the drain of the third MOS transistor.
  • the source of the MOS tube is connected to the drain of the fourth MOS tube, and the voltage between the source of the fifth MOS tube and the drain of the third MOS tube is input to the gate of the fourth MOS tube.
  • the source connection voltage of the MOS tube is converted into a reference voltage, and the gate output of the third MOS tube is the converted voltage.
  • the writing circuit in the read-write module includes a first-pole writing circuit voltage selector and a second-pole writing circuit voltage selector, which are used to select the voltage applied by the corresponding operation to form a loop.
  • the read circuit in the read-write module includes a read voltage follower circuit connected to the storage module, and a read voltage conversion circuit connected to the read voltage follower circuit, which also includes a circuit that forms a loop with a ground reference resistor.
  • a reference voltage follower circuit, and a reference voltage conversion circuit connected to the reference voltage follower circuit, the write voltage conversion circuit and the signal output from the reference voltage conversion circuit are converted into a readout signal output by a differential sensitive amplifier.
  • the present invention also provides an operating method of a memristor chip, which is characterized in that the operating method mainly includes the following steps:
  • the corresponding memristor unit is selected and turned on by the logic control module.
  • the power management module outputs the operating voltage
  • the reading and writing module controls the selector to select the voltage according to the control signal of the corresponding operation to form an operating loop, which is input to the word line transistor in the memory array
  • the voltage of the gate is adjusted by the word line voltage conversion module after the column decoder to achieve current limiting.
  • the word line voltage conversion circuit sets the gate voltage input to the word line transistor according to the current limit, including the following parameters: memristor memory cell high and low resistance, and the word line transistor parameters include width Length ratio, process turn-on voltage Vth.
  • the present invention also discloses a word line voltage conversion circuit of a memristor, which is characterized in that the word line voltage conversion circuit uses the switch tube word line transistor in the memristor storage array as a current limiting device at the same time.
  • the word line voltage conversion circuit is arranged between the word line decoder and the word line transistor, and converts the gate voltage input to the word line transistor according to the set current limit.
  • the power supply voltage is fully utilized on the premise of expanding the use of word line transistors, and the circuit structure is further simplified. Set up voltage conversion between to provide current-limiting voltage.
  • Fig. 1 is a schematic diagram of a memory cell of a memory array in a memristor chip implemented according to the present invention
  • FIG. 2 is a schematic diagram of the basic storage architecture corresponding to the memory cells of the memory array in the memristor chip implemented according to the present invention
  • FIG. 3 is a schematic diagram of the memory array architecture in the memristor chip implemented according to the present invention.
  • FIG. 4 is a schematic diagram of the composition structure of a memristor chip implemented according to the present invention.
  • FIG. 5 is a voltage conversion list under the read and write operation of the memristor chip implemented according to the present invention.
  • FIG. 6 is a schematic diagram of a write circuit structure of a memory array of a memristor chip implemented according to the present invention.
  • FIG. 7 is a block diagram of the structure of the read circuit of the memory array of the memristor chip implemented in accordance with the present invention.
  • FIG. 8 is a schematic diagram of a specific structure of a read circuit of a memory array of a memristor chip implemented according to the present invention.
  • FIG. 9 is one of the implementation modes of the specific circuit structure of the word line voltage conversion of the memristor chip according to the present invention.
  • Fig. 11 is a schematic flow chart of voltage conversion steps of a memristor chip implemented according to the present invention.
  • Storage module 2 Decoding module 3: Wordline voltage conversion module 4: Logic control module
  • Read and write module 6 Power management module 7: I/O module 8: First pole write circuit voltage selector 9: Second pole write circuit voltage selector
  • 111 Upper electrode of memristor (TiN) 110: Function layer of memristor (HfOx) 112: Lower electrode of memristor (TiN) 11: Memristor unit in 1T1R structure 13: Word line transistor in 1T1R structure 132 : Transistor source in the 1T1R structure 12: Bit line selection transistor in the memory array 13: Word line selection transistor in the memory array
  • PMOS tube 32 NMOS tube 33: PMOS tube 34: PMOS tube 35: NMOS tube 36: NMOS tube 37: Inverter
  • Reading voltage following circuit 52 Reading voltage conversion circuit 53: Reference voltage following circuit 54: Reference voltage conversion circuit 55: Reference resistance 56: Sensitive differential amplifier
  • Voltage follower amplifier 512 Voltage follow PMOS tube 521: Voltage conversion PMOS tube 531: Reference voltage follower amplifier 532: Reference voltage PMOS tube 541: Reference voltage PMOS tube
  • FIGS. 1 to 7 The embodiments of the present invention will be described in detail in conjunction with FIGS. 1 to 7 as follows:
  • FIG. 1 is a memory cell used in a memristor read-write circuit implemented according to the present invention, and its structure includes three parts, an upper electrode 100, a functional layer 110, and a lower electrode 120. It is a typical sandwich structure.
  • the electrode materials of the upper electrode and the lower electrode are Ti, Ta, TiN, TaN, and the functional layer material is HfOx.
  • the upper electrode material of the memristive memory cell is TiN
  • the functional layer material is HfOx
  • the lower electrode material is Ti.
  • Fig. 2 is a schematic diagram of the basic memory architecture corresponding to the memory cell used in the memristor read-write circuit implemented according to the present invention, which is a traditional 1T1R architecture, that is, 1 transistor and 1 memristor unit.
  • the gate of the transistor is connected to the word line control signal, the drain is connected to the lower electrode of the memristor, and the upper electrode 111 is connected to the source of the selection transistor.
  • FIG. 3 is a schematic diagram of the memory array structure corresponding to the memory cell used in the memristor read-write circuit implemented according to the present invention.
  • the source of the bit selection transistor 300 is connected to the upper electrode of a column of memory cells, and the word selection transistors 320 share the same gate in the same row, thus forming an N ⁇ M memory array.
  • the Yth bit transistor is selected At the time, only the memory cell in the Xth row and Y column will be selected.
  • Figure 4 is a schematic diagram of the structure of the memristor chip implemented in accordance with the present invention, including a block decoder 22, a row decoder 23, and a column decoder 21 to form the memory array of the memory module 1 (the memory array may have multiple , The 4 mentioned in the figure are just one of the implementations), word line voltage conversion 3, power management module 6, logic control module 4, read/write module 5, and I/O module 7.
  • the power management module 6 can be designed by LDO or DC-DC switching power supply.
  • the logic control module 4 is used to provide a control signal for the entire memristor chip, the decoder module 2 receives the control signal to select the corresponding storage unit in the storage array, and the I/O module 7 is used to read the read-write module 5
  • the data is output to other devices, such as display devices, where the read-write module 5 is used to apply the read-write voltage supplied by the power management module 6 to the storage unit in the selected storage array to complete the corresponding read-write operation.
  • the improvement of the invention is that a word line voltage conversion circuit 3 is provided between the row decoder 23 and the memory array. In this way, the voltage input to the gate of the word line transistor in the memory array through the row decoder 23 is adjusted.
  • the main technical reasons are as follows: (1) There are multiple gate loads in the memory array; 2) The voltage selected by the voltage selector does not directly act on the gate of the bit line transistor; (3) The power supply voltage is modularized and solidified, and the logic voltage output of the decoder is the power supply voltage, which cannot be the input word line transistor The current-limiting voltage required by the gate. Based on the above reasons, in order for the chip to achieve stable read and write operations, a word line voltage conversion module needs to be provided between the row decoder 23 and the memory array.
  • FIG. 5 shows the voltage required for the four basic operations of the chip's read and write operations:
  • Forming operation apply the V_forming voltage to the upper electrode of the selected memristor unit, apply the Vw_forming voltage to the word line transistor, ground the source of the word line transistor, and apply a positive ⁇ V_forming voltage to the memristor unit;
  • Set operation (write 1 operation): apply V_set voltage to the upper electrode of the selected memristor unit, apply Vw_set voltage to the word line transistor, and ground the source of the word line transistor to apply a positive ⁇ V_set voltage to the memristor;
  • Reset operation (write 0 operation): ground the upper electrode of the selected memristor unit, apply vdd voltage to the word line transistor, apply V_reset voltage to the source of the word line transistor, and apply a reversed ⁇ V_reset voltage to the memristor;
  • V_read voltage is applied to the upper electrode of the selected memristor unit, Vdd voltage is applied to the word line transistor, and the source of the word line transistor is grounded to achieve a positive ⁇ V_read voltage applied to the memristor.
  • FIGS. 6-8 it is a schematic diagram of the specific structure of the read-write module corresponding to the above-mentioned chip architecture.
  • the row, column, and block decoders will decode one of the 4 memory arrays, and select a bit and word line in the selected memory array. At this time, the memory will be selected. A cell in the array.
  • the power management module 6 provides the corresponding voltage to the read/write module 5.
  • the first pole write circuit voltage selector 8 and the second pole write circuit voltage selector 9 in the read/write module 5 select the corresponding operating voltage to apply to Bit line selection transistor 12 in the memory array;
  • the word line voltage output by the decoding will be Vw_forming, and the power management module 6 will provide corresponding voltages to the read-write module 5 and the word line voltage conversion module 3.
  • the logic control module 4 will control the reading and writing module 5 to perform the forming operation.
  • the first pole writing circuit voltage selector 8 and the second pole writing circuit voltage selector 9 in the read-write module 5 control signals to select V_forming and gnd to be added to the upper and lower ends of the storage array, respectively. Thus performing the forming operation.
  • the Set operation will apply V_set and gnd voltages to the first and second poles of the memory array, and the word line voltage conversion module 3 will apply Vw_set to the array WL.
  • the first pole writing circuit voltage selector 8 and the second pole writing circuit voltage selector 9 in the reading and writing module 5 apply the gnd and V_reset voltages respectively, and the word line voltage conversion module 3 applies the vdd voltage. In this way, the three operations of Forming, Set and Reset are completed.
  • the module mainly includes the following parts, including a read voltage follower circuit 51 connected to the memory array 1, and a read voltage conversion connected to the read voltage follower circuit 51 Circuit 52, and the reference voltage side, which includes a grounded reference resistor 55, a reference voltage follower circuit 53 that forms a loop with the reference resistor 55, and a reference voltage conversion circuit 54 connected to the reference voltage follower circuit 53, to write voltage conversion
  • the signal output by the circuit 52 and the reference voltage conversion circuit 54 is converted into a readout signal and output by the differential sense amplifier 56.
  • the read voltage follower circuit 51 includes an amplifier 511, a PMOS feedback tube 512, and an input terminal of the amplifier 511 is connected to the V_read input, and the output terminal of the amplifier 511 Connect to the gate of the PMOS feedback tube 512,
  • the other input terminal of the amplifier 511 is also connected to the drain of the PMOS feedback tube 512, wherein the source of the PMOS feedback tube 512 is connected to the read voltage conversion circuit 52, and the read voltage conversion circuit 52 is connected to the gate source of the PMOS tube 521 for saturation connection.
  • the output signal is output to the differential sense amplifier 56.
  • the read reference voltage follower circuit 53 includes an amplifier 531 and a PMOS feedback tube 532.
  • One input of the amplifier 531 is connected to the V_read input, the output terminal of the amplifier 531 is connected to the gate of the PMOS feedback tube 512, and the other input terminal of the amplifier 531 is also Connected to the drain of the PMOS feedback tube 512, wherein the source of the PMOS feedback tube 532 is connected to the reference voltage conversion circuit 54, wherein the drain of the PMOS tube 532 is also grounded through the reference resistor 55, and the reference voltage conversion circuit 53 is connected to the gate of the PMOS tube 541
  • the output signal is output to the differential sense amplifier 56 with a diode formed of a pole source.
  • the power management module 6 will provide the read voltage V_read to the read and write module 5, and the logic control module 4 will provide the control signal to the read and write module 5.
  • Three decoders (row, column, block) will select a memory cell in the memory array.
  • the voltage of the word line is converted into vdd by the word line voltage conversion module 3.
  • the amplifier 511 and the PMOS feedback tube 511 will act as a voltage follower to provide a V_read voltage at the upper end of the selected memristor unit corresponding to the memory array 1 to provide a stable and fast voltage, and the lower end of the corresponding selected memristor unit will be grounded.
  • V_read a positive read voltage V_read will be applied to the selected memristor unit.
  • the branch will generate a read current, and a voltage will be generated at one end of the differential sense amplifier 56 through the PMOS tube 521 connected in saturation.
  • a V_read voltage is generated at the end of the reference resistor 55 to obtain a read current, and a reference voltage is generated at the other end of the differential sense amplifier 531 through a diode connected to the PMOS feedback tube 531.
  • the selection of the reference resistor 55 will intervene between the high resistance and the low resistance of the memristor. For example, when the memristor unit is in the low resistance state, the voltage of the PMOS feedback tube 521 will be lower than the voltage of the PMOS feedback tube 541. When the unit is in the high-impedance state, the voltage of the PMOS feedback tube 521 will be less than the voltage of the PMOS feedback tube 541, and the differential sense amplifier 56 will compare and amplify the voltage at both ends to obtain a high (Vdd) or low (0) voltage value, which represents storage Data 1 and 0. Then the data read by the differential sensitive amplifier 56 is output to other external devices through the IO module 7.
  • Vdd high or low (0) voltage value
  • the main function is to convert the voltage.
  • the following two implementation modes are specifically given, one of which is shown in FIG. 9, where PMOS The tube 31 and the NMOS tube 32 are composed of the input signal to be converted into the gates of the PMOS tube 31 and the NMOS tube 32 at the same time.
  • the drain of the PMOS tube 31 is connected to the source of the NMOS tube 32, and the drain of the NMOS tube 32 is grounded.
  • the source output of the PMOS tube 31 is the converted voltage.
  • the above-mentioned circuit includes a PMOS tube 33, a PMOS tube 34, an NMOS tube 35, an NMOS tube 36, and an inverter 37.
  • the voltage before the voltage conversion is simultaneously input to the NMOS transistor 35, and then input to the gate of the NMOS transistor 36 after the inverter 37.
  • the drains of the NMOS transistor 35 and the NMOS transistor 36 are connected to the ground at the same time, and the source of the NMOS transistor 35 is connected to the PMOS transistor 33.
  • the source of the NMOS tube 36 is connected to the drain of the PMOS tube 34, and the voltage between the source of the NMOS tube 35 and the drain of the PMOS tube 33 is input to the gate of the PMOS tube 34, where the PMOS tube 33 and the PMOS tube
  • the source of 34 is connected to the converted reference voltage, and the output of the gate of the PMOS tube 33 is the converted voltage.
  • the present invention also proposes a word line voltage conversion method of a memristor chip, which mainly includes the following working steps:
  • the same memristor unit is selected and turned on by the logic control module 3.
  • the power management module 6 outputs the corresponding supply voltage
  • the reading and writing module 5 controls the selector to select the voltage input to the corresponding control signal according to the influence of the corresponding operation.
  • the memory array forms a corresponding operation loop.
  • the voltage applied to the word line will be output by the voltage conversion circuit after the column decoder 23 and then applied to the gate of the word line transistor to achieve current limiting.
  • a memristor memory chip is provided, and a reasonable reading and writing method and model are provided for the memristor.
  • the magnitude of the voltage conversion is mainly set according to the current limit, including the following parameters: memristor memory cell high and low resistance, word line transistor parameters including aspect ratio, process turn-on voltage Vth is to evaluate the device parameters of the limited loop to design the current limit.
  • the feedback tube is clearly defined as PMOS in this embodiment, but this is not strictly limited.
  • Different MOS tubes can be selected according to the conduction mode in the circuit, and the conduction connection of each pole can be modified and selected.
  • the high-resistance and low-resistance settings correspond to the forward and reverse voltages applied by various operations such as writing, erasing, and reading, and the corresponding read-write circuit settings, which can be set according to the material properties of the memory cell.
  • the current-limiting circuit structure form, and the current-limiting parameters are designed and modified.
  • the corresponding operating circuit can also be set according to each resistance state, and the operating loops corresponding to different resistance states can be set.
  • the corresponding voltage conversion circuit is designed for the current limit.
  • various control signals need to be generated by the controller to realize the selection and read-write control of the memory cell array.
  • the controller is set as a conventional setting for those skilled in the art.
  • the selector circuit structure They are also products such as chips and circuits that can be obtained in the prior art, and their specific structure forms are not repeated here.

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  • Crystallography & Structural Chemistry (AREA)
  • Read Only Memory (AREA)

Abstract

Puce de mémoire à memristance et son procédé de fonctionnement. La puce comprend un module de gestion d'alimentation électrique (6), un module de décodage, un module de mémoire (1), un module de commande logique (4), un module de lecture/écriture (5), et un module d'E/S (7); le module de lecture/écriture (5) effectue une opération correspondante sur un réseau de mémoire après la sélection d'adresse selon un signal de commande fourni par le module de commande logique (4); un module d'interface est utilisé pour délivrer en sortie des données lues par le module de lecture/écriture (5); un module de conversion de tension de ligne de mots (3) est disposé entre un décodeur de rangée (23) du module de décodage et du module de mémoire (1), et de cette manière, une tension appliquée à la grille d'un transistor de ligne de mots dans le réseau de mémoire est une tension ajustée. Selon la puce à memristance bipolaire et son procédé de fonctionnement, la possibilité d'échec du dispositif de mémoire à memristance après la limitation de courant est réduite, la distribution de résistance élevée et faible du dispositif sera plus uniforme, la lecture de données est stable et la durée de vie du dispositif est significativement prolongée, et lorsque l'invention est appliquée à un dispositif memristif à valeurs multiples, l'état de résistance après limitation de courant sera stable de manière correspondante.
PCT/CN2019/117436 2019-09-17 2019-11-12 Puce de mémoire à memristance et son procédé de fonctionnement WO2021051551A1 (fr)

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JIAO BIN , DENG NING , CHEN PEIYI: "Progress in Development of Resistive RAM Peripheral Circuit", RESEARCH & PROGRESS OF SSE, vol. 33, no. 4, 25 August 2013 (2013-08-25), pages 363 - 370, XP055792573, ISSN: 1000-3819 *
JIN GANG , WU YUXIN , ZHANG JI , HUANG XIAOHUI , WU JINGANG , LIN YINYIN: "Design and Realization of a 0. 13um 1 Mb Resistive Random Access Memory", RESEARCH & PROGRESS OF SSE, vol. 31, no. 2, 25 April 2011 (2011-04-25), pages 174 - 179, XP055792566, ISSN: 1000-3819 *

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